Successive approximation type analog-to-digital converter with data prediction function

Abstract

The invention relates to the technical field of integrated circuits, and discloses a successive approximation type analog-to-digital converter with a data prediction function. The converter comprises a differential capacitor array, a comparator, a control logic module, a prediction control unit and a capacitor switch module. The differential capacitor array is responsible for charge redistribution in the sampling and quantification process; the comparator is used for comparing the array output voltage; the control logic module generates bit-by-bit comparison clock signals; the prediction control unit receives an external prediction signal; the capacitor switch module comprises a plurality of either-or data selectors, first input ends of the either-or data selectors are connected with output of the comparator, second input ends of the either-or data selectors are connected with prediction signals, output ends of the either-or data selectors are connected with the capacitor lower polar plate, and enable ends receive mode selection signals. In a prediction mode, the converter directly uses an external prediction signal to set a high-order capacitance state, and an earlier successive comparison process is skipped, so that the quantization power consumption is remarkably reduced, and the conversion speed is improved.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit technology, specifically relating to a successive approximation analog-to-digital converter with data prediction function. Background Technology

[0002] Successive Approximation Register Analog-to-Digital Converters (SAR ADCs) are widely used in low-power scenarios such as IoT sensors and wearable devices due to their excellent energy efficiency at medium resolution and medium speed. Their core operating principle is based on a binary search algorithm and a charge redistribution mechanism of a capacitor array. They are memoryless systems, meaning that each quantization result depends only on the input signal value at the current sampling moment and is independent of historical quantization values.

[0003] However, in practical applications, many natural signals collected by sensors (such as biomedical signals and environmental temperature and humidity parameters) are low-pass random signals, which exhibit significant correlation in the time domain. This means that the signal value at the current moment is not entirely independent of the signal values ​​at previous moments. This inherent correlation, stemming from the distribution of the signal power spectrum, provides a theoretical basis for signal prediction based on historical data. In recent years, research has proposed introducing digital circuit algorithms to analyze historical quantization results, extract signal features, and predict the current sampled value. This aims to endow SAR ADCs with "memory" and "prediction" functions, thereby potentially further reducing the power consumption of their quantization process.

[0004] In the design of SAR ADC circuits, capacitor switching power consumption is one of the main sources of total system power consumption. To reduce power consumption, existing technologies commonly employ switching timing optimization techniques such as split-capacitor. This technique reduces unnecessary capacitor switching to some extent by splitting the large capacitor of the second-highest bit into two parallel unit capacitors, thereby reducing dynamic power consumption during quantization. However, such techniques still strictly adhere to the basic operational logic of sequential comparison and bit-by-bit switching, and their conversion speed is limited by the number of bits, making it difficult to achieve a step-by-step increase in quantization speed. Especially in potential scenarios where predictive information is used to skip high-bit comparisons, traditional switching control logic cannot be adapted, and the high-bit state cannot be directly set using the prediction results, thus limiting further optimization of power consumption and speed. Summary of the Invention

[0005] In view of the defects of low quantization power consumption and conversion speed of the existing SAR ADC, the application provides a successive approximation type analog-digital converter with data prediction function, which has a novel control architecture with switchable operation modes.

[0006] In order to achieve the above technical purpose, the application specifically adopts the following technical solutions: In one aspect of the application, a successive approximation type analog-digital converter (SAR ADC) with data prediction function is provided, comprising: a differential capacitor array for realizing charge redistribution in the sampling and quantization process; a comparator connected to the output end of the differential capacitor array, for comparing the output voltage of the differential capacitor array bit by bit and outputting the comparison result; a control logic module for generating a bit-by-bit comparison clock signal for controlling the voltage of the lower plate of the capacitor in the capacitor array; a prediction control unit for receiving an external prediction signal and controlling the capacitor flip state of the highest two bits in the prediction mode; a capacitor switch module comprising a plurality of two-way data selectors, the first input end of each data selector being connected to the output of the comparator, the second input end being connected to the corresponding output end of the prediction control unit, the output end being connected to the lower plate of the corresponding capacitor in the differential capacitor array, and the enable end receiving an external enable signal to select the operation mode; The analog-digital converter has two operation modes: a conventional mode and a prediction mode. In the conventional mode, when the external enable signal is invalid, each data selector in the capacitor switch module transmits the signal at the first input end to the output end, and the control logic module generates comparison clock signals for all bits in sequence to complete the complete successive approximation process. In the prediction mode, each data selector in the capacitor switch module transmits the signal at the second input end to the output end, and the prediction control unit directly sets the capacitor flip state of the high bits according to the external prediction signal, skipping the comparison process of the highest two bits.

[0007] In one embodiment, the number of bits controlled by the prediction control unit is the highest two bits, i.e. MSB and MSB-1 bits.

[0008] In one embodiment, the control logic module comprises an additional two-way data selector, a first input of which receives a clock signal for bit-by-bit comparison, a second input of which is connected to a fixed power supply voltage, an output of which outputs a final clock signal to the comparator, and an enable input of which receives the external enable signal; in the prediction mode, the data selector outputs a clock signal corresponding to the first two bits as a valid level to realize the skipping operation.

[0009] In one embodiment, the fixed power supply voltage is a power supply voltage VDD, and the valid level is a high level.

[0010] In one embodiment, a first input of the two-way data selector in the capacitance switching module receives a bit-by-bit comparison result from the comparator, and a second input thereof receives an external prediction signal from the prediction control unit.

[0011] In one embodiment, the precision of the analog-to-digital converter is 8 bits.

[0012] In one embodiment, the analog-to-digital converter is used in a low-power and slowly changing signal scenario, including a wearable health monitoring device or an environmental temperature and humidity sensor.

[0013] In one embodiment, the analog circuit part of the analog-to-digital converter is manufactured using a mature process, the digital prediction circuit part is manufactured using an advanced process, and the two parts are integrated through 3D packaging.

[0014] In one embodiment, the 3D packaging realizes the interconnection between the analog circuit part and the digital prediction circuit part using a through-silicon via structure.

[0015] The beneficial effects of the present application are: 1) Significantly reduce power consumption. By using a correlation algorithm to directly predict and set the capacitance state of the highest two bits (MSB and MSB-1) in the prediction mode, the present application skips the traditional successive approximation process, greatly reducing the energy loss of the capacitance array in charge redistribution. Theoretical calculations show that, only in the flipping process of the first two bits of capacitance, about 57.1% of energy is saved compared with the traditional structure. Circuit simulation results further verify that the average power consumption of the ADC is reduced from 62.7 μW to 51.0 μW, with an overall power consumption reduction of 18.66%, and the energy saving effect is significant.

[0016] 2) Improve conversion speed. Since the setup time of the highest two bits of DAC and the two comparator decision times are saved, the total time required to complete one complete quantization is effectively shortened, and the overall conversion rate (Throughput) of the ADC is improved.

[0017] 3) Performance and cost. In this application, the complex digital prediction circuit is manufactured by advanced process, which ensures the algorithm performance and reduces the power consumption of the digital module itself. The analog capacitor array and other modules with large area ratio are manufactured by mature process, which effectively controls the manufacturing cost of the chip. Finally, the system is integrated through 3D packaging (TSV through silicon via) technology, which makes the interconnection performance close to the level of single chip integration. This fundamentally overcomes the disadvantages of traditional multi-chip packaging solutions, such as large interconnection delay, significant load effect, high additional energy consumption and area overhead, and achieves the best balance between system-level performance and economy.

[0018] 4) Flexible and configurable working mode. This application integrates traditional mode and prediction mode. Users can dynamically switch the working mode through external enable signals according to the signal characteristics (such as signal bandwidth, correlation) of the actual application scene. When the signal predictability is strong (such as slow-changing biological signals, environmental parameters), the prediction mode is enabled to obtain power consumption and speed advantage. When the signal randomness is strong, the traditional mode can be switched back to ensure reliability, which has flexibility and practicality. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a schematic diagram of the split capacitor of the embodiment of the application; Figure 2 is a data prediction type SAR logic circuit of the embodiment of the application; Figure 3 is a schematic diagram of the capacitor switch of the embodiment of the application; Figure 4 is a schematic diagram of the traditional capacitor switch; Figure 5 is a 3D packaging schematic diagram of the embodiment of the application; where a is a traditional successive approximation analog-to-digital converter, and b is a successive approximation analog-to-digital converter with data prediction function of the application; Figure 6 is a traditional capacitor two-time flipping process; Figure 7 is a data prediction type SAR ADC capacitor flipping process of the embodiment of the application; Figure 8 is a power consumption comparison of the traditional and the embodiment of the application in two modes. DETAILED DESCRIPTION

[0020] The technical solutions of the application will be described clearly and completely in combination with specific embodiments, but those skilled in the art will understand that the following described embodiments are part of the embodiments of the application, not all the embodiments, and are only used to illustrate the application, and should not be regarded as limiting the scope of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the application.

[0021] In one embodiment, a successive approximation register analog-to-digital converter with data prediction function is provided, including a differential capacitor array, a comparator, a control logic module, a prediction control unit and a capacitor switch module.

[0022] The differential capacitor array adopts a binary weighted capacitor structure, which is used to realize the functions of sample and hold and digital-to-analog conversion based on charge redistribution. It includes two symmetrical capacitor networks connected to the positive input (V+) and the negative input (V-) of the comparator respectively, and each capacitor network contains a plurality of binary weighted capacitor units, the upper plate of each capacitor is connected to the corresponding comparator input, and the lower plate is connected to the reference voltage or ground through the capacitor switch module.

[0023] The positive input and the negative input of the comparator are connected to the output of the differential capacitor array respectively, which is used to compare the output voltages of the two capacitor arrays bit by bit, and output the comparison result (usually high or low), which is used to indicate the quantization state of the current bit.

[0024] The control logic module is connected to the output of the comparator, which is used to generate a series of bit-by-bit comparison clock signals (CLK1 to CLKn, n is the number of ADC bits) according to the comparison result. These clock signals control the voltage switching time of the lower plate of each capacitor in the capacitor switch module by controlling the comparator, realizing the successive approximation quantization process.

[0025] The prediction control unit is used to receive the prediction signal provided externally (usually generated by a digital signal processor or a special prediction algorithm module), and directly control the capacitor flip state of the highest two bits (MSB and MSB-1) in the prediction mode. The output of the prediction control unit is connected to the second input of the corresponding data selector in the capacitor switch module.

[0026] The capacitor switch module includes a plurality of two-way data selectors (MUX), each corresponding to the control end of the lower plate of a capacitor. Each data selector includes: The first input is connected to the output of the comparator to receive the traditional bit-by-bit comparison result. The second input is connected to the corresponding output of the prediction control unit to receive the external prediction signal. The enable terminal receives the external enable signal (EN) to select the working mode. The output is connected to the lower plate of the corresponding capacitor to control the capacitor to access the reference voltage or ground.

[0027] The analog-to-digital converter has two switchable working modes: traditional mode and prediction mode.

[0028] When the external enable signal EN is in an invalid state (e.g., low level), the analog-to-digital converter operates in conventional mode. In this mode: each data selector in the capacitor switching module transmits the signal from its first input terminal to its output terminal, directly using the comparator's output to control the voltage of the lower capacitor plate; the control logic module sequentially generates comparison clock signals for all bits (CLK1 to CLK8, taking an 8-bit ADC as an example), driving the complete successive approximation process; the quantization process starts from the most significant bit (MSB), comparing and adjusting the capacitor state bit by bit until the least significant bit (LSB) is quantized.

[0029] When the external enable signal EN is active (e.g., high level), the analog-to-digital converter operates in prediction mode. At this time: after the sampling phase, the prediction control unit directly sets the capacitor switching state of the two highest bits (MSB and MSB-1) based on the external prediction signal; the data selector corresponding to the two highest bits in the capacitor switching module transmits the prediction signal from its second input to the output, skipping the use of these two comparators; the control logic module pulls CLK1 and CLK2 high to the power supply voltage (VDD) through its internal 2-to-1 data selector structure, thereby skipping the first two comparison cycles; starting from the third bit (MSB-2), the control logic module sequentially generates clock signals CLK3 to CLK8 to drive the bit-by-bit quantization process of the remaining bits.

[0030] In some embodiments, the differential capacitor array is used as Figure 1 The illustrated split capacitor technique is optimized based on this method, but this embodiment is not limited to this structure. In the capacitor network of the differential capacitor array, the capacitance values ​​are allocated according to binary weights. The unit capacitance corresponding to the least significant bit (LSB) is C, and the capacitance values ​​of each capacitor from MSB to LSB are as follows: 128C, 64C, 32C, 16C, 8C, 4C, 2C, C.

[0031] To reduce the number of types, techniques such as split capacitors can be used to divide high-order capacitors into combinations of multiple unit capacitors. Each capacitor unit has an upper plate and a lower plate. In each capacitor network, the upper plates of all capacitor units are interconnected and connected to a common input terminal of the comparator. The two completely symmetrical capacitor networks of the differential capacitor array are called the positive terminal capacitor array and the negative terminal capacitor array, respectively. Specifically, all upper plates of the positive terminal capacitor array are connected to the non-inverting input terminal (V+) of the comparator; all upper plates of the negative terminal capacitor array are connected to the inverting input terminal (V-) of the comparator. The common connection point of the upper plates is usually connected to the common-mode voltage (VCM) through a switch during the sampling phase, and is in a floating state during the quantization phase, with voltage establishment based on the principle of charge conservation.

[0032] The lower plate of each capacitor cell is connected through an independent control unit in the capacitor switch module. The core of this control unit is a two-input data selector (MUX). Specifically, the output (C) of the data selector is connected to the lower plate of the corresponding capacitor, the first input (A) is connected to the output of the comparator for receiving the traditional successive approximation comparison result, and the second input (B) is connected to the corresponding output of the prediction control unit for receiving the external prediction signal (for the highest two bits MSB and MSB-1), and the enable end (S) receives the external enable signal EN for switching between the traditional mode and the prediction mode.

[0033] In the sampling stage, the lower plates of all capacitors are grounded, the upper plates of the positive capacitor array are connected to the positive differential input signal (VIN+), and the upper plates of the negative capacitor array are connected to the negative differential input signal (VIN-). The input signal is converted into charge and stored in the capacitor array, and the sampling of the input signal is completed.

[0034] In the quantization stage, the sampling switch is turned off, and the common point of the upper plates is floating. After the quantization process starts, the connection of the lower plates of the capacitors is controlled by the data selector: in the traditional mode (EN=0), the data selector outputs the comparator result at the A end to the lower plate of the capacitor, switches it to the reference voltage (VREF) or ground (GND), and performs bit-by-bit charge redistribution. In the prediction mode (EN=1), for the highest two bits (MSB and MSB-1), the data selector ignores the comparator result and directly outputs the prediction signal at the B end to the lower plate of the capacitor, so that it is directly connected to VREF or GND according to the prediction value, thereby skipping the time-consuming successive comparison process of these two bits.

[0035] In some embodiments, a dynamic latch comparator structure is used to adapt to the high-speed rhythm of the SAR ADC successive approximation and to minimize static power consumption. When the clock is effective, the voltages at the positive input (V+) and the inverting input (V-) of the comparator are compared: if V+>V-, a high level (e.g., VDD) is output; if V+<V-, a low level (e.g., GND) is output.

[0036] The positive input (V+) of the comparator is directly and uniquely connected to the lower plate of the corresponding capacitor in the positive capacitor array of the differential capacitor array, and the inverting input (V-) is directly and uniquely connected to the lower plate of the corresponding capacitor in the negative capacitor array of the differential capacitor array.

[0037] The comparator is provided with a clock signal input end connected to the control logic module for receiving a comparator enable signal. This signal controls the working time of the comparator, which is activated only in a short time when comparison is needed (i.e. "dynamic" work), thereby greatly reducing power consumption.

[0038] The comparator is provided with a pair of differential output ends or a single-ended output end, which has a dual connection purpose: connection to the input end of the control logic module, which generates corresponding control timing to control the comparison of the next bit; connection to the first input end (A end) of each two-way data selector in the capacitor switch module, which directly controls the switch state of the corresponding capacitor lower plate in the traditional working mode.

[0039] In the traditional mode, the external enable signal EN is invalid. The control logic module generates a complete comparison clock sequence (CLK1 to CLK8). Starting from the highest bit (MSB), the comparison clock CLK i of each bit triggers the comparator to work once. The comparator compares the positive and negative output ends of the capacitor array, and the output result directly controls the switching of the current bit capacitor lower plate through the capacitor switch module, and provides the control logic to generate the comparison clock of the next bit.

[0040] In the prediction mode, the external enable signal EN is valid. At this time, for the first two comparisons (corresponding to the highest bit MSB and the second highest bit MSB-1), the control logic module does not generate the corresponding comparison clock signals CLK1 and CLK2. Therefore, the comparator skips the comparison of these two periods to improve the overall speed. Starting from the third bit (MSB-2), the control logic generates CLK3 to CLK8 clock signals in sequence to activate the comparator and perform the remaining sequential comparison process, achieving the purpose of reducing power consumption.

[0041] In some embodiments, the control logic module is a sequential logic circuit for generating a series of ordered bit-by-bit comparison clock signals (CLK1, CLK2,..., CLK8, for an 8-bit ADC). These clock signals are used to accurately control the activation time of the comparator and the holding and switching time of the lower plate voltage in the capacitor switch module. The control logic module is usually composed of shift registers, flip-flops and combinational logic circuits inside.

[0042] In one example, the control logic module includes a clock and start input, a data input, a first mode control terminal, and a clock signal output terminal. The clock and start input receives a system master clock (Master CLK) and a start of conversion (SOC) signal, which is active to indicate the start of a new ADC conversion cycle, and the module starts running in synchronization with the master clock. The data input is connected to the output of the comparator, and in the conventional mode, the comparison result of each bit is latched and used to determine the direction of the next bit DAC establishment. The first mode control terminal is provided with an enable signal input for receiving an externally provided mode control signal: when EN=0 (inactive), the module works in the conventional mode; when EN=1 (active), the module works in the prediction mode. The clock signal output terminal is provided with a plurality of comparison clock output terminals (CLK1, CLK2,..., CLK8): CLK3 to CLK8 are directly output to the clock signal input terminal of the comparator for activating the comparator in the corresponding bit period; CLK1 to CLK8 are output to the capacitor switch module as the latch or trigger signal of each capacitor bit switch, controlling when the lower plate voltage is updated according to the output result of the data selector.

[0043] Referring to Figure 2 As shown, the control logic module is internally provided with an internal two-way data selector (MUX) for each CLK1 and CLK2 signal generation path, the first input (A end) of each MUX is connected to the original CLK1 or CLK2 signal generated by the internal conventional timing logic, the second input (B end) of each MUX is fixedly connected to a logic high level (VDD), the selection end (S end) of each MUX receives the external enable signal EN, and the output end (Y end) of each MUX is the final output CLK1 or CLK2 signal.

[0044] In the conventional mode (EN=0), the internal two-way data selector selects the A end path, and the module generates a complete comparison clock sequence CLK1, CLK2, CLK3,..., CLK8 in standard timing, CLK1 and CLK2 are output as active clock pulses to trigger the comparison and capacitor establishment process of the MSB and MSB-1 bits.

[0045] In the prediction mode (EN=1), the internal two-way data selector selects the B terminal, and the CLK1 and CLK2 signals output by the control logic module are forced to be pulled high to a constant logic high level (VDD). Since CLK1 and CLK2 are no longer valid pulse signals, the comparator will not be triggered in these two periods, thereby skipping the comparison operation of the MSB and MSB-1 bits. At the same time, the two-way data selectors corresponding to the MSB and MSB-1 bits in the capacitor switching module select the prediction signal at the B terminal due to EN=1, thereby directly completing the establishment of the capacitor state. The control logic module resumes normal timing from the third period, generates valid CLK3 to CLK8 clock pulses in sequence, and drives the successive approximation process from the MSB-2 bit to the LSB bit.

[0046] The control logic module uses level signals to replace clock pulses through the internal MUX structure, thereby achieving "skipping" of the first two quantization periods, cooperating with the prediction action of the capacitor switching module, and ultimately achieving the purpose of significantly reducing power consumption and shortening conversion time.

[0047] The prediction control unit is an interface and control circuit responsible for introducing external intelligent prediction results. It does not generate a prediction algorithm itself, but serves as a controlled channel or interface for receiving, latching, and forwarding the prediction results calculated by an external digital signal processor (DSP) or a dedicated prediction logic circuit in a specific mode. Its main function is to quickly transfer the digital signal representing the prediction state of the highest two bits (MSB and MSB-1) to the capacitor switching module after the sampling stage ends and before the quantization stage begins.

[0048] In some embodiments, the prediction control unit includes a prediction signal input terminal, a second mode control terminal, and a prediction signal output terminal. The prediction signal input terminal is provided with a multi-bit data input bus for receiving prediction results from an external prediction circuit (usually located on another digital chip manufactured using advanced technology). It can be understood that the prediction results are the prediction values of the MSB and MSB-1 bits calculated based on historical quantization data through a correlation algorithm. The second mode control terminal is provided with an enable signal input terminal connected in parallel with the enable terminals of the control logic module and the capacitor switching module to receive the same mode selection signal from the top-level controller. The prediction signal output terminal is provided with multiple output terminals corresponding to the number of controlled capacitor bits (2 in this embodiment), which are connected to the second input terminals (B terminals) of the two-way data selectors corresponding to the capacitor bits (i.e., the highest two bits) in the capacitor switching module.

[0049] In the conventional mode (EN=0), the prediction control unit is in a high impedance output state due to its output enable terminal being low, and its prediction signal output terminal is disconnected from the back-end circuit. At this time, although the external prediction signal can still exist, the unit does not have any effect on the capacitor switching module. The capacitor switching module is completely controlled by the comparator result and the control logic clock.

[0050] In the prediction mode (EN=1), before the conversion period starts or in the sampling stage, the external prediction circuit has sent the calculated prediction result to the prediction signal input terminal of the prediction control unit, and when the sampling stage ends and the quantization stage starts, the mode control signal jumps to high. This jump simultaneously acts on the control logic module, the capacitor switching module and the unit. The buffer inside the prediction control unit is enabled, immediately transmitting the input prediction signal to the prediction signal output terminal. Since the buffer has strong driving capability, the signal is quickly and stably sent to the B terminal of the corresponding data selector in the capacitor switching module. At the same time, the one-of-two data selector in the capacitor switching module selects the prediction signal at the B terminal to transmit to the capacitor lower plate, and the control logic module pulls up CLK1 and CLK2.

[0051] In some embodiments, the capacitor switching module is composed of multiple independent switching control units, the number of which is equal to the number of bits of the differential capacitor array (for example, an 8-bit ADC requires 8 units, and a positive and negative differential terminal each requires a set, a total of 16 units). The highest bit (MSB) and the second highest bit (MSB-1) switching control units have a one-of-two data selector (Multiplexer, MUX). Under the latch or trigger of the bit clock signal (CLK i ) generated by the control logic module, according to the current mode, the correct voltage control signal (from the comparator or the prediction unit) is applied to the lower plate of the corresponding capacitor, so that it is connected to the reference voltage (V REF ) or ground (GND), thereby realizing the redistribution of charges.

[0052] Each one-of-two data selector (for example, the unit controlling the highest bit MSB, see Figure 3 and Figure 4 ) has the following connection points: First data input terminal (A terminal): connected to the output terminal of the comparator, used in the conventional mode, transmitting the direct result generated by the successive approximation comparison process.

[0053] Second data input terminal (B terminal): connected to the corresponding output terminal of the prediction control unit, used in the prediction mode, transmitting the bit value calculated in advance by the external prediction algorithm.

[0054] Select control terminal (S terminal): connected to an external enable signal, which controls all the data selectors simultaneously, for unified selection of either the A path (EN = 0, traditional mode) or the B path (EN = 1, prediction mode).

[0055] Data output terminal (C terminal): connected to the switch control node of the corresponding capacitor lower plate, the output signal is used to drive the gate of the switch tube (such as CMOS transmission gate or single NMOS / PMOS tube) connected to the final control capacitor lower plate.

[0056] Clock input terminal (CLK i ): connected to the corresponding bit clock signal generated by the control logic module (such as CLK1 for MSB, CLK2 for MSB-1, …, CLK8 for LSB). The clock signal is used to latch or trigger the output state of the data selector, ensuring that the lower plate voltage only flips at a determined time, avoiding glitch interference.

[0057] In the traditional mode (EN = 0), the selection end S of all data selectors is low, and the A path is selected. At this time, the level state of the output end C of each data selector is completely determined by the output result of the comparator. The control logic module generates bit clock signals CLK1 to CLK8 in a predetermined sequence. These clock signals directly act on the switch control node of each corresponding bit in the capacitor array. When the active edge (for example, the rising edge) of the clock signal arrives, the lower plate switch of the bit capacitor is driven to act according to the output level of the data selector C end at that moment. Specifically, during the comparison period of the highest bit (MSB), when the active edge of CLK1 arrives, if the comparator output is high at that moment (indicating V+>V-), the lower plate switch of the MSB negative end capacitor is connected to the reference voltage (VREF); otherwise, it is connected to the ground (GND). The subsequent bits are similar, completing the successive approximation process.

[0058] In the prediction mode (EN = 1), the selection control end (S end) of all two-way data selectors is set to high, causing them all to select the second data input end (B end) path. For the top two bits (MSB and MSB-1), their data selector B end is connected to the prediction signal output by the prediction control unit. Therefore, the level state of the output end (C end) of these two data selectors is directly determined by the external prediction signal. At the same time, the control logic module pulls the first two bit clock signals CLK1 and CLK2 to a constant active level (such as logic high), completely skipping the comparator operation period of these two bits. For the remaining low bits (MSB-2 to LSB), the control logic module normally generates CLK3 to CLK8 clock signals to drive these low bits to continue the traditional successive approximation comparison process.

[0059] In this application, the ADC system is divided into two sub-modules with different functional and process requirements: analog circuit part and digital prediction circuit part. Both are independently manufactured with the most suitable semiconductor process for their performance and cost requirements, and then integrated at system level through 3D packaging technology to form a complete and high-performance ADC system.

[0060] In some embodiments, the analog circuit part includes a differential capacitor array, a comparator, a capacitor switching module, a timing generation circuit in the control logic module, and a reference voltage generation circuit, etc. This part is manufactured with mature process (e.g. 180nm, 130nm or 90nm CMOS process) to take full advantage of its excellent analog characteristics, high yield and low cost, while avoiding the extremely high cost of using expensive advanced process to manufacture large-size capacitor array.

[0061] The digital prediction circuit part includes a prediction control unit and external prediction algorithm circuit (e.g. digital signal processor or special logic to implement correlation calculation, feature extraction and signal prediction) interfaced with it. It is manufactured with advanced process (e.g. 28nm, 16nm or more advanced CMOS process). Small-size transistors of advanced process can provide higher switching speed, lower unit power consumption and higher integration density, perfectly meeting the stringent performance and energy efficiency requirements of complex digital algorithms.

[0062] In some embodiments, referring to Figure 5 The two parts manufactured separately are integrated in vertical direction through 3D packaging technology. The 3D packaging preferably adopts through-silicon via (TSV) based interconnection scheme, with the following specific implementation steps: Manufacture, test and thinning of analog and digital chips are completed on selected mature and advanced process production lines respectively. The two chips are aligned and bonded through chip stacking technology. One preferred way is to flip and bond the digital prediction chip (manufactured with advanced process) on top of the analog base chip (manufactured with mature process). The bonding method can be micro-bump bonding, hybrid bonding or other advanced interconnection technology. Through-silicon via (TSV) is a via structure penetrating the silicon substrate to form vertical electrical connection. In this embodiment, TSV is mainly formed in the analog base chip. One end of TSV is connected to the prediction signal output port, mode control signal port (EN) and power / ground network of the upper digital chip through redistribution layer (RDL) and bonding point; the other end of TSV is directly connected to the B end of the corresponding data selector in the capacitor switching module and the mode control end of the control logic module through the internal metal interconnection layer of the chip. The chip set with completed stacking interconnection is finally packaged in a unified package (e.g. BGA, LGA, etc.) and the necessary input, output, power and ground pins are led out.

[0063] Embodiments Capacitor array switching circuit as shown in Figure 3 The first two bits when in traditional mode, the external enable signal EN of the D flip-flop is low, no data prediction, when the comparator result is high, the C terminal output is low, i.e. the capacitor lower plate is low, the capacitor array is discharged; when the comparator result is low, the C terminal output is high, i.e. the capacitor lower plate is high, the capacitor array is charged. When in data prediction mode, the external enable signal EN of the D flip-flop is high, data prediction. At this time, the first bit capacitor switch C terminal output is the external prediction signal, the capacitor lower plate charges and discharges according to the external prediction signal, and the second bit capacitor is the same. For example, the external input signal is 11, at this time, no comparison is needed, and the first two bits of the capacitor are charged and discharged directly according to the prediction result. The following theoretically proves that the data prediction type ADC can save a lot of power consumption.

[0064] As shown in Figure 6 , it is a traditional successive comparison capacitor flipping diagram (taking 2 bits as an example).

[0065] After the sampling stage is completed, the voltage of the X node , assuming that the capacitor lower plate jumps from 0 to in the time from to , in this process, the current expression is , at this time, the voltage of the X node is , thus the capacitor array obtains energy from :

[0066] The second flipping process is as follows: Assuming that the capacitor lower plate jumps from 0 to in the time from to , in this process, the current expression is , at this time, the voltage of the X node is , thus the capacitor array obtains energy from :

[0067] From the above formula, the total energy consumed by the capacitor array in the second flipping process is: .

[0068] As shown in Figure 7 , it is a data prediction type SAR ADC capacitor flipping diagram.

[0069] X-node voltage after sampling phase Assuming the capacitor and The lower board is arrive Complete from 0 to within the time limit The jump occurs during which the current expression is: At this time, the voltage at node X is Therefore, the capacitor array can be obtained from The energy obtained is:

[0070] Comparing the two calculation results, it can be seen that the data prediction SAR ADC saves approximately 57.1% of energy compared to the traditional SAR ADC in the first two bits of the capacitor flipping stage. Therefore, the power saving function of this structure is theoretically feasible, and the more quantization bits the ADC has, the better the power optimization effect.

[0071] On the other hand, SAR control logic modules such as Figure 2 As shown, in conventional mode, the external enable signal EN is low, and CLK1 and CLK2 are the same as the input at terminal A, directly obtaining the clock signal, which is the same as conventional SAR logic. In prediction mode, the external enable signal EN is high. At this time, EN pulls CLK1 and CLK2 high to VDD through a 2-to-1 data selector. The comparator clock skips the first two cycles, canceling the comparison operation of MSB and MSB-1. At the same time, the first two bits of the capacitor array switch are toggled according to the external prediction signal. After the prediction function is completed, the SAR logic circuit generates the internal clock signals CLK3 to CLK8 sequentially, driving the bit-by-bit quantization process from MSB-2 to LSB.

[0072] Taking an 8-bit predictive SAR ADC as an example, circuit simulation was performed, and the power consumption comparison between the two modes was calculated. Figure 8 As shown, at the TT process angle and 25°C, the average power consumption decreased from 62.7 μW to 51.0 μW, a decrease of 18.66% overall. This experimental result verifies the significant power consumption reduction capability of the data prediction SAR ADC architecture proposed in this invention.

[0073] This prediction mechanism not only significantly reduces power consumption during the quantization process (especially high-weight bit flips), but also effectively shortens the conversion time by skipping the first two comparison cycles, thus improving the overall quantization speed of the ADC. Therefore, this ADC architecture is particularly suitable for power-sensitive applications where signal changes are relatively slow or predictable, such as wearable health monitoring devices and environmental temperature and humidity sensors.

[0074] Although the embodiments of the present application have been described above with reference to the accompanying drawings, the present application is not limited to the above-described specific embodiments and areas of application, and the above-described specific embodiments are merely illustrative and instructive, but are not restrictive. Many modifications can be made by those skilled in the art under the teachings of the present specification and without departing from the scope of the claims of the present application, and all such modifications are intended to be within the scope of the present application.

Claims

1. A successive approximation analog-to-digital converter with data prediction function, characterized in that, include: Differential capacitor arrays are used to achieve charge redistribution during sampling and quantization. A comparator, connected to the output terminal of the differential capacitor array, is used to compare the output voltage of the differential capacitor array bit by bit and output the comparison result; The control logic module is used to generate a bit-by-bit comparison clock signal to control the voltage of the lower-level capacitors in the capacitor array. The prediction control unit is used to receive external prediction signals and control the flip-flop state of the two highest bits of the capacitor in prediction mode; The capacitor switch module includes multiple two-to-one data selectors. The first input terminal of each data selector is connected to the comparator output, the second input terminal is connected to the corresponding output terminal of the prediction control unit, and the output terminal is connected to the lower-level board of the corresponding capacitor in the differential capacitor array. The enable terminal receives an external enable signal to select the working mode. The analog-to-digital converter has two operating modes: conventional mode and predictive mode. In the traditional mode, when the external enable signal is invalid, each data selector in the capacitor switch module transmits the signal at its first input terminal to the output terminal, and the control logic module generates the comparison clock signal for all bits in sequence to complete the complete successive approximation process. In prediction mode, each data selector in the capacitor switching module transmits the signal from its second input terminal to the output terminal. The prediction control unit directly sets the high-order capacitor flip state according to the external prediction signal, skipping the comparison process of the two highest bits.

2. The successive approximation analog-to-digital converter according to claim 1, characterized in that, The predictive control unit controls the highest two bits, namely the MSB and MSB-1 bits.

3. The successive approximation analog-to-digital converter according to claim 1, characterized in that, The control logic module includes an additional two-to-one data selector. Its first input receives a clock signal for bit-by-bit comparison, its second input is connected to a fixed power supply voltage, and its output outputs the final clock signal to the comparator. Its enable input receives the external enable signal. In prediction mode, the data selector fixes the clock signal output corresponding to the first two bits to an active level to achieve a skip operation.

4. The successive approximation analog-to-digital converter according to claim 3, characterized in that, The fixed power supply voltage is the power supply voltage VDD, and the effective level is high.

5. The successive approximation analog-to-digital converter according to claim 1, characterized in that, The first input of the two-to-one data selector in the capacitor switch module receives the bit-by-bit comparison result from the comparator, and the second input receives the external prediction signal from the prediction control unit.

6. The successive approximation analog-to-digital converter according to claim 1, characterized in that, The analog-to-digital converter has an 8-bit precision.

7. The successive approximation analog-to-digital converter according to claim 1, characterized in that, The analog-to-digital converter is used in low-power scenarios where the signal changes slowly, including wearable health monitoring devices or ambient temperature and humidity sensors.

8. The successive approximation analog-to-digital converter according to claim 1, characterized in that, The analog circuit portion of the analog-to-digital converter is manufactured using a mature process technology, while the digital prediction circuit portion is manufactured using an advanced process technology and integrated through 3D packaging.

9. The successive approximation analog-to-digital converter according to claim 8, characterized in that, The 3D package uses a through-silicon via (TSV) structure to interconnect the analog circuit section and the digital prediction circuit section.

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