Video clock recovery method and device, storage medium and electronic equipment

Abstract

The invention discloses a video clock recovery method and device, a storage medium and electronic equipment, and the method comprises the steps: extracting a video time sequence parameter from an auxiliary information packet when the auxiliary information packet transmitted by a transmitting end is received; configuring a phase-locked loop according to the video time sequence parameter, and generating a video clock; when the video data is received, counting the actual clock number of each video line by using a video clock so as to obtain the current clock error of each video line; performing coarse adjustment on the video clock according to the current clock error until the video clock is initially converged; and performing fine adjustment on the video clock after preliminary convergence until the video clock reaches a stable state. According to the invention, the precision of video clock recovery can be improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of video data transmission, and in particular to a video clock recovery method and device, a storage medium and an electronic device. BACKGROUND

[0002] With the rapid development of high-definition video, virtual reality, vehicle-mounted display and other applications, the market demand for high-speed video interfaces (such as DisplayPort, MIPI CSI / DSI, DVI, LVDS, etc.) is growing. When transmitting video data, these interfaces usually use a packed data transmission method. Due to bandwidth, power consumption and interface structure design requirements, independent video clocks are generally not carried in the video data. Therefore, the video clock must be regenerated at the receiving end (i.e., video clock recovery) to ensure the accuracy and real-time performance of subsequent display or data processing.

[0003] However, due to the difference between the clocks of the sending end and the receiving end, combined with the hysteresis of the Phase Locked Loop (PLL) adjustment and the noise and interference in signal sampling, the traditional video clock recovery method has problems such as slow convergence, large error or frequent oscillation, resulting in poor accuracy and real-time performance of video clock recovery, which is difficult to meet strict timing requirements. SUMMARY

[0004] Embodiments of the present application provide a video clock recovery method, device, storage medium and electronic device, which can improve the accuracy of video clock recovery.

[0005] In a first aspect, embodiments of the present application provide a video clock recovery method, comprising:

[0006] When receiving an auxiliary information packet transmitted by the sending end, extracting a video timing parameter from the auxiliary information packet;

[0007] Configuring a Phase Locked Loop (PLL) according to the video timing parameter to generate a video clock;

[0008] When receiving video data, using the video clock to count the actual clock number of each video line to obtain the current clock error of each video line;

[0009] Coarsely adjusting the video clock according to the current clock error until the video clock is preliminarily converged;

[0010] Fine-tuning the preliminarily converged video clock until the video clock reaches a stable state.

[0011] In the video clock recovery method provided by the embodiments of the present application, the video clock is generated by configuring a Phase Locked Loop (PLL) according to the video timing parameter, comprising:

[0012] calculating a target clock frequency according to the video timing parameter;

[0013] setting an integer division coefficient and a decimal division coefficient of a phase-locked loop based on the target clock frequency;

[0014] starting the phase-locked loop to generate an initial video clock.

[0015] In the video clock recovery method provided in the embodiments of the present application, the step of coarsely adjusting the video clock according to the current clock error until the video clock is preliminarily converged includes:

[0016] coarsely adjusting the decimal division coefficient according to the error direction of the current clock error until the video clock is preliminarily converged.

[0017] In the video clock recovery method provided in the embodiments of the present application, the step of coarsely adjusting the decimal division coefficient according to the error direction of the current clock error until the video clock is preliminarily converged includes:

[0018] when the current clock error is greater than or equal to a positive coarse adjustment threshold, increasing the decimal division coefficient;

[0019] when the current clock error is less than or equal to a negative coarse adjustment threshold, decreasing the decimal division coefficient;

[0020] After the decimal division coefficient is adjusted once, the video clock is updated, and the step of counting the actual clock number of each video line by using the video clock to obtain the current clock error of each video line is executed until the video clock is preliminarily converged.

[0021] In the video clock recovery method provided in the embodiments of the present application, the step of finely adjusting the video clock preliminarily converged includes:

[0022] when the video clock is preliminarily converged, detecting a real-time difference between the current data amount of the video buffer area and the initial depth threshold when the effective area of each video line starts to output;

[0023] when the absolute value of the real-time difference is greater than a fine adjustment threshold, finely adjusting the video clock based on the real-time difference until the video clock reaches a stable state.

[0024] In the video clock recovery method provided in the embodiments of the present application, the step of finely adjusting the video clock based on the real-time difference until the video clock reaches a stable state includes:

[0025] The boundary constraint method is used to fine-tune the video clock based on the real-time difference until the video clock reaches a stable state.

[0026] The boundary constraint method is used to fine-tune the video clock based on the real-time difference until the video clock reaches a stable state, and includes:

[0027] The maximum value and the minimum value of the fractional frequency division parameter in the coarse adjustment stage are obtained to form a current oscillation boundary.

[0028] Within the current oscillation boundary, the fractional frequency division coefficient is adjusted based on the real-time difference and a fine adjustment step until the video clock reaches a stable state.

[0029] In the video clock recovery method provided in the embodiments of the present application, the fine-tuning of the video clock based on the real-time difference until the video clock reaches a stable state includes:

[0030] The trend adaptive method is used to fine-tune the video clock based on the real-time difference until the video clock reaches a stable state.

[0031] The trend adaptive method is used to fine-tune the video clock based on the real-time difference until the video clock reaches a stable state, and includes:

[0032] The fractional frequency division coefficient is adjusted once based on the real-time difference and a fine adjustment step.

[0033] The change amplitude of the real-time difference and the direction of the most recent continuous two clock adjustments are obtained.

[0034] The adjustment strategy of the video clock is determined according to the change amplitude of the real-time difference and the direction of the most recent continuous two clock adjustments until the video clock reaches a stable state.

[0035] In a second aspect, the embodiments of the present application provide a video clock recovery device, which includes:

[0036] A parameter extraction unit is configured to extract a video timing parameter from an auxiliary information package transmitted by a sending end when the auxiliary information package is received.

[0037] A clock generation unit is configured to configure a phase-locked loop according to the video timing parameter and generate a video clock.

[0038] An error acquisition unit is configured to count the actual clock number of each video line by using the video clock when video data is received, so as to acquire the current clock error of each video line.

[0039] a clock coarse adjustment unit configured to coarsely adjust the video clock according to the current clock error until the video clock is preliminarily converged;

[0040] a clock fine adjustment unit configured to finely adjust the preliminarily converged video clock until the video clock reaches a stable state.

[0041] In a third aspect, the present application provides a storage medium storing a plurality of instructions, which are adapted to be loaded by a processor to execute the video clock recovery method according to any one of the preceding aspects.

[0042] In a fourth aspect, the present application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the video clock recovery method according to any one of the preceding aspects when executing the computer program.

[0043] To sum up, the video clock recovery method provided by the embodiments of the present application includes: when an auxiliary information packet transmitted by a sending end is received, extracting a video timing parameter from the auxiliary information packet; configuring a phase-locked loop according to the video timing parameter to generate a video clock; when video data is received, using the video clock to count actual clock numbers of each video line to obtain a current clock error of each video line; coarsely adjusting the video clock according to the current clock error until the video clock is preliminarily converged; finely adjusting the preliminarily converged video clock until the video clock reaches a stable state. The embodiments of the present application adopt a two-stage feedback mechanism of "coarse adjustment + fine adjustment", first coarsely adjust the video clock to preliminarily converge, quickly reduce the clock error in the coarse adjustment stage, and then finely adjust to reach a stable state, finely adjust in the fine adjustment stage to ensure the convergence and stability of the video clock adjustment process, effectively eliminate the clock error caused by the response delay of the PLL, signal noise, and the like in the traditional scheme, make the recovered video clock more close to the target video clock, and thus effectively improve the precision of the video clock recovery. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0045] Figure 1 is an application scenario diagram of the video clock recovery method provided by the embodiments of the present application.

[0046] Figure 2FIG. 1 is a flowchart of a method for video clock recovery according to an example embodiment of the present application.

[0047] Figure 3 FIG. 2 is a structural diagram of a device for video clock recovery according to an example embodiment of the present application.

[0048] Figure 4 FIG. 3 is a structural diagram of an electronic device according to an example embodiment of the present application. DETAILED DESCRIPTION

[0049] The example embodiments will be described in detail herein with reference to the attached drawings. The following description is made with reference to the accompanying drawings in which like reference numerals refer to like elements, and the description is made in the order of the following examples. The following description is made with reference to the accompanying drawings in which like reference numerals refer to like elements, and the description is made in the order of the following examples. The following example embodiments described in the following examples do not represent all embodiments in accordance with the present application. Rather, they are merely examples in accordance with some aspects of the present application as detailed in the appended claims.

[0050] It should be noted that, in this document, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element. The terms "an embodiment", "one embodiment", or "some embodiments" do not require that all embodiments include the discussed element, and that the same element can not be present in all embodiments. Identically named components, features, or elements in different embodiments of the present application can or can not have the same functionality and can or can not be present in all embodiments.

[0051] It should be understood that the specific embodiments described herein merely exemplify the application and should not be considered as limiting the application.

[0052] In the following description, the suffixes "module", "part", or "unit" used for an element are merely intended for facilitating the description of the present application, and are not intended to limit the application. Therefore, "module", "part", or "unit" can be mixed and used.

[0053] In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second" and the like are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0054] Due to the difference between the clock of the sending end and the receiving end, plus the hysteresis of the PLL adjustment itself and the noise and interference in signal sampling, the traditional video clock recovery method has problems such as slow convergence, large error or frequent oscillation, resulting in poor precision and real-time performance of video clock recovery, which is difficult to meet the strict timing requirements.

[0055] Based on this, the embodiments of the present application provide a video clock recovery method, device, storage medium and electronic equipment. Specifically, the video clock recovery device can be integrated in an electronic equipment, which can be a server or a terminal device. The terminal device can include a mobile phone, a wearable smart device, a tablet computer, a notebook computer, and a personal computer (PC), etc. The server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0056] For example, as shown in Figure 1 The video clock recovery method is executed by the electronic equipment. Specifically, when the electronic equipment receives the auxiliary information package transmitted by the sending end, the video timing parameters are extracted from the auxiliary information package. The phase-locked loop is configured according to the video timing parameters, and the video clock is generated. When the video data is received, the actual clock number of each video line is counted using the video clock to obtain the current clock error of each video line. The video clock is coarsely adjusted according to the current clock error until the video clock is preliminarily converged. The video clock after preliminary convergence is finely adjusted until the video clock reaches a stable state.

[0057] The technical solutions shown in the present application will be described in detail below through specific embodiments. It should be noted that the description order of the following embodiments is not limited to the priority order of the embodiments.

[0058] Please refer to Figure 2 , Figure 2 is a flowchart of the video clock recovery method provided by the embodiments of the present application. The specific process of the video clock recovery method can be as follows:

[0059] 101、When receiving the auxiliary information packet transmitted by the sending end, extract the video timing parameters from the auxiliary information packet.

[0060] The auxiliary information packet (Auxiliary Info Packet / InfoFrame) is a special data structure used in high-speed video interfaces (such as DisplayPort, HDMI, MIPI, etc.) to carry control information (control parameters) of non-pixel image data. That is, the auxiliary information packet is a metadata structure used in high-speed video transmission to deliver video timing, frequency ratio, image properties, and other control parameters, and is a key basis for the receiving end to achieve video clock recovery and correct display. Therefore, the receiving end will preferentially receive the auxiliary information packet before receiving the video data.

[0061] In some embodiments, when the receiving end receives the auxiliary information packet transmitted by the sending end, the video timing parameters can be extracted from the auxiliary information packet, which can include the total line clock number htotal, the total field line number vtotal, and the pixel clock ratio parameter Mvid / Nvid.

[0062] 102、According to the video timing parameters, configure the phase-locked loop to generate the video clock.

[0063] In some embodiments, the target clock frequency can be calculated according to the video timing parameters; the integer frequency division coefficient pll_int and the fractional frequency division coefficient pll_frac of the phase-locked loop can be set based on the target clock frequency; and the phase-locked loop can be started to generate the initial video clock vid_clk.

[0064] Specifically, the target clock frequency can be calculated based on the pixel clock ratio parameter, and the calculation formula is as follows: F=F_link×(Mvid / Nvid), where F is the target clock frequency, and F_link is the link clock frequency.

[0065] When configuring the phase-locked loop, the ratio of the target clock frequency to the link clock frequency is usually decomposed into an integer part and a fractional part, so as to set the integer frequency division coefficient and the fractional frequency division coefficient respectively.

[0066] For example, assuming that the target video clock frequency is F_target, and the link clock frequency is F_link. First, calculate the overall proportional relationship of the target video clock frequency to the link clock frequency: Ratio=F_target

[0067] / F_link. The ratio Ratio is usually not an integer, and its integer part corresponds to the integer division coefficient, and the remaining fractional part is used for fractional adjustment. Specifically, pll_int = floor(Ratio), where floor(·) represents the floor function. Then, the fractional part of Ratio is calculated: Remainder = Ratio - pll_int. In the PLL, the fractional division coefficient usually adopts a fixed resolution denominator (such as 2^N or other preset value D), so pll_frac can be determined by the following formula: pll_frac = round(Remainder x D), where round(·) represents rounding, and D is the fractional resolution (for example, if the PLL adopts 16-bit fractions, then D = 65536).

[0068] In some embodiments, an initial depth threshold fifo_depth_init of a video buffer (First Input First Output, FIFO) can also be set to ensure that video data is pushed to the subsequent processing unit only when the amount of data in the FIFO exceeds the initial depth threshold.

[0069] 103、When receiving the video data, the actual clock number of each video line is counted using the video clock to obtain the current clock error of each video line.

[0070] After receiving the video data transmitted by the sending end at the receiving end, the start pulse and the end pulse of each video line in the received video data can be converted from the link clock domain of the sending end to the video clock domain of the receiving end. Then, at the start of each video line, a counter (hcounter) based on the video clock is started to count the clock cycles in the video line; at the end of each video line, the counter stops counting and records the actual clock number of the video line; and the current clock error of each video line is calculated according to the video timing parameters and the actual clock number.

[0071] Specifically, the total line clock number htotal can be extracted from the video timing parameters, and then the difference between the total line clock number and the actual clock number can be calculated to obtain the current clock error of each video line.

[0072] 104、According to the current clock error, the video clock is coarsely adjusted until the video clock is preliminarily converged.

[0073] In some embodiments, the fractional division coefficient can be coarsely adjusted according to the error direction of the current clock error until the video clock is preliminarily converged.

[0074] Specifically, when the current clock error is greater than or equal to the positive coarse adjustment threshold, it indicates that the video clock is too slow, and the video clock can be adjusted to be faster by increasing the decimal division coefficient. When the current clock error is less than or equal to the negative coarse adjustment threshold, it indicates that the video clock is too fast, and the video clock can be adjusted to be slower by decreasing the decimal division coefficient.

[0075] It can be understood that when the adjustment of the decimal division coefficient causes a carry or a borrow, the integer division coefficient can be updated accordingly.

[0076] In addition, in the embodiment of the present application, the clock adjustment operation is only allowed to be performed once for each video line, so as to avoid system instability caused by excessive adjustment. In the embodiment, the cumulative coarse adjustment of multiple video lines causes the system to appear obvious back-and-forth oscillation, which indicates that the video clock has been preliminarily converged to a relatively appropriate range, and the video clock is relatively close to the link clock of the sending end, but there is a small amplitude oscillation. At this time, the fine adjustment stage is entered to further reduce the oscillation range.

[0077] That is, in the specific implementation process, the step of "coarsely adjusting the decimal division coefficient according to the error direction of the current clock error until the video clock is preliminarily converged" can include: increasing the decimal division coefficient when the current clock error is greater than or equal to the positive coarse adjustment threshold; decreasing the decimal division coefficient when the current clock error is less than or equal to the negative coarse adjustment threshold; and updating the video clock after completing one adjustment of the decimal division coefficient, and returning to perform the step of counting the actual clock number of each video line by using the video clock to obtain the current clock error of each video line until the video clock is preliminarily converged.

[0078] In actual application, the direction of continuous multiple clock coarse adjustment (such as "faster → slower → faster") can be recorded, and if periodic oscillation occurs, it indicates that the video clock is relatively close to the link clock of the sending end. When the oscillation times reach a preset threshold (such as 3 consecutive direction reversals), it can be determined that the video clock is converged, and the fine adjustment stage is entered.

[0079] It should be noted that the coarse adjustment threshold can be set according to actual conditions, and the embodiment does not limit it. It can be understood that when the decimal division coefficient is increased or decreased each time, the adjustment can be performed according to a preset coarse adjustment step. Similarly, the coarse adjustment step can be set according to actual conditions.

[0080] 105、coarsely adjusting the video clock preliminarily converged until the video clock reaches a stable state.

[0081] When the video clock is initially converged, a real-time difference fifo_diff between the current data amount of the video buffer and the initial depth threshold fifo_depth_init can be detected at the start of the output of the active area of each video line: fifo_diff = current data amount of FIFO - fifo_depth_init. Fine tuning is triggered only when |fifo_diff| exceeds a fine tuning threshold. For example, if the fine tuning threshold is set to 5%, fine tuning is triggered when fifo_diff = +6% or fifo_diff = -7%. It should be noted that during the vertical blanking interval (VBlank) of each video line, fine tuning is not triggered even if |fifo_diff| > fine tuning threshold.

[0082] +6% or fifo_diff = -7%. It should be noted that during the vertical blanking interval (VBlank) of each video line, fine tuning is not triggered even if |fifo_diff| > fine tuning threshold.

[0083] Specifically, when the absolute value of the real-time difference is greater than the fine tuning threshold, the boundary constraint method or the trend adaptive method can be used to fine tune the video clock based on the real-time difference until the video clock reaches a stable state.

[0084] In the embodiments of the present application, fine tuning includes two methods: the boundary constraint method and the trend adaptive method.

[0085] The boundary constraint method can be as follows: first, the maximum value pll_frac_max and the minimum value pll_frac_min of the fractional frequency division coefficient pll_frac in the coarse tuning stage can be obtained to form a current oscillation boundary. Then, the fractional frequency division coefficient is adjusted based on the real-time difference and the fine tuning step within the current oscillation boundary until the video clock reaches a stable state.

[0086] Specifically, if the real-time difference fifo_diff > 0 (the FIFO data amount is too much), it indicates that the video clock needs to be accelerated. At this time, the fractional frequency division coefficient pll_frac can be increased within the current oscillation boundary according to the fine tuning step, but not greater than the maximum value pll_frac_max.

[0087] If the real-time difference fifo_diff < 0 (the FIFO data amount is insufficient), it indicates that the video clock needs to be slowed down. At this time, the fractional frequency division coefficient pll_frac can be decreased within the current oscillation boundary according to the fine tuning step, but not less than the minimum value pll_frac_min.

[0088] Then, the fine tuning step is decreased according to a preset strategy, and the next video line is fine tuned based on the updated fine tuning step until the video clock reaches a stable state.

[0089] That is, the step of "fine tuning the video clock after initial convergence until the video clock reaches a stable state" can include:

[0090] When the video clock is preliminarily converged, a real-time difference between a current data amount of the video buffer area and the initial depth threshold is detected at a start of the active area of each video line;

[0091] When an absolute value of the real-time difference is greater than a fine adjustment threshold, the video clock is fine adjusted based on the real-time difference until the video clock reaches a stable state.

[0092] The step of fine adjusting the video clock based on the real-time difference until the video clock reaches the stable state can include: obtaining a maximum value and a minimum value of the fractional division coefficient in the coarse adjustment stage to form a current oscillation boundary; and adjusting the fractional division coefficient based on the real-time difference and a fine adjustment step within the current oscillation boundary until the video clock reaches the stable state.

[0093] It should be noted that the fine adjustment step is much smaller than the coarse adjustment step. For example, the fine adjustment step can be set to 1 / 5 to 1 / 10 of the coarse adjustment step (e.g., the coarse adjustment step is 10 ppm, and the fine adjustment step is 2 ppm).

[0094] The preset strategy means that the fine adjustment step can be dynamically adjusted according to the current oscillation amplitude, for example, the fine adjustment step is reduced by half when the oscillation amplitude is reduced by 50%. In another embodiment, the fine adjustment step can also be reduced by the same preset value each time.

[0095] It should be noted that if the clock adjustment attempts to break through the current oscillation boundary for three consecutive times, the current oscillation boundary needs to be updated and the fine adjustment step needs to be reset.

[0096] In some embodiments, the video clock reaching the stable state can mean that the absolute value of the real-time difference is less than a stable threshold (such as ±1%) within a plurality of consecutive active line video lines (such as 10 lines).

[0097] The trend adaptive method can be as follows:

[0098] First, the fractional division coefficient can be adjusted once based on the real-time difference and the fine adjustment step, and then the direction of the recent two consecutive clock adjustments and the change amplitude of the real-time difference fifo_diff are obtained. Finally, the adjustment strategy of the video clock is determined according to the direction of the recent two consecutive clock adjustments and the change amplitude of the real-time difference fifo_diff until the video clock reaches the stable state.

[0099] Specifically, if the directions of the two consecutive clock adjustments are consistent (such as both adjusting the clock to be fast), and |fifo_diff| is reduced (such as from +8% to +4%), it indicates that the adjustment is effective, and the current clock adjustment direction can be continued.

[0100] If the clock adjustment direction is consistent for two consecutive times (e.g., both fast forward the clock), but |fifo_diff| increases, it indicates that the adjustment is excessive, and needs to be corrected in the opposite direction.

[0101] If it is detected that the clock adjustment direction is consistent for two consecutive times, and |fifo_diff| decreases, but the decrease rate of |fifo_diff| is lower than expected (e.g., the real-time difference decreases by <1% per time), the adjustment is suspended for 1-3 video line periods to avoid high-frequency disturbance.

[0102] Similarly, within a plurality of consecutive valid line video lines (e.g., 10 lines), when the absolute value of the real-time difference is less than the stable threshold, the trend adaptive method can be stopped.

[0103] In summary, the video clock recovery method provided in the embodiments of the present application includes: when receiving an auxiliary information packet transmitted by a sending end, extracting a video timing parameter from the auxiliary information packet; configuring a phase-locked loop according to the video timing parameter to generate a video clock; when receiving video data, using the video clock to count the actual clock number of each video line to obtain the current clock error of each video line; coarsely adjusting the video clock according to the current clock error until the video clock preliminarily converges; finely adjusting the video clock after preliminary convergence until the video clock reaches a stable state. The video clock recovery method provided in the embodiments of the present application adopts a two-stage feedback mechanism of "coarse adjustment + fine adjustment", quickly reduces the clock error in the coarse adjustment stage, and adjusts the decimal division coefficient through fine adjustment in the fine adjustment stage, so as to ensure the convergence of the video clock adjustment process, effectively eliminate the clock error caused by the response delay of the PLL, signal noise and the like in the traditional scheme, make the recovered video clock more close to the target video clock, and thus improve the precision of the video clock recovery. Moreover, the video clock recovery method provided in the embodiments of the present application detects the real-time difference between the current data amount of the FIFO and the initial depth threshold in the valid area of each video line in real time, so that the PLL can quickly respond to the clock deviation at the line level, thereby greatly shortening the adjustment time of the video clock recovery, and in combination with the fine adjustment step decrement strategy, the video clock can be accurately corrected in a very short time, and the real-time performance of the video clock recovery is significantly improved.

[0104] To better implement the video clock recovery method provided in the embodiments of the present application, the embodiments of the present application further provide a video clock recovery device. The meanings of the terms are the same as those in the above-mentioned video clock recovery method, and the specific implementation details can be referred to the description in the method embodiments.

[0105] Please refer to Figure 3 , Figure 3This is a schematic diagram of the video clock recovery device provided in an embodiment of this application. The video clock recovery device may include a parameter extraction unit 201, a clock generation unit 202, an error acquisition unit 203, a clock coarse adjustment unit 204, and a clock fine adjustment unit 205.

[0106] The parameter extraction unit 201 is used to extract video timing parameters from the auxiliary information packet when it receives the auxiliary information packet transmitted by the sending end;

[0107] The clock generation unit 202 is used to configure the phase-locked loop according to the video timing parameters and generate a video clock.

[0108] The error acquisition unit 203 is used to count the actual clock count of each video line using the video clock when receiving video data, so as to obtain the current clock error of each video line.

[0109] The clock coarse adjustment unit 204 is used to coarsely adjust the video clock according to the current clock error until the video clock initially converges.

[0110] The clock fine-tuning unit 205 is used to fine-tune the video clock after initial convergence until the video clock reaches a stable state.

[0111] For specific implementation methods of each of the above units, please refer to the embodiments of the video clock recovery method described above, which will not be repeated here.

[0112] In summary, the video clock recovery device provided in this application embodiment can receive auxiliary information packets transmitted by the transmitting end through parameter extraction unit 201 and extract video timing parameters from the auxiliary information packets; the clock generation unit 202 configures a phase-locked loop according to the video timing parameters to generate a video clock; when video data is received, the error acquisition unit 203 uses the video clock to count the actual clock count of each video line to obtain the current clock error of each video line; the clock coarse adjustment unit 204 performs coarse adjustment on the video clock according to the current clock error until the video clock initially converges; and the clock fine adjustment unit 205 performs fine adjustment on the initially converged video clock until the video clock reaches a stable state. The video clock recovery device provided in this application embodiment adopts a two-stage feedback mechanism of "coarse adjustment + fine adjustment". In the coarse adjustment stage, the clock error is quickly reduced, and in the fine adjustment stage, the fractional frequency division coefficient is finely adjusted to ensure the convergence and stability of the video clock adjustment process. This can effectively eliminate the clock error caused by PLL response delay, signal noise, etc. in traditional solutions, making the recovered video clock closer to the target video clock, thereby improving the accuracy of video clock recovery.

[0113] This application also provides an electronic device that may integrate the video clock recovery device described in this application, such as... Figure 4As shown in the figure, it shows a structural schematic diagram of an electronic device related to the embodiments of the present application, in particular:

[0114] The electronic device can include a processor 301 with one or more processing cores and a memory 302 with one or more computer readable storage media, etc. Those skilled in the art can understand that, Figure 4 The electronic device structure shown in the figure does not constitute a limitation on the electronic device, and can include more or fewer components than the figure, or combine certain components, or different component arrangements. Among them:

[0115] The processor 301 is the control center of the electronic device, which connects all parts of the electronic device through various interfaces and lines, executes the software programs and / or the present application stored in the memory 302, and calls the data stored in the memory 302, to perform various functions and process data of the electronic device, thereby overall monitoring the electronic device. Optionally, the processor 301 can include one or more processing cores; preferably, the processor 301 can integrate an application processor and a modem processor, wherein the application processor mainly processes operation storage media, user interface and application programs, etc., and the modem processor mainly processes wireless communication. It can be understood that the above-mentioned modem processor can also not be integrated into the processor 301.

[0116] The memory 302 can be used to store software programs and the present application, and the processor 301 executes the software programs and the present application stored in the memory 302, thereby performing various function applications and data processing. The memory 302 can mainly include a program storage area and a data storage area, wherein the program storage area can store application programs required by at least one function, etc.; the data storage area can store data created according to the use of the electronic device, etc. In addition, the memory 302 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other volatile solid-state memory device. Accordingly, the memory 302 can also include a memory controller to provide access for the processor 301 to the memory 302.

[0117] Although not shown, the electronic device can also include a display unit, an input unit, a power supply, etc., which will not be described here. In particular, in the present embodiment, the processor 301 in the electronic device will load the executable file corresponding to the process of one or more application programs into the memory 302 according to the following instructions, and run the application programs stored in the memory 302 by the processor 301, thereby realizing various functions, as follows:

[0118] When receiving the auxiliary information package transmitted by the sending end, extracting the video timing parameters from the auxiliary information package;

[0119] According to the video timing parameter, a phase-locked loop is configured to generate a video clock;

[0120] When receiving the video data, the actual clock number of each video line is counted by using the video clock to obtain a current clock error of each video line;

[0121] According to the current clock error, the video clock is coarsely adjusted until the video clock is preliminarily converged;

[0122] The preliminarily converged video clock is finely adjusted until the video clock reaches a stable state.

[0123] Those skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions or by related hardware controlled by the instructions, which can be stored in a computer readable storage medium and loaded and executed by a processor.

[0124] To this end, an embodiment of the present application provides a storage medium, which stores a plurality of instructions. The instructions can be loaded by a processor to execute steps in any method provided by an embodiment of the present application. For example, the instructions can execute the following steps:

[0125] When receiving the auxiliary information packet transmitted by the sending end, video timing parameters are extracted from the auxiliary information packet;

[0126] According to the video timing parameters, a phase-locked loop is configured to generate a video clock;

[0127] When receiving the video data, the actual clock number of each video line is counted by using the video clock to obtain a current clock error of each video line;

[0128] According to the current clock error, the video clock is coarsely adjusted until the video clock is preliminarily converged;

[0129] The preliminarily converged video clock is finely adjusted until the video clock reaches a stable state.

[0130] The specific implementation of each operation can be referred to the foregoing embodiments, which will not be described here.

[0131] The storage medium can include a read only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0132] Since the instructions stored in the storage medium can execute the steps in any method provided by the embodiments of the present application, the beneficial effects that can be achieved by any method provided by the embodiments of the present application can be achieved. Details are described in the foregoing embodiments, which will not be repeated here.

[0133] The video clock recovery method, device, storage medium and electronic equipment provided by the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above embodiment description is only used to help understand the core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range will be changed; in summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A video clock recovery method, characterized in that, include: When an auxiliary information packet transmitted by the sending end is received, video timing parameters are extracted from the auxiliary information packet; Configure a phase-locked loop based on the video timing parameters to generate a video clock; When video data is received, the actual clock count for each video line is counted using the video clock to obtain the current clock error for each video line. The video clock is coarsely adjusted based on the current clock error until the video clock initially converges. The video clock, after initial convergence, is fine-tuned until it reaches a stable state.

2. The video clock recovery method as described in claim 1, characterized in that, The step of configuring a phase-locked loop and generating a video clock based on the video timing parameters includes: Calculate the target clock frequency based on the video timing parameters; The integer and fractional frequency division coefficients of the phase-locked loop are set based on the target clock frequency; The phase-locked loop is activated to generate the initial video clock.

3. The video clock recovery method as described in claim 2, characterized in that, The step of coarsely adjusting the video clock based on the current clock error until the video clock initially converges includes: The fractional frequency division coefficients are coarsely adjusted according to the error direction of the current clock error until the video clock initially converges.

4. The video clock recovery method as described in claim 3, characterized in that, The step of coarsely adjusting the fractional frequency division coefficients according to the error direction of the current clock error until the video clock initially converges includes: When the current clock error is greater than or equal to the positive coarse adjustment threshold, the fractional frequency division coefficient is increased; When the current clock error is less than or equal to the negative coarse adjustment threshold, the fractional frequency division coefficient is reduced; After adjusting the fractional frequency division coefficient once, the video clock is updated, and the process returns to the step of using the video clock to count the actual clock count of each video line to obtain the current clock error of each video line, until the video clock initially converges.

5. The video clock recovery method as described in claim 3, characterized in that, The fine-tuning of the video clock after initial convergence includes: When the video clock initially converges, and output begins in the effective area of ​​each video line, the real-time difference between the current data volume of the video buffer and the initial depth threshold is detected. When the absolute value of the real-time difference is greater than the fine-tuning threshold, the video clock is fine-tuned based on the real-time difference until the video clock reaches a stable state.

6. The video clock recovery method as described in claim 5, characterized in that, The step of fine-tuning the video clock based on the real-time difference until the video clock reaches a stable state includes: The boundary constraint method is used to fine-tune the video clock based on the real-time difference until the video clock reaches a stable state. The step of employing a boundary constraint method to fine-tune the video clock based on the real-time difference until the video clock reaches a stable state includes: Obtain the maximum and minimum values ​​of the fractional frequency division parameter mentioned in the coarse adjustment stage to form the current oscillation boundary; Within the current oscillation boundary, the fractional frequency division coefficient is adjusted based on the real-time difference and the fine-tuning step size until the video clock reaches a stable state.

7. The video clock recovery method as described in claim 5, characterized in that, The step of fine-tuning the video clock based on the real-time difference until the video clock reaches a stable state includes: The trend-adaptive method is used to fine-tune the video clock based on the real-time difference until the video clock reaches a stable state. The step of employing a trend-adaptive method to fine-tune the video clock based on the real-time difference until the video clock reaches a stable state includes: The fractional frequency division coefficient is adjusted once based on the real-time difference and the fine-tuning step size. Obtain the change magnitude of the real-time difference between the two most recent consecutive clock adjustments; The adjustment strategy for the video clock is determined based on the direction of the two most recent consecutive clock adjustments and the magnitude of the change in the real-time difference, until the video clock reaches a stable state.

8. A video clock recovery device, characterized in that, include: The parameter extraction unit is used to extract video timing parameters from the auxiliary information packet when it receives the auxiliary information packet transmitted by the sending end; A clock generation unit is used to configure a phase-locked loop according to the video timing parameters and generate a video clock. An error acquisition unit is used to, when receiving video data, use the video clock to count the actual clock count of each video line in order to obtain the current clock error of each video line; A clock coarse adjustment unit is used to coarsely adjust the video clock according to the current clock error until the video clock initially converges. The clock fine-tuning unit is used to fine-tune the video clock after initial convergence until the video clock reaches a stable state.

9. A storage medium, characterized in that, The storage medium stores multiple instructions adapted for loading by a processor to execute the video clock recovery method according to any one of claims 1-7.

10. An electronic device, characterized in that, The device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the video clock recovery method as described in any one of claims 1-7.

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