Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate; the bit line structure is arranged on the substrate along a third direction, the third direction is parallel to the substrate, and the bit line structure comprises a first part and a second part which are arranged along the third direction; the first laminated structure and the second laminated structure are arranged on the two sides of the bit line structure and are connected with the first part; the first leading-out structure and the second leading-out structure are arranged on the two sides of the bit line structure and are connected with the second part; the first lead-out structure is provided with first contact pads which are mutually staggered in a first direction, the second lead-out structure is provided with second contact pads which are mutually staggered in the first direction, and the first direction intersects with the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure, a method for manufacturing the same, and an electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Compared to static memory, DRAM has advantages such as simpler structure, lower manufacturing cost, and higher storage density. With the development of technology, the application of DRAM is becoming increasingly widespread.

[0003] To improve storage density, a three-dimensional stacked DRAM structure has been proposed, comprising several vertically stacked memory cells. Each memory cell includes a transistor and a capacitor. The active region of the transistor extends approximately along a horizontal direction, and a capacitor electrode electrically connected to the transistor also extends approximately along this horizontal direction. One end of the active region of the transistor is connected to the capacitor, and the other end is connected to a bit line. In this DRAM structure, a typical set of stacked structures corresponds to a set of bit line lead-out structures. These lead-out structures are generally stepped structures, occupying a large area, which is not conducive to improving storage density. Summary of the Invention

[0004] According to an embodiment of this disclosure, a semiconductor device is provided, comprising:

[0005] Substrate; bit line structure, the bit line structure is disposed on the substrate along a third direction, the third direction is parallel to the substrate, the bit line structure includes a first part and a second part arranged along the third direction;

[0006] The first stacked structure and the second stacked structure are disposed on both sides of the bit line structure and connected to the first part;

[0007] The first lead-out structure and the second lead-out structure are disposed on both sides of the bit line structure and connected to the second part; the first lead-out structure has a first contact pad that is offset from each other in a first direction and the second lead-out structure has a second contact pad that is offset from each other in a first direction, the first direction intersecting with the substrate.

[0008] In some embodiments, the first lead-out structure and the second lead-out structure further include a contact plug disposed on the contact pad.

[0009] In some embodiments, the contact pad and the contact plug are integrally formed.

[0010] In some embodiments, the bit line structure includes multiple bit lines, which are connected to corresponding layers of the first and second stacked structures, and each bit line corresponds to a contact pad.

[0011] In some embodiments, the contact pads of the first lead-out structure are connected to the bit lines of the odd-numbered layers, and the contact pads of the second lead-out structure are connected to the bit lines of the even-numbered layers.

[0012] In some embodiments, the bit line structure includes two sets of bit lines. In a first direction, the first set of bit lines is disposed between the second set of bit lines and the substrate. The contact pad of the first lead-out structure is connected to the first set of bit lines, and the contact pad of the second lead-out structure is connected to the second set of bit lines.

[0013] In some embodiments, the first stacked structure and / or the second stacked structure have a memory structure, the memory structure including a memory node and a memory transistor, the source and drain of the memory transistor being connected to the bit line structure and the memory node, respectively; the gates of the memory transistors corresponding to different layers of the first stacked structure and / or the second stacked structure are connected.

[0014] In some embodiments, the bit line structure includes multiple bit lines, and the storage structures of corresponding layers of the first stacked structure and the second stacked structure are connected to the same bit line.

[0015] In some embodiments, the semiconductor device further includes a first sub-word line driver connected to the gate of the first stacked structure, and a second sub-word line driver connected to the gate of the second stacked structure.

[0016] In some embodiments, the bit line structure has a plurality of through holes, which are arranged along a third direction and penetrate the bit line structure along a first direction. An insulating material is disposed in the through holes, and the first direction intersects with the substrate.

[0017] According to some other embodiments of this disclosure, a method for manufacturing a semiconductor structure is also provided.

[0018] Provide substrate;

[0019] An initial stacked structure is formed on the substrate;

[0020] In the initial stacked structure, a bit line structure is formed along a third direction. The bit line structure includes multiple bit lines stacked along a first direction. The bit lines are correspondingly arranged with the initial stacked structure. The third direction is parallel to the substrate, and the first direction intersects the substrate. The bit line structure also includes a first part and a second part.

[0021] A first stacked structure and a second stacked structure are formed on both sides of the first part, and the corresponding layers of the first stacked structure and the second stacked structure are connected to the same bit line.

[0022] A first lead-out structure and a second lead-out structure are formed on both sides of the second part. The first lead-out structure and the second lead-out structure include contact pads that are staggered in a first direction. The contact pads are connected to the bit lines one by one.

[0023] The step of forming the contact pad includes: forming an opening in the initial stacked structure to expose the corresponding layer, etching the corresponding layer to the position of the corresponding bit line, and depositing a contact pad at the bottom of the hole.

[0024] In the embodiments of this disclosure, a semiconductor device and its manufacturing method are provided, which have the advantages of being easy to manufacture and occupying less area; multiple stacked structures share a bit line structure, that is, one bit line can connect two corresponding memory structures, and each bit line only needs one contact pad, thus saving the area occupied by the entire device, and the manufacturing method is easy to implement; the lead-out structure is easy to manufacture, has high reliability, and occupies a small area. Attached Figure Description

[0025] Figure 1 A schematic diagram of a semiconductor structure provided for some embodiments of this disclosure;

[0026] Figure 2 A schematic diagram of a semiconductor structure provided for some embodiments of this disclosure;

[0027] Figure 3a , Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Figure 10a , Figure 11a This is a cross-sectional view along a second direction showing the location of the bitline structure to be set in the initial stacked structure provided in some embodiments of this disclosure;

[0028] Figure 3b , Figure 4b , Figure 5b , Figure 6b , Figure 7b , Figure 8b , Figure 9b , Figure 10b , Figure 11b This is a cross-sectional view along a third direction showing the location where a contact pad will be placed in the initial stacked structure provided in some embodiments of this disclosure. Detailed Implementation

[0029] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0030] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0031] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0032] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0033] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0034] It should be noted that the technical solutions and technical features described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0035] At least some embodiments of this disclosure provide a semiconductor device, including:

[0036] Substrate; bit line structure, the bit line structure is disposed on the substrate along a third direction, the third direction is parallel to the substrate, the bit line structure includes a first part and a second part arranged along the third direction;

[0037] The first stacked structure and the second stacked structure are disposed on both sides of the bit line structure and connected to the first part;

[0038] The first lead-out structure and the second lead-out structure are disposed on both sides of the bit line structure and connected to the second part; the first lead-out structure has a first contact pad that is offset from each other in a first direction and the second lead-out structure has a second contact pad that is offset from each other in a first direction, the first direction intersecting with the substrate.

[0039] like Figure 1As shown, in some embodiments, a semiconductor device 10 is provided, optionally a three-dimensional dynamic random access memory, including: a substrate 100, optionally made of semiconductor materials such as single crystal silicon, germanium silicon, and silicon carbide, and may include other pre-prepared structures, such as transistors disposed in the substrate.

[0040] A bit line structure 5000 is disposed on the substrate 100 along a third direction D3 parallel to the plane of the substrate. Optionally, the bit line structure includes a first part 31 and a second part 30 arranged along the third direction. Optionally, there can be multiple first parts; the optional second part can be in the middle of multiple first parts, preferably at one end of the bit line structure; the optional second part can be multiple.

[0041] In some embodiments, the bit line structure includes multiple bit lines 200, 201, 202, 203, which are spaced apart along a first direction D1 perpendicular to the plane of the substrate, and an insulating layer (not shown) is disposed between the multiple bit lines.

[0042] In some embodiments, the insulating layer material is selected from silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

[0043] In some embodiments, the bit line structure 5000 further includes a plurality of through holes 900. Optionally, the through holes penetrate the bit line structure along a first direction, and an insulating material (not shown) is disposed in the through holes, with multiple bit lines surrounding the insulating material. Optionally, the number of through holes is at least two.

[0044] In some embodiments, the insulating material is selected from silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

[0045] The first stacked structure 1000 and the second stacked structure 2000 are disposed on both sides of the bit line structure and connected to the first part. The first stacked structure and the second stacked structure share a bit line structure. Preferably, the first stacked structure and the second stacked structure are disposed opposite each other on both sides of the bit line structure along the second direction D3. The second direction is parallel to the plane where the substrate is located and intersects with the third direction. Optionally, there may be multiple first stacked structures and / or multiple second stacked structures.

[0046] In some embodiments, the first stacked structure and / or the second stacked structure has a memory structure 50, which includes a memory node 700 and a memory transistor 40; the memory transistor includes a source 300, a drain 600, an active layer 500, and a gate 400; the source and drain of the memory transistor are respectively connected to a bit line structure and a memory node, and a gate insulating layer (not shown) is disposed between the gate and the active layer; optionally, the first stacked structure and / or the second stacked structure includes multiple spaced memory structures, and the memory structures of different layers are connected to the corresponding bit lines of each layer; optionally, each layer of the first stacked structure and / or the second stacked structure includes multiple spaced memory structures, and the memory structures of each layer are connected to a corresponding bit line; optionally, multiple spaced memory structures are disposed in the same layer of the first stacked structure and / or the second stacked structure. The storage array is composed of a storage structure and multiple layers of spaced storage structures. Preferably, the storage structures in the same layer of the first stacked structure and the second stacked structure share a bit line and are mirror images of each other relative to the shared bit line. Optionally, the gates of corresponding storage transistors in different layers are connected to form word lines. The word lines formed by the gates of the storage transistors in the first stacked structure are connected to the first sub-word line driver 21, and the word lines formed by the gates of the storage transistors in the second stacked structure are connected to the second sub-word line driver 20. Optionally, the semiconductor device includes multiple first sub-word line drivers and / or multiple second sub-word line drivers. Each word line in the first stacked structure is connected to a first sub-word line driver, and each word line in the second stacked structure is connected to a second sub-word line driver.

[0047] In some embodiments, the gate insulating layer material is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof.

[0048] In some embodiments, a first sub-word line driver and a second sub-word line driver are disposed on the substrate 100 and connected to word lines via traces.

[0049] In some embodiments, the semiconductor device further includes another substrate, on which the first sub-word line driver and the second sub-word line driver are disposed and connected to the word line by bonding. The bonding method can be selected from microbump bonding, hybrid bonding, wire bonding, etc.

[0050] In some embodiments, the storage node may be a storage capacitor disposed along the second direction. Optionally, the storage node may be one of phase change memory, magnetoresistive memory, ferroelectric memory, etc.

[0051] In some embodiments, the storage node is a storage capacitor. The dielectric material of the storage capacitor may be formed from at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, or may include at least one of, for example, hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0052] In some embodiments, the semiconductor device includes a plurality of bit line structures, which are spaced apart on a substrate along a second direction. Each bit line structure is connected to at least one first stacked structure and a second stacked structure. Preferably, the word lines of the first stacked structures to which each bit line structure is connected are connected to the same first sub-word line driver, and the word lines of the second stacked structures to which each bit line structure is connected are connected to the same second sub-word line driver.

[0053] In some embodiments, a bit line structure connects multiple first stacked structures and multiple second stacked structures. Each first stacked structure and / or second stacked structure contains multiple memory structures spaced apart on the same layer and multiple memory structures spaced apart on multiple layers to form a memory array. The gate connections of corresponding memory transistors on different layers form word lines. Each word line in each first stacked structure is connected to a first sub-word line driver, and each word line in each second stacked structure is connected to a second sub-word line driver. Each bit line in the bit line structure is connected to a sensitive amplifier.

[0054] The first lead-out structure 3000 and the second lead-out structure 4000 are disposed on both sides of the bit line structure and connected to the second part of the bit line structure. The first lead-out structure has first contact pads 800 and 801 that are offset from each other in a first direction, and the second lead-out structure has second contact pads 802 and 803 that are offset from each other in a first direction. An insulating material (not shown) is disposed between the contact pads. "Offset from each other" means that the projections of the contact pads on the substrate along the first direction do not overlap. Preferably, the first lead-out structure and the second lead-out structure are disposed opposite each other on both sides of the second part of the bit line structure in a second direction.

[0055] In some embodiments, the contact pads are connected one-to-one with the bit lines to lead out the bit lines and connect the bit lines to the sensitive amplifier.

[0056] In some embodiments, the multiple bit lines in the bit line structure can be divided into two groups: the bit lines closer to the substrate are the first group, and the bit lines farther from the substrate are the second group. The first group of bit lines is connected to a first contact pad in a one-to-one correspondence, and the second group of bit lines is connected to a second contact pad in a one-to-one correspondence. Optionally, the number of bit lines in the first group and the second group can be equal or unequal; preferably, the number of bit lines in the first group and the second group is equal.

[0057] In some embodiments, such as Figure 2 In the bit line structure, the odd-numbered bit lines are connected one-to-one with the first contact pad, and the even-numbered bit lines are connected one-to-one with the second contact pad.

[0058] In some embodiments, the first lead-out structure and the second lead-out structure further include contact plugs 900 disposed on contact pads, with each contact plug corresponding to a contact pad. Preferably, the contact plugs and contact pads are made of the same material and are integrally formed. The bit line is connected to the sensitive amplifier through the contact pads and contact plugs.

[0059] In some embodiments, the semiconductor device includes another substrate, on which the sensitive amplifier is disposed and connected to a contact plug via bonding, thereby connecting to a bit line. The bonding method is selected from microbump bonding, hybrid bonding, wire bonding, etc.

[0060] In other embodiments of this disclosure, a method for fabricating a semiconductor device is further provided, including...

[0061] Provide substrate;

[0062] An initial stacked structure is formed on the substrate;

[0063] In the initial stacked structure, a bit line structure is formed along a third direction. The bit line structure includes multiple bit lines stacked along a first direction. The bit lines are correspondingly arranged with the initial stacked structure. The third direction is parallel to the substrate, and the first direction intersects the substrate. The bit line structure also includes a first part and a second part.

[0064] A first stacked structure and a second stacked structure are formed on both sides of the first part, and the corresponding layers of the first stacked structure and the second stacked structure are connected to the same bit line.

[0065] A first lead-out structure and a second lead-out structure are formed on both sides of the second part. The first lead-out structure and the second lead-out structure include contact pads that are staggered in a first direction. The contact pads are connected to the bit lines one by one.

[0066] The step of forming the contact pad includes: forming an opening in the initial stacked structure to expose the corresponding layer, etching the corresponding layer to the position of the corresponding bit line, and depositing a contact pad at the bottom of the hole.

[0067] like Figures 3a-11b As shown, a substrate has an initial stacked structure formed on it, which is formed by alternating material layers M1 and M2. Figure 3a 4a, 5a, 6a, 7a, 8a, 9a, 10a, and 11a are cross-sectional views perpendicular to the second direction and passing through the positions where the bit line structures will be set in the initial stacked structure. Figure 3b 4b, 5b, 6b, 7b, 8b, 9b, 10b, and 11b represent the positions of a contact pad to be placed in the initial stacked structure, perpendicular to the third-direction cross-sectional view.

[0068] In some embodiments, the initial stacked structure may be selected from alternatingly deposited silicon nitride and silicon oxide, or from single-crystal silicon and single-crystal silicon germanium fabricated by epitaxial growth, or from alternating preparation of two different thin film materials with high etching selectivity. Material layer M1 and material layer M2 represent the two selected different materials, respectively.

[0069] In the initial stacked structure, a bit line structure is formed along a third direction. The bit line structure includes multiple bit lines stacked along the first direction, with the bit lines corresponding to the initial stacked structure. The bit line structure also includes a first part and a second part. The fabrication method includes fabricating multiple vias penetrating the initial stacked structure at the locations where the bit line structure is formed, and laterally etching a material layer M2 within the vias. Figure 4a , Figure 4b As shown, the distance between the slots is controlled, and the material layer M2 between adjacent slots is etched away during the lateral etching process. Optionally, the number of slots is at least two, and can be more than one.

[0070] In some embodiments, the method for etching the hole grooves can be a dry etching process.

[0071] In some embodiments, the method for lateral etching of material layer M2 can be a liquid phase etching process. Optionally, the etching rate of the etchant in the liquid phase etching process on material layer M2 is greater than the etching rate of the etchant on material layer M1.

[0072] Furthermore, such as Figure 5a , Figure 5b , Figure 6a , Figure 6b As shown, a material layer M3 is deposited in the hole, and then anisotropic etching is performed to remove part of the material layer M3 on the surface of the hole. Since there are grooves left by lateral etching on the sidewall of the hole, the part of the material layer M3 that is blocked by the grooves will be retained to form independent bit lines.

[0073] In some embodiments, anisotropic etching is a dry etching process, plasma etching process, etc.

[0074] In some embodiments, the material layer M3 may include metals, metal nitrides, metal oxides, metal silicides, conductive carbon, and combinations thereof; such as titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof, or non-metallic materials such as polycrystalline silicon, gallium indium tin oxide, indium tin oxide, etc., or combinations thereof.

[0075] In some embodiments, the deposition method of material layer M3 is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, and other processes.

[0076] Optionally, after the bit lines are formed, insulating material is deposited to fill the holes and grooves to form the bit line structure.

[0077] Furthermore, a first layered structure and a second layered structure are formed on both sides of the first part, with corresponding layers of the first layered structure and the second layered structure connected to the same bit line. Optionally, the first layered structure and the second layered structure are fabricated after the bit line structure is fabricated, and the first layered structure and the second layered structure are connected to the first part of the bit line structure.

[0078] In some embodiments, a plurality of first stacked structures and a plurality of second stacked structures are formed on both sides of the first portion, and corresponding layers of the first stacked structures and the second stacked structures are connected to the same bit line. Isolation trenches are formed between the plurality of first stacked structures and isolation trenches are formed between the plurality of second stacked structures.

[0079] In some embodiments, the first and second stacked structures are fabricated prior to the bitline structure.

[0080] In some embodiments, a memory structure is formed in the first stacked structure and / or the second stacked structure. The memory structure includes a memory node and a memory transistor. The memory transistor includes a source, a drain, an active layer, and a gate. The source and drain of the memory transistor are respectively connected to the bit line structure and the memory node, and a gate insulating layer (not shown) is disposed between the gate and the active layer. Optionally, the first stacked structure and / or the second stacked structure includes a memory structure formed by multiple layers of spacing, and the memory structures of different layers are connected to the corresponding bit lines of each layer. Optionally, each layer of the first stacked structure and / or the second stacked structure includes multiple memory structures formed by spacing, and the memory structures of each layer are connected to a corresponding bit line. Optionally, the multiple memory structures formed by spacing in the same layer and the memory structures arranged by multiple layers of spacing in the first stacked structure and / or the second stacked structure form a memory array. Preferably, the memory structures of the same layer in the first stacked structure and the second stacked structure are connected to a common bit line and are arranged in a mirror image relative to the common bit line. Optionally, the gates of the corresponding memory transistors of different layers are connected to form word lines.

[0081] In some embodiments, material layers M1 and M2 are selected from silicon and silicon-germanium, and the active layer in the storage transistor is formed by etching silicon or silicon-germanium. In this embodiment, the gate can be formed in the via by etching vias at corresponding positions on the initial stack surface.

[0082] In some embodiments, the active layer in the storage transistor can be an oxide semiconductor material. In this embodiment, the storage transistor can be fabricated by etching a trench at the location corresponding to the storage transistor on the initial stacked surface, laterally etching a lateral groove in the trench, forming an active layer material layer, and then using an anisotropic etching process to form an independent active layer. Further, a gate insulating layer and a gate electrode are fabricated. In this embodiment, the source of the storage transistor can be formed in the same process as the bit line. Optionally, if the storage node is a storage capacitor, the drain of the storage transistor can be formed in the same process as the lower electrode of the storage capacitor.

[0083] In some embodiments, the storage node is a storage capacitor. The dielectric material of the storage capacitor may be formed from at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, or may include at least one of, for example, hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0084] In some embodiments, the gate insulating layer material is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof.

[0085] Furthermore, the method for fabricating contact pads in the initial laminated structure is as follows: Figure 7b , Figure 8b , Figure 9b , Figure 10b , Figure 11b As shown, a via is etched at the corresponding position in the second part of the bit line structure, with the depth of the via reaching the corresponding layer. A material layer M4 is deposited within the via. An anisotropic etching process is used to remove the material layer M4 at the bottom of the via, exposing the corresponding material layer M3. An isotropic etching process is then used to etch away part of the exposed material layer M3, exposing the corresponding bit line and forming a groove at the bottom of the via. A material layer M5 is formed within this groove, forming a contact pad that connects to the corresponding bit line. Optionally, the method for forming the material layer M5 within the groove at the bottom of the via can be as follows: Figure 11b As shown, a material layer M5 is formed simultaneously in the groove at the bottom of the hole and in the hole groove. Then, the material layer M5 in the hole groove is etched away, and the remaining material layer M5 forms a contact pad. Optionally, after forming the contact pad, insulating material is further filled into the hole groove.

[0086] Optionally, the methods for forming the material layer M5 include: physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, and other processes.

[0087] Optional anisotropic etching processes include dry etching, plasma etching, etc.

[0088] Optionally, the isotropic etching process includes a liquid phase etching process, wherein the etching rate of the etchant on material layer M2 is greater than the etching rate of the etchant on material layer M1, and the etching rate of the etchant on material layer M2 is greater than the etching rate of the etchant on material layer M4.

[0089] In some embodiments, the contact pads are prepared before the bit lines. When a portion of the exposed material layer M3 is etched away using an isotropic etching process, etching stops when the corresponding bit line is formed, creating a bottom recess. A material layer M5 is then deposited within the bottom recess to form the contact pads. In the subsequent bit line formation step, the corresponding contact pads are exposed during lateral etching of the material layer M3, forming the bit lines and connecting them to the contact pads.

[0090] In some embodiments, the material layer M5 may include metals, metal nitrides, metal oxides, metal silicides, conductive carbon, and combinations thereof; such as titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof, or non-metallic materials such as polycrystalline silicon, gallium indium tin oxide, indium tin oxide, etc., or combinations thereof.

[0091] Furthermore, multiple contact pads are prepared as described above, with each contact pad corresponding to a bit line and staggered from the others, meaning that the projections of the contact pads onto the substrate along the first direction do not overlap. Optionally, a portion of contact pads are formed on each side of the bit line structure, namely, a first lead-out structure and a second lead-out structure. Optionally, the number of contact pads in the first lead-out structure and the second lead-out structure are not equal. Preferably, the number of contact pads in the first lead-out structure and the second lead-out structure are equal. Optionally, a portion of the contact pads closer to the substrate are disposed on the same side of the bit line structure to form the first lead-out structure or the second lead-out structure, and a portion of the contact pads farther from the substrate are disposed on the other side of the bit line structure to form the first lead-out structure or the second lead-out structure. Preferably, a portion of the contact pads closer to the substrate are disposed on the same side of the bit line structure to form the first lead-out structure or the second lead-out structure. A portion of the contact pads near the substrate are disposed on the same side of the bit line structure to form a first lead-out structure, and a portion of the contact pads away from the substrate are disposed on the other side of the bit line structure to form a second lead-out structure. The first lead-out structure is disposed close to the first stacked structure, and the second lead-out structure is disposed away from the second stacked structure. Optionally, the contact pads of an odd number of layers are disposed on the same side of the bit line structure to form the first lead-out structure or the second lead-out structure, and the contact pads of an even number of layers are disposed on the other side of the bit line structure to form the first lead-out structure or the second lead-out structure. Optionally, the contact pads in the first lead-out structure and / or the second lead-out structure are closer to the substrate in the first direction and closer to the corresponding first stacked structure and / or the second stacked structure in the third direction.

[0092] In some embodiments, the first lead-out structure and the second lead-out structure further include contact plugs disposed on the contact pads, with each contact plug corresponding to a contact pad; optionally, such as Figure 10b After a contact pad is formed in the groove at the bottom of the hole, a contact plug is further formed in the groove. The contact plug and the contact pad can be made of the same material or different materials; preferably, the contact plug and the contact pad are made of the same material and are integrally formed, such as... Figure 11b As shown, a material layer M5 is formed in both the groove at the bottom of the hole and the groove inside the hole, so that the contact pad and the contact plug can be formed simultaneously in one process.

[0093] In some embodiments provided in this disclosure, the first stacked structure and the second stacked structure share a bit line structure, which connects the first lead-out structure and the second lead-out structure. Compared with related embodiments, this saves the substrate area occupied by the lead-out structure, thus enabling the design of semiconductor device structures with higher integration.

[0094] The bit line structure includes multiple bit lines, through holes, and insulating material (not shown) is placed inside the through holes. Multiple bit lines are arranged around the insulating material. This structure is easier to manufacture, and because the bit lines are arranged around the through holes, it forms a... Figure 1 The shape of the bit line 203 includes two lines connecting the sources of the memory transistors in the corresponding layers, as well as a line segment connecting the two lines. Therefore, while ensuring ease of fabrication, the overall conductivity of the bit line can be improved. Optionally, the more vias are added to the bit line, the more line segments connect the two lines, and the better the conductivity of the bit line.

[0095] Since each bit line only requires one contact pad for lead-out, the overall area occupied by the lead-out structure is reduced compared to related implementations due to the reduced number of contact pads.

[0096] The memory structures in the opposing layers of the first and second stacked structures are connected to the same bit line and will receive bit line signals simultaneously. Therefore, they need to be driven by different sub-word line drivers. When the sub-word line driver, the first stacked structure, and the second stacked structure are disposed on the same substrate in the semiconductor device, the sub-word line driver is formed before the first and second stacked structures, and the first and second stacked structures can be disposed on the sub-word line driver. The substrate areas occupied by the two do not overlap, thus improving integration density in this embodiment. Optionally, the sub-word line driver can also be disposed on another substrate and then connected by a bonding process. In this embodiment, since the sub-word line driver and the stacked structure are fabricated on different substrates, their fabrication processes do not affect each other, thus further improving product yield.

[0097] In embodiments using contact pads to lead bit lines, the contact pads are fabricated separately, occupying less area compared to stepped lead-out methods. In stepped lead-out methods, the lower layer protrudes beyond the upper layer, resulting in a significantly longer lead length for the bottom layer compared to the top layer. This not only occupies a larger area but also leads to higher resistance due to the longer lead length, causing inconsistent signal transmission performance across different layers and impacting semiconductor device performance. Furthermore, because the contact pads are staggered and do not overlap, parasitic capacitance can be reduced. Optionally, a number of contact pads closer to the substrate are placed on the same side of the bit line structure to form a first lead-out structure, while a number of contact pads farther from the substrate are placed on the opposite side to form a second lead-out structure. Placing the first lead-out structure closer to the first stacked structure and the second lead-out structure farther from the second stacked structure balances the overall trace length in the lead-out structure, ensuring similar signal transmission distances for each layer and thus improving semiconductor device performance. Furthermore, the closer the contact pads in the first and / or second lead-out structures are to the substrate in the first direction, and the closer they are to the corresponding first and / or second stacked structures in the third direction, the closer the routing distance of each bit line in the first and second lead-out structures can be. Optionally, in embodiments where odd-numbered layers of contact pads are placed on the same side of the bit line structure to form the first or second lead-out structure, and even-numbered layers of contact pads are placed on the other side of the bit line structure to form the first or second lead-out structure, during the fabrication of the contact pads, the etching depth of the layers corresponding to the gaps between two adjacent holes used to fabricate the contact pads is easier to control when etching the holes. The greater the distance between the contact pads, the less mutual influence during fabrication will cause defects between the contact pads. This can reduce the difficulty of process implementation, increase the process window, and improve product yield.

[0098] Molding the contact pads and contact plugs into a single unit reduces process complexity, makes fabrication easier, and results in higher product yield. There is no contact resistance between the contact pads and contact plugs. Furthermore, using the same material for the bit lines as the contact pads and contact plugs further reduces resistance, thereby lowering the power consumption of the semiconductor device.

[0099] Contact pads and contact plugs together form the lead-out structure, which connects to the sensitive amplifier via the contact plug for bit line signal transmission. In this embodiment, the sensitive amplifier can be placed on another substrate, without occupying the area of ​​the substrate with the stacked structure, thus improving the integration density of the semiconductor device. The sensitive amplifier and the stacked structure are fabricated on different substrates, and their fabrication processes do not affect each other, thus improving product yield. The sensitive amplifier and peripheral circuits such as the sub-word line driver can be jointly disposed on another substrate, saving substrate area and simplifying the fabrication process, thereby improving product yield. Furthermore, because the fabrication processes of the peripheral circuits are similar, but the fabrication processes of the stacked structure differ significantly, fabricating them separately can improve yield and save costs.

[0100] The embodiments or implementation methods described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0101] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A bitline structure is disposed on the substrate along a third direction, the third direction being parallel to the substrate, and the bitline structure includes a first part and a second part arranged along the third direction; A first stacked structure and a second stacked structure are disposed on both sides of the bit line structure and connected to the first part; A first lead-out structure and a second lead-out structure are disposed on both sides of the bit line structure and connected to the second part; the first lead-out structure has a first contact pad that is offset from each other in a first direction and the second lead-out structure has a second contact pad that is offset from each other in a first direction, the first direction intersecting the substrate.

2. The semiconductor device according to claim 1, characterized in that, The first lead-out structure and the second lead-out structure further include a contact plug disposed on the contact pad.

3. The semiconductor device according to claim 2, characterized in that, The contact pad and the contact plug are integrally formed.

4. The semiconductor device according to claim 1, characterized in that, The bit line structure includes multiple bit lines, which are connected to corresponding layers of the first stacked structure and the second stacked structure, and each bit line corresponds to a contact pad.

5. The semiconductor device according to claim 4, characterized in that, The contact pad of the first lead-out structure is connected to the bit line of the odd-numbered layer, and the contact pad of the second lead-out structure is connected to the bit line of the even-numbered layer.

6. The semiconductor device according to claim 4, characterized in that, The bit line structure includes two sets of bit lines. In the first direction, the first set of bit lines is disposed between the second set of bit lines and the substrate. The contact pad of the first lead-out structure is connected to the first set of bit lines, and the contact pad of the second lead-out structure is connected to the second set of bit lines.

7. The semiconductor device according to claim 1, characterized in that, The first stacked structure and / or the second stacked structure have a memory structure, the memory structure including a memory node and a memory transistor, the source and drain of the memory transistor being connected to the bit line structure and the memory node respectively; the gates of the memory transistors corresponding to different layers of the first stacked structure and / or the second stacked structure are connected.

8. The semiconductor device according to claim 7, characterized in that, The bit line structure includes multiple bit lines, and the memory structures of corresponding layers of the first stacked structure and the second stacked structure are connected to the same bit line.

9. The semiconductor device according to claim 7, characterized in that, The semiconductor device further includes a first sub-word line driver connected to the gate of the first stacked structure, and a second sub-word line driver connected to the gate of the second stacked structure.

10. The semiconductor device according to claim 1, characterized in that, The bit line structure has multiple through holes, which are arranged along the third direction and penetrate the bit line structure along the first direction. Insulating material is disposed in the through holes, and the first direction intersects the substrate.

11. A method for manufacturing a semiconductor structure, characterized in that, Provide substrate; An initial stacked structure is formed on the substrate; In the initial stacked structure, a bit line structure is formed along a third direction. The bit line structure includes multiple bit lines stacked along a first direction. The bit lines are correspondingly arranged with respect to the initial stacked structure. The third direction is parallel to the substrate. The first direction intersects the substrate. The bit line structure also includes a first part and a second part. A first stacked structure and a second stacked structure are formed on both sides of the first part, and the corresponding layers of the first stacked structure and the second stacked structure are connected to the same bit line; A first lead-out structure and a second lead-out structure are formed on both sides of the second part. The first lead-out structure and the second lead-out structure include contact pads that are staggered in a first direction. The contact pads are connected to the bit lines one by one. The step of forming the contact pad includes: forming an opening in the initial stacked structure to expose the corresponding layer, etching the corresponding layer to the position of the corresponding bit line, and depositing a contact pad at the bottom of the hole.

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