Forming method of memory and memory
By using deuterium annealing and porous structure design in phase change memory, the problem of controlling hydrogen diffusion in phase change memory was solved, thereby improving the stability and reliability of the memory and extending its service life.
Patent Information
- Application Number
- CN202511015820.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-23
- Publication Date
- 2025-11-28
AI Technical Summary
In the existing technology, hydrogen annealing treatment makes it difficult to precisely control the release and retention of hydrogen in phase change memory, which leads to the inability to effectively guarantee the working performance of the memory.
During the formation of the memory, deuterium gas is used to anneal the first and second dielectric layers with different hydrogen contents. The diffusion of hydrogen is controlled by forming a porous first dielectric layer. Combined with the design of dielectric layers with different densities, a "hydrogen storage-hydrogen barrier" structure is formed to achieve directional diffusion and stable release of hydrogen.
It improves the stability and reliability of the memory, extends the memory's lifespan, and mitigates interface defects and material degradation issues.
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Figure CN121038291A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, and particularly relates to a forming method of a memory and the memory. BACKGROUND
[0002] Phase change memory (PCM) is a kind of memory which realizes data storage by using reversible transformation between crystalline state and amorphous state of specific phase change material. The atomic structure of the phase change layer is constantly reorganized due to the transformation between crystalline state and amorphous state, which leads to the deterioration of microstructure, the appearance of dangling bonds and vacancy defects in the crystal lattice, and further affects the durability and reliability of the phase change memory.
[0003] In the related art, hydrogen annealing treatment can be used to repair dangling bonds to improve the working performance of the phase change memory. However, due to the high migration of hydrogen in the medium material, the release and retention of hydrogen in the annealing process are difficult to accurately control, so even if hydrogen annealing treatment is used, the working performance of the phase change memory cannot be guaranteed. SUMMARY
[0004] In view of the above defects of the prior art, the technical problem to be solved by the present application is how to improve the control ability of hydrogen diffusion to improve the working reliability and stability of the memory.
[0005] In order to solve at least one of the above technical problems, the present application discloses a forming method of a memory and the memory.
[0006] According to an aspect of the present application, a forming method of a memory is provided, comprising:
[0007] providing a substrate;
[0008] forming a device layer on the substrate, the device layer comprising a memory cell;
[0009] forming a first dielectric layer and a second dielectric layer on a side of the device layer away from the substrate, the second dielectric layer being on a side of the first dielectric layer away from the device layer, the hydrogen content of the first dielectric layer being greater than that of the second dielectric layer;
[0010] performing annealing treatment on the first dielectric layer and the second dielectric layer, the gas of the annealing treatment comprising deuterium;
[0011] after the annealing treatment, forming a first plug penetrating through the second dielectric layer, the first dielectric layer and the device layer.
[0012] Optionally, forming the first dielectric layer and the second dielectric layer on the side of the device layer away from the substrate comprises:
[0013] The first deposition process is used to form a first dielectric layer on a side of the device layer away from the substrate; the process gas of the first deposition process comprises a first forming material and a first auxiliary gas;
[0014] The second deposition process is used to form a second dielectric layer on a side of the first dielectric layer away from the device layer; the process gas of the second deposition process comprises a second forming material and a second auxiliary gas;
[0015] The liquid flow rate of the first forming material is greater than the liquid flow rate of the second forming material, the gas flow rate of the first auxiliary gas is equal to the gas flow rate of the second auxiliary gas, and the density of the second dielectric layer is greater than the density of the first dielectric layer.
[0016] Optionally, the liquid flow rate of the first forming material ranges from 2000 mg / min to 6000 mg / min, and the liquid flow rate of the second forming material ranges from 500 mg / min to 1500 mg / min.
[0017] Optionally, the first dielectric layer and the second dielectric layer are subjected to an annealing process, which comprises:
[0018] The first dielectric layer and the second dielectric layer are subjected to an annealing process using deuterium gas, so that the first dielectric layer after the annealing process has a porous structure.
[0019] Optionally, after the first plug is formed, the method comprises:
[0020] A pad is formed, the pad being located at an end of the first plug away from the substrate;
[0021] A protective layer is formed on the end of the first plug away from the substrate, the protective layer being located on the surface of the pad and the second dielectric layer;
[0022] A first barrier layer is formed on a side of the protective layer away from the substrate;
[0023] An opening is formed, the opening penetrating through the first barrier layer and the protective layer so that the pad is exposed in the opening.
[0024] Optionally, the thickness of the first barrier layer ranges from 700 nm to 2000 nm.
[0025] According to a second aspect of the present application, a memory is provided, comprising:
[0026] a substrate;
[0027] a device layer located on a side of the substrate and comprising a memory cell;
[0028] a first dielectric layer and a second dielectric layer; the first dielectric layer is located on a side of the device layer away from the substrate, and the second dielectric layer is located on a side of the first dielectric layer away from the substrate; the hydrogen content of the first dielectric layer is greater than the hydrogen content of the second dielectric layer.
[0029] The first plug penetrates the second dielectric layer, the first dielectric layer and the device layer.
[0030] Optionally, the density of the second dielectric layer is greater than the density of the first dielectric layer.
[0031] Optionally, the first dielectric layer has a porous structure.
[0032] Optionally, the device layer comprises a device structure, an electrical interconnection structure, and a third dielectric layer surrounding the device structure and the electrical interconnection structure, and the device structure comprises a memory cell.
[0033] Optionally, the first plug is electrically connected to the device structure.
[0034] Optionally, the memory further comprises:
[0035] a pad located at an end of the first plug away from the substrate;
[0036] a protective layer located on the surface of the pad and the surface of the second dielectric layer;
[0037] a first barrier layer located at a side of the protective layer away from the substrate, and the thickness of the first barrier layer ranges from 700 nm to 2000 nm;
[0038] an opening penetrating the first barrier layer and the protective layer so that the pad is exposed in the opening.
[0039] The disclosed memory forming method can improve the working performance of the memory by using the annealing process, and improve the control ability of hydrogen diffusion, improve the interface defects or material deterioration caused by hydrogen, and thus improve the stability and reliability of the memory.
[0040] Other features and advantages of the present application will be described in detail in the following detailed description of the embodiments. BRIEF DESCRIPTION OF DRAWINGS
[0041] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.
[0042] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.
[0043] Figure 1 A flow chart of a method for forming a memory according to an example embodiment of the present application is shown in FIG. 8.
[0044] Figure 2 A structure of a device layer of a memory according to an example embodiment of the present application is shown in FIG. 9.
[0045] Figure 3 A structure of a memory cell according to an example embodiment of the present application is shown in FIG. 10.
[0046] Figure 4 A structure of a first plug according to an example embodiment of the present application is shown in FIG. 11. Figure 1
[0047] Figure 5 A structure of a first plug according to an example embodiment of the present application is shown in FIG. 12. Figure 2
[0048] Figure 6 A structure of a pad of a memory according to an example embodiment of the present application is shown in FIG. 13.
[0049] Figure 7 A structure of a memory according to an example embodiment of the present application is shown in FIG. 14.
[0050] Figure 8 A comparison of hydrogen release characteristics according to an example embodiment of the present application is shown in FIG. 15.
[0051] Legend of reference numerals:
[0052] 10 - substrate;
[0053] 20 - device layer, 21 - device structure, 22 - memory cell, 23 - electrical interconnection structure, 24 - conductive layer, 25 - second barrier layer, 26 - second plug, 27 - third dielectric layer;
[0054] 30 - first dielectric layer, 31 - second dielectric layer;
[0055] 40 - first plug, 41 - via;
[0056] 50 - pad;
[0057] 60 - protective layer, 61 - first barrier layer, 62 - opening;
[0058] 70 - first electrode, 71 - gating layer, 72 - second electrode, 73 - phase change storage layer, 74 - third electrode. DETAILED DESCRIPTION
[0059] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of them. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this application.
[0060] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such as a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.
[0061] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.
[0062] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.
[0063] In this document, the term "and / or" describes a relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.
[0064] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed description. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.
[0065] Figure 1A flowchart illustrating the method for forming a memory as provided in an exemplary embodiment of this application. For example... Figure 1 As shown, a method for forming a memory includes:
[0066] Step S1: Provide substrate 10.
[0067] In some embodiments, the substrate 10 may be made of silicon. The substrate 10 provides mechanical support for subsequent layers, ensuring structural stability during memory fabrication.
[0068] Step S2: A device layer 20 is formed on the substrate 10, the device layer 20 including memory cells 22.
[0069] In some embodiments, device layer 20 includes device structure 21, electrical interconnect structure 23, and a third dielectric layer 27 surrounding device structure 21 and electrical interconnect structure 23. Device structure 21 includes memory cell 22, and electrical interconnect structure 23 includes a conductive layer 24, a second barrier layer 25, and a second plug 26 located within the third dielectric layer 27.
[0070] In some embodiments, the TEOS layer (Tetraethyl Orthosilicate) can be divided into multiple dielectric layers, such as a third dielectric layer 27. Each dielectric layer is made of the same material, specifically silicon dioxide generated during the decomposition of TEOS in chemical vapor deposition. That is, the dielectric layer material can be silicon dioxide generated during the decomposition of TEOS in chemical vapor deposition. The different dielectric layers in the memory serve different purposes, and there are differences in hydrogen content, material density, etc., between at least two dielectric layers. The third dielectric layer 27 serves as both an electrical insulation layer and a structural support layer. During the formation of the memory, it is used to cover and separate the various structures of the device layer 20, such as separating the electrical interconnect structure 23 and the device structure 21, to prevent electrical signal crosstalk. It can also be used to protect the various structures of the device layer 20.
[0071] In device layer 20, the third dielectric layer 27 can be divided into multiple parts by the layer structure. For example... Figure 2 As shown, a partial third dielectric layer 27 is formed on one side of the substrate 10. The partial third dielectric layer 27 is patterned to obtain multiple trenches, and a conductive material corresponding to the conductive layer 24 is deposited inside the trenches to form the conductive layer 24. The conductive material corresponding to the conductive layer 24 can be a metal, such as copper. The surface of the conductive layer 24 away from the substrate 10 is flush with the surface of the partial third dielectric layer 27 away from the substrate 10. The conductive layer 24 performs electrical signal transmission functions, used to realize electrical connections between layers and devices, and to realize the transmission of electrical signals between external circuits and signals from the memory cell 22.
[0072] A second barrier layer 25 is formed on the side of the conductive layer 24 away from the substrate 10. The second barrier layer 25 covers the conductive layer 24 and part of the surface of the third dielectric layer 27. The material of the second barrier layer 25 may be silicon nitride, which is used to constrain the conductive layer 24 and prevent the conductive layer 24 from diffusing, so as to ensure the reliability of the electrical interconnect structure 23.
[0073] A portion of a third dielectric layer 27 is formed on the side of the second barrier layer 25 away from the substrate 10, and a plurality of memory cells 22 and a second plug 26 are formed thereon. The portion of the third dielectric layer 27 is formed on the side of the second plug 26 and the plurality of memory cells 22 away from the substrate 10, such that the plurality of memory cells 22 and the second plug 26 are covered by the third dielectric layer 27. The second plug 26 penetrates the second barrier layer 25 and is connected to the conductive layer 24. The material of the second plug 26 can be a metal, such as tungsten, used to achieve electrical connection between the memory cells 22 and the conductive layer 24. The memory cells 22 are located on the side of the conductive layer 24 away from the substrate 10 and are electrically connected to the conductive layer 24, so that the conductive layer 24 enables signal transmission between the memory cells 22 and external circuitry.
[0074] like Figure 3 As shown, the storage unit 22 may include a first electrode 70, a gate layer 71, a second electrode 72, a phase change storage layer 73 and a third electrode 74 stacked in sequence.
[0075] In some embodiments, the memory may be a phase-change memory. Phase-change memories typically employ a cross-array architecture of three-dimensional stacked memory cells 22, such as two-layer, four-layer, or eight-layer stacks.
[0076] Taking a two-layer stacked phase-change memory as an example, the phase-change memory includes multiple memory cells 22. Each memory cell 22 may include a first electrode 70, a gate layer 71, a second electrode 72, a phase-change storage layer 73, and a third electrode 74, which are stacked sequentially along a direction perpendicular to the surface of the substrate 10. Two memory cells 22 in the same group share the same word line, and the top bit line and the bottom bit line are respectively arranged on both sides of the group of memory cells 22.
[0077] Step S3: A first dielectric layer 30 and a second dielectric layer 31 are formed on the side of device layer 20 away from substrate 10. The second dielectric layer 31 is located on the side of first dielectric layer 30 away from device layer 20. The hydrogen content of the first dielectric layer 30 is greater than the hydrogen content of the second dielectric layer 31. The density of the second dielectric layer 31 is greater than the density of the first dielectric layer 30.
[0078] In some embodiments, the first dielectric layer 30 and the second dielectric layer 31 are also components of the TEOS layer, both formed by TEOS deposition. Specifically, a first deposition process is used to form the first dielectric layer 30 on the side of the device layer 20 away from the substrate 10; the process gas for the first deposition process includes a first forming material and a first auxiliary gas. A second deposition process is used to form the second dielectric layer 31 on the side of the first dielectric layer 30 away from the device layer 20; the process gas for the second deposition process includes a second forming material and a second auxiliary gas. The liquid flow rate of the first forming material can be set to be greater than the liquid flow rate of the second forming material.
[0079] Both the first and second forming materials can be TEOS liquid. By adjusting the flow rate of the TEOS liquid, the first dielectric layer 30 has a high hydrogen content, forming a "hydrogen storage" structure. The flow rate of the first forming material can be from 2000 mg / min to 6000 mg / min. The flow rate of the second forming material can be from 500 mg / min to 1500 mg / min.
[0080] Both the first and second auxiliary gases can be O2. During deposition, the flow rate of the first auxiliary gas can be between 5000 sccm and 13000 sccm, and the flow rate of the second auxiliary gas can also be between 5000 sccm and 13000 sccm. The flow rates of the first and second auxiliary gases can be approximately equal.
[0081] Since the density of the second dielectric layer 31 is greater than that of the second dielectric layer 32, the second dielectric layer 31 can act as a slow-release barrier to limit the diffusion of hydrogen ions, thereby achieving a long-term and stable hydrogen supply to the storage cell 22 and avoiding interference with the performance of other layers due to hydrogen diffusion.
[0082] A first dielectric layer 30 with a high hydrogen content and a second dielectric layer 31 with a low hydrogen content are sequentially formed on the device layer 20. This can form a "hydrogen storage-hydrogen barrier" structure, which is beneficial for achieving directional diffusion of hydrogen during the annealing process. This allows hydrogen to concentrate on the defect passivation of the device layer 20 and its adjacent areas, thereby improving the interface repair efficiency.
[0083] Meanwhile, the first dielectric layer 30 and the second dielectric layer 31 are made of the same material, achieving functional differentiation of "hydrogen storage-hydrogen barrier" within the same material system. Under the condition of achieving accurate hydrogen control, stress defects caused by heterogeneous interfaces can be avoided.
[0084] Step S4: Anneal the first dielectric layer 30 and the second dielectric layer 31. The annealing gas includes deuterium. After annealing, the first dielectric layer 30 has a porous structure.
[0085] In some embodiments, after the deuterium annealing treatment, the structure of the second dielectric layer 31 remains unchanged, while the first dielectric layer 30 may have a porous structure. The porous structure can increase the surface area of the first dielectric layer 30, which is beneficial for hydrogen to reach the storage unit 22 through diffusion channels, making it easier for hydrogen to be released into the storage unit 22, thereby achieving rapid hydrogen supply and repairing defects in the phase change material.
[0086] Annealing with deuterium gas offers several advantages. Because deuterium forms more stable chemical bonds with the material, it reduces hydrogen migration activity and prolongs hydrogen residence time compared to hydrogen annealing, thus improving the repair effect. Furthermore, deuterium annealing maintains passivation over longer periods without increasing the annealing temperature, significantly suppressing bond breakage and defect recurrence caused by high temperatures or stress, thereby improving the memory's cycle stability and data retention capabilities.
[0087] Step S5: After annealing, a first plug 40 is formed that penetrates the second dielectric layer 31, the first dielectric layer 30, and the device layer 20. The first plug 40 is electrically connected to the device structure 21.
[0088] The method of forming the first plug 40 includes:
[0089] A via 41 is formed in the second dielectric layer 31, the first dielectric layer 30 and the device layer 20 to expose the conductive layer 24;
[0090] The through hole 41 is filled with conductive material to form the first plug 40.
[0091] In some embodiments, such as Figure 4 As shown, after determining the position of the first plug 40, a through-hole 41 is formed at its position within the second barrier layer 25, which is located within the second dielectric layer 31, the first dielectric layer 30, and the device layer 20, and exposes the conductive layer 24. Further, as... Figure 5 As shown, conductive material is filled inside the through-hole 41 to form a first plug 40. The conductive material can be tungsten. The first plug 40 penetrates the second dielectric layer 31, the first dielectric layer 30, and the second barrier layer 25, and is connected to the conductive layer 24. Simultaneously, the first plug 40 is electrically connected to the storage cell 22.
[0092] The first plug 40 is fabricated after annealing, which allows the first plug 40 to form in a material-stable environment, thus helping to improve the contact reliability and conductivity between the first plug 40 and the conductive layer 24.
[0093] Step S6: Form pad 50, which is located at the end of the first plug 40 away from the conductive layer 24.
[0094] In some embodiments, such as Figure 5As shown, a pad 50 is formed at the end of the first plug 40 away from the conductive layer 24. The material of the pad 50 can be metal, such as aluminum. The pad 50 is used to connect leads to enable signal transmission between external circuitry and the memory cell 22.
[0095] Step S7: A protective layer 60 is formed at the end of the first plug 40 away from the substrate 10. The protective layer 60 is located on the surface of the pad 50 and the second dielectric layer 31.
[0096] Step S8: A first barrier layer 61 is formed on the side of the protective layer 60 away from the substrate 10. The thickness of the first barrier layer 61 ranges from 700 nm to 2000 nm.
[0097] Step S9: Form an opening 62 that penetrates the first barrier layer 61 and the protective layer 60, so that the pad 50 is exposed in the opening 62.
[0098] In some embodiments, the protective layer 60 is also part of the TEOS layer, and its material is the same as that of the first dielectric layer 30, the second dielectric layer 31, and the third dielectric layer 27. During the memory fabrication process, after the pads 50 are formed, as... Figure 6 As shown, a protective layer 60 is formed on the surface of the second dielectric layer 31 away from the substrate 10 and covers the pad 50. The protective layer 60 is used to protect the device, for example, to protect the first plug 40 from external environmental interference.
[0099] Furthermore, a first barrier layer 61 is formed on the surface of the protective layer 60 away from the substrate 10. The first barrier layer 61 can be made of silicon oxynitride, and the ratio of silicon, oxygen, and nitrogen can be adjusted according to different memory fabrication processes. The hardness of the first barrier layer 61 is greater than that of the protective layer 60, which can further protect the device from external environmental interference. In addition, the thickness of the first barrier layer 61 can be 70nm to 2000nm, and the increased thickness of the first barrier layer 61 can further prevent hydrogen diffusion.
[0100] In some embodiments, after the protective layer 60 and the first barrier layer 61 are formed, at the corresponding positions of the pads 50, such as Figure 7 As shown, an opening 62 is formed that penetrates the protective layer 60 and the first barrier layer 61, so that the pad 50 is exposed from the opening 62.
[0101] Figure 8 It can be the detection result obtained by using a residual gas analyzer to detect hydrogen-containing gases released from different layers. Figure 8The horizontal axis represents time, reflecting the sequence of gas release at different stages, while the vertical axis represents gas signal intensity, indicating the concentration or release amount of a specific gas. The leftmost dark blue curve represents a TEOS mixed layer containing SiON; the red curve represents a silicon nitride layer; the blue curve represents a TEOS layer at different temperatures; the pink curve represents a silicon oxynitride layer; and the gray curve represents the substrate layer.
[0102] according to Figure 8 As can be seen, in the silicon oxynitride layer corresponding to the pink curve, the nitrogen-hydrogen ratio is larger, and the atomic radius of nitrogen is larger than that of oxygen, resulting in a more stable structure. Hydrogen release requires higher energy, and the high density inhibits hydrogen diffusion. In the TEOS layer corresponding to the blue curve, the high hydroxyl content makes it more prone to breakage, resulting in a more porous structure that promotes hydrogen diffusion and release.
[0103] In this embodiment, by sequentially forming a first dielectric layer 30 and a second dielectric layer 31 with different hydrogen contents on the device layer 20, and performing deuterium annealing on the first dielectric layer 30 and the second dielectric layer 31 before forming the first plug 40, the annealing process improves the memory's working performance, enhances the control capability of hydrogen diffusion, and improves interface defects or material degradation caused by hydrogen, thereby improving the stability and reliability of the memory.
[0104] The thickness setting of the first barrier layer 61, the difference in hydrogen content and density between the first dielectric layer 30 and the second dielectric layer 31, and the deuterium annealing treatment work together to ensure continuous and efficient repair of the memory cell 22 by hydrogen, thereby extending the lifespan of the memory and improving device stability and reliability. Furthermore, the formation steps of each layer can all be performed using PECVD (Plasma-Enhanced Chemical Vapor Deposition) and standard annealing equipment, requiring no additional masks or photolithography, thus exhibiting good process compatibility.
[0105] Accordingly, this application also discloses a memory, formed based on the memory formation method in any of the above embodiments. Figure 7 As shown, the memory includes:
[0106] Substrate 10;
[0107] Device layer 20 is located on one side of substrate 10 and includes memory cell 22;
[0108] A first dielectric layer 30 and a second dielectric layer 31; the first dielectric layer 30 is located on the side of the device layer 20 away from the substrate 10, and the second dielectric layer 31 is located on the side of the first dielectric layer 30 away from the substrate 10; the hydrogen content of the first dielectric layer 30 is greater than the hydrogen content of the second dielectric layer 31.
[0109] The first plug 40 penetrates the second dielectric layer 31, the first dielectric layer 30, and the device layer 20.
[0110] In some embodiments, device layer 20 includes device structure 21, electrical interconnect structure 23, and a third dielectric layer 27 surrounding device structure 21 and electrical interconnect structure 23. Device structure 21 includes memory cell 22, and electrical interconnect structure 23 includes a conductive layer 24, a second barrier layer 25, and a second plug 26 located within the third dielectric layer 27.
[0111] In some embodiments, the density of the second dielectric layer 31 is greater than the density of the first dielectric layer 30. Furthermore, the first dielectric layer 30 has a porous structure after deuterium annealing.
[0112] In some embodiments, the first plug 40 penetrates the second dielectric layer 31, the first dielectric layer 30, and the second barrier layer 25 of the device layer 20, and one end near the substrate 10 is connected to the conductive layer 24 of the device layer 20.
[0113] like Figure 7 As shown, the other end of the first plug 40 also has a solder pad 50. Furthermore, a protective layer 60 and a first barrier layer 61 are sequentially disposed on the surface of the second dielectric layer 31. The solder pad 50 is exposed from an opening 62 penetrating the protective layer 60 and the first barrier layer 61.
[0114] The memory obtained by the above-described method has a good service life and working performance because hydrogen can be stably and continuously released into the storage unit 22.
[0115] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0116] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0117] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.
[0118] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent variations, or alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application. The terminology used herein is chosen to best explain the principles, practical applications, or technical improvements to the market of the various embodiments, or to enable other persons skilled in the art to understand the various embodiments disclosed herein.
Claims
1. A method for forming a memory, characterized in that, The method includes: Provide substrate; A device layer is formed on the substrate, the device layer including memory cells; A first dielectric layer and a second dielectric layer are formed on the side of the device layer away from the substrate. The second dielectric layer is located on the side of the first dielectric layer away from the device layer. The hydrogen content of the first dielectric layer is greater than the hydrogen content of the second dielectric layer. Annealing is performed on the first dielectric layer and the second dielectric layer; After the annealing process, a first plug is formed that penetrates the second dielectric layer, the first dielectric layer, and the device layer.
2. The method for forming a memory according to claim 1, characterized in that, The formation of the first dielectric layer and the second dielectric layer on the side of the device layer away from the substrate includes: A first deposition process is used to form the first dielectric layer on the side of the device layer away from the substrate; the process gas of the first deposition process includes a first forming material and a first auxiliary gas. A second deposition process is used to form a second dielectric layer on the side of the first dielectric layer away from the device layer; the process gas of the second deposition process includes a second forming material and a second auxiliary gas. The liquid flow rate of the first forming material is greater than the liquid flow rate of the second forming material, the gas flow rate of the first auxiliary gas is equal to the gas flow rate of the second auxiliary gas, and the density of the second medium layer is greater than the density of the first medium layer.
3. The method for forming a memory according to claim 2, characterized in that, The liquid flow rate of the first forming material ranges from 2000 mg / min to 6000 mg / min, and the liquid flow rate of the second forming material ranges from 500 mg / min to 1500 mg / min.
4. The method for forming a memory according to claim 1, characterized in that, Annealing the first dielectric layer and the second dielectric layer includes: The first dielectric layer and the second dielectric layer are annealed with deuterium gas to give the first dielectric layer a porous structure after annealing.
5. The method for forming a memory according to claim 1, characterized in that, After the first plug is formed, the method includes: A pad is formed at the end of the first plug that is away from the substrate; A protective layer is formed at the end of the first plug away from the substrate, the protective layer being located on the surface of the pad and the surface of the second dielectric layer; A first barrier layer is formed on the side of the protective layer away from the substrate; An opening is formed that penetrates the first barrier layer and the protective layer, so that the pads are exposed in the opening.
6. A memory formed using the memory formation method according to any one of claims 1 to 5, characterized in that, include: Substrate; A device layer, located on one side of the substrate, includes memory cells; First dielectric layer and second dielectric layer; The first dielectric layer is located on the side of the device layer away from the substrate, and the second dielectric layer is located on the side of the first dielectric layer away from the substrate; the hydrogen content of the first dielectric layer is greater than the hydrogen content of the second dielectric layer; A first plug penetrates the second dielectric layer, the first dielectric layer, and the device layer.
7. The memory according to claim 6, characterized in that, The density of the second dielectric layer is greater than the density of the first dielectric layer.
8. The memory according to claim 6, characterized in that, The first dielectric layer has a porous structure.
9. The memory according to claim 6, characterized in that, The device layer includes a device structure, an electrical interconnect structure, and a third dielectric layer surrounding the device structure and the electrical interconnect structure, wherein the device structure includes the memory cell; The first plug is electrically connected to the device structure.
10. The memory according to claim 6, characterized in that, The memory also includes: The pad is located at the end of the first plug furthest from the substrate; A protective layer is located on the surface of the pads and the surface of the second dielectric layer; A first barrier layer is located on the side of the protective layer away from the substrate, and the thickness of the first barrier layer ranges from 700 nm to 2000 nm. An opening is provided that extends through the first barrier layer and the protective layer, so that the pads are exposed within the opening.