Semiconductor device with mim capacitor and method of making the same

Abstract

The application discloses a semiconductor device with MIM capacitor and a manufacturing method thereof. The manufacturing method comprises the following steps: providing an intermetal dielectric layer; forming an intermediate dielectric layer on the intermetal dielectric layer; forming a metal layer on the intermediate dielectric layer and the intermetal dielectric layer; grinding the metal layer until the surface of the metal layer is flat and the intermediate dielectric layer is exposed; etching the metal layer at a position with a certain distance from the intermediate dielectric layer, forming an upper plate and a lower plate of the MIM capacitor on both sides of the intermediate dielectric layer, and isolating the MIM capacitor area and the non-MIM capacitor area. The semiconductor device with the MIM capacitor formed by the application has good performance and high reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and more particularly to a semiconductor device with MIM capacitors and a method for manufacturing the same. Background Technology

[0002] MIM (Metal-Insulator-Metal) capacitors are currently widely used in display drivers. Existing manufacturing processes for products with MIM structures involve first fabricating the MIM structure itself. For example... Figure 1 As shown, the MIM structure is a stacked structure, consisting of an upper metal electrode, an intermediate dielectric layer, and a lower metal electrode from top to bottom. After fabricating the MIM structure, the lower metal electrode is etched to isolate the MIM capacitor region from the non-MIM capacitor region. However, during the etching process, inaccurate control of the etching time often leads to incomplete etching of the lower electrode, resulting in a short circuit, or over-etching of the upper electrode, causing a top loss. This affects the electrical parameters of the device, further impacting product yield. Furthermore, to avoid these issues during etching, the etching time needs to be continuously optimized based on the specific product, increasing the manufacturing complexity. Summary of the Invention

[0003] The main objective of this invention is to provide a semiconductor device with MIM capacitors and its fabrication method, which eliminates the need for additional photomask costs and effectively avoids the short circuit of the lower electrode and TIN loss of the upper electrode caused by existing MIM structure fabrication processes, thereby improving product reliability.

[0004] The technical solution adopted in this invention is:

[0005] A method for fabricating a semiconductor device with MIM capacitors is provided, comprising the following steps:

[0006] Provide an intermetallic dielectric layer;

[0007] An intermediate dielectric layer is formed on the intermetallic dielectric layer;

[0008] A metal layer is formed on the intermediate dielectric layer and the intermetallic dielectric layer;

[0009] Grind the metal layer until its surface is flat and the intermediate dielectric layer is exposed;

[0010] At a certain distance from the intermediate dielectric layer, a metal layer is etched to form the upper and lower plates of the MIM capacitor on both sides of the intermediate dielectric layer, while simultaneously isolating the MIM capacitor region and the non-MIM capacitor region.

[0011] According to the above technical solution, the step of forming the intermediate dielectric layer includes: covering an insulating layer on the intermetallic dielectric layer; forming a first mask layer covering the insulating layer; using the first mask layer as a mask, etching the insulating layer to form the intermediate dielectric layer of the MIM capacitor; and removing the first mask layer.

[0012] Following the above technical solution, it further includes: forming a barrier layer located above the intermediate dielectric layer and the intermetallic dielectric layer and below the metal layer, the barrier layer being used to enhance the adhesion between the metal layer and the underlying material.

[0013] According to the above technical solution, the steps of forming the upper and lower plates and isolating the non-MIM capacitor region include: forming a second mask layer covering the polished intermediate dielectric layer and the metal layer; using the second mask layer as a mask, etching the metal layer to form the upper and lower plates on both sides of the intermediate dielectric layer and isolate the non-MIM capacitor region; and removing the second mask layer.

[0014] Following the above technical solution, it also includes:

[0015] After isolating the non-MIM capacitor region, an isolation layer is formed that covers both the MIM capacitor region and the non-MIM capacitor region.

[0016] Conductive pillars for the upper and lower plates of the MIM capacitor and conductive pillars for the non-MIM capacitor region are fabricated on the isolation layer, with each conductive pillar connected to the metal layer of the corresponding region.

[0017] According to the above technical solution, the material of the metal layer includes titanium nitride (TIN) or copper-aluminum alloy.

[0018] Following the above technical solution, the material of the barrier layer includes titanium nitride (TIN) or a titanium layer.

[0019] The present invention also provides a semiconductor device having a MIM capacitor, comprising:

[0020] Intermetallic dielectric layer;

[0021] The MIM capacitor region and the non-MIM capacitor region are located on the intermetallic dielectric layer, wherein the MIM capacitor includes the intermediate dielectric layer and the upper and lower electrodes on both sides, and the non-MIM capacitor region is formed by isolating during the etching of the upper and lower electrodes.

[0022] The above technical solution further includes: an isolation layer covering the MIM capacitor region and the non-MIM capacitor region, and the isolation layer is provided with conductive pillars for the MIM capacitor region and the non-MIM capacitor region.

[0023] The beneficial effects of this invention are as follows: This invention ingeniously designs the metal layers of the upper and lower plates of the MIM capacitor region and the electrode layers of the non-MIM region on the same layer with the same height. An unexpected effect is that the non-MIM region can be isolated at the same time as the metal layer is etched to form the upper and lower plates. Therefore, the upper plate of the MIM capacitor is less affected during the isolation operation. Even if the etching time is not optimized, there will be no top loss of the upper plate or short circuit of the lower plate, thus improving the reliability of the product.

[0024] Furthermore, the present invention only requires two etching processes when fabricating the MIM capacitor and isolating the non-MIM capacitor area, and a photomask is required for both etching processes. In contrast, the prior art also requires the use of a photomask during two photolithography processes. Therefore, the improved fabrication process of the present invention does not require additional photomask costs.

[0025] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic cross-sectional view of a semiconductor device with MIM capacitors fabricated using existing technology.

[0028] Figure 2 This is a flowchart illustrating the fabrication method of a semiconductor device with MIM capacitors according to an embodiment of the present invention.

[0029] Figures 3-10 This is a cross-sectional structural diagram of a semiconductor device with MIM capacitors during the fabrication process according to an embodiment of the present invention.

[0030] In the figure: 101, intermetallic dielectric layer; 102, insulating layer; 1021, intermediate dielectric layer; 1022, upper electrode; 1023, lower electrode; 103, barrier layer; 104, metal layer; M, photoresist layer; 105, isolation layer; 106, conductive pillar. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0032] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0033] In this invention, it should also be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0034] The present invention provides a method for fabricating a semiconductor device with a MIM capacitor, such as... Figure 2 , Figure 4 , Figure 5 , Figure 6 , Figure 8 As shown, the main steps include:

[0035] S1. Provide an intermetallic dielectric layer 101;

[0036] S2. An intermediate dielectric layer 1021 is formed on the intermetallic dielectric layer 101;

[0037] S3. A metal layer 104 is formed on the intermediate dielectric layer 1021 and the intermetallic dielectric layer 101;

[0038] S4. Grind the metal layer 104 until its surface is flat and the intermediate dielectric layer 1021 is exposed;

[0039] S5. At a certain distance from the intermediate dielectric layer 1021, the metal layer 104 is etched to form the upper electrode 1022 and the lower electrode 1023 of the MIM capacitor on both sides of the intermediate dielectric layer 1021, while simultaneously isolating the MIM capacitor region and the non-MIM capacitor region.

[0040] Please refer to Figures 3-10 The diagram shows a schematic cross-sectional view of the main structure during the fabrication process of a semiconductor device with MIM capacitors according to an embodiment of the present invention.

[0041] Please refer to Figure 3An inter-metal dielectric layer 101 (IMD) is provided, which serves as a dielectric between different metal interconnects located within the same metal layer 104, ensuring that each interconnect structure is independent and preventing crosstalk. In this embodiment of the invention, both the MIM capacitor region and the non-MIM capacitor region are fabricated on this IMD, and the material of the inter-metal dielectric layer 101 is generally silicon dioxide.

[0042] Step S2 specifically involves covering the intermetallic dielectric layer 101 with a dielectric layer, which is an insulating layer 102, and its material can be SiN. This dielectric layer forms the intermediate dielectric layer 1021 of the MIM capacitor. Figure 3 , Figure 4 As shown, the steps for forming the intermediate dielectric layer 1021 include: covering an insulating layer 102 on the intermetallic dielectric layer 101, the insulating layer 102 being formed by chemical deposition; forming a photoresist layer M covering the surface of the insulating layer 102; defining the position and size of the intermediate dielectric layer 1021 using a photomask; and transferring the pattern on the photomask to the photoresist layer M by exposure; using the photoresist layer M as a mask, etching the insulating layer 102 to form the intermediate dielectric layer 1021 of the MIM capacitor; and removing the photoresist layer M after the intermediate dielectric layer 1021 is formed.

[0043] like Figure 5 As shown, step S3 specifically involves forming a metal layer 104 on the intermediate dielectric layer 1021 and the intermetallic dielectric layer 101. This metal layer 104 is subsequently used to fabricate the upper electrode 1022 and lower electrode 1023 of the MIM capacitor, as well as the electrode layer in the non-MIM capacitor region. The material of the metal layer 104 is titanium nitride (TiN) or a copper-aluminum alloy. In this embodiment, the metal layer 104 is a copper-aluminum alloy (AlCu) and is formed using a sputtering process.

[0044] To enhance the adhesion between the metal layer 104 and the underlying material, such as Figure 5 As shown, the method further includes the step of forming a barrier layer 103 located above the intermediate dielectric layer 1021 and the intermetallic dielectric layer 101, and below the metal layer 104. The barrier layer 103 is made of titanium nitride (TIN) or a titanium layer; in this embodiment, titanium nitride (TIN) is used. The barrier layer 103 also prevents the metal layer 104 from migrating into the intermediate dielectric layer 1021 and the intermetallic dielectric layer 101, thus preventing leakage.

[0045] like Figure 6 As shown, in step S4, the surface of the metal layer 104 is flattened and the intermediate dielectric layer 1021 (SiN) is exposed by chemical mechanical polishing (CMP, Chemical Mechanical Polishing or Chemical Mechanical Planarization).

[0046] like Figure 7 , Figure 8 As shown, the next step is step S5: forming the upper and lower electrode plates of the MIM capacitor and isolating the MIM capacitor region and the non-MIM capacitor region. Specifically, a photoresist layer M is formed covering the polished intermediate dielectric layer 1021 and the metal layer 104. The position and size of the upper electrode plate 1022 and the lower electrode plate 1023 are defined by a photomask. Then, the pattern on the photomask is transferred to the photoresist layer M by exposure and development. Using the photoresist layer M as a mask, the metal layer 104 and the barrier layer 103 are etched to form the upper electrode plate 1022 and the lower electrode plate 1023 on both sides of the intermediate dielectric layer 1021, and the non-MIM capacitor region is isolated. Finally, the photoresist layer M is removed. It can be seen that this step integrates the formation of the upper electrode plate 1022 and the lower electrode plate 1023 and the isolation of the non-MIM capacitor region into one, isolating the MIM capacitor region and the non-MIM capacitor region while forming the upper electrode plate 1022 and the lower electrode plate 1023. Since the upper electrode 1022 and the lower electrode 1023 use the same metal layer 104 with the same thickness as the non-MIM capacitor region, the etching time will not be optimized when isolating the non-MIM capacitor region, so the situation of short circuit between the top loss of the upper electrode 1022 and the lower electrode 1023 will not occur.

[0047] Furthermore, after separating the MIM capacitor region and the non-MIM capacitor region, this embodiment also includes the following steps:

[0048] like Figure 9 As shown, an isolation layer 105 is covered in the MIM capacitor region and the non-MIM capacitor region. This isolation layer 105 is mainly used for the subsequent fabrication of the conductive pillars 106. The material of the isolation layer 105 can be silicon oxide, which can be formed by chemical vapor deposition.

[0049] like Figure 10 As shown, conductive pillars 106 for the upper electrode 1022 and lower electrode 1023 of the MIM capacitor, and conductive pillars 106 for the non-MIM capacitor region are respectively fabricated on the isolation layer 105. Each conductive pillar 106 is connected to the metal layer 104 of the corresponding region. The steps for forming the conductive pillars 106 mainly include: forming a mask layer on the surface of the isolation layer 105; defining the size and position of the conductive pillars 106 for the upper electrode 1022 and lower electrode 1023 of the MIM capacitor, as well as the size and position of the conductive pillars 106 for the non-MIM capacitor region on the mask layer; using the mask layer as a mask to etch the isolation layer 105, forming multiple openings, each opening reaching the metal layer 104 of its respective region; and filling the openings with conductive material to form the corresponding conductive pillars 106.

[0050] After the above steps are completed, the semiconductor device with MIM capacitor of this embodiment of the invention is fabricated.

[0051] In summary, by designing the metal layer 104 of the upper and lower electrodes 1023 of the MIM capacitor region and the electrode layer of the non-MIM region on the same layer with the same height, the present invention achieves an unexpected effect: when the metal layer 104 is etched to form the upper electrode 1022 and the lower electrode 1023, the non-MIM region can be isolated simultaneously. The etching time is easy to control, and there will be no situation of top loss of the upper electrode 1022 or short circuit of the lower electrode 1023, thereby improving the reliability of the semiconductor device.

[0052] refer to Figure 10 The present invention also provides a semiconductor device having a MIM capacitor, comprising:

[0053] Intermetallic dielectric layer 101;

[0054] The MIM capacitor region and the non-MIM capacitor region are located on the intermetallic dielectric layer 101, wherein the MIM capacitor includes the intermediate dielectric layer 1021 and the upper electrode 1022 and the lower electrode 1023 on both sides, and the non-MIM capacitor region is formed by isolating during the etching of the upper electrode 1022 and the lower electrode 1023.

[0055] Furthermore, the semiconductor device with MIM capacitors also includes an isolation layer 105 covering the MIM capacitor region and the non-MIM capacitor region, and conductive pillars 106 for the MIM capacitor region and the non-MIM capacitor region are provided within the isolation layer 105. The conductive pillars 106 are made of a highly conductive material, such as copper (Cu) or aluminum (Al).

[0056] In one embodiment of the present invention, in order to enhance the adhesion between the metal layer 104 and the adjacent contact material, a barrier layer 103 is provided between the intermediate dielectric layer 1021 and the upper and lower electrode plates 1023, and a barrier layer 103 is also provided between the upper and lower electrode plates and the bottom metal dielectric layer 101.

[0057] The materials and formation processes of each structure have been described in detail in the above method embodiments, and will not be repeated here.

[0058] In summary, the semiconductor device with MIM capacitor and its fabrication method of the present invention design the metal layer 104 of the upper and lower plates of the MIM capacitor region and the electrode layer of the non-MIM region on the same layer with the same height. An unexpected effect is that the non-MIM region can be isolated while the upper and lower plate metal layers are being etched. Therefore, the upper plate 1022 of the MIM capacitor is less affected during the isolation operation. Even if the etching time is not optimized, there will be no top loss of the upper plate or short circuit of the lower plate. The capacitor performance is good, and the reliability of the product is improved.

[0059] It should be noted that, depending on the implementation needs, the various steps / components described in this application can be broken down into more steps / components, or two or more steps / components or parts of the operation of steps / components can be combined into new steps / components to achieve the purpose of this invention.

[0060] The order of the steps in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0061] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method for fabricating a semiconductor device with MIM capacitors, characterized in that, Includes the following steps: Provide an intermetallic dielectric layer; An intermediate dielectric layer is formed on the intermetallic dielectric layer; A metal layer is formed on the intermediate dielectric layer and the intermetallic dielectric layer; Grind the metal layer until its surface is flat and the intermediate dielectric layer is exposed; At a certain distance from the intermediate dielectric layer, a metal layer is etched to form the upper and lower plates of the MIM capacitor on both sides of the intermediate dielectric layer, while simultaneously isolating the MIM capacitor region and the non-MIM capacitor region. The steps for forming the upper and lower plates and isolating the non-MIM capacitor region include: forming a second mask layer covering the polished intermediate dielectric layer and metal layer; Using the second mask layer as a mask, the metal layer is etched to form an upper electrode and a lower electrode on both sides of the intermediate dielectric layer, and to isolate the non-MIM capacitor region; the second mask layer is then removed.

2. The method for fabricating a semiconductor device with a MIM capacitor according to claim 1, characterized in that, The steps for forming the intermediate dielectric layer include: covering an insulating layer on the intermetallic dielectric layer; forming a first mask layer covering the insulating layer; using the first mask layer as a mask, etching the insulating layer to form the intermediate dielectric layer of the MIM capacitor; and removing the first mask layer.

3. The method for fabricating a semiconductor device with a MIM capacitor according to claim 1, characterized in that, Also includes: A barrier layer is formed above the intermediate dielectric layer and the intermetallic dielectric layer, and below the metal layer. This barrier layer is used to enhance the adhesion between the metal layer and the underlying material.

4. The method for fabricating a semiconductor device with a MIM capacitor according to claim 1, characterized in that, Also includes: After isolating the non-MIM capacitor region, an isolation layer is formed that covers both the MIM capacitor region and the non-MIM capacitor region. Conductive pillars for the upper and lower plates of the MIM capacitor and conductive pillars for the non-MIM capacitor region are fabricated on the isolation layer, with each conductive pillar connected to the metal layer of the corresponding region.

5. The method for fabricating a semiconductor device with a MIM capacitor according to claim 1, characterized in that, The materials for the metal layer include titanium nitride (TIN) or copper-aluminum alloy.

6. The method for fabricating a semiconductor device with a MIM capacitor according to claim 2, characterized in that, The insulating layer material includes silicon nitride (SiN) or silicon oxynitride (SiON).

7. The method for fabricating a semiconductor device with a MIM capacitor according to claim 3, characterized in that, The barrier layer material includes titanium nitride (TIN) or a titanium layer.

8. A semiconductor device with a MIM capacitor, characterized in that, include: Intermetallic dielectric layer; The MIM capacitor region and the non-MIM capacitor region are located on the intermetallic dielectric layer. The MIM capacitor includes the intermediate dielectric layer and the upper and lower electrodes on both sides, and the non-MIM capacitor region is formed by isolating the upper and lower electrodes during etching. The formation of the upper and lower electrodes and the isolation of the non-MIM capacitor region are as follows: a second mask layer is formed to cover the polished intermediate dielectric layer and the metal layer; the metal layer is etched using the second mask layer as a mask to form the upper and lower electrodes on both sides of the intermediate dielectric layer and isolate the non-MIM capacitor region; the second mask layer is removed.

9. The semiconductor device with MIM capacitor according to claim 8, characterized in that, Also includes: An isolation layer is placed over the MIM capacitor region and the non-MIM capacitor region, and conductive pillars for the MIM capacitor region and the non-MIM capacitor region are provided within the isolation layer.

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