A semiconductor device

Abstract

The application discloses a kind of semiconductor devices, belong to semiconductor technical field, the device includes: substrate, source region and drift region are arranged in interval within it;Isolation structure is set in substrate to divide active region, first isolation structure extends from source region towards drift region, second isolation structure is set in drift region, and extend in the orthogonal direction of first isolation structure;Active region includes first boundary and second boundary, first boundary is the boundary of active region and first isolation structure, second boundary is the boundary of active region and second isolation structure, the intersection point of first boundary and second boundary is corner portion;Gate oxide layer is set on active region;Gate electrode is set on gate oxide layer, and gate electrode overlaps with first isolation structure and second isolation structure, gate electrode is set opening portion or shear portion on corner portion.The semiconductor device provided by the application can reduce the thickness of gate oxide layer and reduce the size of semiconductor device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a semiconductor device. Background Technology

[0002] In metal-oxide-semiconductor field-effect transistors (MOSFETs), such as high-voltage MOSFETs (HVMOS), the active area (AA) is defined by a shallow trench isolation (STI) structure, and a gate oxide layer is formed in the active area. The thickness of the gate oxide layer near the edge of the STI is less than the thickness of the gate oxide layer in the remaining areas, making gate oxide layer breakdown and leakage prone to occur at the STI edge. Furthermore, while increasing the thickness of the gate oxide layer at the STI edge can solve this problem, the gate oxide layer in the remaining areas becomes excessively thick, leading to degraded device performance and increased MOSFET size. Moreover, when testing time-dependent dielectric breakdown (TDDB) reliability, it is difficult to sufficiently accelerate the test voltage in flat areas, significantly increasing test time and extending development time. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device that can reduce the thickness of the gate oxide layer in the flat region, prevent breakdown leakage at the edge of the isolation structure, reduce the size of the semiconductor device, and increase and accelerate the test voltage in the dielectric layer breakdown reliability test, thereby shortening the test time.

[0004] To address the aforementioned technical problems, the present invention provides a semiconductor device, comprising:

[0005] A substrate, wherein a source region and a drift region are spaced apart within the substrate;

[0006] An isolation structure is disposed within the substrate to divide the active region, and includes a first isolation structure and a second isolation structure. The first isolation structure extends from the source region toward the drift region, and the second isolation structure is disposed in the drift region and extends in a direction orthogonal to the first isolation structure. The active region includes a first boundary and a second boundary. The first boundary is the boundary between the active region and the first isolation structure, and the second boundary is the boundary between the active region and the second isolation structure. The intersection of the first boundary and the second boundary is a corner.

[0007] A gate oxide layer is disposed on the active region;

[0008] A gate electrode is disposed on the gate oxide layer, and the gate electrode overlaps with the first isolation structure and the second isolation structure. An opening or a shearing portion is provided on the corner of the gate electrode.

[0009] In one embodiment of the present invention, the distance between the end of the opening or the shear portion on the first boundary and the corner is less than or equal to the distance between the end of the drift region and the corner.

[0010] In one embodiment of the present invention, the length of the gate electrode and the second boundary coinciding when the opening or the shearing portion is not provided is denoted as AY1, and the length of the gate electrode and the second boundary coinciding when the opening or the shearing portion is provided is denoted as AY2, where AY2 is greater than 70% of AY1.

[0011] In one embodiment of the present invention, the thickness of the gate oxide layer on the first boundary and the second boundary is less than the thickness of the gate oxide layer on the flat region of the active region, and the thickness of the gate oxide layer on the corner is less than the thickness of the gate oxide layer on the first boundary and the second boundary.

[0012] In one embodiment of the present invention, the gate electrode and the opening or the shearing portion are formed in one step.

[0013] In one embodiment of the present invention, one end of the drift region is located below the gate electrode and overlaps with the gate oxide layer. A drain region is provided in the drift region, and the drain region is located on the side of the second isolation structure away from the gate electrode.

[0014] In one embodiment of the present invention, the substrate further includes an extended source region spaced apart from the drift region, the source region being disposed within the extended source region; the isolation structure includes a third isolation structure, the third isolation structure being disposed within the extended source region between the source region and the end of the gate oxide layer, and extending in a direction orthogonal to the first isolation structure.

[0015] In one embodiment of the present invention, one end of the gate electrode is located on and overlaps with the third isolation structure. The boundary between the active region and the third isolation structure is defined as the third boundary. The opening or the shearing portion is provided at the corner where the third boundary and the first boundary intersect.

[0016] In one embodiment of the present invention, the gate electrode includes a main region and an extended region. The main region is disposed on the gate oxide layer on the active region. The extended region is continuously disposed with the main region and disposed on the gate oxide layer and part of the isolation structure in the first boundary, the second boundary and the third boundary.

[0017] In one embodiment of the present invention, the semiconductor device is a symmetrical device or an asymmetrical device.

[0018] In summary, this invention provides a semiconductor device. Through improvements to the semiconductor device, the unexpected technical effects of this application include the ability to reduce the thickness of the gate oxide layer in the flat region and prevent breakdown leakage at the edge of the isolation structure. Furthermore, while ensuring a large drain current, the size of the semiconductor device can be reduced. The increased breakdown voltage of the gate oxide layer allows for higher and faster test voltages in time-lapse dielectric breakdown reliability tests, thereby shortening the test time. Ensuring the width of the effective channel region prevents a decrease in drain current due to a reduction in the effective channel region width, thus increasing the drain current. Enhancing the electric field distribution in the drift region below the gate oxide layer causes the longitudinal electric field of the substrate to concentrate from the gate electrode to the surface of the drift region, thereby obtaining a higher current density and increasing the drain current value. In the device off state, it prevents the generation of parasitic MOS caused by the electric field from the upper metal wiring, thereby preventing leakage current from the drain region to the source region in the boundary region and mitigating the electric field concentration in the drift region near the channel region.

[0019] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a semiconductor device according to the first embodiment of the present invention. Figure 1 Part (a) in the diagram represents a top view of a semiconductor device. Figure 1 Part (b) in the diagram is a cross-sectional view along the bb direction in the top view. Figure 1 Part (c) in the diagram is a cross-sectional view along the cc direction in the top view.

[0022] Figure 2This is a top view schematic diagram of the semiconductor device before the gate electrode is formed in the first embodiment of the present invention.

[0023] Figure 3 This is a schematic diagram showing the relationship between the size of the gate electrode opening, the active region, and the thickness of the gate oxide layer at the boundary of the isolation structure.

[0024] Figure 4 This is a schematic diagram of a semiconductor device according to the second embodiment of the present invention.

[0025] Figure 5 This is a schematic diagram of a semiconductor device according to the third embodiment of the present invention. Figure 5 Part (a) in the diagram represents a top view of a semiconductor device. Figure 5 Part (b) in the diagram is a cross-sectional view along the bb direction in the top view. Figure 5 Part (c) in the diagram is a cross-sectional view along the cc direction in the top view.

[0026] Figure 6 This is a top view schematic diagram of the semiconductor device before the formation of the gate electrode in the third embodiment of the present invention.

[0027] Figure 7 This is a schematic diagram of a semiconductor device according to the fourth embodiment of the present invention.

[0028] Label Explanation:

[0029] 11. High-voltage MOS transistor; 12. Source region; 13. Drain region; 14. Substrate; 15. Extended source region; 16. Channel region; 17. Drift region; 18. Isolation structure; 18a. First isolation structure; 18b. Second isolation structure; 18c. Third isolation structure; 21. Active region; 22a. First boundary; 22b. Second boundary; 22c. Third boundary; 23. Corner; 24. Gate oxide layer; 25. Gate electrode; 26. Main region; 27. Extended region; 27a. First extended region; 27b. Second extended region; 27c. Third extended region; 28. Opening; 31. Guard ring region; 32. Connector region; 42. Shear portion. Detailed Implementation

[0030] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0032] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0033] In semiconductor devices, such as high-voltage MOS transistors, if a design with a slit-like gap on the gate electrode along the boundary between the active region and the shallow trench isolation structure is adopted, the area of ​​the active region covered by the gate electrode becomes smaller, resulting in a decrease in drain current. This is because the slit-like gap reduces the width of the effective channel region, thus reducing drain current. Furthermore, when the high-voltage MOS transistor is in the ON state, in the drift region not covered by the gate electrode due to the slit-like gap, the electric field from the gate electrode towards the substrate weakens, the current density on the surface of the drift region decreases, and the drain current decreases. The wider the slit-like gap, the greater the impact on reducing drain current. Additionally, since the gate electrode is cut off by the gap, a higher metal wiring layer is required for connection, reducing the freedom of layout design. The semiconductor device provided by this application provides semiconductor device performance without increasing fabrication difficulty.

[0034] Please see Figure 1 As shown, Figure 1 This illustrates the structure of the semiconductor device according to the first embodiment of the present invention, namely the high-voltage MOS transistor 11. Wherein, Figure 1 Part (a) in the diagram represents a top view of a semiconductor device. Figure 1 Part (b) in the diagram is a cross-sectional view along the bb direction in the top view. Figure 1 Part (c) is a cross-sectional view along the cc direction in the top view. The high-voltage MOS transistor 11 is used, for example, in a device integrated circuit (IC) of a display panel. In one embodiment of the invention, the operating voltage of the high-voltage MOS transistor 11 is, for example, 25V to 40V.

[0035] Please see Figure 1 As shown, in the first embodiment of the present invention, the high-voltage MOS transistor 11 includes a substrate 14, a drift region 17, an extended source region 15, a channel region 16, a guard ring region 31, a source region 12, a drain region 13, a tap region 32, an isolation structure 18, a gate oxide layer 24, and a gate electrode 25. The isolation structure 18 is, for example, a shallow trench isolation structure.

[0036] Please see Figure 1 As shown, in the first embodiment of the present invention, the high-voltage MOS transistor 11 is described as, for example, an N-channel MOS transistor. In the following description, the first conductivity type is p-type, and the second conductivity type is the opposite of the first conductivity type, for example, n-type. When the high-voltage MOS transistor 11 is, for example, a P-channel MOS transistor, simply replace the first conductivity type with n-type and the second conductivity type with the opposite of the first conductivity type, for example, p-type.

[0037] Please see Figure 1 As shown, in the first embodiment of the present invention, the substrate 14 is, for example, a silicon wafer, and the doping type of the silicon wafer is, for example, p-type. A drift region 17 extends from the surface of the substrate 14 into the substrate 14. The drift region 17 is, for example, an n-type diffusion layer region, serving as a diffusion layer region for forming a depletion layer and for carrier drift when the high-voltage MOS transistor 11 is operating. One end of the drift region 17 is located below the gate electrode 25 and overlaps with the gate oxide layer 24. The drain region 13 is an n-type diffusion layer region, serving as the drain of the high-voltage MOS transistor 11. The doping concentration of the drain region 13 is higher than that of the drift region 17, and the drain region 13 is disposed within the drift region 17, specifically on the side of the drift region 17 away from the gate oxide layer 24 and the gate electrode 25.

[0038] Please see Figure 1As shown, in the first embodiment of the present invention, the extended source region 15 and the source region 12 extend from the surface of the substrate 14 into the substrate 14. The extended source region 15 and the source region 12 are spaced apart from the drift region 17, and the extended source region 15 and the source region 12 are n-type diffusion layer regions, serving as the diffusion layer regions of the source of the high-voltage MOS transistor 11. In other embodiments, for example, the extended source region 15 and the source region 12 are collectively referred to as the source region. One end of the extended source region 15 is located below the gate electrode 25 and overlaps with the gate oxide layer 24, and the source region 12 is disposed within the extended source region 15. The doping concentration of the source region 12 is higher than that of the extended source region 15, and the region between the extended source region 15 and the drift region 17 is the channel region 16.

[0039] Please see Figure 1 As shown, in the first embodiment of the present invention, the guard ring region 31 serves as a p-type diffusion layer region isolating the high-voltage MOS transistor 11 from other components, and the guard ring region 31 surrounds the drift region 17, the extended source region 15, and the channel region 16. The connector region 32 is a p-type diffusion layer region used to apply voltage to the guard ring region 31, and the connector region 32 is disposed within the guard ring region 31, with a higher doping concentration than that of the guard ring region 31.

[0040] Please see Figures 1 to 2 As shown, in the first embodiment of the present invention, the isolation structure 18 is used to insulate the components of the high-voltage MOS transistor 11 from each other and to mitigate the electric field between the drain region 13 and the gate electrode 25. The isolation structure 18 is, for example, made of a silicon oxide film or a silicon nitride film. Figure 2 As shown, the isolation structure 18 includes a first isolation structure 18a and a second isolation structure 18b. The first isolation structure 18a extends parallel to each other from the source region 12 toward the drift region 17. The second isolation structure 18b is disposed in the drift region 17 between the drain region 13 and the end of the gate oxide layer 24, and extends in a direction orthogonal to the first isolation structure 18a. The active region 21 is divided by the first isolation structure 18a and the second isolation structure 18b.

[0041] Please see Figures 1 to 2As shown, in the first embodiment of the present invention, a second isolation structure 18b is disposed within the drift region 17, and a drain region 13 is disposed on the side of the second isolation structure 18b away from the gate electrode 25, for mitigating the electric field between the drain region 13 and the gate electrode 25. By providing the second isolation structure 18b, the drain region 13 can be formed in a self-aligned manner, thereby reliably ensuring the distance between the drain region 13 and the gate electrode 25. One end of the gate electrode 25 is located on the upper part of the second isolation structure 18b and partially overlaps with the second isolation structure 18b. By overlapping the gate electrode 25 to the upper part of the second isolation structure 18b in such a way that it spans the end of the channel region 16 and the end of the active region 21, the electric field concentration in the drift region 17 located near the channel region 16 can be mitigated.

[0042] Please see Figures 1 to 2 As shown, in the first embodiment of the present invention, a gate oxide layer 24 is formed on the active region 21, and the thickness of the gate oxide layer 24 is, for example, 60 nm to 100 nm, to ensure that the operating voltage of the high-voltage MOS transistor 11 is 25 V to 40 V. The gate oxide layer 24 is formed, for example, by a thermal oxidation process, in which silicon in the substrate 14 is oxidized to form the gate oxide layer 24. While a silicon oxide film is formed by thermal oxidation of the substrate 14, a problem arises in the boundary region between the isolation structure 18 and the active region 21: the thickness of the silicon oxide film is less than the thickness of the flat region of the active region 21.

[0043] Please see Figures 1 to 3 As shown, in the first embodiment of the present invention, the boundary between the active region 21 and the first isolation structure 18a is defined as the first boundary 22a, and the boundary between the active region 21 and the second isolation structure 18b is defined as the second boundary 22b. During the thermal oxidation process to form the gate oxide layer 24, the thickness of the gate oxide layer 24 at the first boundary 22a and the second boundary 22b decreases. For example, if the thickness of the gate oxide layer 24 in the flat region of the active region 21 is denoted as T1, and T1 is 110 nm, the thickness T2 of the gate oxide layer 24 at the first boundary 22a and the second boundary 22b is approximately 80 nm, that is, the thickness of the gate oxide layer 24 at the first boundary 22a and the second boundary 22b is approximately 73% of the thickness of the gate oxide layer 24 in the flat region.

[0044] Please see Figures 1 to 3As shown, in the first embodiment of the present invention, at the corner 23 of the active region 21 where it intersects with the first boundary 22a and the second boundary 22b, i.e., at the intersection of the isolation structure 18 and the active region 21 at a 90° angle, the problem of thinning of the gate oxide layer 24 at the corner 23 is more prominent. For example, when the thickness T1 of the gate oxide layer 24 in the flat region of the active region 21 is 110 nm, the thickness T3 of the gate oxide layer 24 at the corner 23 is approximately 65 nm, i.e., the thickness of the gate oxide layer 24 at the corner 23 is approximately 59% of the thickness of the gate oxide layer 24 in the flat region.

[0045] Please see Figures 1 to 2 As shown, in the first embodiment of the present invention, a gate electrode 25 is formed on the gate oxide layer 24. The gate electrode 25 is, for example, a polysilicon layer, a metal layer, a metal silicide layer, or a stacked structure of a polysilicon layer and a metal layer or a polysilicon layer and a metal silicide layer. The gate electrode 25 includes a main region 26 and an extended region 27. The main region 26 is disposed on the gate oxide layer 24 on the active region 21. The extended region 27 is continuously disposed on the main region 26 and is formed on the gate oxide layer 24 and a portion of the isolation structure 18 in the first boundary 22a and the second boundary 22b. The extended region 27 includes a first extended region 27a that overlaps with the first isolation structure 18a and a second extended region 27b that overlaps with the second isolation structure 18b.

[0046] Please see Figures 1 to 2 As shown, in the first embodiment of the present invention, the gate electrode 25 has an opening 28 on the corner 23 of the active region 21. The opening 28 is, for example, a hole pattern formed by a photolithography process and an etching process. In the photolithography process, a mask with a gate electrode pattern is used, and the gate electrode pattern has an opening pattern corresponding to the opening 28. In the etching process, the opening 28 and the gate electrode 25 are formed in one step. Therefore, no additional manufacturing process is added during the fabrication of the semiconductor device. When an interlayer insulating film (not shown) is subsequently formed, the interlayer insulating film is formed on the upper layer of the gate electrode 25, and no interlayer insulating film is provided on the opening 28.

[0047] Please see Figures 1 to 3As shown, in the first embodiment of the present invention, the smaller the thickness of the gate oxide layer 24, the larger the drain current of the high-voltage MOS transistor 11. Furthermore, when designing the thickness of the gate oxide layer 24, it is necessary to ensure that the thickness of the gate oxide layer 24 can guarantee the reliability of the device operating at the working voltage for ten years. Since the thickness of the gate oxide layer 24 is smallest at the corner 23, the thickness T3 of the gate oxide layer 24 in the corner 23 needs to be designed to ensure the reliability of the device operating at the working voltage for ten years. For example, to ensure the reliability of the device for ten years, the electric field applied to the gate oxide layer is set to less than 5 MV / cm. Therefore, when the working voltage is set to 32V, the required thickness of the gate oxide layer 24 needs to be greater than 64 nm. When there is no opening 28 on the gate electrode 25, the thickness T3 of the gate oxide layer 24 in the corner 23 needs to be greater than 64 nm. Therefore, as mentioned above, T3 / T1 is approximately 59%. Therefore, the thickness T1 of the gate oxide layer 24 in the flat region needs to be greater than 108 nm. When an opening 28 is provided on the gate electrode 25, no gate voltage is applied to the gate oxide layer 24 in the corner 23. Therefore, as long as the thickness T2 of the gate oxide layer 24 in the first boundary 22a and the second boundary 22b is set to be greater than 64nm, as mentioned above, T2 / T1 is approximately 73%. Therefore, as long as the thickness T1 of the gate oxide layer 24 in the flat region is set to be greater than 88nm.

[0048] Please see Figures 1 to 3 As shown, in the first embodiment of the present invention, by providing an opening 28 on the gate electrode 25, the thickness T1 of the gate oxide layer 24 in the flat region can be designed to be smaller, and a larger drain current can be ensured. Furthermore, while ensuring a larger drain current, the size of the high-voltage MOS transistor 11 can be reduced. In addition, because the opening 28 is provided, a gate voltage is not applied to the gate oxide layer 24 in the corner portion 23; therefore, the breakdown voltage of the gate oxide layer 24 becomes higher, which can increase and accelerate the test voltage in the TDDB reliability test, thereby shortening the test time.

[0049] Please see Figures 1 to 2As shown, in the first embodiment of the present invention, the larger the area of ​​the active region 21 covered by the gate electrode 25, the larger the drain current of the high-voltage MOS transistor 11. By overlapping the gate electrode 25 to the upper part of the first isolation structure 18a across the end of the active region 21, the area of ​​the active region 21 covered by the gate electrode 25 is increased, thereby ensuring the width of the effectively effective channel region 16 and increasing the drain current. Furthermore, by overlapping the gate electrode 25 to the upper part of the second isolation structure 18b across the end of the active region 21, the area of ​​the active region 21 covered by the gate electrode 25 is increased, thereby increasing the drain current. By overlapping the gate electrode 25 across the end of the active region 21 onto the upper part of the second isolation structure 18b, the electric field distribution within the drift region 17 below the gate oxide layer 24 is enhanced when the high-voltage MOS transistor 11 is in the on state. This design causes the longitudinal electric field of the substrate 14 to concentrate from the gate electrode 25 to the surface of the drift region, thereby achieving a higher current density and increasing the drain current value. In particular, providing an opening 28 at the corner 23 of the device ensures the same area of ​​the active region 21 covered by the gate electrode 25 as in the case where the opening 28 is not provided. Providing an opening 28 at the corner 23 also ensures that the area of ​​the active region 21 covered by the gate electrode 25 reaches the same level as in the case where the opening 28 is not provided.

[0050] Please see Figures 1 to 3 As shown, in the first embodiment of the present invention, when an opening 28 is provided on the corner 23, the gate electrode 25 includes a first extended region 27a overlapping the first isolation structure 18a and a second extended region 27b overlapping the second isolation structure 18b. Through the first extended region 27a, the gate electrode 25 can cover the boundary region between the active region 21 and the first isolation structure 18a, preventing the generation of parasitic MOS caused by the electric field from the upper metal wiring when the high-voltage MOS transistor 11 is turned off, thereby preventing leakage current from the drain region 13 to the source region 12 in the boundary region. Through the second extended region 27b, a gate voltage can be applied to the drift region 17 near the channel region 16, mitigating electric field concentration.

[0051] Please see Figure 3 As shown, in the first embodiment of the present invention, Figure 3 A schematic diagram showing the relationship between the size of the opening 28 of the gate electrode 25 and the thickness of the gate oxide layer 24. (See diagram) Figure 3As shown, PX1 is the distance between the end of the opening 28 and the corner 23 on the first boundary 22a, and PY1 is the distance between the end of the opening 28 and the corner 23 on the second boundary 22b. PX2 is the distance between the end of the opening 28 and the corner 23 on the second isolation structure 18b. PX2 is the distance between the end of the opening 28 and the corner 23 on the first isolation structure 18a.

[0052] Please see Figure 3 As shown, in the first embodiment of the present invention, the dimensions of the lower limits of the distances from PX1, PX2, PY1, and PY2 need to be set to dimensions that are not affected by the gate oxide layer 24 at the diagonal 23 of the gate voltage. During design, the dimensions are obtained by adding a 10% margin to the thickness of the gate oxide layer, which ensures the device's reliability for ten years at the operating voltage, plus the size margins and overlap margins of each process forming the isolation structure 18 and the gate electrode 25. For example, to ensure ten years of reliability, the electric field applied to the gate oxide layer needs to be set to below 5 MV / cm. Therefore, with the operating voltage set to 32V, the required gate oxide layer thickness is greater than 64 nm. In this case, the distances from PX1, PX2, PY1, and PY2 can be 100 nm or greater, calculated based on 64 nm plus a 10% margin of 6.4 nm, plus the size margin and overlap margin of 30 nm.

[0053] Please see Figures 1 to 3 As shown, in the first embodiment of the present invention, the upper limit of the distance PX1 can be, for example, less than or equal to the distance from the boundary of the channel region 16 and the drift region 17 to the corner 23, that is, less than or equal to the distance between the end of the drift region 17 and the corner 23. By making the distance PX1 less than or equal to the distance between the end of the drift region 17 and the corner 23, the opening 28 can be omitted from the channel region 16, and the reduction in drain current caused by the reduction in the width of the effective channel region 16 can be prevented. In addition, the first extended region 27a can prevent leakage current from the drain region 13 to the source region 12. In one embodiment of the present invention, the distance PX1 is, for example, less than 1 μm.

[0054] Please see Figures 1 to 3As shown, in the first embodiment of the present invention, when designing the upper limit of PY1, the length of the overlap between the gate electrode 25 and the second boundary 22b without the opening 28 is denoted as AY1, and the length of the overlap between the gate electrode 25 and the second boundary 22b with the opening 28 is denoted as AY2. AY2 is greater than 70% of AY1, and AY2 = AY1 - PY1 × 2. If AY2 is greater than 70% of AY1, the effect of reduced drain current caused by the smaller area of ​​the active region 21 covered by the gate electrode 25 can be reduced. In addition, the electric field concentration in the drift region 17 near the channel region 16 can be mitigated by the second extended region 27b. In one embodiment of the present invention, the distance to PY1 is, for example, less than 1 μm.

[0055] Please see Figures 1 to 3 As shown, in the first embodiment of the present invention, the opening 28 can also be configured as a square, a circle, or a rectangle. When the opening 28 is rectangular, the length of the short side of the rectangle must at least meet the lower limit of the distance from PX1, PX2, PY1, and PY2, and the length of the long side of the rectangle must meet the upper limit of the distance from PX1 and PY1.

[0056] Please see Figure 4 As shown, Figure 4 This is the structure of a high-voltage MOS transistor 11, a semiconductor device according to the second embodiment of the present invention. In this embodiment, a shear portion 42 is provided within the gate electrode 25, and the shear portion 42 is disposed on the corner 23 of the active region 21. The shear portion 42 is, for example, a shear pattern formed by a photolithography process and an etching process. In the photolithography process, a mask with a gate electrode pattern is used, and an opening pattern corresponding to the shear portion 42 is provided on the gate electrode pattern. In the etching process, the shear portion 42 and the gate electrode 25 are formed in one step, therefore, no additional manufacturing process is added during the fabrication of the semiconductor device. When an interlayer insulating film (not shown in the figure) is subsequently formed, the interlayer insulating film is formed on the upper layer of the gate electrode 25, and an interlayer insulating film is also provided on the shear portion 42. In this embodiment, the other structures of the semiconductor device are the same as in the first embodiment.

[0057] Please see Figure 1 , Figure 4As shown, in the second embodiment of the present invention, a shearing portion 42 is provided on the gate electrode 25. Therefore, no gate voltage is applied to the gate oxide layer 24 at the corner 23, which reduces the film thickness T1 of the gate oxide layer 24 in the flat region, ensuring a larger drain current. Furthermore, since a larger drain current is ensured, the size of the high-voltage MOS transistor 11 can be reduced. Because the shearing portion 42 is provided, no gate voltage is applied to the gate oxide layer 24 at the corner 23, resulting in a higher breakdown voltage of the gate oxide layer 24. This allows for increased test voltage and accelerated testing in TDDB reliability testing, thereby shortening the test time.

[0058] Please see Figure 4 As shown, in the second embodiment of the present invention, the lower and upper limits of the distance between the end of the shear portion 42 on the first boundary 22a of the active region 21 and the corner portion 23 are the same as the distance PX1 in the first embodiment. The lower and upper limits of the distance between the end of the shear portion 42 on the second boundary 22b of the active region 21 and the corner portion 23 are the same as the distance PY1 in the first embodiment.

[0059] Please see Figure 4 As shown, in the second embodiment of the present invention, the structure of the first extended region 27a, which coincides with the first boundary 22a, is the same as that in the first embodiment. Therefore, the effect of the decrease in drain current caused by the smaller area of ​​the active region 21 covered by the gate electrode 25 is reduced. In addition, the first extended region 27a can achieve the effect of preventing leakage current from the drain region 13 to the source region 12.

[0060] Please see Figure 4 As shown, in the second embodiment of the present invention, the structure of the second extended region 27b, which coincides with the second boundary 22b, is the same as that in the first embodiment. Therefore, the effect of the decrease in drain current caused by the smaller area of ​​the active region 21 covered by the gate electrode 25 is reduced. In addition, the second extended region 27b provides a field concentration mitigation effect for the drift region 17 near the channel region 16.

[0061] Please see Figure 5 As shown, Figure 5 The structure of the semiconductor device, namely the high-voltage MOS transistor 11, is described in the third embodiment of the present invention. Figure 5 Part (a) in the diagram represents a top view of a semiconductor device. Figure 5 Part (b) in the diagram is a cross-sectional view along the bb direction in the top view. Figure 5Part (c) in the diagram is a cross-sectional view along the cc direction in the top view. In this embodiment, the high-voltage MOS transistor 11 includes a substrate 14, a drift region 17, an extended source region 15, a channel region 16, a guard ring region 31, a source region 12, a drain region 13, a junction region 32, an isolation structure 18, a gate oxide layer 24, and a gate electrode 25.

[0062] Please see Figure 1 and Figure 5 As shown, Figure 1 The high-voltage MOS transistor 11 in the first embodiment shown is an asymmetric transistor with different structures on the drain and source sides. Figure 5 The high-voltage MOS transistor 11 in the third embodiment shown is a symmetrical transistor with identical structures on both the drain and source sides. In this symmetrical transistor, the source and drain directions are not defined, allowing voltage to be applied in both directions. In the third embodiment, the structures of the substrate 14, drift region 17, drain region 13, guard ring region 31, and junction region 32 are the same as those in the first embodiment.

[0063] Please see Figure 5 As shown, in the third embodiment of the present invention, the drain side and source side have a linearly symmetrical structure. Extended source region 15 and source region 12 extend from the substrate 14 into the substrate 14 and are n-type diffusion layer regions spaced apart from the drift region 17, serving as the n-type diffusion layer regions of the source of the high-voltage MOS transistor 11. In other embodiments, for example, extended source region 15 and source region 12 are collectively referred to as source regions. One end of extended source region 15 is located below the gate electrode 25 and overlaps with the gate oxide layer 24, and source region 12 is disposed within extended source region 15. The doping concentration of source region 12 is higher than that of extended source region 15, and the region between extended source region 15 and drift region 17 is the channel region 16.

[0064] Please see Figure 5 As shown, in the third embodiment of the present invention, the isolation structure 18 insulates the components of the high-voltage MOS transistor 11 from each other and mitigates the electric field between the drain region 13 and the gate electrode 25. The isolation structure 18 is, for example, made of a silicon oxide film or a silicon nitride film. Figure 6As shown, the first isolation structure 18a extends parallel to each other from the source region 12 toward the drift region 17. The second isolation structure 18b is disposed within the drift region 17 between the drain region 13 and the end of the gate oxide layer 24, and extends in a direction orthogonal to the first isolation structure 18a. The third isolation structure 18c is disposed within the extended source region 15 between the source region 12 and the end of the gate oxide layer 24, and extends in a direction orthogonal to the first isolation structure 18a. The active region 21 is defined by the first isolation structure 18a, the second isolation structure 18b, and the third isolation structure 18c.

[0065] Please see Figure 2 , Figure 5 and 6 As shown, in the third embodiment of the present invention, the structure of the second isolation structure 18b is the same as that of the second isolation structure 18b in the first embodiment.

[0066] Please see Figure 5 and 6 As shown, in the third embodiment of the present invention, a third isolation structure 18c is disposed within the extended source region 15 for self-alignment to form the source region 12, thereby reliably ensuring the distance between the source region 12 and the gate electrode 25. One end of the gate electrode 25 is located on and overlaps with the third isolation structure 18c. By overlapping the gate electrode 25 to the upper part of the third isolation structure 18c across the end of the channel region 16 and the end of the active region 21, the overlapping area of ​​the active region 21 and the gate electrode 25 can be ensured, thereby ensuring that the drain side obtains the same effect as the source side.

[0067] Please see Figure 3 , Figure 5 and 6 As shown, in the third embodiment of the present invention, a gate oxide layer 24 is formed on the active region 21. The boundary between the first isolation structure 18a and the active region 21 is defined as the first boundary 22a, the boundary between the second isolation structure 18b and the active region 21 is defined as the second boundary 22b, and the boundary between the third isolation structure 18c and the active region 21 is defined as the third boundary 22c. In the first embodiment, due to the influence of the gate oxide layer formation process, the thickness of the gate oxide layer 24 at the boundary is reduced. For example, when the thickness T1 of the gate oxide layer 24 on the flat region of the active region 21 is set to 110 nm, the thickness T2 of the gate oxide layer 24 on the first boundary 22a, the second boundary 22b, and the third boundary 22c is approximately 80 nm, that is, the thickness of the gate oxide layer 24 at the boundary is approximately 73% of the thickness of the gate oxide layer 24 on the flat region.

[0068] Please see Figure 2 and Figure 3 , Figure 5 and 6 As shown, in the third embodiment of the present invention, the problem of thinning of the gate oxide layer 24 is more prominent at the corner 23 where it intersects with the first boundary 22a, the second boundary 22b, and the third boundary 22c and the active region 21. The corner 23 is the intersection point of the isolation structure 18 and the active region 21 at a 90° angle. In the first embodiment, the corner 23 coinciding with the gate electrode 25 is two locations on the drain region 13 side. However, in this embodiment, the corner 23 coinciding with the gate electrode 25 is two locations on the drain region 13 side and two locations on the source region 12 side. That is, in this embodiment, there are four corners 23. For example, if the thickness T1 of the gate oxide layer 24 in the flat region of the active region 21 is 110 nm, the thickness T3 of the gate oxide layer 24 at the corner 23 is approximately 65 nm, that is, the thickness of the gate oxide layer 24 at the corner 23 is approximately 59% of the thickness of the gate oxide layer 24 in the flat region.

[0069] Please see Figure 5 and 6 As shown, in the third embodiment of the present invention, a gate electrode 25 is formed on the gate oxide layer 24. The gate electrode 25 is, for example, a polysilicon layer, a metal layer, a metal silicide layer, or a stacked structure of a polysilicon layer and a metal layer or a polysilicon layer and a metal silicide layer. The gate electrode 25 includes a main region 26 and an extended region 27. The main region 26 is disposed on the gate oxide layer 24 on the active region 21. The extended region 27 is continuously disposed on the main region 26 and is formed on the gate oxide layer 24 and a portion of the isolation structure 18 in the first boundary 22a, the second boundary 22b, and the third boundary 22c. The extended region 27 includes a first extended region 27a overlapping the first isolation structure 18a, a second extended region 27b overlapping the second isolation structure 18b, and a third extended region 27c overlapping the third isolation structure 18c.

[0070] Please see Figure 2 , Figure 5 and 6 As shown, in the third embodiment of the present invention, an opening 28 is provided in the gate electrode 25 on the corner 23 of the active region 21. The method for forming the opening 28 is the same as that for the first embodiment, i.e., formed by photolithography and etching processes. The structure of the corner 23 and the opening 28 of the active region 21 located on the drain region 13 side is the same as that of the corner 23 and the opening 28 of the active region 21 in the first embodiment. In this application, the structure of the corner 23 and the opening 28 of the active region 21 located on the source region 12 side is linearly symmetrical to the structure of the corner 23 and the opening 28 of the active region 21 located on the drain region 13 side.

[0071] Please see Figure 3 , Figure 5 and 6 As shown, in the third embodiment of the present invention, by providing an opening 28 on the gate electrode 25, no gate voltage is applied to the gate oxide layer 24 at the corner 23. Therefore, the film thickness T1 of the gate oxide layer 24 in the flat region can be reduced, ensuring a large drain current. Furthermore, since a large drain current can be ensured, the size of the high-voltage MOS transistor 11 can be reduced. Additionally, due to the presence of the opening 28, no gate voltage is applied to the gate oxide layer 24 in the corner 23, thus increasing the breakdown voltage of the gate oxide layer 24. This allows for higher test voltage and faster testing in TDDB reliability tests, shortening the test time.

[0072] Please see Figure 5 and 6 As shown, in the third embodiment of the present invention, the structure of the first extended region 27a that coincides with the first boundary 22a is the same as the structure of the first extended region in the first embodiment. Therefore, the effect of the reduction in drain current caused by the smaller area of ​​the active region 21 covered by the gate electrode 25 can be reduced. In addition, the first extended region 27a can reduce the leakage current from the drain region 13 to the source region 12.

[0073] Please see Figure 5 and 6 As shown, in the third embodiment of the present invention, the structure of the second extended region 27b, which coincides with the second boundary 22b, is the same as the structure of the second extended region in the first embodiment. Therefore, the effect of reduced drain current caused by the smaller area of ​​the active region 21 covered by the gate electrode 25 can be reduced. Furthermore, the second extended region 27b can mitigate the electric field concentration in the drift region 17 near the channel region 16. The structure of the third extended region 27c, which coincides with the third boundary 22c, is the same as the structure of the second extended region 27b. Therefore, the effect of reduced drain current caused by the smaller area of ​​the active region 21 covered by the gate electrode 25 can be reduced.

[0074] Please see Figure 7 As shown, Figure 7This is the structure of a high-voltage MOS transistor 11, a semiconductor device according to the fourth embodiment of the present invention. In this embodiment, a shear portion 42 is provided within the gate electrode 25. The shear portion 42 is located on the corner 23 of the active region 21, and the shear portion 42 is, for example, a shear pattern formed by a photolithography process and an etching process. In the photolithography process, a mask with a gate electrode pattern is used, and an opening pattern corresponding to the shear portion 42 is provided on the gate electrode pattern. In the etching process, the shear portion 42 and the gate electrode 25 are formed in one step, therefore, no additional manufacturing process is added during the fabrication of the semiconductor device. When an interlayer insulating film (not shown in the figure) is subsequently formed, the interlayer insulating film is formed on the upper layer of the gate electrode 25, and an interlayer insulating film is also provided on the shear portion 42. Other structures are the same as in the third embodiment.

[0075] Please see Figure 5 , Figure 7 As shown, in the fourth embodiment of the present invention, a shearing portion 42 is provided on the gate electrode 25, so that no gate voltage is applied to the gate oxide layer in the corner 23. Therefore, the film thickness T1 of the gate oxide layer in the flat region can be reduced to ensure a large drain current. Furthermore, since a large drain current can be ensured, the size of the high-voltage MOS transistor 11 can be reduced. In addition, because the shearing portion 42 is provided, no gate voltage is applied to the gate oxide layer at the corner 23, so the breakdown voltage of the gate oxide layer becomes higher. This allows for increased test voltage and accelerated testing in TDDB reliability testing, thereby shortening the test time.

[0076] Please see Figure 7 As shown, in the fourth embodiment of the present invention, the lower and upper limits of the distance between the end of the shear portion 42 on the first boundary of the active region 21 and the corner portion 23 are the same as in the third embodiment. The lower and upper limits of the distance between the end of the shear portion 42 on the second boundary of the active region 21 and the corner portion 23 are the same as in the third embodiment. The lower and upper limits of the distance between the end of the shear portion 42 on the third boundary of the active region 21 and the corner portion 23 are the same as the lower and upper limits of the distance between the end of the shear portion 42 on the second boundary of the active region 21 and the corner portion 23.

[0077] Please see Figure 7 As shown, in the fourth embodiment, the structure of the first extended region 27a, which coincides with the first boundary, is the same as in the third embodiment. Therefore, the effect of the decrease in drain current caused by the smaller area of ​​the active region 21 covered by the gate electrode 25 is reduced. In addition, the first extended region 27a can achieve the effect of preventing leakage current from the drain region 13 to the source region 12.

[0078] Please see Figure 7As shown, in the fourth embodiment, the structure of the second extended region 27b, which coincides with the second boundary, is the same as in the third embodiment. Therefore, the effect of the decrease in drain current caused by the smaller area of ​​the active region 21 covered by the gate electrode 25 is reduced. Furthermore, the second extended region 27b provides a mitigation effect on the electric field concentration in the drift region 17 near the channel region 16. The structure of the third extended region 27c, which coincides with the third boundary, is the same as that of the second extended region 27b. Therefore, the effect of the decrease in drain current caused by the smaller area of ​​the active region 21 covered by the gate electrode 25 is reduced.

[0079] In summary, this invention provides a semiconductor device. Through improvements to the semiconductor device, the unexpected technical effects of this application include the ability to reduce the thickness of the gate oxide layer in the flat region and prevent breakdown leakage at the edge of the isolation structure. Furthermore, while ensuring a large drain current, the size of the semiconductor device can be reduced. The increased breakdown voltage of the gate oxide layer allows for higher and faster test voltages in time-lapse dielectric breakdown reliability tests, thereby shortening the test time. Ensuring the width of the effective channel region prevents a decrease in drain current due to a reduction in the effective channel region width, thus increasing the drain current. Enhancing the electric field distribution in the drift region below the gate oxide layer causes the longitudinal electric field of the substrate to concentrate from the gate electrode to the surface of the drift region, thereby obtaining a higher current density and increasing the drain current value. In the device off state, it prevents the generation of parasitic MOS caused by the electric field from the upper metal wiring, thereby preventing leakage current from the drain region to the source region in the boundary region and mitigating the electric field concentration in the drift region near the channel region.

[0080] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, characterized in that, include: A substrate, wherein a source region and a drift region are spaced apart within the substrate; An isolation structure is disposed within the substrate to divide the active region, and includes a first isolation structure and a second isolation structure. The first isolation structure extends from the source region toward the drift region, and the second isolation structure is disposed in the drift region and extends in a direction orthogonal to the first isolation structure. The active region includes a first boundary and a second boundary. The first boundary is the boundary between the active region and the first isolation structure, and the second boundary is the boundary between the active region and the second isolation structure. The intersection of the first boundary and the second boundary is a corner. A gate oxide layer is disposed on the active region; A gate electrode is disposed on the gate oxide layer, and the gate electrode overlaps with the first isolation structure and the second isolation structure. An opening or a shearing portion is provided on the corner of the gate electrode.

2. The semiconductor device according to claim 1, characterized in that, The distance between the end of the opening or the shear portion on the first boundary and the corner is less than or equal to the distance between the end of the drift region and the corner.

3. The semiconductor device according to claim 1, characterized in that, The length of the gate electrode coinciding with the second boundary when the opening or the shearing portion is not provided is denoted as AY1, and the length of the gate electrode coinciding with the second boundary when the opening or the shearing portion is provided is denoted as AY2, where AY2 is greater than 70% of AY1.

4. The semiconductor device according to claim 1, characterized in that, The thickness of the gate oxide layer on the first boundary and the second boundary is less than the thickness of the gate oxide layer on the flat region of the active region, and the thickness of the gate oxide layer on the corner is less than the thickness of the gate oxide layer on the first boundary and the second boundary.

5. The semiconductor device according to claim 1, characterized in that, The gate electrode and the opening or the shearing portion are formed in one step.

6. The semiconductor device according to claim 1, characterized in that, One end of the drift region is located below the gate electrode and overlaps with the gate oxide layer. A drain region is provided in the drift region, and the drain region is located on the side of the second isolation structure away from the gate electrode.

7. The semiconductor device according to claim 1, characterized in that, The substrate further includes an extended source region spaced apart from the drift region, the source region being disposed within the extended source region; the isolation structure includes a third isolation structure, the third isolation structure being disposed within the extended source region between the source region and the end of the gate oxide layer, and extending in a direction orthogonal to the first isolation structure.

8. The semiconductor device according to claim 7, characterized in that, One end of the gate electrode is located on and overlaps with the third isolation structure. The boundary between the active region and the third isolation structure is defined as the third boundary. The opening or the shearing portion is provided at the corner where the third boundary and the first boundary intersect.

9. The semiconductor device according to claim 8, characterized in that, The gate electrode includes a main region and an extended region. The main region is disposed on the gate oxide layer on the active region. The extended region is continuously disposed on the main region and disposed on the gate oxide layer and part of the isolation structure at the first boundary, the second boundary and the third boundary.

10. The semiconductor device according to claim 1, characterized in that, The semiconductor device is either a symmetrical device or an asymmetrical device.

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