Method for forming semiconductor device structure

Abstract

A method of forming a semiconductor device structure includes forming a fin structure on a substrate, wherein the fin structure includes a first plurality of semiconductor layers made of a first semiconductor material and a second plurality of semiconductor layers made of a second semiconductor material. A sacrificial gate stack is formed over the fin structure. Portions of the fin structure adjacent the sacrificial gate stack are removed to expose portions of the substrate. A plurality of edge portions of the second plurality of semiconductor layers are removed in a lateral direction to form a plurality of recesses, wherein removing the edge portions includes performing a selective dry etching process using a gas etchant including chlorine trifluoride. An internal spacer is formed in the recess. A source / drain region is formed adjacent the sacrificial gate stack. The sacrificial gate stack and the second plurality of semiconductor layers are removed. A gate structure is formed to replace the sacrificial gate stack and the second plurality of semiconductor layers.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a method of forming a semiconductor device structure. BACKGROUND

[0002] In recent years, the semiconductor integrated circuit (IC) industry has experienced tremendous growth. As ICs evolve, the functionality of ICs increases while the geometry of the components decreases. This scaling of the components provides benefits in terms of increased functionality and lower costs. However, this scaling also places more demands on the manufacturing process.

[0003] Therefore, there is a need to improve the processing and manufacturing of ICs. SUMMARY

[0004] According to some embodiments of the present disclosure, a method of forming a semiconductor device structure includes forming one or more fin structures on a substrate, wherein the one or more fin structures include a first plurality of semiconductor layers made of a first semiconductor material and a second plurality of semiconductor layers made of a second semiconductor material; forming a plurality of sacrificial gate stacks above the one or more fin structures, wherein a first distance between a first pair of adjacent sacrificial gate stacks of the plurality of sacrificial gate stacks is defined as a first pitch, and wherein a second distance between a second pair of adjacent sacrificial gate stacks of the plurality of sacrificial gate stacks is defined as a second pitch that is different from the first pitch; removing portions of the one or more fin structures adjacent to the plurality of sacrificial gate stacks to expose portions of the substrate; removing edge portions of the second plurality of semiconductor layers along a lateral direction to form a recess, wherein removing the edge portions includes performing a selective dry etch process using a gas etchant including ClF3; forming an inner spacer in the recess; forming source / drain (S / D) regions adjacent to the plurality of sacrificial gate stacks; removing the plurality of sacrificial gate stacks and the second plurality of semiconductor layers; forming one or more gate structures to replace the plurality of sacrificial gate stacks and the second plurality of semiconductor layers.

[0005] According to some embodiments of the present disclosure, a method of forming a semiconductor device structure includes forming a plurality of fin structures on a substrate, the plurality of fin structures including a first plurality of semiconductor layers made of a first semiconductor material and a second plurality of semiconductor layers made of a second semiconductor material, wherein a first fin structure and a second fin structure of the plurality of fin structures extend longitudinally along a first axis, and wherein a first width of the first fin structure is defined along a second axis that is perpendicular to the first axis, a second width of the second fin structure is defined along the second axis, and the first width is different from the second width; forming a sacrificial gate stack over the first fin structure and the second fin structure, wherein the sacrificial gate stack extends longitudinally along the second axis; removing portions of the first fin structure and the second fin structure adjacent to the sacrificial gate stack to expose portions of the substrate; removing edge portions of the second plurality of semiconductor layers along a lateral direction to form a plurality of recesses, wherein removing the edge portions includes performing a selective dry etch process using a gas etchant including chlorine trifluoride; forming a plurality of interior spacers in the plurality of recesses; forming a plurality of source / drain regions adjacent to the sacrificial gate stack; removing the sacrificial gate stack and the second plurality of semiconductor layers; and forming a gate structure to replace the sacrificial gate stack and the second plurality of semiconductor layers.

[0006] According to some embodiments of the present disclosure, a method of forming a semiconductor device structure includes forming a fin structure on a substrate, wherein the fin structure includes a first plurality of semiconductor layers made of silicon and a second plurality of semiconductor layers made of silicon germanium; forming a sacrificial gate stack over the fin structure; removing portions of the fin structure adjacent to the sacrificial gate stack to expose a portion of the substrate; removing edge portions of the second plurality of semiconductor layers along a lateral direction to form a plurality of recesses, wherein removing the edge portions includes performing a selective dry etch process using a gas etchant including chlorine trifluoride; forming a plurality of interior spacers in the plurality of recesses; forming a source / drain region adjacent to the sacrificial gate stack; removing the sacrificial gate stack and the second plurality of semiconductor layers; and forming a gate structure to replace the sacrificial gate stack and the second plurality of semiconductor layers. BRIEF DESCRIPTION OF DRAWINGS

[0007] The present disclosure will be better understood with reference to the following detailed description when considered in conjunction with the following drawings, in which like reference numerals and symbols in the various figures are intended to represent the same components, features or structures. Figure One Aspects of the present disclosure can be best understood with reference to the following detailed description when considered in conjunction with the accompanying drawings in which:

[0008] Figures 1 to 5 is a perspective view of various stages of fabricating a semiconductor device structure according to some embodiments;

[0009] Figures 6 to 9 is a perspective view of various stages of fabricating a semiconductor device structure according to some embodiments; Figure 5is a cross-sectional side view of the semiconductor device structure taken along line A-A at a stage of manufacturing the semiconductor device structure according to some embodiments;

[0010] Figure 10A is a cross-sectional side view of the semiconductor device structure taken along line A-A at another stage of manufacturing the semiconductor device structure according to some embodiments; Figure 5

[0011] Figure 10B is a close-up view of Figure 10A

[0012] Figure 10C is a partial top view of Figure 10A

[0013] Figure 11 is a cross-sectional side view of the semiconductor device structure taken along line A-A at another stage of manufacturing the semiconductor device structure according to some embodiments; Figure 5

[0014] Figure 12A and Figure 12B is a cross-sectional side view taken along line A-A of Figure 5 depicting an alternative view of the semiconductor device structure at the same stage of the process shown in Figure 11

[0015] Figure 13A is a cross-sectional side view of the semiconductor device structure taken along line B-B of Figure 11 at the same stage of the process shown in Figure 5

[0016] Figure 13B is a cross-sectional side view of the semiconductor device structure taken along line C-C or C'-C' of Figure 13A

[0017] Figure 14A is a cross-sectional side view taken along line B-B of Figure 5 depicting an alternative view of the semiconductor device structure at the same stage of the process shown in Figure 13A

[0018] Figure 14B is a cross-sectional side view of the semiconductor device structure taken along line D-D of Figure 14A

[0019] Figure 14C and Figure 14D are partial perspective views of the semiconductor device structure shown in cross-section in Figure 13B and Figure 14B respectively, according to some embodiments.​​​​​​​​​

[0020] Figure 14E and Figure 14F are partial top views of a semiconductor device structure according to some embodiments, taken along the X-Y plane of Figure 5 and respectively corresponding to Figure 13A and Figure 14A

[0021] Figures 15 to 23 are cross-sectional side views of various stages of manufacturing a semiconductor device structure according to some embodiments, taken along line A-A of Figure 5

[0022]

Symbolic Representation

[0023] 100: semiconductor device structure

[0024] 101: substrate

[0025] 104: semiconductor layer stack

[0026] 106: first semiconductor layer

[0027] 108: second semiconductor layer

[0028] 112: fin structure

[0029] 112a: first fin structure

[0030] 112b: second fin structure

[0031] 114: trench

[0032] 116: well portion

[0033] 118: insulating material

[0034] 120: isolation region

[0035] 130: sacrificial gate structure, sacrificial gate stack

[0036] 131a: first pair

[0037] 131b: second pair

[0038] 132: sacrificial gate dielectric layer

[0039] 134: sacrificial gate electrode layer

[0040] 136: masking layer

[0041] 138: first gate spacer

[0042] 139: second gate spacer

[0043] 140: recess​​

[0044] 140a: first recess

[0045] 140b: second recess

[0046] 140c: first recess

[0047] 140d: second recess

[0048] 144: inner spacer

[0049] 150: first semiconductor material

[0050] 151: trench

[0051] 152: dielectric layer

[0052] 154: masking layer

[0053] 156: second semiconductor material

[0054] 162: contact etch stop layer, CESL

[0055] 164: interlayer dielectric layer, ILD layer

[0056] 170: gate dielectric layer

[0057] 172: gate electrode layer

[0058] 174: gate structure

[0059] A-A: line

[0060] B-B: line

[0061] C-C: line

[0062] C’-C’: line

[0063] CL: center line

[0064] D-D: line

[0065] D1: first distance

[0066] D2: second distance

[0067] H: height

[0068] P1: first pitch

[0069] P2: second pitch

[0070] T: thickness

[0071] W: width

[0072] W0: width

[0073] W1: first lateral width

[0074] W2: second lateral width

[0075] W3: first width

[0076] W4: second width

[0077] W5: first lateral width

[0078] W6: second lateral width

[0079] W F : fin width

[0080] X: direction

[0081] Y: direction

[0082] Z: direction DETAILED DESCRIPTION

[0083] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of the embodiments. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature can include embodiments in which the first and second features are formed directly on each other, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features can not be directly in contact. In addition, the various embodiments of the present disclosure can refer to a number of references by reference numerals and / or letters in different examples. This repetition is for simplicity and clarity and does not itself convey a relationship between the various embodiments discussed and / or configurations.

[0084] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0085] While embodiments of the disclosure are discussed with respect to nanosheet channel field-effect transistors (FETs), such as gate all around (GAA) FETs (e.g., horizontal gate all around (HGAA) FETs or vertical gate all around (VGAA) FETs), implementations of some aspects of the disclosure can be used in other processes and / or other devices, such as planar FETs, Fin-FETs, and other suitable devices. Those of ordinary skill in the art will readily understand that other modifications can be made that will fall within the scope of the present disclosure. In cases where a gate all around (GAA) transistor structure is employed, the GAA transistor structure can be patterned by any suitable method. For example, one or more lithography processes (including double patterning or multiple patterning processes) can be used to pattern the structure. Generally, double patterning or multiple patterning processes combine lithography processes with self-alignment processes, allowing for the creation of patterns having, for example, smaller pitch than is obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0086] Figures 1 to 23 An exemplary process for fabricating a semiconductor device structure 100 according to embodiments of the disclosure is shown. It is understood that additional embodiments of the method can be provided before, during, and after the process shown, and some of the operations described below can be replaced or eliminated. The order of the operations / processes is not limited and can be interchanged. Figures 1 to 23 Additional operations can be provided before, during, and after the processes shown, and some of the operations described below can be replaced or eliminated. The order of the operations / processes is not limited and can be interchanged.

[0087] Figures 1 to 5 are perspective views of various stages of fabricating a semiconductor device structure 100 according to some embodiments. As Figure 1As shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed over a front side of a substrate 101. The substrate 101 can be a semiconductor substrate. The substrate 101 can include a crystalline semiconductor material such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), aluminum indium arsenide (AlInAs), indium gallium arsenide (InGaAs), gallium antimonide phosphide (GaSbP), gallium arsenide antimonide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for enhanced isolation. In one aspect, the insulating layer is an oxygen-containing layer.

[0088] The substrate 101 can include various regions that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants can be, for example, phosphorus for n-type field effect transistors (NFETs) and boron for p-type field effect transistors (PFETs).

[0089] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate formation of a nanostructured channel in a multi-gate element such as a nanostructured channel FET. In some embodiments, the semiconductor layer stack 104 includes first semiconductor layers 106 and second semiconductor layers 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layers 106 and the second semiconductor layers 108 are made of semiconductor materials having different etch selectivity and / or oxidation rates. For example, the first semiconductor layers 106 can be made of silicon (Si) and the second semiconductor layers 108 can be made of silicon germanium (SiGe). In some examples, the first semiconductor layers 106 can be made of silicon germanium (SiGe) and the second semiconductor layers 108 can be made of silicon (Si). Alternatively, in some embodiments, either of the semiconductor layers 106, 108 can be or include other materials such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0090] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process (e.g., epitaxy). For example, the epitaxial growth of the layers of the semiconductor layer stack 104 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0091] The first semiconductor layer 106, or a portion thereof, may form nanostructured channels of the semiconductor device structure 100 in subsequent manufacturing stages. The term "nanostructure" is used herein to refer to any portion of material having nanoscale or even micrometer-scale dimensions and an elongated shape, regardless of the cross-sectional shape of that portion. Thus, the term refers to elongated material portions with circular and substantially circular cross-sections, as well as beam-shaped or rod-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The nanostructured channels of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include nanostructured transistors. Nanostructured transistors may be referred to as nanosheet transistors, nanowire transistors, gate-around-an-a-loop (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0092] Each first semiconductor layer 106 may have a thickness ranging from approximately 5 nm to approximately 30 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness ranging from approximately 2 nm to approximately 50 nm. Three first semiconductor layers 106 and three second semiconductor layers 108 are arranged as follows... Figure 1 The alternating arrangement shown is for illustrative purposes and is not intended to limit the scope beyond what is specifically stated in the claims. It will be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the semiconductor layer stack 104, and the number of layers depends on a predetermined number of channels in the semiconductor device structure 100. In some embodiments, the semiconductor layer stack 104 includes two first semiconductor layers 106. In some embodiments, the semiconductor layer stack 104 includes three first semiconductor layers 106. In some embodiments, the semiconductor layer stack 104 includes four first semiconductor layers 106.

[0093] like Figure 2As shown, the fin structures 112 are formed from the semiconductor layer stack 104 and the substrate 101. Each fin structure 112 has an upper portion including the semiconductor layers 106, 108 and a well portion 116 formed from the substrate 101. The fin structures 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 using a multiple patterning operation including lithography and etching processes. The etching processes can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The lithography processes can include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure bake process, and developing the photoresist layer to form mask elements including the photoresist layer. In some embodiments, patterning the photoresist layer to form the mask elements can be performed using an electron beam (e-beam) lithography process. The etching processes form trenches 114 through the hard mask layer in unprotected areas, through the semiconductor layer stack 104, and into the substrate 101, leaving a plurality of extended fin structures 112. The trenches 114 extend along the X-direction. The trenches 114 can be etched using dry etching (e.g., RIE), wet etching, and / or combinations thereof.

[0094] As Figure 3 shown, after the fin structures 112 are formed, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structures 112 are embedded in the insulating material 118. Then, a planarization operation such as a chemical mechanical polishing (CMP) method and / or an etch-back method is performed so that the tops of the fin structures 112 are exposed. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-K dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any appropriate method, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or flowable CVD (FCVD).

[0095] As Figure 4As shown, insulating material 118 is recessed to form isolation region 120. The recess in insulating material 118 exposes portions of fin structures 112, such as semiconductor layer stack 104. The recess in insulating material 118 exposes trenches 114 between adjacent fin structures 112. Isolation region 120 can be formed using suitable processes, such as dry etching, wet etching, or combinations thereof. The top surface of insulating material 118 may be flush with or below the surface of the second semiconductor layer 108 that contacts the well portion 116 formed by substrate 101. In some embodiments, isolation region 120 is a shallow trench isolation (STI) region.

[0096] like Figure 5 As shown, one or more sacrificial gate structures 130 (only one is shown) are formed over a semiconductor device structure 100, which may also be referred to herein as a “sacrificial gate stack”. The sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a masking layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136, and then patterning these layers into the sacrificial gate structure 130. The semiconductor device structure 100 may include any number of sacrificial gate structures 130. For example, although one sacrificial gate structure 130 is shown, in some embodiments two or more sacrificial gate structures 130 may be arranged along the X direction. In some embodiments, two sacrificial gate structures 130 are shown arranged along the X direction, such as... Figure 11 and Figures 15 to 20 As shown.

[0097] The sacrificial gate dielectric layer 132 may include one or more dielectric materials, such as silicon oxide-based materials. The sacrificial gate electrode layer 134 may include polycrystalline silicon or amorphous silicon. The masking layer 136 may include more than one layer, such as an oxide layer and a nitride layer above the oxide layer. The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region of the semiconductor device structure 100.

[0098] like Figure 6As shown, a first gate isolator 138 is deposited on an exposed surface of the semiconductor device structure 100. For example, the first gate isolator 138 is deposited on the fin structure 112, the isolation region 120, and the sacrificial gate structure 130. The first gate isolator 138 can be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiCON, and / or combinations thereof. The first gate isolator 138 can be formed by any suitable process. In some embodiments, the first gate isolator 138 is a conformal layer formed by a conformal process such as atomic layer deposition (ALD).

[0099] like Figure 7 As shown, a second gate separator 139 is deposited on the first gate separator 138. The second gate separator 139 may comprise any suitable dielectric material, such as SiOx, SiON, SiN, SiCON, or SiCO. The second gate separator 139 may have a thickness ranging from about 0.5 nm to about 5 nm. The second gate separator 139 may be formed by any suitable process. In some embodiments, the second gate separator 139 is deposited by CVD, PECVD, or electron cyclotron resonance CVD (ECR-CVD).

[0100] like Figure 8 As shown, the horizontal portions of the first gate separator 138 and the second gate separator 139 are removed. In some embodiments, the horizontal portions of the first gate separator 138 and the second gate separator 139 are removed by an anisotropic etching process. The anisotropic etching process can be a selective etching process that substantially does not affect the photomask layer 136, the semiconductor layer stack 104, and the isolation region 120.

[0101] like Figure 9 As shown, the portion of the fin structure 112 not covered by the sacrificial gate structure 130 and the first gate separator 138 and the second gate separator 139 is recessed to a level above, at, or below the top surface of the isolation region 120. This recess in the fin structure 112 can be achieved through an etching process. The etching process can be dry etching, such as RIE, NBE, etc., or wet etching, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant. The well portion 116 is exposed on the opposite side of the sacrificial gate structure 130, as... Figure 9As shown. Although two gate isolations 138, 139 are shown in the semiconductor device structure 100, depending on the device design and / or manufacturing recipe, fewer or more dielectric layers may be formed on the sidewalls of the sacrificial gate structure 130 as gate isolations.

[0102] Figure 10A It is according to some embodiments along Figure 5 A cross-sectional side view of the semiconductor device structure taken by line AA. Figure 10B According to some embodiments Figure 10A Enlarged image. Figure 10C According to some embodiments Figure 10A A partial top view. (e.g.) Figures 10A to 10C As shown, the edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are removed horizontally (laterally) along the X direction. Removing the edge portions of the second semiconductor layer 108 forms a recess 140. The recess 140 can be defined according to a lateral width W in the X direction and a height H in the Z direction. As shown, the lateral width W can be measured from the position (on the X-axis) of the side surface of the adjacent first semiconductor layer 106 (e.g., directly above or below the recess 140) to the position (on the X-axis) of the side surface of the second semiconductor layer 108 remaining after the removal of the corresponding edge portion. In some embodiments, the lateral width W corresponds to the width of the corresponding edge portion that was removed. For example, the lateral width W can be measured from the position (on the X-axis) of the side surface of each second semiconductor layer 108 before the removal of the corresponding edge portion. Figure 9 The position of the corresponding edge portion is measured to the location of the side surface of each second semiconductor layer 108 remaining after removal. Figure 10B In some embodiments, the lateral width W can be in the range of 5 nm to 15 nm. In some embodiments, the lateral width W can vary depending on the position of each second semiconductor layer 108 within the semiconductor layer stack 104. For example, as... Figure 10B As shown, there are three distinct locations: a top layer, a middle layer, and a bottom layer, as described in more detail below. In some embodiments, the difference in lateral width W between the different layers can be 1 nm or less, such as 0.5 nm or less, such as 0.3 nm or less.

[0103] As shown, the height H can be measured from the bottom surface of the corresponding first semiconductor layer 106 above each recess 140 to the top surface of the corresponding first semiconductor layer 106 (or a portion of the substrate 101) below each recess 140. In some embodiments, the height H corresponds to the height of the corresponding edge portion that has been removed. For example, the height H can be measured from the position of the top surface to the position of the bottom surface of each second semiconductor layer 108 before the corresponding edge portion is removed. Figure 9). In some embodiments, the height H can be in a range between 3 nm and 10 nm. In some embodiments, as shown in FIG. 1C, the width W0 of the remaining portion of the second semiconductor layer 108 (between the trenches 140) can be in a range between 5 nm and 20 nm. In some embodiments, the side surfaces of the remaining portion of each second semiconductor layer 108 are curved with respect to the Z direction (FIG. 1C) such that the width W0 at the center (in the Z direction) is less than the width closer to the top or bottom. In some embodiments, the difference in width between the center and the top or bottom can be in a range between 0 nm and 3 nm. In some embodiments, the side surfaces of the remaining portion of each second semiconductor layer 108 are curved with respect to the Y direction (FIG. 1C) such that the width W0 at the center (in the Y direction) is less than the width closer to the edge of the fin, which is adjacent to the sacrificial gate dielectric layer 132. In some embodiments, the difference in width (or critical dimension (CD) range) between the center and the edge can be in a range between 0 nm and 3 nm. In some embodiments, the thickness T of the first semiconductor layer 106 can be in a range between 3 nm and 10 nm. Figures 10B to 10C Figure 10B Figure 10C

[0104] In some embodiments, the edge portions of the second semiconductor layer 108 are removed by performing a selective dry etch process, as described in more detail below. In some embodiments (e.g., when the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon), a gas etchant including chlorine trifluoride (ClF3) can be used to selectively etch the material of the second semiconductor layer 108. In some embodiments, the gas etchant includes or consists of a mixture of chlorine trifluoride (ClF3) and fluorine gas (F2). In some embodiments, the gas etchant does not include hydrogen fluoride (HF). In some embodiments, the flow rate of ClF3 is in a range between 50 standard cubic centimeters per minute (SCCM) and 100 SCCM. In some embodiments, the volume fraction of ClF3 in the gas etchant is in a range between 50% and 100%. In some embodiments, the temperature of the gas etchant and / or the process temperature is in a range between 25 °C and 35 °C, for example, about 30 °C. The use of ClF3 provides certain advantages over other gases, for example, improved profile control of the critical dimension (CD) of the metal gate (MG), reduction of loading, improvement of device performance, and / or improvement of yield, as described in more detail below.

[0105] ​​​Figure 11 depicts a semiconductor device structure 100 at the same stage of the process shown in Figure 10A depicts an alternative view of the semiconductor device structure 100 at the same stage of the process shown in FIG. 1. As described above, the semiconductor device structure 100 can include any number of sacrificial gate stacks 130. The process to form the structure shown in this alternative view can optionally include any portion of the process described above, up to and including all of it. To form the structure shown in Figure 11 depicts an alternative view of the semiconductor device structure 100 at the same stage of the process shown in FIG. 1. As described above, the semiconductor device structure 100 can include any number of sacrificial gate stacks 130. The process to form the structure shown in this alternative view can optionally include any portion of the process described above, up to and including all of it. To form the structure shown in

[0106] Figure 12A and Figure 12B depicts a semiconductor device structure 100 at the same stage of the process shown in Figure 11 depicts an alternative view of the semiconductor device structure 100 at the same stage of the process shown in FIG. 1. As described above, the semiconductor device structure 100 can include any number of sacrificial gate stacks 130. The process to form the structure shown in this alternative view can optionally include any portion of the process described above, up to and including all of it. To form the structure shown in Figure 12A and Figure 12BEach includes two different pairs of adjacent sacrificial gate stacks 130, which can be located anywhere on the same semiconductor device structure 100. For example, the two different pairs can be located on the same wafer (or the same substrate 101). In some embodiments, the two different pairs can be positioned directly adjacent to each other in the X-direction and / or the Y-direction. In some embodiments, the two different pairs can be located in different circuit regions of the same semiconductor device structure 100, wafer, and / or substrate 101, such as logic device regions, memory regions, and / or input / output element regions. In Figure 12A In some embodiments, the two different pairs of adjacent sacrificial gate stacks 130 have the same pitch (e.g., a first pitch PI defined by a first distance Dl). In some embodiments, Figure 12B In some embodiments, the two different pairs of adjacent sacrificial gate stacks 130 have different pitches (e.g., a first pitch PI and a second pitch P2 defined by a second distance D2 different from the first distance Dl). In some embodiments Figure 12B ), the first pitch PI is smaller than the second pitch P2.

[0107] Referring to Figure 12A and Figure 12B , the recesses 140 formed by removing edge portions of the second plurality of semiconductor layers 108 (as described above) include sacrificial gate stacks 130 adjacent to a first recess 140a associated with a first pair 131a of adjacent sacrificial gate stacks 130 and a second recess 140b associated with a second pair 131b of adjacent sacrificial gate stacks 130. In some embodiments, when the first pitch PI is equal to the second pitch P2 Figure 12A ), a first lateral width Wl of the first recess 140a is equal to a second lateral width W2 of the second recess 140b. In other words, when the first pitch PI is the same as the second pitch P2, the loading effect is zero, and the first recess 140a and the second recess 140b have equal lateral widths. The term "loading effect" refers to process non-uniformity caused by different geometric features (e.g., different pattern densities, different pitches, etc.) within a substrate, wafer, or device. During etching, the loading effect can be caused by different exposure areas or etching areas, making it difficult to control etching uniformity due to the loading effect. Depending on the integration of the fin structure and the etching strategy, the loading effect is that the etching rate of a large exposure area is faster or slower than the etching rate of a small exposure area. In other words, the loading effect is that the etching rate of a large area does not match the etching rate of a small area. This means that the loading effect can be affected by the pattern density. In some embodiments, when the first pitch PI is smaller than the second pitch P2 Figure 12B), a first lateral width W1 of the first recess 140a is less than a second lateral width W2 of the second recess 140b. In other words, the loading effect of the first pitch PI is less than the second pitch P2, at least because the first pitch PI is less than the second pitch P2. The use of a gas etchant including C1F3 in the dry etch process that forms the recesses 140 can provide a significant reduction in loading compared to other gases, as described below. For example, using C1F3, even when the first pitch PI is less than the second pitch P2, the difference between the first lateral width W1 and the second lateral width W2 is below a threshold that is less than a feature threshold for etching differences with other gases. In other words, using a gas etchant containing HF results in higher loading, higher thresholds, and greater etching differences based on gate pitch compared to C1F3.

[0108] In some embodiments, when the first pitch P1 is less than 80% of the second pitch P2, the difference between the first lateral width W1 and the second lateral width W2 is less than 5% of W2. For example, the first lateral width W1 may be 5% higher or lower than the second lateral width W2, or less. In some embodiments, when the first pitch P1 is less than 60% of the second pitch P2, the difference between the first lateral width W1 and the second lateral width W2 is less than 10% of W2. For example, the first lateral width W1 may be 10% higher or lower than the second lateral width W2, or less. In some embodiments, when the first pitch P1 and the second pitch P2 are in the range between 44nm and 72nm, the difference between the first lateral width W1 and the second lateral width W2 is 10% higher or lower than W2. For example, the first lateral width W1 may be 10% higher or lower than the second lateral width W2, or less. In some embodiments, when the first pitch P1 and the second pitch P2 are within the range of 44 nm to 72 nm and the first pitch P1 is within the range of 80% to 90% of the second pitch P2, the difference between the first lateral width W1 and the second lateral width W2 is 2% or less. For example, the first lateral width W1 may be 2% higher or lower than the second lateral width W2 or less. In some embodiments, when the first pitch P1 and the second pitch P2 are within the range of 44 nm and 72 nm and the first pitch P1 is within the range of 60% to 90% of the second pitch P2, the difference between the first lateral width W1 and the second lateral width W2 is 5% or less of W2. For example, the first lateral width W1 may be 5% higher or lower than the second lateral width W2 or less. In some embodiments, the difference between the first lateral width W1 and the second lateral width W2 is 0.5 nm or less, for example, 0.25 nm or less, for example, 0.1 nm or less. In some embodiments, the difference between the first lateral width W1 and the second lateral width W2 is 0.05 nm to 0.5 nm, for example, 0.05 nm to 0.25 nm, for example, 0.05 nm to 0.1 nm.

[0109] Figure 13A Is Figure 11 The same stage of the process shown along Figure 5 The cross-sectional side view is taken from line BB. In this view, fin structure 112 (which may be referred to as "multiple fin structures") can be determined according to the fin width W in the Y direction. F To define it. For example... Figure 13A As shown, the fin structure 112 includes a first fin structure 112a and a second fin structure 112b extending longitudinally along a first axis (along the X direction). The fin width W of the first fin structure 112a and the second fin structure 112b is... Fdefined along a second axis perpendicular to the first axis (in the Y direction). In some embodiments, the fin width W F are the same Figure 13A ). In some other embodiments, the fin width W F are different from each other Figure 14A , as described in more detail below.

[0110] As Figure 13A illustrated, the first recess 140c resulting from the removal of the edge portion of the second semiconductor layer 108 of the first fin structure 112a has a first width W3. Likewise, the second recess 140d resulting from the removal of the edge portion of the second semiconductor layer 108 of the second fin structure 112b has a second width W4. The first width W3 and the second width W4 correspond to the fin width W F of the respective fin structure 112. Thus, when the fin width W F of the first fin structure 112a and the second fin structure 112b are the same Figure 13A , the first width W3 is equal to the second width W4. The height H of the recess 140 corresponds to the height of the respective edge portion of the second semiconductor layer 108 that is removed, as described above in connection with Figure 10A . Figure 13B is a cross-sectional side view taken along line C-C or line C'-C' of Figure 13A . The side view through the fin structure 112a or 112b is the same because the width of the respective recess 140c or 140d in the X direction (lateral width W5) is equal. In other words, when the first width W3 is the same as the second width W4, the loading effect is zero and the first recess 140c and the second recess 140d have an equal lateral width W5.

[0111] Figure 14A and Figure 14B depict alternative views of the semiconductor device structure 100 at the same stage of the process as illustrated in Figure 13A and Figure 13B . Figure 14B is a cross-sectional side view taken along line D-D of Figure 14A . In Figure 14A , the first width W3 is smaller than the second width W4. In some embodiments, when the first width W3 is smaller than the second width W4, the lateral width W5 of the first recess 140c (first lateral width W5) Figure 13B ) is greater than the second lateral width W6 of the second recess 140d (second lateral width W6) Figure 14B). In other words, the loading effect of the first width W3 is greater compared to the second width W4, at least because the first width W3 is smaller than the second width W4. Using a gas etchant including C1F3 in the dry etch process that forms the recess 140 can provide a significant reduction in loading compared to other gases, as described below. For example, using C1F3, even when the first width W3 is smaller than the second width W4, the difference between the first lateral width W5 and the second lateral width W6 is below a threshold value that is less than a characteristic threshold value for etching differences with other gases. In other words, using a gas etchant including HF compared to C1F3 results in higher loading, higher threshold values, and greater etching differences based on fin width.

[0112] In some embodiments, when the first width W3 is 60% or less of the second width W4, the difference between the first lateral width W5 and the second lateral width W6 is 5% or less of the second lateral width W6. For example, the first lateral width W5 can be 5% or less higher or lower than the second lateral width W6. In some embodiments, when the first width W3 is 30% or less of the second width W4, the difference between the first lateral width W5 and the second lateral width W6 is 10% or less of the second lateral width W6. For example, the first lateral width W5 can be 10% or less higher or lower than the second lateral width W6. In some embodiments, when the first width W3 and the second width W4 are in a range between 19 nm and 60 nm, the difference between the first lateral width W5 and the second lateral width W6 is 10% or less of the second lateral width W6. For example, the first lateral width W5 can be 10% or less higher or lower than the second lateral width W6. In some embodiments, when the first width W3 and the second width W4 are in a range between 19 nm and 60 nm and the first width W3 is in a range between 60% and 90% of the second width W4, the difference between the first lateral width W5 and the second lateral width W6 is 2% or less of the second lateral width W6. For example, the first lateral width W5 can be 2% or less higher or lower than the second lateral width W6. In some embodiments, when the first width W3 and the second width W4 are in a range between 19 nm and 60 nm and the first width W3 is in a range between 30% and 90% of the second width W4, the difference between the first lateral width W5 and the second lateral width W6 is 5% or less of the second lateral width W6. For example, the first lateral width W5 can be 5% or less higher or lower than the second lateral width W6. In some embodiments, the difference between the first lateral width W5 and the second lateral width W6 is 0.5 nm or less, for example, 0.25 nm or less, for example, 0.1 nm or less. In some embodiments, the difference between the first lateral width W5 and the second lateral width W6 is in a range between 0.05 nm and 0.5 nm, for example, in a range between 0.05 nm and 0.25 nm, for example, in a range between 0.05 nm and 0.1 nm.

[0113] Figure 14C and Figure 14D are partial perspective views of a semiconductor device structure shown in cross-section along the X-Y plane of Figure 13B and Figure 14B are partial perspective views of a semiconductor device structure shown in cross-section along the X-Y plane of Figure 14E and Figure 14F are partial perspective views of a semiconductor device structure shown in cross-section along the X-Y plane of Figure 5 and Figure 13A and Figure 14AFIG. 6 illustrates a partial top view of a semiconductor device structure. As shown, the lateral widths W5, W6 of the recesses 140c, 140d of the second semiconductor layers 108 depend on the fin widths W3, W4 subject to loading effects. For example, the greater the difference in lateral widths, the higher the loading. The processing techniques of the present disclosure can be used to reduce loading effects (e.g., based on fin width), such as using a gas etchant including C1F3 in a dry etch process to form the recesses, as described in more detail below.

[0114] As described above, the lateral widths can differ depending on the location of each second semiconductor layer 108 within the semiconductor layer stack 104. In some embodiments, the differences in lateral widths described in connection with different pitch Figure 12A and Figure 12B ) and / or different fin widths Figure 14A and Figure 14B include comparisons of lateral widths only between matching layers (e.g., top layer vs. top layer, middle layer vs. middle layer, bottom layer vs. bottom layer) and not between different layers (e.g., top layer vs. middle layer or top layer vs. bottom layer). In some other embodiments, the comparisons can apply between matching layers as well as between different layers, e.g., when the difference in lateral widths between layers is nominal (e.g., 5% or less).

[0115] As shown in Figure 15 , which can be immediately after Figure 11 , after removing the edge portions of each second semiconductor layer 108, a dielectric layer is deposited in the cavities to form inner spacers 144. The inner spacers 144 can be made of a low-K dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The inner spacers 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process such as ALD, and then performing an anisotropic etch to remove portions of the conformal dielectric layer other than the inner spacers 144. The inner spacers 144 are protected by the first semiconductor layers 106 during the anisotropic etch process. The remaining second semiconductor layers 108 cover between the inner spacers 144 along the X-direction.

[0116] As shown in Figure 16As shown, a first semiconductor material 150 is formed on an exposed well portion 116 located at the bottom of trench 151. In some embodiments, the first semiconductor material 150 comprises undoped silicon or undoped SiGe. The first semiconductor material 150 may be first formed epitaxially on a semiconductor surface, such as on the exposed well portion 116 and on the first semiconductor layer 106. The first semiconductor material 150 may be a buried epitaxial layer. A subsequent etching process is performed to remove portions of the first semiconductor material 150 formed on the first semiconductor layer 106. As a result of the etching process, the first semiconductor material 150 formed on the exposed well portion 116 may form a concave top surface. In some embodiments, the first semiconductor material 150 has a thickness ranging from about 5 nm to about 50 nm along the Z direction.

[0117] Next, as Figure 16 As shown, a dielectric layer 152 is formed on a semiconductor device structure 100. In some embodiments, the formation of the dielectric layer 152 may define a deposition portion of a deposition-etching topography-selective (DETS) process. In some embodiments, the formation of the dielectric layer 152 may be performed directly after an alumina removal process. The dielectric layer 152 is formed in the trench 151 and over the sacrificial gate structure 130 and the first gate spacer 138 and the second gate spacer 139. The dielectric layer 152 may include any suitable dielectric material. In some embodiments, the dielectric layer 152 includes SiN. The dielectric layer 152 may be formed by any suitable process. In some embodiments, the dielectric layer 152 is formed by CVD. A portion of the dielectric layer 152 formed on a vertical surface may have a first thickness, and a portion of the dielectric layer 152 formed on a horizontal surface may have a second thickness substantially greater than the first thickness. In some embodiments, the dielectric layer 152 includes a sidewall portion disposed on a vertical surface within each trench 151 and a bottom portion disposed on a first semiconductor material 150. For example, the sidewall portion of dielectric layer 152 can be formed on the vertical surfaces of internal separator 144, first semiconductor layer 106, first gate separator 138, and second gate separator 139, such as... Figure 16 As shown. In some embodiments, the bottom portion of dielectric layer 152 is substantially thicker than the sidewall portions of dielectric layer 152. In some embodiments, the width of trench 151 in the X direction ranges from about 22 nm to about 26 nm, and the thickness T1 can be greater than about 5 nm and less than about 10 nm. The bottom of dielectric layer 152 can serve as an isolation layer to prevent current leakage through a portion of the well portion 116 located below the bottommost second semiconductor layer 108.

[0118] likeFigure 17 As shown, a masking layer 154 is formed on the dielectric layer 152 and partially fills the trench 151. The masking layer 154 may be a bottom antireflective coating (BARC). The masking layer 154 can be formed by first forming a layer that completely fills the trench 151 and is located above the sacrificial gate structure 130, and then recessing that layer to form the masking layer 154. In some embodiments, the masking layer 154 can be recessed by a selective etching process that substantially does not affect the dielectric layer 152. The selective etching process may be dry etching, wet etching, or a combination thereof. In some embodiments, the selective etching process is wet etching. In some embodiments, the masking layer 154 contacts the lower portion of the sidewall portion of the dielectric layer 152 in the trench 151, and the upper portion of the sidewall portion of the dielectric layer 152 in the trench 151 is exposed. In some embodiments, the top surface of the masking layer 154 in the trench 151 is located at a level between the top and bottom surfaces of the sacrificial gate electrode layer 134, as shown. Figure 17 As shown. In some embodiments, the top surface of the masking layer 154 in trench 151 may be located at a level below the bottom surface of the sacrificial gate electrode layer 134, for example, at a level below the topmost first semiconductor layer 106, for example, between the top and bottom surfaces of the second semiconductor layer 106 from the bottom. The sidewall portions of dielectric layer 152 will be removed in a subsequent process, while the bottom portion of dielectric layer 152 will be retained. Therefore, the masking layer 154 protects the bottom portion of dielectric layer 152 during the subsequent removal of the upper portion of the sidewall portions of dielectric layer 152 and the subsequent recessing of the lower portion of the sidewall portions of dielectric layer 152.

[0119] like Figure 18 As shown, the exposed upper portion of the sidewall portion of the dielectric layer 152 in each trench 151, as well as the portion of the dielectric layer 152 located above the sacrificial gate structure 130 and the first gate spacer 138 and the second gate spacer 139, is removed. These portions of the dielectric layer 152 can be removed by a selective etching process, such as dry etching, wet etching, or a combination thereof. The selective etching process removes the exposed upper portion of the sidewall portion of the dielectric layer 152 but substantially does not affect the mask layer 154, the first gate spacer 138 and the second gate spacer 139, or the mask layer 136. The remaining lower portion of the sidewall portion of the dielectric layer 152 located in the trench 151 may include a top surface substantially coplanar with the top surface of the photomask layer 154, such as... Figure 18 As shown.

[0120] like Figure 19As shown, the lower portions of the sidewall portions of the masking layer 154 and the dielectric layer 152 are removed. The sidewall portions of the masking layer 154 and the dielectric layer 152 can be removed by any suitable process. In some embodiments, the lower portions of the sidewall portions of the dielectric layer 152 are first recessed by a selective etching process, and the top surface of the recessed dielectric layer 152 is substantially below the top surface of the masking layer 154. The selective etching process recesses the dielectric layer 152 but substantially does not affect the masking layer 136, the first gate spacer 138 and the second gate spacer 139, and the masking layer 154. In some embodiments, the top surface of the recessed dielectric layer 152 is at a level between the top surface and the bottom surface of the bottommost first semiconductor layer 106. In some embodiments, the selective etching process used to recess the lower portions of the sidewall portions of the dielectric layer 152 and the selective etching process used to remove the exposed upper portions of the sidewall portions of the dielectric layer 152 are the same selective etching process. In other words, a single selective etching process can be performed to remove the exposed upper portions of the sidewall portions of the dielectric layer 152 and to recess the lower portions of the sidewall portions of the dielectric layer 152.

[0121] Next, the masking layer 154 is removed. The masking layer 154 can be removed by a selective process. In some embodiments, a lift-off process, such as using a solvent or an oxygen plasma, is used to remove the masking layer 154. The selective process to remove the masking layer 154 substantially does not affect the masking layer 136, the first gate spacer 138 and the second gate spacer 139, the first semiconductor layer 106, the internal spacer 144, and the dielectric layer 152. After the masking layer 154 is removed, the dielectric layer 152 includes a sidewall portion and a bottom portion, the sidewall portion being the recessed lower portion of the sidewall portion. As described above, the top surface of the sidewall portion of the dielectric layer 152 can be at a level between the top surface and the bottom surface of the bottommost first semiconductor layer 106.

[0122] Next, an etching process is performed to remove the sidewall portion of the dielectric layer 152 while leaving the bottom portion of the dielectric layer 152. As described above, the sidewall portion of the dielectric layer 152 has a first thickness that is substantially less than a second thickness of the bottom portion of the dielectric layer 152. As a result, the etching process completely removes the sidewall portion of the dielectric layer 152 while reducing the second thickness of the bottom portion of the dielectric layer 152. In some embodiments, the second thickness of the bottom portion of the dielectric layer 152 after the sidewall portion of the dielectric layer 152 is removed is in a range from about 5 nm to about 8 nm. The etching process can be any suitable etching process, such as a dry etching process, a wet etching process, or a combination thereof. After the etching process to remove the sidewall portion of the dielectric layer 152, the dielectric layer 152 (the remaining bottom portion) is disposed on the first semiconductor material 150, as Figure 19 shown.

[0123] As Figure 20As shown, a second semiconductor material 156 is formed in trench 151, and the second semiconductor material 156 can be epitaxially grown from the first semiconductor layer 106. The second semiconductor material 156 can be grown vertically and horizontally to form facets, which can correspond to the crystal planes of the material used for the first semiconductor layer 106. The second semiconductor material 156 can be a source / drain (S / D) region. In this disclosure, source and drain regions are used interchangeably and their structures are substantially the same. Furthermore, source / drain regions may refer individually or jointly to a source or drain depending on the context. For an n-channel FET, the second semiconductor material 156 can be made of one or more layers of Si, SiP, SiC, and SiCP, or for a p-channel FET, the second semiconductor material 156 can be made of Si, SiGe, or Ge. For a p-channel FET, the second semiconductor material 156 may also include a p-type dopant, such as boron (B). The second semiconductor material 156 can be formed using epitaxial growth methods such as CVD, ALD, or MBE.

[0124] Figures 21 to 23 It is along Figure 5 The figures are cross-sectional side views taken by line AA, showing various stages of manufacturing the semiconductor device structure 100. The semiconductor device structure 100 may include any number of sacrificial gate structures 130, as described above. However, only one sacrificial gate structure 130 is shown in these figures (similar to...). Figures 6 to 10C ).like Figure 21 As shown, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. CESL 162 covers the second gate separator 139, the isolation region 120, and the second semiconductor material 156. CESL 162 may comprise an oxygen-containing or nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc., or combinations thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, CESL 162 is a single layer, such as... Figure 21As shown. In some embodiments, CESL 162 comprises two or more layers. Next, an interlayer dielectric (ILD) layer 164 is formed on CESL 162. The material of ILD layer 164 may include compounds containing Si, O, C and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials such as polymers may also be used for ILD layer 164. ILD layer 164 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the formation of ILD layer 164, the semiconductor device structure 100 may be thermally treated to anneal ILD layer 164. After the formation of ILD layer 164, the semiconductor device structure 100 may be planarized, such as CMP, until the sacrificial gate electrode layer 134 is exposed, as shown. Figure 21 As shown.

[0125] like Figure 22 As shown, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. The removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms an opening between the first gate spacer 138 and the first semiconductor layer 106. The ILD layer 164 protects the second semiconductor material 156 during the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can be removed first by any suitable process, such as dry etching, wet etching, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer 132, which can also be performed by any suitable process. Wet etching or a combination thereof. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer 134, but not the first gate spacer 138, the ILD layer 164, and the CESL 162.

[0126] A selective wet etching process can be used to remove the second semiconductor layer 108. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemicals used in the selective wet etching process remove the SiGe while substantially not affecting the dielectric materials of the Si, the first gate spacer 138, and the internal separator 144. In one embodiment, a wet etchant can be used to remove the second semiconductor layer 108, such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), or phosphoric acid (H3PO4).

[0127] like Figure 23As shown, after the nanochannel is formed (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed to surround the first semiconductor layer 106, the interior spacer 144, the sidewall spacer 138, and the exposed portion of the isolation region 118. A gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 can be collectively referred to as a gate structure 174. In some embodiments, an interfacial layer (IL) (not shown) is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, or high-K dielectric material, other suitable dielectric material, and / or combinations thereof. Examples of high-K dielectric material include Hf02, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (Hf02-Al203) alloy, other suitable high-K dielectric material, and / or combinations thereof. The gate dielectric layer 170 can be formed by CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 can include one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloy, other suitable material, and / or any combination thereof. The gate electrode layer 172 can be formed by CVD, ALD, electroplating, or other suitable deposition technique. The gate electrode layer 172 can also be deposited over the upper surface of the ILD layer 164. Then, the gate dielectric layer 170 and the gate electrode layer 172 formed over the ILD layer 164 are removed by using, for example, CMP until the top surface of the ILD layer 164 is exposed.

[0128] It should be appreciated that the semiconductor device structure 100 can undergo further processes to form conductive contacts to be electrically connected to the second semiconductor material 156 in the ILD layer 164 and to form conductive contacts to be electrically connected to the gate electrode layer 172. Interconnect structures can be formed over the semiconductor device structure 100 to provide electrical paths to the devices formed on the substrate 101.

[0129] Embodiments of the present disclosure provide a method of forming a semiconductor device structure having a fin structure including a first plurality of semiconductor layers made of Si and a second plurality of semiconductor layers made of SiGe. The method includes removing edge portions of the second plurality of semiconductor layers along a lateral direction to form a recess. To remove the edge portions, according to embodiments disclosed herein, a selective dry etch process is performed using a gas etchant including ClF3. For semiconductor elements having varying gate pitch or fin width across different structures on the same substrate, there can be a loading effect that causes the amount of etching of the recess to vary based on the respective differences in gate pitch or fin width. This can present a particular problem for certain non-uniform recesses that are subsequently filled with insulating material having an undesirable thickness. For example, when the loading effect causes the amount of etching of the recess to be too small, the dielectric spacers that form in place of the recess can be too thin, resulting in current leakage across the dielectric layer. However, using ClF3 for the selective dry etch process is able to overcome this problem. Using a gas etchant including ClF3 in the dry etch process to form the recess can provide a significant reduction in loading and an improvement in recess uniformity (dielectric spacer uniformity) compared to other gases, as described herein. For example, using ClF3, the differences in etching (and recess width) remain below a threshold value, even when the gate pitch or fin width varies, that is less than a characteristic threshold value for etching differences with other gases. In other words, using a gas etchant containing HF compared to ClF3 will result in higher loading, a higher threshold value, and greater differences in etching based on gate pitch or fin width. In addition to, or as a result of, the reduction in loading, using a gas etchant including ClF3 as described herein can provide improved control over MG CD profiles, improved device performance, and / or improved yield.

[0130] In some embodiments, a method includes forming one or more fin structures on a substrate, wherein the one or more fin structures include a first plurality of semiconductor layers made of a first semiconductor material and a second plurality of semiconductor layers made of a second semiconductor material; forming a plurality of sacrificial gate stacks over the one or more fin structures, wherein a first distance between a first pair of adjacent sacrificial gate stacks of the plurality of sacrificial gate stacks is defined as a first pitch, and wherein a second distance between a second pair of adjacent sacrificial gate stacks of the plurality of sacrificial gate stacks is defined as a second pitch different from the first pitch; removing portions of the one or more fin structures adjacent to the plurality of sacrificial gate stacks to expose portions of the substrate; removing edge portions of the second plurality of semiconductor layers along a lateral direction to form recesses, wherein removing the edge portions includes performing a selective dry etch process using a gas etchant including C1F3; forming inner spacers in the recesses; forming source / drain (S / D) regions adjacent to the plurality of sacrificial gate stacks; removing the plurality of sacrificial gate stacks and the second plurality of semiconductor layers; forming one or more gate structures to replace the plurality of sacrificial gate stacks and the second plurality of semiconductor layers.

[0131] According to one or more implementations, the first pitch is less than the second pitch, wherein removing the plurality of edge portions of the second plurality of semiconductor layers includes forming a plurality of first recesses associated with the first pair of adjacent sacrificial gate stacks and forming a plurality of second recesses associated with the second pair of adjacent sacrificial gate stacks, and wherein a difference between a first lateral width of the plurality of first recesses and a second lateral width of the plurality of second recesses is below a threshold value. According to one or more implementations, when the first pitch is 80% or less of the second pitch, the difference between the first lateral width and the second lateral width is 5% or less of the second lateral width. According to one or more implementations, when the first pitch is 60% or less of the second pitch, the difference between the first lateral width and the second lateral width is 10% or less of the second lateral width. According to one or more implementations, the first pitch is in a range of 44 nanometers to 72 nanometers, wherein the second pitch is in a range of 44 nanometers to 72 nanometers, and wherein the difference between the first lateral width and the second lateral width is 10% or less of the second lateral width. According to one or more implementations, the first pitch is in a range of 44 nanometers to 72 nanometers, wherein the second pitch is in a range of 44 nanometers to 72 nanometers, wherein the first pitch is in a range of 80% to 90% of the second pitch, and wherein the difference between the first lateral width and the second lateral width is 2% or less of the second lateral width. According to one or more implementations, the first pitch is in a range of 44 nanometers to 72 nanometers, wherein the second pitch is in a range of 44 nanometers to 72 nanometers, wherein the first pitch is in a range of 60% to 90% of the second pitch, and wherein the difference between the first lateral width and the second lateral width is 5% or less of the second lateral width.

[0132] In some embodiments, a method includes forming a plurality of fin structures on a substrate, the plurality of fin structures including a first plurality of semiconductor layers made of a first semiconductor material and a second plurality of semiconductor layers made of a second semiconductor material, wherein a first fin structure and a second fin structure of the plurality of fin structures extend longitudinally along a first axis, and wherein a first width of the first fin structure is defined along a second axis perpendicular to the first axis, a second width of the second fin structure is defined along the second axis, and the first width is different than the second width; forming a sacrificial gate stack over the first fin structure and the second fin structure, wherein the sacrificial gate stack extends longitudinally along the second axis; removing portions of the first fin structure and the second fin structure adjacent to the sacrificial gate stack to expose portions of the substrate; removing edge portions of the second plurality of semiconductor layers along a lateral direction to form a plurality of recesses, wherein removing the edge portions includes performing a selective dry etch process using a gas etchant including chlorine trifluoride; forming a plurality of interior spacers in the plurality of recesses; forming a plurality of source / drain regions adjacent to the sacrificial gate stack; removing the sacrificial gate stack and the second plurality of semiconductor layers; and forming a gate structure to replace the sacrificial gate stack and the second plurality of semiconductor layers.

[0133] According to one or more embodiments, the first width is less than the second width, wherein removing the plurality of edge portions of the second plurality of semiconductor layers includes forming a plurality of first recesses associated with the first fin structure and forming a plurality of second recesses associated with the second fin structure, and wherein a difference between a first lateral width of the plurality of first recesses and a second lateral width of the plurality of second recesses is below a threshold value. According to one or more embodiments, when the first width is 60% or less of the second width, the difference between the first lateral width and the second lateral width is 5% or less of the second lateral width. According to one or more embodiments, when the first width is 30% or less of the second width, the difference between the first lateral width and the second lateral width is 10% or less of the second lateral width. According to one or more embodiments, the first width is in a range of 19 nanometers to 60 nanometers, wherein the second width is in a range of 19 nanometers to 60 nanometers, and wherein the difference between the first lateral width and the second lateral width is 10% or less of the second lateral width. According to one or more embodiments, the first width is in a range of 19 nanometers to 60 nanometers, wherein the second width is in a range of 19 nanometers to 60 nanometers, wherein the first width is in a range of 60% to 90% of the second width, and wherein the difference between the first lateral width and the second lateral width is 2% or less of the second lateral width. According to one or more embodiments, the first width is in a range of 19 nanometers to 60 nanometers, wherein the second width is in a range of 19 nanometers to 60 nanometers, wherein the first width is in a range of 30% to 90% of the second width, and wherein the difference between the first lateral width and the second lateral width is 5% or less of the second lateral width.

[0134] In some embodiments, a method includes forming a fin structure on a substrate, wherein the fin structure includes a first plurality of semiconductor layers made of silicon and a second plurality of semiconductor layers made of silicon germanium; forming a sacrificial gate stack over the fin structure; removing portions of the fin structure adjacent to the sacrificial gate stack to expose a portion of the substrate; removing edge portions of the second plurality of semiconductor layers along a lateral direction to form recesses, wherein removing the edge portions includes performing a selective dry etch process using a gas etchant including chlorine trifluoride; forming internal spacers in the recesses; forming source / drain regions adjacent to the sacrificial gate stack; removing the sacrificial gate stack and the second plurality of semiconductor layers; and forming a gate structure to replace the sacrificial gate stack and the second plurality of semiconductor layers.

[0135] According to one or more embodiments, the gas etchant further includes fluorine gas. According to one or more embodiments, the gas etchant does not include hydrogen fluoride. According to one or more embodiments, the flow rate of chlorine trifluoride is in the range of 50 standard cubic centimeters per minute to 100 standard cubic centimeters per minute. According to one or more embodiments, the volume fraction of chlorine trifluoride is in the range of 50% to 90%. According to one or more embodiments, the temperature of the gas etchant is in the range of 25°C to 35°C.

[0136] Although this disclosure has been described in considerable detail with reference to certain embodiments, other embodiments may also be possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0137] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of this disclosure without departing from its scope or spirit. In view of the foregoing, this disclosure is intended to cover any modifications and variations falling within the appended claims.

Claims

1. A method of forming a semiconductor device structure, comprising: comprise a first plurality of semiconductor layers made of a first semiconductor material and a second plurality of semiconductor layers made of a second semiconductor material; forming a plurality of sacrificial gate stacks on the one or more fin structures, wherein a first distance between a first pair of adjacent sacrificial gate stacks of the plurality of sacrificial gate stacks defines a first pitch, and wherein a second distance between a second pair of adjacent sacrificial gate stacks of the plurality of sacrificial gate stacks defines a second pitch different from the first pitch; removing portions of the one or more fin structures adjacent to the plurality of sacrificial gate stacks to expose portions of the substrate; removing edge portions of the second plurality of semiconductor layers along a lateral direction to form recesses, wherein removing the edge portions comprises performing a selective dry etch process using a gaseous etchant comprising chlorine trifluoride; forming internal spacers in the recesses; forming source / drain regions adjacent to the plurality of sacrificial gate stacks; removing the plurality of sacrificial gate stacks and the second plurality of semiconductor layers; and forming one or more gate structures to replace the plurality of sacrificial gate stacks and the second plurality of semiconductor layers. wherein the first pitch is less than the second pitch, wherein removing the edge portions of the second plurality of semiconductor layers comprises forming first recesses associated with the first pair of adjacent sacrificial gate stacks and forming second recesses associated with the second pair of adjacent sacrificial gate stacks, and wherein a difference between a first lateral width of the first recesses and a second lateral width of the second recesses is below a threshold value. wherein the difference between the first lateral width and the second lateral width is below 5% of the second lateral width when the first pitch is below 80% of the second pitch.

2. The method of forming a semiconductor device structure of claim 1, wherein comprise a first plurality of semiconductor layers made of a first semiconductor material and a second plurality of semiconductor layers made of a second semiconductor material; 3. The method of forming a semiconductor device structure of claim 2, wherein forming a sacrificial gate stack over the first fin structure and the second fin structure, wherein the sacrificial gate stack extends longitudinally along the second axis; 4. A method of forming a semiconductor device structure, characterized by, removing portions of the first fin structure and the second fin structure adjacent to the sacrificial gate stack to expose portions of the substrate; removing edge portions of the second plurality of semiconductor layers along a lateral direction to form recesses, wherein removing the edge portions comprises performing a selective dry etch process using a gaseous etchant comprising chlorine trifluoride; forming internal spacers in the recesses; forming source / drain regions adjacent to the sacrificial gate stack; removing the sacrificial gate stack and the second plurality of semiconductor layers; and ​ ​ ​ ​ forming a gate structure to replace the sacrificial gate stack and the second plurality of semiconductor layers.

5. The method of forming a semiconductor device structure according to Claim 4, wherein wherein the first width is less than the second width, wherein removing the plurality of edge portions of the second plurality of semiconductor layers includes forming a plurality of first recesses associated with the first fin structure and forming a plurality of second recesses associated with the second fin structure, and wherein a difference between a first lateral width of the plurality of first recesses and a second lateral width of the plurality of second recesses is below a threshold value.

6. The method of forming a semiconductor device structure of claim 5, wherein, wherein when the first width is 60% or less of the second width, the difference between the first lateral width and the second lateral width is 5% or less of the second lateral width.

7. The method of forming a semiconductor device structure of claim 5, wherein wherein the first width is in a range of 19 nanometers to 60 nanometers, wherein the second width is in a range of 19 nanometers to 60 nanometers, and wherein the difference between the first lateral width and the second lateral width is 10% or less of the second lateral width.

8. A method of forming a semiconductor device structure, characterized by, comprising: forming a fin structure on a substrate, wherein the fin structure includes a first plurality of semiconductor layers made of silicon and a second plurality of semiconductor layers made of silicon germanium; forming a sacrificial gate stack over the fin structure; removing portions of the fin structure adjacent to the sacrificial gate stack to expose a portion of the substrate; removing edge portions of the second plurality of semiconductor layers along a lateral direction to form recesses, wherein removing the edge portions includes performing a selective dry etch process using a gas etchant including chlorine trifluoride; forming internal spacers in the recesses; forming a source / drain region adjacent to the sacrificial gate stack; removing the sacrificial gate stack and the second plurality of semiconductor layers; and forming a gate structure to replace the sacrificial gate stack and the second plurality of semiconductor layers.

9. The method of forming a semiconductor device structure of claim 8, wherein, wherein the gas etchant further includes fluorine gas.

10. The method of forming a semiconductor device structure of claim 9, wherein, wherein the gas etchant does not include hydrogen fluoride.

Images