Dual-wavelength LED chip

Abstract

The invention relates to the technical field of semiconductor light-emitting devices, in particular to a dual-wavelength LED chip. The dual-wavelength LED chip comprises an N-type semiconductor layer, a first stress buffer layer, a first long-wave light-emitting well layer, a current expansion layer, a second stress buffer layer, a second short-wave light-emitting well layer and a P-type semiconductor layer. The first stress buffer layer comprises a plurality of InGaN first sub-layers, and the In content in the InGaN first sub-layers is gradually increased in the direction from the N-type semiconductor layer to the P-type semiconductor layer; and / or the second stress buffer layer comprises a plurality of InGaN second sub-layers, and the In content in the InGaN second sub-layers is gradually increased in the direction from the N-type semiconductor layer to the P-type semiconductor layer. In contents in the first stress buffer layer and the second stress buffer layer are gradually increased, so that the phenomenon of V-pits clustering can be improved, the stress of the first long-wave light-emitting well layer and the stress of the second short-wave light-emitting well layer can be released, and the QCSE phenomenon is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor light-emitting devices, in particular to a dual-wavelength LED chip. BACKGROUND

[0002] Light-emitting diodes (LEDs) can efficiently convert electric energy into light energy by emitting light through the recombination of electrons and holes, and are widely used in the fields of lighting, displays, etc.

[0003] With the development of technology, the demand for full spectrum in white light illumination increases, and integrating multiple wavelengths on the same chip can effectively reduce the manufacturing cost of full spectrum devices. It is difficult for InGaN LED devices to achieve red light emission. Heterogeneous integration of InGaN and AlGaInP LEDs, such as wafer stacking and adhesive epitaxial layer bonding, is a potential solution for high-brightness full-spectrum devices. However, integrating three different epitaxial layers of LEDs is challenging, and therefore, it is desirable to simplify the integration process.

[0004] Currently, InGaN blue / green dual-wavelength LEDs are grown and manufactured based on the same monochromatic LED process. Blue and green sub-pixels can be formed on the same epitaxial wafer, thereby greatly simplifying the heterogeneous integration process of full-color micro-displays. Only by bonding an AlGaInP red LED array to a driving substrate with a dual-wavelength LED through flip-chip technology can a full-color display be achieved.

[0005] However, the existing blue-green dual-wavelength LED technology has poor crystal quality and V-pits clustering phenomenon, resulting in a more serious QCSE (quantum confinement Stark effect) phenomenon. In addition, the blue light trap has a low light-emitting efficiency.

[0006] Therefore, the present application is proposed. SUMMARY

[0007] The present application aims to provide a dual-wavelength LED chip, by setting the increasing In content in the first stress buffer layer and the second stress buffer layer, the V-pits clustering phenomenon can be improved, and the stress of the first long-wave light-emitting trap layer and the second short-wave light-emitting trap layer can be released, and the QCSE phenomenon can be reduced. The problem of the existing blue-green dual-wavelength LED technology that the V-pits clustering phenomenon leads to a serious QCSE phenomenon is solved.

[0008] In order to achieve the above-mentioned purpose of the present application, the following technical solutions are adopted:

[0009] A dual-wavelength LED chip comprises an N-type semiconductor layer, a first stress buffer layer, a first long-wave light emitting well layer, a current spreading layer, a second stress buffer layer, a second short-wave light emitting well layer, and a P-type semiconductor layer; wherein the first stress buffer layer comprises a plurality of InGaN first sub-layers, and the In content in the InGaN first sub-layers gradually increases from the N-type semiconductor layer to the P-type semiconductor layer; and / or the second stress buffer layer comprises a plurality of InGaN second sub-layers, and the In content in the InGaN second sub-layers gradually increases from the N-type semiconductor layer to the P-type semiconductor layer.

[0010] Further, the In content in the InGaN first sub-layers gradually increases.

[0011] Further, the In content in the InGaN second sub-layers gradually increases.

[0012] Further, the highest In content in the first stress buffer layer is greater than the highest In content in the second stress buffer layer.

[0013] Further, the second short-wave light emitting well layer comprises InGaN second barrier layers and InGaN second well layers which are alternately and cyclically arranged.

[0014] Further, the In element concentration in the InGaN second barrier layers is 0.05-0.1 of the In element concentration in the InGaN second well layers.

[0015] Further, the first long-wave light emitting well layer comprises GaN first barrier layers and InGaN first well layers which are alternately and cyclically arranged.

[0016] Further, the first stress buffer layer comprises GaN third sub-layers and the InGaN first sub-layers which are alternately and cyclically arranged.

[0017] Further, the number of layers of the InGaN first sub-layers is 2-20 layers.

[0018] Further, the second stress buffer layer comprises GaN fourth sub-layers and the InGaN second sub-layers which are alternately and cyclically arranged.

[0019] Further, the number of layers of the InGaN second sub-layers is 2-20 layers.

[0020] Further, the Si average doping concentration of the current spreading layer is ≥2×10 17 atoms / cm 3 , and ≤3×10 19 atoms / cm 3 .

[0021] Further, the current spreading layer comprises a low-doped layer and a high-doped layer, and a ratio of an average Si doping concentration of the high-doped layer to an average Si doping concentration of the low-doped layer is greater than or equal to 2.

[0022] Further, the first long-wave light emitting well layer is a green light well, and the second short-wave light emitting well layer is a blue light well, and the dual-wavelength LED chip is a high color gamut green light eutectic LED.

[0023] Further, a peak wavelength of the first long wave is 440-465 nm, and a peak wavelength of the second short wave is 520-545 nm.

[0024] Compared with the prior art, the beneficial effects of the present application are:

[0025] (1) The dual-wavelength LED chip provided by the present application can improve InGaN / GaN stress release and relieve QCSE by gradually changing the In component from low to high in the first stress buffer layer and the second stress buffer layer, and can improve V-pits clusters. The problem of QCSE caused by V-pits cluster phenomenon existing in the prior art blue-green dual-wavelength LED technology is solved.

[0026] (2) The dual-wavelength LED chip provided by the present application can reduce the lattice mismatch between the well layer and the barrier layer in the second short-wave light emitting well layer by optimizing the barrier structure design of the blue light well and using InGaN with low In component instead of GaN as the quantum barrier, greatly increasing the light emitting quality of the blue light emitting active region, and further reducing the barrier height compared with the traditional GaN blue light quantum well structure, facilitating holes to enter more second short-wave light emitting well layers and increasing the light emitting performance of the second short-wave light emitting well layer. The problem of low blue light well light emitting efficiency is solved. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed in the specific embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0028] Figure 1 The structure schematic diagram of the dual-wavelength LED chip provided by the present application is shown in the figure.

[0029] Figure 2 The In content change schematic diagram of the dual-wavelength LED chip of an embodiment provided by the present application is shown in the figure.

[0030] Figure 3In content variation diagram of the dual-wavelength LED chip of another embodiment provided by the present application;

[0031] Figure 4 In content variation diagram of the dual-wavelength LED chip of another embodiment provided by the present application;

[0032] Figure 5 In content variation diagram of the second short-wave light emitting well layer of another embodiment provided by the present application;

[0033] Figure 6 Morphology under AFM measurement of the first stress buffer layer without In incremental growth provided by the present application;

[0034] Figure 7 Morphology under AFM measurement of the first stress buffer layer with In incremental growth provided by the present application.

[0035] Reference signs:

[0036] 100-substrate; 110-buffer layer; 120-N-type semiconductor layer; 130-first stress buffer layer; 131-InGaN first sub-layer; 132-GaN third sub-layer; 140-first long-wave light emitting well layer; 141-GaN first barrier layer; 142-InGaN first well layer; 150-current spreading layer; 160-second stress buffer layer; 161-InGaN second sub-layer; 162-GaN fourth sub-layer; 170-second short-wave light emitting well layer; 171-InGaN second barrier layer; 172-InGaN second well layer; 180-electron blocking layer; 190-P-type GaN layer; 21-N electrode; 22-P electrode. DETAILED DESCRIPTION

[0037] The technical solutions of the present application will be described clearly and completely in combination with the drawings and specific embodiments, but those skilled in the art will understand that the following described embodiments are part of the embodiments of the present application, not all the embodiments, and are only used to illustrate the present application, and should not be regarded as limiting the scope of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present application. The specific conditions are not specified in the embodiments, and are carried out according to the conventional conditions or the conditions recommended by the manufacturer. The reagents or instruments used are not specified by the manufacturer, and are conventional products that can be purchased on the market.

[0038] If not specifically stated, the "includes" and "contains" mentioned in the present application represent open type, and can also be closed type. For example, the "includes" and "contains" can represent that other components not listed can also be included or contained, or can only include or contain the listed components.

[0039] The present application provides a dual-wavelength LED chip, referring to Figure 1 as shown, which comprises a substrate 100, and a buffer layer 110, an N-type semiconductor layer 120, a first stress buffer layer 130, a first long-wave light emitting well layer 140, a current spreading layer 150, a second stress buffer layer 160, a second short-wave light emitting well layer 170 and a P-type semiconductor layer, which are sequentially stacked on the surface of the substrate 100. The P-type semiconductor layer can include an electron blocking layer 180 on the surface of the second short-wave light emitting well layer 170, and a P-type GaN layer 190 on the surface of the electron blocking layer 180.

[0040] The substrate 100 can include a material with excellent heat conduction, and can include a conductive substrate or an insulating substrate. For example, the substrate 100 can include at least one of sapphire (Al2O3), SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge and Ga2O3.

[0041] A light reflection pattern is provided to enhance light extraction efficiency. The patterned substrate 100 applied in a light emitting diode can enhance light extraction efficiency. For example, a regularly arranged pattern is constructed on a sapphire substrate 100 to enhance light extraction efficiency. The pattern can be composed of at least one of Al2O3, SiO2, TiO2.

[0042] The buffer layer 110 is formed on the substrate 100 to reduce the lattice mismatch between the first long-wave light emitting well layer 140 and the substrate 100 due to different materials. For example, the buffer layer 110 can be formed by at least one of III-V compound semiconductors, such as GaN, InN, AlN, InGaN, AlGaN, InAlGaN and AlInN, but is not limited thereto. The N-type semiconductor layer 120 is formed on the buffer layer 110.

[0043] It can be understood that the light emitting wavelength of the first long-wave light emitting well layer 140 is greater than that of the second short-wave light emitting well layer 170. For example, the first long-wave light emitting well layer 140 is a green light well, the second short-wave light emitting well layer 170 is a blue light well, and the dual-wavelength LED chip is a high color gamut blue-green eutectic chip. The peak wavelength of the first long-wave is 440-465 nm, and the peak wavelength of the second short-wave is 520-545 nm.

[0044] The first stress buffer layer 130 includes a plurality of InGaN first sub-layers 131, and the In content in the InGaN first sub-layers 131 gradually increases from the N-type semiconductor layer 120 to the P-type semiconductor layer.

[0045] And / or, the second stress buffer layer 160 includes several InGaN second sub-layers 161, and the In content in the InGaN second sub-layers 161 gradually increases from the substrate 100 to the P-type semiconductor layer.

[0046] The double-wavelength LED chip provided by the application can improve the V-pits cluster and the crystal quality of the blue light trap and / or the green light trap, and reduce the dislocation density, by growing the pre-strain layer In in an incremental form before the blue light trap and / or the green light trap.

[0047] The gradual change of the In component from low to high in the first stress buffer layer 130 and / or the second stress buffer layer 160 can improve the InGaN / GaN stress release and relieve the QCSE, and can improve the V-pits cluster in the AFM test observation.

[0048] In some specific embodiments, the first stress buffer layer 130 includes 2-20 InGaN first sub-layers 131.

[0049] In some specific embodiments, the second stress buffer layer 160 includes 2-20 InGaN second sub-layers 161.

[0050] In some specific embodiments, the In content in the InGaN first sub-layers 131 gradually increases from the N-type semiconductor layer 120 to the P-type semiconductor layer. This is conducive to further improving the light efficiency of the double-wavelength LED chip.

[0051] In some specific embodiments, the In content in the InGaN second sub-layers 161 gradually increases from the N-type semiconductor layer 120 to the P-type semiconductor layer. This is conducive to further improving the light efficiency of the double-wavelength LED chip.

[0052] In some specific embodiments, the highest In content in the first stress buffer layer 130 is greater than the highest In content in the second stress buffer layer 160, Figure 2 The In concentration diagram of the double-wavelength LED chip provided by the present embodiment is shown in FIG. 2. Figure 2As shown, along the semiconductor growth direction, a first stress buffer layer 130, a first long-wavelength light-emitting well layer 140, and a current spreading layer 150 are first grown, followed by the growth of a second stress buffer layer and a second short-wavelength light-emitting well layer 170. The first stress buffer layer 130 contains 2 to 10 InGaN first sublayers 131 and GaN third sublayers 132, with the In content of the first sublayer gradually increasing along the semiconductor growth direction. The second stress buffer layer 160 contains 2 to 8 InGaN second sublayers 161 and GaN fourth sublayers 162, with the In content of the second sublayer gradually increasing along the semiconductor growth direction. The main reason for this is that the first long-wavelength light-emitting well layer 140 has a longer wavelength than the second short-wavelength light-emitting well layer 170, resulting in a relatively higher In content. The first stress buffer layer 130 and the second stress buffer layer 160 primarily alleviate the stress of the light-emitting layer; therefore, the first stress buffer layer 130 has a higher In content.

[0053] That is, the In content in the first InGaN sublayer 131, which has the highest In content, is greater than the In content in the second InGaN sublayer 161, which also has the highest In content. In other words, the highest In concentration point in the first stress buffer layer 130 is greater than the highest In concentration point in the second stress buffer layer 160.

[0054] The second short-wavelength luminescent well layer 170 includes an alternating stacked InGaN second barrier layer 171 and an InGaN second well layer 172. This invention optimizes the barrier structure design of the blue light-emitting well by using low-In-content InGaN instead of GaN as the quantum barrier (replacing the pure GaN barrier layer in traditional single-wavelength blue light MQWS). This reduces the lattice mismatch between the well layer and the barrier layer in the second short-wavelength luminescent well layer 170, significantly increasing the luminescence quality of the blue light-emitting active region. Simultaneously, compared to the traditional GaN blue light quantum well structure, it further reduces the barrier height, facilitating the entry of more holes into the second short-wavelength luminescent well layer 170 (blue light well), thus increasing the luminescence performance of the second short-wavelength luminescent well layer 170. This solves the problem of low luminescence efficiency in blue light-emitting wells.

[0055] In some specific implementation methods, such as Figure 3 The schematic diagram of the In concentration of the dual-wavelength LED chip provided in this embodiment shows that the first stress buffer layer 130 includes 2 to 8 InGaN first sub-layers 131, and the In content in the InGaN first sub-layers 131 gradually increases in the direction from the N-type semiconductor layer 120 to the P-type semiconductor layer; the second stress buffer layer 160 includes 2 to 10 InGaN second sub-layers 161, and the In content in the InGaN second sub-layers 161 remains basically unchanged in the direction from the N-type semiconductor layer 120 to the P-type semiconductor layer.

[0056] In some specific implementation methods, such as Figure 4The double-wavelength LED chip In concentration diagram provided by the embodiment shown, the first stress buffer layer 130 includes 2-8 layers of InGaN first sub-layers 131, and the In content in the InGaN first sub-layers 131 remains basically unchanged from the direction of the N-type semiconductor layer 120 to the P-type semiconductor layer; the second stress buffer layer 160 includes 2-10 layers of InGaN second sub-layers 161, and the In content in the InGaN second sub-layers 161 gradually increases from the direction of the N-type semiconductor layer 120 to the P-type semiconductor layer. The number of layers of the InGaN second sub-layers 161 is higher than the number of layers of the InGaN first sub-layers 131, the In content of part of the second sub-layers is lower than the In content of the first sub-layers, the In content of another part of the second sub-layers is higher than the In content of the first sub-layers, and the total thickness of the second stress buffer layer 160 is greater than the total thickness of the first stress buffer layer 130.

[0057] In some specific embodiments, referring to Figure 5 As shown, the In element concentration in the InGaN second barrier layer 171 in the second short-wave light emitting well layer 170 is 0.05-0.1 of the In element concentration in the InGaN second well layer 172, including but not limited to any one of the point values of 0.05, 0.06, 0.07, 0.08, 0.09, 0.1 or a range value between any two of them.

[0058] In some specific embodiments, the first long-wave light emitting well layer 140 includes GaN first barrier layers 141 and InGaN first well layers 142 arranged in an alternating cycle and stacked.

[0059] In some specific embodiments, the first stress buffer layer 130 includes GaN third sub-layers 132 and the InGaN first sub-layers 131 arranged in an alternating cycle and stacked; preferably, the number of layers of the InGaN first sub-layers 131 is 2-20 layers, such as 2 layers, 3 layers, 5 layers, 8 layers, 10 layers, 13 layers, 15 layers, 18 layers or 20 layers.

[0060] In some specific embodiments, the second stress buffer layer 160 includes GaN fourth sub-layers 162 and the InGaN second sub-layers 161 arranged in an alternating cycle and stacked; preferably, the number of layers of the InGaN second sub-layers 161 is 2-20 layers, such as 2 layers, 3 layers, 5 layers, 8 layers, 10 layers, 13 layers, 15 layers, 18 layers or 20 layers.

[0061] Referring to Figure 6 The morphology under AFM measurement for the first stress buffer layer 130 without using In incremental growth; Figure 7 The morphology under AFM measurement for the first stress buffer layer 130 with In incremental growth. As can be seen, Figure 6The AFM image of the LED chip has more V-pits cluster phenomenon (the part in the circle) Figure 6 The AFM image of the LED chip has more V-pits cluster phenomenon (the part in the circle) Figure 7 The V-pits cluster phenomenon is reduced under the AFM test by using the wafer source with the increasing In growth, and the V-pits are uniformly distributed, thereby improving the light emitting uniformity of the light emitting diode.

[0062] In some specific embodiments, the Si average doping concentration of the current spreading layer 150 is ≥ 2×10 17 atoms / cm 3 and ≤ 3×10 19 atoms / cm 3 .

[0063] In some specific embodiments, the current spreading layer 150 comprises a low-doped layer and a high-doped layer, and the ratio of the Si average doping concentration of the high-doped layer to the Si average doping concentration of the low-doped layer is ≥ 2.

[0064] In some specific embodiments, the dual-wavelength LED chip further comprises a P electrode 22 and an N electrode 21, wherein the P electrode 22 is electrically connected with the P-type semiconductor layer, and the N electrode 21 is electrically connected with the N-type semiconductor layer 120.

[0065] Further, the application also provides a preparation method of the above-mentioned dual-wavelength LED chip, comprising the following steps:

[0066] The N-type semiconductor layer 120, the first stress buffer layer 130, the first long-wave light emitting well layer 140, the current spreading layer 150, the second stress buffer layer 160, the second short-wave light emitting well layer 170 and the P-type semiconductor layer are sequentially grown on the surface of the substrate 100.

[0067] The dual-wavelength LED chip prepared by the method has good crystal quality, and the V-pits cluster phenomenon and the QCSE (quantum confinement Stark effect) phenomenon are improved.

[0068] In some specific embodiments, the growth temperature of the first stress buffer layer 130 is 750-800 ℃, including but not limited to any one of 750 ℃, 760 ℃, 770 ℃, 780 ℃, 790 ℃, 800 ℃ or a range value between any two of them.

[0069] In some specific embodiments, the growth temperature of the second stress buffer layer 160 is 780-830 ℃, including but not limited to any one of 780 ℃, 790 ℃, 800 ℃, 810 ℃, 820 ℃, 830 ℃ or a range value between any two of them.

[0070] Although the present application has been described and illustrated with a certain degree of particularity, it is understood that the present application has been made by way of examples only and that numerous changes in the details of execution can be made by those skilled in the art without departing from the spirit and scope of the application. It is therefore intended to cover in the appended claims all such changes and modifications that come within the scope of the application.

Claims

1. A dual-wavelength LED chip, characterized in that, It includes an N-type semiconductor layer, a first stress buffer layer, a first long-wavelength light-emitting trap layer, a current spreading layer, a second stress buffer layer, a second short-wavelength light-emitting trap layer, and a P-type semiconductor layer; The first stress buffer layer includes several InGaN first sub-layers, and the In content in the InGaN first sub-layers gradually increases in the direction from the N-type semiconductor layer to the P-type semiconductor layer. And / or, the second stress buffer layer includes several InGaN second sub-layers, and the In content in the InGaN second sub-layers gradually increases in the direction from the N-type semiconductor layer to the P-type semiconductor layer.

2. The dual-wavelength LED chip according to claim 1, characterized in that, The In content in the first sublayer of InGaN increases in a gradient.

3. The dual-wavelength LED chip according to claim 1, characterized in that, The In content in the second sublayer of InGaN increases in a gradient.

4. The dual-wavelength LED chip according to claim 1, characterized in that, The highest In content in the first stress buffer layer is greater than the highest In content in the second stress buffer layer.

5. The dual-wavelength LED chip according to claim 1, characterized in that, The second short-wavelength light-emitting well layer comprises an alternating stacked InGaN second barrier layer and an InGaN second well layer; Preferably, the In element concentration in the InGaN second barrier layer is 0.05 to 0.1 times the In element concentration in the InGaN second well layer.

6. The dual-wavelength LED chip according to any one of claims 1 to 5, characterized in that, The first long-wavelength light-emitting well layer includes alternating GaN first barrier layers and InGaN first well layers stacked in a circular fashion.

7. The dual-wavelength LED chip according to any one of claims 1 to 5, characterized in that, The first stress buffer layer comprises an alternately stacked GaN third sublayer and the InGaN first sublayer; Preferably, the number of layers in the first InGaN sublayer is 2 to 20.

8. The dual-wavelength LED chip according to any one of claims 1 to 5, characterized in that, The second stress buffer layer comprises an alternately stacked GaN fourth sublayer and the InGaN second sublayer; Preferably, the number of layers in the second InGaN sublayer is 2 to 20.

9. The dual-wavelength LED chip according to claim 1, characterized in that, The average Si doping concentration of the current spreading layer is ≥2×10⁻⁶. 17 atoms / cm 3 And ≤3×10 19 atoms / cm 3 .

10. The dual-wavelength LED chip according to claim 1, characterized in that, The current spreading layer comprises a low-doped layer and a high-doped layer, wherein the ratio of the average Si doping concentration of the high-doped layer to the average Si doping concentration of the low-doped layer is ≥2.

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