A processor power consumption dynamic control system

Abstract

The application discloses a processor power consumption dynamic control system, which comprises a core request control unit, a state control module, an output control module and a register module. The core request control unit converts an output signal of a processor core, a current power consumption state of the state control module and a wake-up signal from a system interrupt module into a power consumption state which the processor core needs to enter; the state control module uses a state machine and a power consumption state request output by the core request control unit to realize dynamic switching of the power consumption state of the processor core; the output control module dynamically and flexibly configures a power consumption control process of different processor cores through configuration parameters of the register module, so as to meet power consumption control requirements of different processor cores; and the register module comprises various control and state registers, so as to realize flexible control of the power consumption of the processor core. The application realizes real-time dynamic adjustment of the power consumption state of each core in a multi-core heterogeneous processor.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and in particular to a processor power consumption dynamic control system. Background Technology

[0002] With the widespread application of multi-core heterogeneous processors in high-performance computing, artificial intelligence, and the Internet of Things, power management has become a key challenge in improving system energy efficiency. Traditional processor power management schemes are usually based on static strategies, which are difficult to meet the differentiated power state switching requirements of different cores in a multi-core system. Different cores in a multi-core processor have significantly different timing requirements for power signals, which may prevent the system from optimizing power management according to core characteristics.

[0003] In complex systems, software configuration requests and hardware automatic switching requests may occur simultaneously, and existing technologies lack clear priority rules. For example, when software attempts to force a power state switch, load-based automatic switching by hardware may cause conflicts, leading to system instability or power management failure.

[0004] Traditional solutions typically power on all cores by default during system startup, resulting in excessively high overall power consumption during the boot phase. This is especially problematic in large-scale multi-core systems, where peak power consumption during startup can significantly impact energy efficiency. The lack of a mechanism to dynamically disable low-power states is a significant concern in certain applications (such as real-time task processing), where ensuring continuous core operation is crucial to avoid performance fluctuations. However, current technologies cannot dynamically prevent cores from entering low-power states, leading to unnecessary power switching and performance degradation.

[0005] To address the aforementioned issues, there is an urgent need for a configurable dynamic power consumption hardware management architecture that can achieve dynamic power consumption control for multi-core heterogeneous processors through multi-level power states, priority management, flexible timing control, and interrupt linkage mechanisms. Summary of the Invention

[0006] The purpose of this invention is to provide a processor power consumption dynamic control system to solve the problems in the background art.

[0007] To address the aforementioned technical problems, this invention provides a processor power consumption dynamic control system, comprising: a core request control unit, a status control module, an output control module, and a register module;

[0008] The core request control unit converts the processor core's output signal, the current power consumption state of the state control module, and the wake-up signal from the system interrupt module into the power consumption state that the processor core needs to enter.

[0009] The state control module uses a state machine and, based on the power consumption state request output by the core request control unit, realizes dynamic switching of the processor core's power consumption state.

[0010] Since different processor cores have different timing processes for the control signals for power state switching, the output control module dynamically and flexibly configures the power control process of different processor cores through the configuration parameters of the register module to meet the power control requirements of different processor cores.

[0011] The register module includes various control registers and status registers to achieve flexible control over the processor core power consumption; among them,

[0012] The control registers include a power consumption status control register, a delay register and a holding register, an interrupt enable register, a DEV_OFF_DISABLE register, and a SYS_POWER_ON register.

[0013] The register module sets a power consumption state control register to control the switching of power consumption states in the state control module; when the power consumption state control register is configured, the state control module switches from the current power consumption state to the power consumption state control register state.

[0014] During the design, the priority of the power state control register being configured is higher than the priority of the power switching generated by the core request control unit. When the power state control register is being configured and the core request control unit generates a power state switching request at the same time, the power state switching of the power state control register is executed first. If the output control module is executing the power switching generated by the core request control unit, the power state control register is configured at this time. During the design, it is ensured that the power state control module executes the power state switching of the power state control register only after the output control module has completed the power switching generated by the core request control unit.

[0015] In one implementation, the core request control unit converts the processor core's output signal into a power consumption state and then sends it to the state control module. The state control module implements four power consumption states: DEV_OFF, DEV_OFF_SIM, DEV_ON, and DEV_WARM_RST. core_pvalid and core_pack are handshake signals between the core request control unit and the state control module. When both core_pvalid and core_pack are high, the core request control unit sends the power consumption state to the state control module via core_pstate.

[0016] In one implementation, the core request control unit sends the power consumption state to the state control module via core_pstate, including the following steps:

[0017] Step 1: When the state control module is in the DEV_OFF state, if the wake request signal from the system interrupt module is high or the interface signal DBGPWRUPREQ of the processor core is high, the power consumption state is switched to DEV_ON; otherwise, the power consumption state remains DEV_OFF.

[0018] Step 2: When the state control module is in the DEV_OFF_SIM state, if the wake request signal from the system interrupt module is high, the power consumption state switches to DEV_ON; if the processor core interface signal DGBNOPWRDWN is low and DBGPWRUPREQ is low, the power consumption state switches to DEV_ON; if the above conditions are not met, the power consumption state remains DEV_OFF_SIM.

[0019] Step 3: When the state control module is in the DEV_ON state,

[0020] Step 3.1: Under the conditions that the processor core interface signal SMPEN is low, the processor core interface signal STANDBYWFI is high, and the configuration signal r_dev_pd_en from the top level is high:

[0021] When DBGPWRUPREQ is high or DBGNOPWRDWN is high, the power consumption state transitions to DEV_OFF_SIM;

[0022] When both DBGPWRUPREQ and DBGNOPWRDWN are low, the power consumption state transitions to DEV_OFF;

[0023] Step 3.2: When the processor core's interface signal DBGRSTREQ is high or WARMRSTREQ and STANDBYWFI are high, the power consumption state transitions to DEV_WARM_RST;

[0024] If the conditions in steps 3.1 and 3.2 are not met, the power consumption state transitions to DEV_ON;

[0025] Step 4: When the state control module is in the DEV_WARM_RST state, design the warm_rst_cnt counter; warm_rst_cnt remains 0 and does not count when the state control module is not in the DEV_WARM_RST state; when the state control module is in the DEV_WARM_RST state, warm_rst_cnt starts counting, and when warm_rst_cnt counts to RESETn_HOLD_TIME, warm_rst_cnt remains unchanged at RESETn_HOLD_TIME; when the state control module is in the DEV_WARM_RST state and warm_rst_cnt is greater than or equal to RESETn_HOLD_TIME, the power consumption state is switched to DEV_ON, otherwise it remains in DEV_WARM_RST.

[0026] In one implementation, the core request control unit outputs a dev_active signal. This dev_active signal is synchronized by a synchronization unit and then sent to the DBGPWRDUP port of the processor core. The dev_active signal is also connected to the system interrupt module, which uses this signal to determine whether the processor core is in a normal operating state or a low-power state. The system interrupt module then determines whether to send certain interrupt requests to the current processor core. Finally, the system interrupt module sends a wake-up request to the core request control unit, thereby waking up the processor core.

[0027] In one implementation, the register module includes a SYS_POWER_ON register, which indicates whether the current processor core needs to be powered on when the chip starts up. The default value of the SYS_POWER_ON register needs to be determined based on whether the processor core needs to be powered on when the system starts up: if the processor core needs to be powered on when the system starts up, the default value of SYS_POWER_ON is set to high level; if the processor core does not need to be powered on when the system starts up, the default value of SYS_POWER_ON is set to low level.

[0028] When the system starts up, if SYS_POWER_ON is high, the state control module performs a DEV_OFF switch to the DEV_ON state; when the system starts up, if SYS_POWER_ON is low, the state control module maintains the default DEV_OFF state; by configuring the default value of the SYS_POWER_ON register of some cores to be low, the power consumption of the whole chip during startup is reduced.

[0029] In one implementation, the register module supports configuring the DEV_OFF and DEV_OFF_SIM states of the shutdown state control module; the configuration method is as follows:

[0030] The register module is designed with the DEV_OFF_DISABLE register. When DEV_OFF_DISABLE is enabled, even if the processor core requires a power shutdown, the state control module will maintain the current power consumption state and will not switch to the DEV_OFF or DEV_OFF_SIM state. When DEV_OFF_DISABLE is disabled and the processor core requires a power shutdown, the state control module will automatically switch to the DEV_OFF or DEV_OFF_SIM state according to the processor core's needs.

[0031] The DEV_OFF_DISABLE register is used to control whether the processor core will automatically shut down its power supply for a certain period of time, ensuring that the processor core continues to run to avoid performance fluctuations.

[0032] In one implementation, the output control module records the current power consumption state and the power consumption state to be switched to, and then outputs control signals; the output control module outputs the following signals: PWRUP, ISOLATEn, CLKEN, and RESETn; PWRUP is the processor core power-on / off control signal; ISOLATEn is the processor core isolation control signal; CLKEN is the processor core clock enable signal; RESETn is the processor core reset signal;

[0033] pvalid and pack are handshake signals between the state control module and the output control module, used to control the transmission of the pstate signal; pstate is the power consumption status signal output by the state control module, and the output control module is designed to store the power consumption status register.

[0034] The control process of the output control module is as follows: when pvalid and pack are both high, the output control module updates pstate to its internal power status register; after detecting the update of the power status register, the output control module maintains the levels of PWRUP, ISOLATEn, CLKEN, and RESETn before the update of the power status register.

[0035] When the power status register is updated to DEV_ON, DEV_OFF, and DEV_OFF_SIM, PWRUP, ISOLATEn, CLKEN, and RESETn will remain at the level required for the current power status until the next update of the power status register.

[0036] In one embodiment, the power consumption state control register is used to control the power consumption state of the state control module, the delay register is used to control the delay of the output signal of the output control module, the holding register is used to control the holding time of the RESETn signal of the output control module in the DEV_WARM_RST power consumption state, the interrupt enable register is used to control whether the interrupt unit in the register module generates an interrupt, the DEV_OFF_DISABLE register is used to control whether the power consumption state of the state control module enters the DEV_OFF state or the DEV_OFF_SIM state, and the SYS_POWER_ON register is used to control whether the processor core is powered on when the chip starts.

[0037] The present invention provides a processor power consumption dynamic control system, which, through the collaborative work and multi-parameter configuration of the core request control unit, state control module, output control module and register module, constructs a dynamic, flexible, low-latency and highly adaptable multi-core heterogeneous processor power consumption management system, providing a key technical solution for energy efficiency optimization in high-performance computing scenarios. Attached Figure Description

[0038] Figure 1 This is an overall structural diagram of the present invention;

[0039] Figure 2 This is a power consumption state switching diagram of the state control module of the present invention. Detailed Implementation

[0040] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the processor power consumption dynamic control system proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0041] The overall structure of the present invention is as follows Figure 1 As shown, the system includes a core request control unit, a state control module, an output control module, and a register module. The core request control unit converts the processor core's output signals, the current power consumption state of the state control module, and the wake-up signal from the system interrupt module into the power consumption state the processor core needs to enter. The state control module uses a state machine to automatically switch power consumption states. Since different processor cores have different timing sequences for power consumption state switching control signals, the output control module can dynamically and flexibly configure the power consumption control flow for different processor cores through delay registers and holding registers in the register module, meeting the power consumption control requirements of different processor cores. The register module is designed with various control and status registers to achieve flexible control of the processor core's power consumption.

[0042] The core request control unit (CPU) converts the processor core's output signals into power states and then sends them to the status control module. `core_pvalid` and `core_pack` are handshake signals between the CPU and the status control module. When both `core_pvalid` and `core_pack` are high, the CPU sends the power states to the status control module via `core_pstate`.

[0043] The interface signals of the processor core are shown in Table 1:

[0044] Table 1 Interface Signals of the Processor Core

[0045] signal name direction describe DBGRSTREQ Output Warm Reset request; WARMRSTREQ Output 0: Do not enable Warm Reset; 1: Enable Warm Reset; SMPEN Output 0: Indicates the kernel is not executing a coherency consistency request; 1: Indicates the kernel is executing a coherency consistency request. STANDBYWFI Output Indicates whether the core is in a WFI low-power state: 0: The core is not in a low-power state; 1: The core is in a low-power state. DBGWRUPREQ Output 0: Core power-on not required; 1: Core power-on required; DBGNOPWRDWN Output 0: Core not required to be powered on; 1: Core required to be powered on; DBGPWRDUP enter 0. Core not powered on 1. Core powered on

[0046] The state control module sends its current power consumption status to the core request control unit via the pstate signal. The core request control unit outputs the core_pstate power consumption status. The design and implementation are as follows:

[0047] 1. When the state control module is in the DEV_OFF state, if the wakerequest signal from the system interrupt module is high or the processor core interface signal DBGPWRUPREQ is high, the power consumption state will switch to DEV_ON; otherwise, the power consumption state will remain in the DEV_OFF state.

[0048] 2. When the state control module is in the DEV_OFF_SIM state, if the wake request signal from the system interrupt module is high, the power consumption state will switch to DEV_ON; if the processor core interface signal DGBNOPWRDWN is low and DBGPWRUPREQ is low, the power consumption state will switch to DEV_ON; if the above conditions are not met, the power consumption state will remain in DEV_OFF_SIM.

[0049] 3. When the status control module is in the DEV_ON state,

[0050] 3.1. Under the conditions that the processor core interface signal SMPEN is low, the processor core interface signal STANDBYWFI is high, and the configuration signal r_dev_pd_en from the top level is high:

[0051] When DBGPWRUPREQ is high or DBGNOPWRDWN is high, the power consumption state transitions to DEV_OFF_SIM;

[0052] When both DBGPWRUPREQ and DBGNOPWRDWN are low, the power consumption state transitions to DEV_OFF.

[0053] 3.2. When the processor core interface signal DBGRSTREQ is high or WARMRSTREQ and STANDBYWFI are high, the power consumption state transitions to DEV_WARM_RST.

[0054] If conditions 3.1 and 3.2 are not met, the power consumption state transitions to DEV_ON.

[0055] 4. When the state control module is in the DEV_WARM_RST state, a warm_rst_cnt counter is designed. warm_rst_cnt remains 0 and does not count when the state control module is not in the DEV_WARM_RST state. When the state control module is in the DEV_WARM_RST state, warm_rst_cnt starts counting. When warm_rst_cnt counts to RESETn_HOLD_TIME, warm_rst_cnt remains unchanged at RESETn_HOLD_TIME. When the state control module is in the DEV_WARM_RST state and warm_rst_cnt is greater than or equal to RESETn_HOLD_TIME, the power consumption state transitions to DEV_ON; otherwise, it remains in DEV_WARM_RST.

[0056] The aforementioned power consumption status will be sent to the status control module via the core_pstate signal.

[0057] The core request control unit outputs a `dev_active` signal. This signal, synchronized by the synchronization unit, is then sent to the processor core's DBGPWRDUP port. Simultaneously, the `dev_active` signal connects to the system interrupt module, which uses this signal to determine whether the processor core is in normal operation or a low-power state. The system interrupt module then determines whether to send certain interrupt requests to the current processor core. The system interrupt module can also send a wake-up request to the core request control unit, thereby waking up the processor core.

[0058] The state control module implements four power consumption states: DEV_OFF, DEV_OFF_SIM, DEV_ON, and DEV_WARM_RST.

[0059] DEV_WARM_RST: Performs a Warm Reset on the logic of the processor core, and the logic and RAM in the processor core are powered on.

[0060] DEV_ON: The logic and RAM in the processor core are powered on, and the processor core is working normally.

[0061] DEV_OFF_SIM: The logic and RAM in the processor core are in a powered-on state. This state is used to simulate the conditions for entering DEV_OFF without powering down.

[0062] DEV_OFF: The logic and RAM in the processor core are in a power-off state.

[0063] The four power consumption state codes are shown in Table 2:

[0064] Table 2. Power Consumption State Codes

[0065] Power consumption status Power state coding DEV_WARM_RST 4’b1000 DEV_ON 4’b0100 DEV_OFF_SIM 4’b0010 DEV_OFF 4’b0001

[0066] A higher power state code value indicates a higher priority. Power state transitions are as follows: Figure 2 As shown:

[0067] Arrows indicate that a power state can be directly switched to another power state. If there is no arrow connecting two states, it means that a state cannot be directly switched to another state.

[0068] DEV_OFF is the default power consumption state of the state control module.

[0069] The register module includes a SYS_POWER_ON register, which indicates whether the current processor core needs to be powered on during chip startup. The default value of the SYS_POWER_ON register is determined based on whether the processor core needs to be powered on during system startup. If the processor core needs to be powered on during system startup, the default value of SYS_POWER_ON is set to high; if the processor core does not need to be powered on during system startup, the default value of SYS_POWER_ON is set to low. During system startup, if SYS_POWER_ON is high, the state control module will execute a DEV_OFF switch to the DEV_ON state. During system startup, if SYS_POWER_ON is low, the state control module maintains the DEV_OFF default state. By configuring the default value of the SYS_POWER_ON register for some cores to be low, the overall chip power consumption during startup is reduced.

[0070] The register module configures the power consumption state control register, which controls the power consumption state switching within the state control module. When configuring the power consumption state control register, the state control module switches from the current power consumption state to the power consumption state control register state. During design, the power consumption state control register being configured has a higher priority than the power consumption switching priority generated by the core request control unit. When the power consumption state control register is being configured and the core request control unit simultaneously generates a power consumption state switching request, the power consumption state switching of the power consumption state control register is executed first. If the output control module is executing a power consumption switching request generated by the core request control unit, and the power consumption state control register is configured at this time, the design ensures that the state control module executes the power consumption state switching of the power consumption state control register only after the output control module has completed executing the power consumption switching request generated by the core request control unit.

[0071] Supports configuring the DEV_OFF and DEV_OFF_SIM states. The configuration method is as follows: The register module is designed with the DEV_OFF_DISABLE register. When DEV_OFF_DISABLE is enabled, even if the processor core requires a power-off, the state control module maintains the current power consumption state and will not switch to the DEV_OFF or DEV_OFF_SIM state. When DEV_OFF_DISABLE is disabled and the processor core requires a power-off, the state control module will automatically switch to the DEV_OFF or DEV_OFF_SIM state according to the processor core's needs. Using the DEV_OFF_DISABLE register, the processor core can be controlled to not automatically power off for a certain period of time. In some application scenarios (such as multi-core real-time task processing), this can ensure the processor core continues to run to avoid performance fluctuations.

[0072] The output control module records the current power consumption state and the power consumption state to be switched to, and then outputs a control signal. Since different processing cores, GPU cores, and NPU cores have different timing procedures and requirements for the control signals for power consumption state switching, a dynamic and flexible output control module was designed.

[0073] The output control module outputs the following signals: PWRUP, ISOLATEn, CLKEN, and RESETn. PWRUP is the processor core power-on / off control signal; ISOLATEn is the processor core isolation control signal; CLKEN is the processor core clock enable signal; and RESETn is the processor core reset signal.

[0074] `pvalid` and `pack` are handshake signals between the state control module and the output control module, used to control the transmission of the `pstate` signal. `pstate` is the power consumption status signal output by the state control module. The output control module is designed to store the power consumption status in a register.

[0075] PWRUP_DELAY_TIME, ISOTLATEn_DELAY_TIME, CLKEN_DELAY_TIME, RESETn_DELAY_TIME, and RESETn_HOLD_TIME are registers included in the register module, used to control the timing of the output signals of the output control module. Among them, PWRUP_DELAY_TIME, ISOTLATEn_DELAY_TIME, CLKEN_DELAY_TIME, and RESETn_DELAY_TIME are used to control the delay, and RESETn_HOLD_TIME is used to control the hold time of the reset signal RESETn in the DEV_WARM_RST power consumption state.

[0076] The control process of the output control module is as follows: When both pvalid and pack are high, the output control module updates pstate to the power consumption status register inside the output control module. After detecting the update of the power consumption status register, the output control module maintains the levels of PWRUP, ISOFLATEn, CLKEN, and RESETn at the levels before the update of the power consumption status register. The specific holding time is configured by PWRUP_DELAY_TIME, ISOFLATEn_DELAY_TIME, CLKEN_DELAY_TIME, and RESETn_DELAY_TIME. After PWRUP, ISOFLATEn, CLKEN, and RESETn reach the holding time, they automatically switch to the output level required by the current power consumption state, as shown in Table 3.

[0077] Table 3. Output Levels Required for Power Consumption Status

[0078] DEV_ON DEV_WARM_RST DEV_OFF DEV_OFF_SIM PWRUP 1 1 0 0 ISOLATEn 1 1 0 0 CLKEN 1 1 0 0 RESETN 1 0 0 0

[0079] When the power status register is updated to DEV_ON, DEV_OFF, and DEV_OFF_SIM, PWRUP, ISOLATEn, CLKEN, and RESETn will remain at the output level required for the current power status until the next update of the power status register. When the power status register is updated to DEV_WARM_RST, the low-level holding time of the RESETn output is configured according to RESETn_HOLD_TIME. After the time set by RESETn_HOLD_TIME is reached, RESETn automatically switches to outputting a high level.

[0080] The output control module dynamically configures to meet the power consumption control requirements of different processor cores. It is particularly suitable for situations where different processor cores in a multi-core heterogeneous processor have different timing requirements for power consumption control, clock control, and reset control.

[0081] The register module includes a bus interface unit, control registers, status registers, and an interrupt unit. The bus interface unit performs the conversion of bus signals to register signals.

[0082] The control registers include a power consumption status control register, delay registers (PWRUP_DELAY_TIME, ISOLATEn_DELAY_TIME, CLKEN_DELAY_TIME, RESETn_DELAY_TIME) and holding register (RESETn_HOLD_TIME), interrupt enable register, DEV_OFF_DISABLE register and SYS_POWER_ON register.

[0083] The power consumption status control register controls the power consumption status of the status control module. The delay register controls the delay of the output signals from the output control module. The hold register controls the hold time of the output control module's RESETn signal in the DEV_WARM_RST power consumption state. The interrupt enable register controls whether the interrupt unit in the register module generates an interrupt. The DEV_OFF_DISABLE register controls whether the status control module's power consumption status enters the DEV_OFF or DEV_OFF_SIM state. The SYS_POWER_ON register controls whether the processor core powers on during chip startup.

[0084] Status registers: including the power consumption status register. The power consumption status register is used to store the current power consumption status of the status control module.

[0085] Interrupt Unit: When the output control module outputs a control signal, the interrupt unit triggers an interrupt. The specific implementation is as follows: After the register module determines that both the pstate and pack interface signals are high, it uses a counter to count. When the counter reaches the configured maximum delay value, an interrupt is triggered.

[0086] The register module enables flexible control of the processor core's power consumption status by designing various control registers and status registers.

[0087] The working process of this invention is as follows:

[0088] When the chip boots up, the register module sends the default configuration of the SYS_POWER_ON register corresponding to the current processor core to the status control module. If the default value of the SYS_POWER_ON register is set to low, the status control module will maintain the DEV_OFF power consumption state. If the default value of the SYS_POWER_ON register is set to high, meaning the current processor core needs to be powered on during chip boot, the status control module will switch the power consumption state from DEV_OFF to DEV_ON. The status control module sends the DEV_ON state to the output control module via pstate and handshake signals. The output control module first registers the DEV_ON state, and then, based on the delay values ​​of PWRUP_DELAY_TIME, ISOLATEn_DELAY_TIME, CLKEN_DELAY_TIME, and RESETn_DELAY_TIME in the register module and the level that the output signal of the output control module needs to switch to, generates the timing sequence of the PWRUP, ISOLATEn, CLKEN, and RESETn control signals to complete the power-on process for the current processor core.

[0089] When the chip is operating normally, the core request control unit monitors the current processor core's output signals, the current power consumption state of the state control module, and the wake-up signal from the system interrupt module in real time. The core request control unit converts the processor core's output signals, the current power consumption state of the state control module, and the wake-up signal from the system interrupt module into the power consumption state that the processor core needs to enter. The specific power consumption state conversion method of the core request control unit is detailed in the design and implementation steps of the output signal `core_pstate`. The core request control unit sends the power consumption state to the state control module via `core_pstate` and its handshake signal. When `core_pstate` switches to the `DEV_ON` power consumption state, the core request control unit outputs a high level `dev_active`. This `dev_active` signal is synchronized by the synchronization unit and then sent to the processor core's `DBGPWRDUP` port (a high level on the `DBGPWRDUP` port indicates the core is powered on, and a low level indicates the core is not powered on). The `dev_active` signal is also connected to the system interrupt module, which uses this signal to determine whether the current processor core is in a normal operating state or a low-power state. The system interrupt module then determines whether to send an interrupt request to the current processor core. The processor core supports interrupt wake-up functionality. The system interrupt module can send an interrupt wake-up request to the core request control unit. When the state control module is in the DEV_OFF power state and the core request control unit receives a high-level wake request sent by the system interrupt module, the core_pstate output by the core request control unit switches from the DEV_OFF state to the DEV_ON power state. Then, the state control module and the output control module switch to the DEV_ON power state, completing the entire process from the system interrupt module sending the interrupt wake request to the processor core power-on.

[0090] The state control module implements four power consumption states: DEV_OFF, DEV_OFF_SIM, DEV_ON, and DEV_WARM_RST, with DEV_OFF being the default. When the power consumption state control register in the register module is configured and the output control module has completed a previous power consumption control switch, the state control module switches from the current power consumption state to the power consumption state control register state. Upon receiving the core_pstate and handshake signals, the state control module determines: 1. Whether the power consumption state control register in the register module is currently being updated; 2. Whether the output control module has completed a previous power consumption control switch. If the power consumption state control register is not currently being updated and the output control module has completed a previous power consumption control switch, the state control module switches the current power consumption state to the power consumption state requested by the core request control unit via the power consumption state machine. After the power consumption state machine of the state control module completes the power consumption state transition, it sends the transitioned power consumption state to the output control module via pstate and handshake signals. The output control module first registers the pstate power consumption state, and then, based on: 1. the delay values ​​of PWRUP_DELAY_TIME, ISOTLATEn_DELAY_TIME, CLKEN_DELAY_TIME, and RESETn_DELAY_TIME in the register module; 2. the RESETn_HOLD_TIME in the register module, which controls the hold time of RESETn in the DEV_WARM_RST power consumption state; and 3. the level that the output signal of the output control module needs to switch to, it finally generates the timing sequence of the PWRUP, ISOTLATEn, CLKEN, and RESETn control signals to complete the power consumption switching process of the current processor core.

[0091] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A processor power consumption dynamic control system, characterized in that, include: The core components include a request control unit, a status control module, an output control module, and a register module. The core request control unit converts the processor core's output signal, the current power consumption state of the state control module, and the wake-up signal from the system interrupt module into the power consumption state that the processor core needs to enter. The state control module uses a state machine and, based on the power consumption state request output by the core request control unit, realizes dynamic switching of the processor core's power consumption state. Since different processor cores have different timing processes for the control signals for power state switching, the output control module dynamically and flexibly configures the power control process of different processor cores through the configuration parameters of the register module to meet the power control requirements of different processor cores. The register module includes various control registers and status registers to achieve flexible control over the processor core power consumption; among them, The control registers include a power consumption status control register, a delay register and a holding register, an interrupt enable register, a DEV_OFF_DISABLE register, and a SYS_POWER_ON register. The register module sets a power consumption state control register to control the switching of power consumption states in the state control module; when the power consumption state control register is configured, the state control module switches from the current power consumption state to the power consumption state control register state. During the design, the priority of the power state control register being configured is higher than the priority of the power switching generated by the core request control unit. When the power state control register is being configured and the core request control unit generates a power state switching request at the same time, the power state switching of the power state control register is executed first. If the output control module is executing the power switching generated by the core request control unit, the power state control register is configured at this time. During the design, it is ensured that the power state control module executes the power state switching of the power state control register only after the output control module has completed the power switching generated by the core request control unit.

2. The processor power consumption dynamic control system as described in claim 1, characterized in that, The core request control unit converts the processor core's output signal into a power consumption state and then sends it to the state control module. The state control module implements four power consumption states: DEV_OFF, DEV_OFF_SIM, DEV_ON, and DEV_WARM_RST. core_pvalid and core_pack are handshake signals between the core request control unit and the state control module. When both core_pvalid and core_pack are high, the core request control unit sends the power consumption state to the state control module via core_pstate.

3. The processor power consumption dynamic control system as described in claim 2, characterized in that, The core request control unit sends the power consumption status to the status control module via core_pstate, including the following steps: Step 1: When the state control module is in the DEV_OFF state, if the wake request signal from the system interrupt module is high or the interface signal DBGPWRUPREQ of the processor core is high, the power consumption state is switched to DEV_ON; otherwise, the power consumption state remains DEV_OFF. Step 2: When the state control module is in the DEV_OFF_SIM state, if the wake request signal from the system interrupt module is high, the power consumption state switches to DEV_ON; if the processor core interface signal DGBNOPWRDWN is low and DBGPWRUPREQ is low, the power consumption state switches to DEV_ON; if the above conditions are not met, the power consumption state remains DEV_OFF_SIM. Step 3: When the state control module is in the DEV_ON state, Step 3.1: Under the conditions that the processor core interface signal SMPEN is low, the processor core interface signal STANDBYWFI is high, and the configuration signal r_dev_pd_en from the top level is high: When DBGPWRUPREQ is high or DBGNOPWRDWN is high, the power consumption state transitions to DEV_OFF_SIM; When both DBGPWRUPREQ and DBGNOPWRDWN are low, the power consumption state transitions to DEV_OFF; Step 3.2: When the processor core's interface signal DBGRSTREQ is high or WARMRSTREQ and STANDBYWFI are high, the power consumption state transitions to DEV_WARM_RST; If the conditions in steps 3.1 and 3.2 are not met, the power consumption state transitions to DEV_ON; Step 4: When the state control module is in the DEV_WARM_RST state, design the warm_rst_cnt counter; warm_rst_cnt remains 0 and does not count when the state control module is not in the DEV_WARM_RST state; when the state control module is in the DEV_WARM_RST state, warm_rst_cnt starts counting, and when warm_rst_cnt counts to RESETn_HOLD_TIME, warm_rst_cnt remains unchanged at RESETn_HOLD_TIME; when the state control module is in the DEV_WARM_RST state and warm_rst_cnt is greater than or equal to RESETn_HOLD_TIME, the power consumption state is switched to DEV_ON, otherwise it remains in DEV_WARM_RST.

4. The processor power consumption dynamic control system as described in claim 1, characterized in that, The core request control unit outputs a dev_active signal, which is then synchronized by the synchronization unit and sent to the DBGPWRDUP port of the processor core. The dev_active signal is connected to the system interrupt module on the other hand. The system interrupt module uses this signal to determine whether the current processor core is in a normal working state or a low power state. The system interrupt module determines whether to send certain interrupt requests to the current processor core; The system interrupt module sends a wake-up request to the core request control unit, thereby waking up the processor core.

5. The processor power consumption dynamic control system as described in claim 4, characterized in that, The register module includes a SYS_POWER_ON register, which indicates whether the current processor core needs to be powered on when the chip starts up. The default value of the SYS_POWER_ON register needs to be determined based on whether the processor core needs to be powered on when the system starts up: if the processor core needs to be powered on when the system starts up, the default value of SYS_POWER_ON is set to high level; if the processor core does not need to be powered on when the system starts up, the default value of SYS_POWER_ON is set to low level. When the system starts up, if SYS_POWER_ON is high, the state control module performs a DEV_OFF switch to the DEV_ON state; when the system starts up, if SYS_POWER_ON is low, the state control module maintains the default DEV_OFF state; by configuring the default value of the SYS_POWER_ON register of some cores to be low, the power consumption of the whole chip during startup is reduced.

6. The processor power consumption dynamic control system as described in claim 1, characterized in that, The register module supports configuring the DEV_OFF and DEV_OFF_SIM states of the shutdown control module; the configuration method is as follows: The register module is designed with the DEV_OFF_DISABLE register. When DEV_OFF_DISABLE is enabled, even if the processor core requires a power shutdown, the state control module will maintain the current power consumption state and will not switch to the DEV_OFF or DEV_OFF_SIM state. When DEV_OFF_DISABLE is disabled and the processor core requires a power shutdown, the state control module will automatically switch to the DEV_OFF or DEV_OFF_SIM state according to the processor core's needs. The DEV_OFF_DISABLE register is used to control whether the processor core will automatically shut down its power supply for a certain period of time, ensuring that the processor core continues to run to avoid performance fluctuations.

7. The processor power consumption dynamic control system as described in claim 1, characterized in that, The output control module records the current power consumption state and the power consumption state to be switched to, and then outputs control signals. The output control module outputs the following signals: PWRUP, ISOLATEn, CLKEN, and RESETn; PWRUP is the processor core power-on / off control signal; ISOLATEn is the processor core isolation control signal; CLKEN is the processor core clock enable signal; and RESETn is the processor core reset signal. pvalid and pack are handshake signals between the state control module and the output control module, used to control the transmission of the pstate signal; pstate is the power consumption status signal output by the state control module, and the output control module is designed to store the power consumption status register. The control process of the output control module is as follows: when pvalid and pack are both high, the output control module updates pstate to its internal power status register; after detecting the update of the power status register, the output control module maintains the levels of PWRUP, ISOLATEn, CLKEN, and RESETn before the update of the power status register. When the power status register is updated to DEV_ON, DEV_OFF, and DEV_OFF_SIM, PWRUP, ISOLATEn, CLKEN, and RESETn will remain at the level required for the current power status until the next update of the power status register.

8. The processor power consumption dynamic control system as described in claim 1, characterized in that, The power consumption state control register is used to control the power consumption state of the state control module. The delay register is used to control the delay of the output signal of the output control module. The holding register is used to control the holding time of the RESETn signal of the output control module in the DEV_WARM_RST power consumption state. The interrupt enable register is used to control whether the interrupt unit in the register module generates an interrupt. The DEV_OFF_DISABLE register is used to control whether the power consumption state of the state control module enters the DEV_OFF state or the DEV_OFF_SIM state. The SYS_POWER_ON register is used to control whether the processor core is powered on when the chip starts.

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