Data processing method and device, computer device, storage medium and program product

Abstract

The application relates to a data processing method and device, computer equipment, a storage medium and a program product, and relates to the technical field of artificial intelligence chips. The application can reduce the hardware design burden of a chip while reducing the data reading bandwidth pressure of the chip. The method comprises the following steps: obtaining a control instruction, the control instruction being used for indicating the data to be broadcast and the target calculation unit to be broadcast required by each calculation unit in a chain connection in a chip; in response to the control instruction, each calculation unit reads the data to be broadcast from the memory and broadcasts the read data to the target calculation unit; wherein the data channel of each calculation unit in the target direction through which the data to be broadcast passes is configured to transmit the data to be broadcast; the target direction is the direction of the calculation unit pointing to the corresponding target calculation unit; and the data to be broadcast is shared by the calculation unit and the corresponding target calculation unit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of artificial intelligence chips, in particular to a data processing method and device, computer equipment, a storage medium and a program product. BACKGROUND

[0002] Matrix multiplication is a common and important operator in the fields of linear algebra, deep learning and large models. Due to its importance in various application fields, optimization designs for matrix multiplication are often present in the architecture design of various chips including artificial intelligence chips. Among them, artificial intelligence chips are hardware chips specially designed and optimized for artificial intelligence tasks, including but not limited to GPUs (Graphics Processing Unit), NPUs (Neural Network Processing Unit), and GPGPUs (General-Purpose computing on Graphics Processing Unit).

[0003] Due to the high cost of high-bandwidth memory of chips, the performance bottleneck of operators such as matrix multiplication is often on the bandwidth of reading data. In the traditional technology, when running operators such as matrix multiplication in the chip, each computing unit of the chip needs to independently read data from the memory. The same data used for operator operations in the memory will be read twice, and there is a technical problem of high data reading bandwidth pressure. SUMMARY

[0004] Therefore, it is necessary to provide a data processing method, device, computer equipment, storage medium and program product to solve the above technical problems.

[0005] In a first aspect, the present application provides a data processing method, comprising:

[0006] obtaining a control instruction; wherein the control instruction is used to indicate the data to be broadcast and the target computing unit to be broadcast for each computing unit in a chain connection in a chip;

[0007] In response to the control instruction, controlling each computing unit to read the data to be broadcast from the memory and broadcast the read data to the target computing unit; wherein the data channel of each computing unit in the target direction through which the data to be broadcast passes is configured to transmit the data to be broadcast; the target direction is the direction of the computing unit pointing to the corresponding target computing unit; and the data to be broadcast is shared by the computing unit and the corresponding target computing unit.

[0008] In a second aspect, the present application also provides a data processing apparatus, comprising:

[0009] an obtaining module, configured to obtain a control instruction; wherein the control instruction is used to indicate data to be broadcast and a target computing unit to which the data to be broadcast needs to be broadcast by each computing unit in a chain connection in a chip;

[0010] a control module, configured to control each computing unit to read the data to be broadcast from the memory and broadcast the read data to the target computing unit in response to the control instruction; wherein a data channel of each computing unit in a target direction through which the data to be broadcast passes is configured to transmit the data to be broadcast; the target direction is a direction in which the computing unit points to the corresponding target computing unit; and the data to be broadcast is shared by the computing unit and the corresponding target computing unit.

[0011] In a third aspect, a computer device is also provided, comprising a memory and a processor, the memory stores a computer program, and the processor implements the steps in the above method when executing the computer program.

[0012] In a fourth aspect, a computer readable storage medium is provided, which stores a computer program, and the computer program is executed by a processor to implement the steps in the above method.

[0013] In a fifth aspect, a computer program product is provided, comprising a computer program, and the computer program is executed by a processor to implement the steps in the above method.

[0014] The above data processing method, apparatus, computer device, storage medium and program product, obtain a control instruction, the control instruction is used to indicate data to be broadcast and a target computing unit to which the data to be broadcast needs to be broadcast by each computing unit in a chain connection in a chip, control each computing unit to read the data to be broadcast from the memory and broadcast the read data to the target computing unit in response to the control instruction; wherein a data channel of each computing unit in a target direction through which the data to be broadcast passes is configured to transmit the data to be broadcast; the target direction is a direction in which the computing unit points to the corresponding target computing unit; and the data to be broadcast is shared by the computing unit and the corresponding target computing unit. Thus, the scheme is applied to a chip comprising chain-connected computing units, which can reduce the hardware design burden of the chip, and by reading the data to be broadcast by each computing unit from the memory and broadcasting the data to the corresponding target computing unit, it can avoid the same data in the memory for matrix multiplication and other operator operations being read twice, reduce the data reading bandwidth pressure of the chip, and achieve the effect of reducing the hardware design burden of the chip while reducing the data reading bandwidth pressure of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application or the related art. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other related drawings can also be obtained on the basis of these drawings without creative effort.

[0016] Figure 1 An application environment diagram of the data processing method in an embodiment;

[0017] Figure 2 A schematic diagram of the data processing method in some technologies;

[0018] Figure 3 A schematic diagram of the full connection mode of the computing units in a chip;

[0019] Figure 4 A schematic diagram of the chain connection mode of the computing units in a chip;

[0020] Figure 5 A schematic diagram of the data processing method in some other technologies;

[0021] Figure 6 A flowchart of the data processing method in an embodiment;

[0022] Figure 7 A schematic diagram of the data processing method in an embodiment;

[0023] Figure 8 A schematic diagram of the data processing method in another embodiment;

[0024] Figure 9 A schematic diagram of the data processing method in yet another embodiment;

[0025] Figure 10 A structural block diagram of the data processing apparatus in an embodiment;

[0026] Figure 11 An internal structure diagram of the computer device in an embodiment. DETAILED DESCRIPTION

[0027] In order to make the objects, technical solutions and advantages of the present application clearer, the following will further describe the present application with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0028] It should be noted that the terms "first", "second", etc. used in the present application can be used to describe various objects, but these objects are not limited by these terms. These terms are only used to distinguish the first object from the second object. The terms "include" and "have" and any variations thereof used in the present application are intended to cover non-exclusive inclusion. The term "a plurality of" used in the present application refers to two or more. The term "and / or" used in the present application refers to one of the options or any combination of the options.

[0029] The data processing method provided by the embodiments of the present application can be applied to an application environment as shown in Figure 1 The chip can be an artificial intelligence chip, which includes but is not limited to a GPU (Graphics Processing Unit), an NPU (Neural Network Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Unit). The data processing method provided by the embodiments of the present application can be executed by an artificial intelligence chip. The chip as shown in Figure 1 The chip can include a computing cluster and a memory. The computing cluster can include a plurality of computing units connected in a chain. The computing unit is an independent computing component in the chip, and a GPU or the like generally provides computing capability by a plurality of computing units. Each computing unit can include a tensor core (also referred to as a matrix multiplication computing unit), a vector computing unit, an instruction control unit, and a shared memory. The shared memories of two computing units connected in a chain can be connected, and the shared memory of each computing unit can be connected to the memory of the chip. The memory in the chip can include a high-bandwidth memory HBM.

[0030] As shown in Figure 2 Four computing units of the GPU need to calculate the results of four different parts of a matrix multiplication C=AxB, respectively. During the calculation process, the data of a partial matrix A and a partial matrix B will be needed as input data by different computing units. In the conventional technology, each computing unit needs to independently read a copy of the data of the matrix A and a copy of the data of the matrix B, and all the data of the matrix A and the matrix B will be read twice.

[0031] To this end, broadcast read is an available way to read more input data in matrix multiplication operation with limited bandwidth. Hardware can allow users to broadcast data to other compute units while loading a piece of data in a compute unit by providing a data channel between the instruction and the compute unit, so as to reduce the overall read pressure on high-bandwidth memory when there is a need to read repeated data between different compute units, so as to improve the average read bandwidth of each compute unit. Thus, in the related art of broadcast read, each small matrix block can be further divided into two blocks of the same size, and the compute unit reads one of the two and broadcasts the data to another compute unit that also needs the data, while the other compute unit reads the other half of the data and broadcasts it to the current compute unit. Specifically, as shown in Figure 2 , compute unit 1 and compute unit 2 both need data A1, which is divided into two equal-sized data A11 and A12. Compute unit 1 reads data A11 and broadcasts A11 to compute unit 2, and compute unit 2 reads data A12 and broadcasts A12 to compute unit 1. Other data A2, B1 and B2 are also divided, read and broadcast in a similar manner. Thus, from the perspective of reading from the video memory, the data of matrix A and matrix B is read twice without broadcast read, and the video memory is read only once with broadcast read, greatly reducing the video memory bandwidth pressure.

[0032] However, the above broadcast read related art needs to rely on the full connection of the data channel between different compute units, that is, there is an independent data channel between different compute units that can communicate with each other without being affected by other data units. Based on the current design process, it is difficult to implement such a connection mode, and a large amount of hardware area resources will be consumed for data broadcast.

[0033] Compared with the above full connection connection mode in the hardware design of chips such as GPU, chain connection is a simpler connection mode, in which Figure 3 a schematic diagram of full connection is shown, Figure 4 a schematic diagram of chain connection is shown, and the chain connection mode can greatly reduce the number of data channels between compute units, thereby simplifying the design difficulty and hardware area occupation number of chips such as GPU.

[0034] However, although chain connection can greatly reduce the hardware design burden, it also introduces the bottleneck problem of broadcast bandwidth. Still taking the above four compute units for matrix multiplication as an example, as shown in Figure 5As shown, the data of the matrix A needs to be broadcasted between the computing units 1 and 2, and the data of the matrix B needs to be broadcasted between the computing units 3 and 4. At this time, because independent data channels are used, the bandwidths are not contended. However, when the data of the matrix B is loaded, because the data needs to be broadcasted between the computing units 1 and 3, and between the computing units 2 and 4, and because there is no direct data channel between the computing units 1 and 3 or between the computing units 2 and 4, the data needs to be forwarded through the intermediate computing units. Specifically, because there is no direct data channel between the computing units 1 and 3, the data needs to be forwarded through the computing unit 2. Because there is no direct data channel between the computing units 2 and 4, the data needs to be forwarded through the computing unit 3. In the forwarding process, the bidirectional data channel between the computing units 2 and 3 is used by two different computing units, which halves the bandwidth available for broadcasting of each computing unit and affects the performance of broadcasting.

[0035] In one example embodiment, as shown in Figure 6 a data processing method is provided, which can be performed by a chip as shown in Figure 1 The method can include the following steps:

[0036] In step S601, a control instruction is obtained.

[0037] The chip can receive the control instruction from an external hardware such as a CPU. The control instruction can be used to indicate the data to be broadcasted and the target computing unit to which the data is to be broadcasted for each computing unit in the chain connection. The data to be broadcasted can be shared by the computing unit reading the data and the target computing unit to which the data is to be broadcasted. For example, the computing unit 1 can read the data A1 of the matrix A from the memory as the data to be broadcasted, and the target computing unit to which the data is to be broadcasted can be the computing unit 2. The computing unit 1 and the computing unit 2 can share the data A1 of the matrix A, for example, the computing unit 1 can use the data A1 of the matrix A to multiply the data B1 of the matrix B to obtain the corresponding calculation result C1, and the computing unit 2 can use the data A1 of the matrix A to multiply the data B2 of the matrix B to obtain the corresponding calculation result C2, and so on. For the control instruction, an assembly instruction can be used. The bitmask can be added to the assembly instruction for loading data to control which computing unit or computing units the current computing unit needs to broadcast the loaded data to. Each bit of the bitmask can be used to identify the target computing unit to which the data is to be broadcasted, for example, the nth bit from the low bit being 1 represents that the data needs to be broadcasted to the nth computing unit, and 0 represents that the data is not broadcasted. For example, 0b0011 represents that the data is broadcasted to the computing units 0 and 1, 0b1100 represents that the data is broadcasted to the computing units 2 and 3, and so on. The chip can be as shown inFigure 1 the instruction control units in each of the computing units to execute the control instructions of the corresponding computing units.

[0038] In step S602, in response to the control instructions, each of the computing units reads the respective to-be-broadcast data from the memory and broadcasts the read to-be-broadcast data to the destination computing unit.

[0039] In this step, each of the computing units can read the respective to-be-broadcast data from the memory and also broadcast the read to-be-broadcast data to the corresponding destination computing unit. Wherein, the data channel of each computing unit in the target direction through which the to-be-broadcast data passes is configured to transmit the to-be-broadcast data, and the target direction is the direction in which the computing unit points to the corresponding destination computing unit. In this regard, for each of the chain-connected computing units, two data channels can be included between the two connected computing units, and the two data channels correspond to different directions. Assuming that the direction from the computing unit 1 to the computing unit N (the last computing unit) is the first direction, and the direction from the computing unit N to the computing unit 1 is the second direction, thus the two connected computing units can include a data channel in the first direction and a data channel in the second direction. In this step, for the two data channels between the two connected computing units, each data channel can be configured to transmit at most one to-be-broadcast data. Therefore, when, for example, one computing unit broadcasts one to-be-broadcast data to the destination computing unit, the computing units through which the to-be-broadcast data passes can be one or more, and the data channel of the one or more computing units in the target direction (the first direction or the second direction) is configured to transmit the to-be-broadcast data.

[0040] Thus, in the case of limited hardware design conditions, the data content that each of the computing units needs to calculate can be adjusted, so as to change the data distribution that needs to be loaded by different computing units, so as to fully utilize the broadcast bandwidth, and to avoid the existence of bandwidth bottleneck in the data path, so as to cause other paths to be fully utilized.

[0041] For the embodiment of the present application, assuming that the number of data in the matrices A and B is M: A1=A2=B1=B2=M, and the one-way bandwidth of the data channel for broadcasting between the computing units is b, then the time consumption during broadcasting can be represented as M / b. According to the related art described above, the data in the matrices A and B is loaded respectively after being divided, and the time consumption for broadcasting is (M / 2) / b+(M / 2) / (b / 2)=3M / 2b, because there is a bottleneck in part of the data loading process, so the total time consumption is longer.

[0042] The embodiment can enable each computing unit of the chain connection to load respective to-be-broadcast data and make full use of each available data channel, while any data channel can be used by only one computing unit to broadcast its to-be-broadcast data, and the entire data flow process will not cause other data channels on the same path to be underutilized due to excessive congestion of a part of data channels.

[0043] The data processing method of the embodiment acquires a control instruction, which is used to indicate to-be-broadcast data required to be read by each computing unit of the chain connection in the chip and a target computing unit required to be broadcast by each computing unit. In response to the control instruction, each computing unit reads respective to-be-broadcast data from the memory and broadcasts the read to-be-broadcast data to the target computing unit. Each computing unit in a target direction through which the to-be-broadcast data passes is configured to transmit the to-be-broadcast data. The target direction is a direction in which the computing unit points to the corresponding target computing unit. The to-be-broadcast data is shared by the computing unit and the corresponding target computing unit. Thus, the scheme is applied to a chip including computing units in chain connection, can reduce the hardware design burden of the chip, and through the manner that each computing unit reads respective to-be-broadcast data from the memory and broadcasts the to-be-broadcast data to the corresponding target computing unit, can avoid the same data used for matrix multiplication or other operator operations in the memory being read twice, reduce the data read bandwidth pressure of the chip, and achieve the effect of reducing the hardware design burden of the chip while reducing the data read bandwidth pressure of the chip.

[0044] In an exemplary embodiment, the to-be-broadcast data read by the computing unit from the memory belongs to first part operation data or second part operation data. The first part operation data and the second part operation data are used to perform target operations.

[0045] In this embodiment, the target operation can include a matrix multiplication operation, and the input data of the matrix multiplication operation can include two parts of operation data, which can be denoted as a first part of operation data and a second part of operation data. For example, for the matrix multiplication operation C = A x B, the matrix A can correspond to the first part of operation data, and the matrix B can correspond to the second part of operation data. Further, the matrix A can be split into data A1 and A2, and the data A1 and A2 of the matrix A belong to the first part of operation data. The matrix B can be split into data B1 and B2, and the data B1 and B2 of the matrix B belong to the second part of operation data. The first part of operation data and the second part of operation data can be used to perform the target operation, and the data split from the first part of operation data and the second part of operation data can be used to perform partial operations of the target operation. Thus, the to-be-broadcast data read from the memory by the computing unit can be data belonging to the first part of operation data or data belonging to the second part of operation data. The to-be-broadcast data read by the computing unit can be used to perform a partial operation of the target operation when the corresponding data is received, and can also be used to be broadcast to a destination computing unit for performing another partial operation of the target operation. Therefore, in the scheme of this embodiment, each computing unit does not need to read two parts of operation data of the target operation, and each computing unit can obtain the corresponding input data required for performing a partial operation of the target operation based on the broadcasting manner of the chain-connected computing units.

[0046] In one exemplary embodiment, further, the first part of operation data includes first sub-data and second sub-data, and the second part of operation data includes third sub-data and fourth sub-data. The chip includes a chain-connected first computing unit, a second computing unit, a third computing unit, and a fourth computing unit. Specifically, the target operation can be a matrix multiplication operation, the first part of operation data can be a matrix A, and the second part of operation data can be a matrix B. The first part of operation data A can be split into first sub-data and second sub-data, the first sub-data can be denoted as A1, and the second sub-data can be denoted as A2. The second part of operation data B can be split into third sub-data B1 and fourth sub-data B2. The first computing unit, the second computing unit, the third computing unit, and the fourth computing unit can be denoted as computing units 1 to 4, respectively.

[0047] Thus, in response to the control instruction in step S602, the control of the computing units to read the respective to-be-broadcast data from the memory and broadcast the read to-be-broadcast data to the destination computing unit can include:

[0048] In response to a control command, the first computing unit is controlled to read first sub-data from memory and broadcast the first sub-data to the second computing unit via a data channel in a first direction; in response to a control command, the second computing unit is controlled to read fourth sub-data from memory and broadcast the fourth sub-data to the third computing unit via a data channel in a first direction, and the third sub-data broadcast by the third computing unit is broadcast to the first computing unit via a data channel in a second direction; in response to a control command, the third computing unit is controlled to read third sub-data from memory and broadcast the third sub-data to the second computing unit via a data channel in a second direction, and the fourth sub-data broadcast by the second computing unit is broadcast to the fourth computing unit via a data channel in a first direction; in response to a control command, the fourth computing unit is controlled to read second sub-data from memory and broadcast the second sub-data to the third computing unit via a data channel in a second direction.

[0049] like Figure 7 As shown, specifically, control computing unit 1 reads first sub-data A1 from memory and broadcasts it to computing unit 2 via a data channel in the first direction; control computing unit 2 reads fourth sub-data B2 from memory and broadcasts it to computing unit 3 via a data channel in the first direction, and broadcasts third sub-data B1 broadcast by computing unit 3 to computing unit 1 via a data channel in the second direction; control computing unit 3 reads third sub-data B1 from memory and broadcasts it to computing unit 2 via a data channel in the second direction, and broadcasts fourth sub-data B2 broadcast by computing unit 2 to computing unit 4 via a data channel in the first direction; control computing unit 4 reads second sub-data A2 from memory and broadcasts it to computing unit 3 via a data channel in the second direction. Therefore, computing unit 1 can calculate C1 = A1 × B1, computing unit 2 can calculate C2 = A1 × B2, computing unit 3 can calculate C3 = A2 × B1, and computing unit 4 can calculate C4 = A2 × B2.

[0050] The bandwidth bottleneck in some technologies mainly comes from the two computing units that need to broadcast. Since the sub-data shared by the two computing units is further divided into two equal parts, bidirectional broadcasting is needed. Computing unit 1 needs to broadcast data to computing unit 2, and at the same time, computing unit 2 needs to broadcast data to computing unit 1, which will introduce too much data flow and cause a bandwidth bottleneck. In the scheme of the embodiment, the complete sub-data can be loaded by one computing unit. By adjusting the data distribution and broadcasting mode between different computing units, the bottleneck problem caused by mutual broadcasting of data flow under the chain broadcasting topology can be reduced, and the same data channel can be avoided from being occupied by different computing units. In the embodiment, the entire process can load matrix A and matrix B at the same time and fully utilize each available data channel. At the same time, any data channel will only be used by one computing unit. During the entire data flow process, no other data channel on the same path will be underutilized due to excessive congestion of a part of the data channel.

[0051] In an exemplary embodiment, the first portion of operation data includes first sub-data and second sub-data; the second portion of operation data includes third sub-data, fourth sub-data, fifth sub-data, and sixth sub-data; and the chip includes a chain-connected first computing unit, a second computing unit, a third computing unit, a fourth computing unit, a fifth computing unit, a sixth computing unit, a seventh computing unit, and an eighth computing unit.

[0052] Specifically, the target operation can be a matrix multiplication operation, the first portion of operation data can be a matrix A, and the second portion of operation data can be a matrix B. The first portion of operation data A can be divided into first sub-data A1 and second sub-data A2. The second portion of operation data B can be divided into third sub-data B1, fourth sub-data B2, fifth sub-data B3, and sixth sub-data B4. The first computing unit, the second computing unit, the third computing unit, the fourth computing unit, the fifth computing unit, the sixth computing unit, the seventh computing unit, and the eighth computing unit can be denoted as computing units 1 to 8, respectively.

[0053] Therefore, the step S602 of controlling each computing unit to read the respective to-be-broadcast data from the memory and broadcasting the read to-be-broadcast data to the destination computing unit in response to the control instruction can include:

[0054] In response to the control instruction, the first computing unit is controlled to read the first sub-data from the memory and broadcast the first sub-data to the second computing unit through the data channel in the first direction; in response to the control instruction, the second computing unit is controlled to read the fourth sub-data from the memory and broadcast the fourth sub-data to the third computing unit through the data channel in the first direction, and broadcast the third sub-data broadcasted by the third computing unit to the first computing unit through the data channel in the second direction; in response to the control instruction, the third computing unit is controlled to read the third sub-data from the memory and broadcast the third sub-data to the second computing unit through the data channel in the second direction, and broadcast the fourth sub-data broadcasted by the second computing unit to the fourth computing unit through the data channel in the first direction; in response to the control instruction, the fourth computing unit is controlled to read the second sub-data from the memory and broadcast the second sub-data to the third computing unit through the data channel in the second direction, and broadcast the second sub-data to the fifth computing unit through the data channel in the first direction; in response to the control instruction, the fifth computing unit is controlled to broadcast the second sub-data broadcasted by the fourth computing unit to the sixth computing unit through the data channel in the first direction; in response to the control instruction, the sixth computing unit is controlled to read the fifth sub-data from the memory and broadcast the fifth sub-data to the seventh computing unit through the data channel in the first direction, and broadcast the sixth sub-data broadcasted by the seventh computing unit to the fifth computing unit through the data channel in the second direction; in response to the control instruction, the seventh computing unit is controlled to read the sixth sub-data from the memory and broadcast the sixth sub-data to the sixth computing unit through the data channel in the second direction, and broadcast the fifth sub-data broadcasted by the sixth computing unit to the eighth computing unit through the data channel in the first direction; in response to the control instruction, the eighth computing unit is controlled to read the first sub-data from the memory and broadcast the first sub-data to the seventh computing unit through the data channel in the second direction.

[0055] As Figure 8As shown, specifically, the control computing unit 1 reads the first sub-data A1 from the memory, and broadcasts the first sub-data A1 to the computing unit 2 through the data channel in the first direction, the control computing unit 2 reads the fourth sub-data B2 from the memory, and broadcasts the fourth sub-data B2 to the computing unit 3 through the data channel in the first direction, and broadcasts the third sub-data B1 broadcasted by the computing unit 3 to the computing unit 1 through the data channel in the second direction, the control computing unit 3 reads the third sub-data B1 from the memory, and broadcasts the third sub-data B1 to the computing unit 2 through the data channel in the second direction, and broadcasts the fourth sub-data B2 broadcasted by the computing unit 2 to the computing unit 4 through the data channel in the first direction, the control computing unit 4 reads the second sub-data A2 from the memory, and broadcasts the second sub-data A2 to the computing unit 3 through the data channel in the second direction, and broadcasts the second sub-data A2 to the computing unit 5 through the data channel in the first direction, the control computing unit 5 broadcasts the second sub-data A2 broadcasted by the computing unit 4 to the computing unit 6 through the data channel in the first direction, the control computing unit 6 reads the fifth sub-data B3 from the memory, and broadcasts the fifth sub-data B3 to the computing unit 7 through the data channel in the first direction, and broadcasts the sixth sub-data B4 broadcasted by the computing unit 7 to the computing unit 5 through the data channel in the second direction, the control computing unit 7 reads the sixth sub-data B4 from the memory, and broadcasts the sixth sub-data B4 to the computing unit 6 through the data channel in the second direction, and broadcasts the fifth sub-data B3 broadcasted by the computing unit 6 to the computing unit 8 through the data channel in the first direction, the control computing unit 8 reads the first sub-data A1 from the memory, and broadcasts the first sub-data A1 to the computing unit 7 through the data channel in the second direction. Thus, the computing unit 1 can calculate C1=A1×B1, the computing unit 2 can calculate C2=A1×B2, the computing unit 3 can calculate C3=A2×B1, the computing unit 4 can calculate C4=A2×B2, the computing unit 5 can calculate C5=A2×B4, the computing unit 6 can calculate C6=A2×B3, the computing unit 7 can calculate C=A1×B4, and the computing unit 8 can calculate C8=A1×B3. Among them, because there is no direct broadcast data channel between the computing unit 1 and 3, it is needed to be forwarded through the computing unit 2, because there is no direct broadcast data channel between the computing unit 2 and 4, it is needed to be forwarded through the computing unit 3, because there is no direct broadcast data channel between the computing unit 5 and 7, it is needed to be forwarded through the computing unit 6, and because there is no direct broadcast data channel between the computing unit 6 and 8, it is needed to be forwarded through the computing unit 7. In this way, the broadcast path is used by at most one operation, and there is no bottleneck caused by bandwidth preemption.In this embodiment, since there is no direct connection between the computing units 1 and 8, broadcasting the first sub-data A1 can cause high delay and affect the broadcasting of other data if the link is too long. Therefore, the first sub-data A1 can not be broadcasted but reloaded by the computing unit 8.

[0056] In one exemplary embodiment, the first partial operation data includes first sub-data and second sub-data, the second partial operation data includes third sub-data, fourth sub-data, fifth sub-data and sixth sub-data, and the chip includes a chain of first computing unit, second computing unit, third computing unit, fourth computing unit, fifth computing unit, sixth computing unit, seventh computing unit and eighth computing unit.

[0057] Specifically, the target operation can be a matrix multiplication operation, the first partial operation data can be a matrix A, and the second partial operation data can be a matrix B. The first partial operation data A can be split into first sub-data A1 and second sub-data A2, and the second partial operation data B can be split into third sub-data B1, fourth sub-data B2, fifth sub-data B3 and sixth sub-data B4. The first computing unit, the second computing unit, the third computing unit, the fourth computing unit, the fifth computing unit, the sixth computing unit, the seventh computing unit and the eighth computing unit can be denoted as computing units 1 to 8, respectively.

[0058] Therefore, the step S602 of controlling each computing unit to read the respective to-be-broadcast data from the memory and broadcast the read to-be-broadcast data to the destination computing unit in response to the control instruction can include:

[0059] In response to the control instruction, the first computing unit is controlled to read the first sub-data from the memory and broadcast the first sub-data to the second computing unit through the data channel in the first direction; in response to the control instruction, the second computing unit is controlled to read the fourth sub-data from the memory and broadcast the fourth sub-data to the third computing unit through the data channel in the first direction, and broadcast the third sub-data broadcasted by the third computing unit to the first computing unit through the data channel in the second direction; in response to the control instruction, the third computing unit is controlled to read the third sub-data from the memory and broadcast the third sub-data to the second computing unit through the data channel in the second direction, and broadcast the fourth sub-data broadcasted by the second computing unit to the fourth computing unit through the data channel in the first direction; in response to the control instruction, the fourth computing unit is controlled to read the second sub-data from the memory and broadcast the second sub-data to the third computing unit through the data channel in the second direction; in response to the control instruction, the fifth computing unit is controlled to read the second sub-data from the memory and broadcast the second sub-data to the sixth computing unit through the data channel in the first direction; in response to the control instruction, the sixth computing unit is controlled to read the fifth sub-data from the memory and broadcast the fifth sub-data to the seventh computing unit through the data channel in the first direction, and broadcast the sixth sub-data broadcasted by the seventh computing unit to the fifth computing unit through the data channel in the second direction; in response to the control instruction, the seventh computing unit is controlled to read the sixth sub-data from the memory and broadcast the sixth sub-data to the sixth computing unit through the data channel in the second direction, and broadcast the fifth sub-data broadcasted by the sixth computing unit to the eighth computing unit through the data channel in the first direction; in response to the control instruction, the eighth computing unit is controlled to read the first sub-data from the memory and broadcast the first sub-data to the seventh computing unit through the data channel in the second direction.

[0060] As Figure 9As shown, specifically, the control computing unit 1 reads the first sub-data A1 from the memory, and broadcasts the first sub-data A1 to the computing unit 2 through the data channel in the first direction, the control computing unit 2 reads the fourth sub-data B2 from the memory, and broadcasts the fourth sub-data B2 to the computing unit 3 through the data channel in the first direction, and broadcasts the third sub-data B1 broadcasted by the computing unit 3 to the computing unit 1 through the data channel in the second direction, the control computing unit 3 reads the third sub-data B1 from the memory, and broadcasts the third sub-data B1 to the computing unit 2 through the data channel in the second direction, and broadcasts the fourth sub-data B2 broadcasted by the computing unit 2 to the computing unit 4 through the data channel in the first direction, the control computing unit 4 reads the second sub-data A2 from the memory, and broadcasts the second sub-data A2 to the computing unit 3 through the data channel in the second direction, the control computing unit 5 reads the second sub-data A2 from the memory, and broadcasts the second sub-data A2 to the computing unit 6 through the data channel in the first direction, the control computing unit 6 reads the fifth sub-data B3 from the memory, and broadcasts the fifth sub-data B3 to the computing unit 7 through the data channel in the first direction, and broadcasts the sixth sub-data B4 broadcasted by the computing unit 7 to the computing unit 5 through the data channel in the second direction, the control computing unit 7 reads the sixth sub-data B4 from the memory, and broadcasts the sixth sub-data B4 to the computing unit 6 through the data channel in the second direction, and broadcasts the fifth sub-data B3 broadcasted by the computing unit 6 to the computing unit 8 through the data channel in the first direction, the control computing unit 8 reads the first sub-data A1 from the memory, and broadcasts the first sub-data A1 to the computing unit 7 through the data channel in the second direction. Thus, the computing unit 1 can calculate C1=A1×B1, the computing unit 2 can calculate C2=A1×B2, the computing unit 3 can calculate C3=A2×B1, the computing unit 4 can calculate C4=A2×B2, the computing unit 5 can calculate C5=A2×B4, the computing unit 6 can calculate C6=A2×B3, the computing unit 7 can calculate C=A1×B4, and the computing unit 8 can calculate C8=A1×B3. Among them, because there is no direct broadcasting data channel between the computing unit 1 and 3, it is needed to be forwarded through the computing unit 2, because there is no direct broadcasting data channel between the computing unit 2 and 4, it is needed to be forwarded through the computing unit 3, because there is no direct broadcasting data channel between the computing unit 5 and 7, it is needed to be forwarded through the computing unit 6, and because there is no direct broadcasting data channel between the computing unit 6 and 8, it is needed to be forwarded through the computing unit 7. In this regard, the broadcasting path is used by at most one operation, and there is no bottleneck caused by bandwidth preemption. In the scheme of the embodiment, eight computing units can be divided into two groups, and for the matrix shared by the two groups (for example, the matrix A in the example), the two groups load respectively without broadcasting sharing, and thus all the cases of computing units of four multiples can be classified into the processing mode of four computing units.

[0061] It should be understood that although each step in the flowchart involved in each embodiment as described above is shown in sequence according to the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, at least part of the steps in the flowchart involved in each embodiment as described above can include multiple steps or stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be alternately or alternately executed with at least part of other steps or steps or stages in other steps. It can be understood that the steps in different embodiments can be freely combined as needed, and various non-contradictory schemes formed by the combination are within the scope of protection of the present application.

[0062] Based on the same inventive concept, the embodiments of the present application also provide a data processing apparatus for implementing the above-mentioned data processing method. The implementation scheme for solving the problem provided by the apparatus is similar to the implementation scheme described in the above method, so the specific limitations in one or more data processing apparatus embodiments provided below can refer to the limitations of the data processing method described above, which will not be repeated here.

[0063] In one exemplary embodiment, as shown in Figure 10 A data processing apparatus is provided, the apparatus 1000 comprising:

[0064] An acquisition module 1001 is configured to acquire a control instruction; wherein the control instruction is used to indicate the data to be broadcast required to be read by each computing unit in the chain connection of the chip and the destination computing unit required to be broadcast;

[0065] A control module 1002 is configured to control each computing unit to read the data to be broadcast of each computing unit from the memory and broadcast the read data to be broadcast to the destination computing unit in response to the control instruction; wherein the data channel of each computing unit in the target direction through which the data to be broadcast passes is configured to transmit the data to be broadcast when the data to be broadcast is broadcast; the target direction is the direction of the computing unit pointing to the corresponding destination computing unit; the data to be broadcast is shared by the computing unit and the corresponding destination computing unit.

[0066] In one exemplary embodiment, the data to be broadcast read by the computing unit from the memory belongs to the first part of the operation data or the second part of the operation data; the first part of the operation data and the second part of the operation data are used to perform the target operation.

[0067] In one example embodiment, the first portion of operation data includes a first sub-data and a second sub-data; the second portion of operation data includes a third sub-data and a fourth sub-data; the chip includes a first computing unit, a second computing unit, a third computing unit and a fourth computing unit connected in a chain; and the control module 1002 is configured to, in response to the control instruction, control the first computing unit to read the first sub-data from the memory and broadcast the first sub-data to the second computing unit through a data channel in a first direction; in response to the control instruction, control the second computing unit to read the fourth sub-data from the memory and broadcast the fourth sub-data to the third computing unit through the data channel in the first direction, and broadcast the third sub-data broadcasted by the third computing unit to the first computing unit through a data channel in a second direction; in response to the control instruction, control the third computing unit to read the third sub-data from the memory and broadcast the third sub-data to the second computing unit through the data channel in the second direction, and broadcast the fourth sub-data broadcasted by the second computing unit to the fourth computing unit through the data channel in the first direction; and in response to the control instruction, control the fourth computing unit to read the second sub-data from the memory and broadcast the second sub-data to the third computing unit through the data channel in the second direction.

[0068] In one example embodiment, the first portion of operation data includes a first sub-data and a second sub-data; the second portion of operation data includes a third sub-data, a fourth sub-data, a fifth sub-data and a sixth sub-data; the chip includes a first computing unit, a second computing unit, a third computing unit, a fourth computing unit, a fifth computing unit, a sixth computing unit, a seventh computing unit and an eighth computing unit connected in a chain; and the control module 1002 is configured to, in response to the control instruction, control the first computing unit to read the first sub-data from the memory and broadcast the first sub-data to the second computing unit through a data channel in a first direction; in response to the control instruction, control the second computing unit to read the fourth sub-data from the memory and broadcast the fourth sub-data to the third computing unit through the data channel in the first direction, and broadcast the third sub-data broadcasted by the third computing unit to the first computing unit through a data channel in a second direction; in response to the control instruction, control the third computing unit to read the third sub-data from the memory and broadcast the third sub-data to the second computing unit through the data channel in the second direction, and broadcast the fourth sub-data broadcasted by the second computing unit to the fourth computing unit through the data channel in the first direction; in response to the control instruction, control the fourth computing unit to read the second sub-data from the memory and broadcast the second sub-data to the third computing unit through the data channel in the second direction, and broadcast the second sub-data to the fifth computing unit through the data channel in the first direction; in response to the control instruction, control the fifth computing unit to broadcast the second sub-data broadcasted by the fourth computing unit to the sixth computing unit through the data channel in the first direction; in response to the control instruction, control the sixth computing unit to read the fifth sub-data from the memory and broadcast the fifth sub-data to the seventh computing unit through the data channel in the first direction, and broadcast the sixth sub-data broadcasted by the seventh computing unit to the fifth computing unit through the data channel in the second direction; in response to the control instruction, control the seventh computing unit to read the sixth sub-data from the memory and broadcast the sixth sub-data to the sixth computing unit through the data channel in the second direction, and broadcast the fifth sub-data broadcasted by the sixth computing unit to the eighth computing unit through the data channel in the first direction; and in response to the control instruction, control the eighth computing unit to read the first sub-data from the memory and broadcast the first sub-data to the seventh computing unit through the data channel in the second direction.

[0069] In an example embodiment, the first part of operation data includes first sub-data and second sub-data; the second part of operation data includes third sub-data, fourth sub-data, fifth sub-data and sixth sub-data; the chip includes a chain-connected first computing unit, a second computing unit, a third computing unit, a fourth computing unit, a fifth computing unit, a sixth computing unit, a seventh computing unit and an eighth computing unit; the control module 1002 is configured to, in response to the control instruction, control the first computing unit to read the first sub-data from the memory and broadcast the first sub-data to the second computing unit through a data channel in a first direction; in response to the control instruction, control the second computing unit to read the fourth sub-data from the memory and broadcast the fourth sub-data to the third computing unit through the data channel in the first direction, and broadcast the third sub-data broadcasted by the third computing unit to the first computing unit through a data channel in a second direction; in response to the control instruction, control the third computing unit to read the third sub-data from the memory and broadcast the third sub-data to the second computing unit through the data channel in the second direction, and broadcast the fourth sub-data broadcasted by the second computing unit to the fourth computing unit through the data channel in the first direction; in response to the control instruction, control the fourth computing unit to read the second sub-data from the memory and broadcast the second sub-data to the third computing unit through the data channel in the second direction; in response to the control instruction, control the fifth computing unit to read the second sub-data from the memory and broadcast the second sub-data to the sixth computing unit through the data channel in the first direction; in response to the control instruction, control the sixth computing unit to read the fifth sub-data from the memory and broadcast the fifth sub-data to the seventh computing unit through the data channel in the first direction, and broadcast the sixth sub-data broadcasted by the seventh computing unit to the fifth computing unit through the data channel in the second direction; in response to the control instruction, control the seventh computing unit to read the sixth sub-data from the memory and broadcast the sixth sub-data to the sixth computing unit through the data channel in the second direction, and broadcast the fifth sub-data broadcasted by the sixth computing unit to the eighth computing unit through the data channel in the first direction; in response to the control instruction, control the eighth computing unit to read the first sub-data from the memory and broadcast the first sub-data to the seventh computing unit through the data channel in the second direction.

[0070] In an example embodiment, the chip is an artificial intelligence chip; and the memory includes a high bandwidth memory.

[0071] The above data processing apparatus can be implemented by software, hardware and combinations thereof. The above modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory in the computer device in software form, so as to be called and executed by the processor to perform the operations corresponding to the above modules.

[0072] In an example embodiment, a computer device is provided, which can be a server or a terminal, and an internal structure diagram thereof can be as shown in Figure 11 The computer device includes a processor, a memory, an input / output interface (I / O) and a communication interface. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is configured to exchange information between the processor and external devices. The communication interface of the computer device is configured to communicate with external devices through network connection. The computer program is executed by the processor to implement a data processing method.

[0073] Those skilled in the art can understand that Figure 11 The structure shown in the above embodiment is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0074] In an example embodiment, a computer device is provided, which can be a server or a terminal, and an internal structure diagram thereof can be as shown in

[0075] In an example embodiment, a computer readable storage medium is provided, which stores a computer program. The computer program is executed by a processor to implement the steps in the above method embodiments.

[0076] In an example embodiment, a computer program product is provided, which includes a computer program. The computer program is executed by a processor to implement the steps in the above method embodiments.

[0077] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant regulations.

[0078] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiment methods. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. The non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. The volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., without being limited thereto.

[0079] The technical features of the above embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0080] The above-described embodiments are merely illustrative of several embodiments of the present application, and the description is relatively specific and detailed, but should not be understood as a limitation on the scope of the patent. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A data processing method, characterized by, The method comprises: acquiring a control instruction; wherein the control instruction is used to indicate data to be broadcast and a target computing unit to which the data to be broadcast is required to be broadcast by each computing unit in a chain connection in a chip; in response to the control instruction, controlling each computing unit to read the data to be broadcast from a memory and broadcast the read data to the target computing unit; wherein a data channel of each computing unit in a target direction through which the data to be broadcast passes is configured to transmit the data to be broadcast; the target direction is a direction in which the computing unit points to the target computing unit; and the data to be broadcast is shared by the computing unit and the target computing unit.

2. The method of claim 1, wherein, The data to be broadcast read from the memory by the computing unit belongs to first partial operation data or second partial operation data; the first partial operation data and the second partial operation data are used to perform a target operation.

3. The method of claim 2, wherein, The first partial operation data comprises first sub-data and second sub-data; the second partial operation data comprises third sub-data and fourth sub-data; and the chip comprises a chain connection of a first computing unit, a second computing unit, a third computing unit and a fourth computing unit. The response to the control instruction, controlling each computing unit to read the data to be broadcast from a memory and broadcast the read data to the target computing unit, comprises: in response to the control instruction, controlling the first computing unit to read the first sub-data from the memory and broadcast the first sub-data to the second computing unit through a data channel in a first direction; in response to the control instruction, controlling the second computing unit to read the fourth sub-data from the memory and broadcast the fourth sub-data to the third computing unit through the data channel in the first direction, and broadcast the third sub-data broadcast by the third computing unit to the first computing unit through a data channel in a second direction; in response to the control instruction, controlling the third computing unit to read the third sub-data from the memory and broadcast the third sub-data to the second computing unit through the data channel in the second direction, and broadcast the fourth sub-data broadcast by the second computing unit to the fourth computing unit through the data channel in the first direction; in response to the control instruction, controlling the fourth computing unit to read the second sub-data from the memory and broadcast the second sub-data to the third computing unit through the data channel in the second direction.

4. The method of claim 2, wherein, The first partial operation data comprises first sub-data and second sub-data; the second partial operation data comprises third sub-data, fourth sub-data, fifth sub-data and sixth sub-data; and the chip comprises a chain connection of a first computing unit, a second computing unit, a third computing unit, a fourth computing unit, a fifth computing unit, a sixth computing unit, a seventh computing unit and an eighth computing unit. The response to the control instruction, controlling each computing unit to read the data to be broadcast from a memory and broadcast the read data to the target computing unit, comprises: in response to the control instruction, controlling the first computing unit to read the first sub-data from the memory and broadcast the first sub-data to the second computing unit through a data channel in a first direction; in response to the control instruction, controlling the second computing unit to read the fourth sub-data from the memory and broadcast the fourth sub-data to the third computing unit through a data channel in the first direction, and broadcast the third sub-data broadcasted by the third computing unit to the first computing unit through a data channel in a second direction; in response to the control instruction, controlling the third computing unit to read the third sub-data from the memory and broadcast the third sub-data to the second computing unit through a data channel in the second direction, and broadcast the fourth sub-data broadcasted by the second computing unit to the fourth computing unit through a data channel in the first direction; in response to the control instruction, controlling the fourth computing unit to read the second sub-data from the memory and broadcast the second sub-data to the third computing unit through a data channel in the second direction, and broadcast the second sub-data to the fifth computing unit through a data channel in the first direction; in response to the control instruction, controlling the fifth computing unit to broadcast the second sub-data broadcasted by the fourth computing unit to the sixth computing unit through a data channel in the first direction; in response to the control instruction, controlling the sixth computing unit to read the fifth sub-data from the memory and broadcast the fifth sub-data to the seventh computing unit through a data channel in the first direction, and broadcast the sixth sub-data broadcasted by the seventh computing unit to the fifth computing unit through a data channel in the second direction; in response to the control instruction, controlling the seventh computing unit to read the sixth sub-data from the memory and broadcast the sixth sub-data to the sixth computing unit through a data channel in the second direction, and broadcast the fifth sub-data broadcasted by the sixth computing unit to the eighth computing unit through a data channel in the first direction; in response to the control instruction, controlling the eighth computing unit to read the first sub-data from the memory and broadcast the first sub-data to the seventh computing unit through a data channel in the second direction.

5. The method of claim 2, wherein, the first part of operation data includes first sub-data and second sub-data; the second part of operation data includes third sub-data, fourth sub-data, fifth sub-data and sixth sub-data; the chip includes first computing unit, second computing unit, third computing unit, fourth computing unit, fifth computing unit, sixth computing unit, seventh computing unit and eighth computing unit connected in a chain; in response to the control instruction, controlling each computing unit to read respective to-be-broadcast data from the memory and broadcast the read to-be-broadcast data to the destination computing unit, including: in response to the control instruction, controlling the first computing unit to read the first sub-data from the memory and broadcast the first sub-data to the second computing unit through a data channel in a first direction; in response to the control instruction, controlling the second computing unit to read fourth sub-data from the memory and broadcast the fourth sub-data to the third computing unit through a data channel in the first direction, and broadcast third sub-data broadcasted by the third computing unit to the first computing unit through a data channel in the second direction; in response to the control instruction, controlling the third computing unit to read third sub-data from the memory and broadcast the third sub-data to the second computing unit through a data channel in the second direction, and broadcast fourth sub-data broadcasted by the second computing unit to the fourth computing unit through a data channel in the first direction; in response to the control instruction, controlling the fourth computing unit to read second sub-data from the memory and broadcast the second sub-data to the third computing unit through a data channel in the second direction; in response to the control instruction, controlling the fifth computing unit to read second sub-data from the memory and broadcast the second sub-data to the sixth computing unit through a data channel in the first direction; in response to the control instruction, controlling the sixth computing unit to read fifth sub-data from the memory and broadcast the fifth sub-data to the seventh computing unit through a data channel in the first direction, and broadcast sixth sub-data broadcasted by the seventh computing unit to the fifth computing unit through a data channel in the second direction; in response to the control instruction, controlling the seventh computing unit to read sixth sub-data from the memory and broadcast the sixth sub-data to the sixth computing unit through a data channel in the second direction, and broadcast fifth sub-data broadcasted by the sixth computing unit to the eighth computing unit through a data channel in the first direction; in response to the control instruction, controlling the eighth computing unit to read first sub-data from the memory and broadcast the first sub-data to the seventh computing unit through a data channel in the second direction.

6. The method according to any one of claims 1 to 5, characterized in that, The chip is an artificial intelligence chip; and the memory includes a high-bandwidth memory.

7. A data processing apparatus, characterized by, The apparatus comprises: an obtaining module configured to obtain a control instruction; wherein the control instruction is used to indicate data to be broadcasted and a destination computing unit to which each computing unit in a chain connection in a chip needs to broadcast in each computing unit; a control module configured to, in response to the control instruction, control each computing unit to read the data to be broadcasted from a memory and broadcast the read data to the destination computing unit; wherein a data channel of each computing unit in a target direction through which the data to be broadcasted passes is configured to be used to transmit the data to be broadcasted; the target direction is a direction in which the computing unit points to the corresponding destination computing unit; and the data to be broadcasted is shared by the computing unit and the corresponding destination computing unit.

8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that, The processor executes the computer program to implement the steps of the method in any one of claims 1 to 6.

9. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 6.

10. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 6.

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