Pixel circuit and vehicle display device

Abstract

A pixel circuit includes a first driving transistor, a second driving transistor, a first light emission control transistor, a second light emission control transistor, and a light emitting element. The control terminals of the first and second driving transistors are coupled to each other, and the first terminal of the first driving transistor receives a system high voltage. The second driving transistor and the second end of the first light-emitting control transistor are coupled to the first end of the second light-emitting control transistor. The control ends of the first and second light-emitting control transistors respectively receive first and second light-emitting control signals, and the first end of the first light-emitting control transistor is coupled to the second end of the first driving transistor and the first end of the second driving transistor. The first end of the light-emitting element is coupled to the second end of the second light-emitting control transistor, and the second end of the light-emitting element receives system low voltage.

Description

Technical Field

[0001] This disclosure relates to a pixel circuit and an automotive display device, and more particularly to a pixel circuit and an automotive display device having a daytime mode and a nighttime mode. Background Technology

[0002] In recent years, the application of display devices in the automotive field has gradually emerged as display technology has matured. To ensure clear visibility under strong external light, the display device needs to be designed with high current to enhance the brightness of the display panel. However, in dim environments, this current design can result in excessively bright display panels, causing eye discomfort and potentially affecting driving safety. Summary of the Invention

[0003] This disclosure provides a pixel circuit and an automotive display device in some embodiments. By splitting a single driving transistor in the pixel circuit into two driving transistors connected in series, and connecting a next-stage light emission control signal between the series driving transistors, the magnitude of the current in the pixel circuit and the current path through which the current flows can be controlled by the series driving transistors and the next-stage light emission control signal. This allows the pixel circuit to have a daytime mode that requires a larger current and a nighttime mode that requires a smaller current. In this way, the problem of excessive brightness in the nighttime mode due to the use of a larger current in the daytime mode can be avoided.

[0004] This disclosure provides a pixel circuit in some embodiments. The pixel circuit includes a first driving transistor, a second driving transistor, a first light-emitting control transistor, a second light-emitting control transistor, and a light-emitting element. The control terminal of the first driving transistor is coupled to a first node, and a first terminal of the first driving transistor receives a system high voltage. The control terminal of the second driving transistor is coupled to the first node, and a second terminal of the second driving transistor is coupled to a second node. The control terminal of the first light-emitting control transistor receives a first light-emitting control signal, and a first terminal of the first light-emitting control transistor is coupled to a second terminal of the first driving transistor and a first terminal of the second driving transistor. The second terminal of the first light-emitting control transistor is coupled to the second node. The control terminal of the second light-emitting control transistor receives a second light-emitting control signal, and a first terminal of the second light-emitting control transistor is coupled to the second node. A first terminal of the light-emitting element is coupled to the second terminal of the second light-emitting control transistor, and the second terminal of the light-emitting element receives a system low voltage.

[0005] According to some embodiments of this disclosure, the ratio of the channel width to the channel length of the first driving transistor is different from the ratio of the channel width to the channel length of the second driving transistor.

[0006] According to some embodiments of this disclosure, during daytime illumination, the first driving transistor is turned on, the first light-emitting control transistor is turned on according to the first light-emitting control signal, and the second light-emitting control transistor is turned on according to the second light-emitting control signal, so as to conduct a first circuit path from the system high voltage through the first driving transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the light-emitting element to the system low voltage.

[0007] According to some embodiments of this disclosure, in the daytime mode, the enable period of the first light emission control signal partially overlaps with the enable period of the second light emission control signal, and the start time of the enable period of the first light emission control signal and the start time of the enable period of the second light emission control signal are staggered by a data time, wherein the data time is defined as the time during which the pixel circuit drives a corresponding pixel column in each frame time.

[0008] According to some embodiments of this disclosure, during the illumination period of the daytime mode, when the enable period of the second illumination control signal is greater than a data time, the first output current flows through the first circuit path, wherein the data time is defined as the time during which the pixel circuit drives a corresponding pixel column in each frame time.

[0009] According to some embodiments of this disclosure, during the illumination period of the night mode, both the first driving transistor and the second driving transistor are turned on, the first light-emitting control transistor is turned off according to the first light-emitting control signal, and the second light-emitting control transistor is turned on according to the second light-emitting control signal, so as to conduct a second circuit path from the system high voltage through the first driving transistor, the second driving transistor, the second light-emitting control transistor and the light-emitting element to the system low voltage.

[0010] According to some embodiments of this disclosure, in the night mode, the enabling period of the first light emission control signal and the enabling period of the second light emission control signal do not overlap.

[0011] According to some embodiments of this disclosure, during the illumination period of the night mode, when the enable period of the second illumination control signal is less than the data time, the second output current flows through the second circuit path.

[0012] According to some embodiments of this disclosure, the first output current is greater than the second output current.

[0013] According to some embodiments of this disclosure, the emission period of the daytime mode is longer than the emission period of the nighttime mode.

[0014] According to some embodiments of this disclosure, the daytime mode and the nighttime mode have the same data voltage, wherein the third node is used to receive the data voltage.

[0015] According to some embodiments of the present disclosure, the bottom gate of the first driving transistor is coupled to the top gate of the first driving transistor, the bottom gate of the second driving transistor is coupled to the top gate of the second driving transistor, and the bottom gate of the first light-emitting control transistor is coupled to the top gate of the first light-emitting control transistor.

[0016] According to some embodiments of the present disclosure, the bottom gate of the first driving transistor is coupled to the top gate of the first driving transistor, and the bottom gate of the second driving transistor and the bottom gate of the first light-emitting control transistor are coupled to the top gate of the first light-emitting control transistor.

[0017] According to some embodiments of this disclosure, the bottom gate of the first driving transistor, the bottom gate of the second driving transistor, and the bottom gate of the first light-emitting control transistor are coupled to the top gate of the first light-emitting control transistor.

[0018] This disclosure provides a vehicle display device in some embodiments. The vehicle display device includes a base and a display panel. The base is disposed in the driver's area of ​​the vehicle. The display panel is disposed on the base, wherein the display panel includes pixel circuitry as described above. Attached Figure Description

[0019] To gain a more complete understanding of the embodiments and their advantages, the following description is made in conjunction with the accompanying drawings.

[0020] Figure 1 This is an example of an equivalent circuit for a pixel circuit according to a partial embodiment of the present disclosure.

[0021] Figure 2 for Figure 1 An example of the timing of a pixel circuit.

[0022] Figures 3A to 3D for Figure 1 A schematic diagram of the pixel circuit operating at different times.

[0023] Figure 4 for Figure 1 An example of the timing of a pixel circuit.

[0024] Figure 5A as well as Figure 5B for Figure 1 The pixel circuit operates at Figure 4 A schematic diagram of the time sequence period.

[0025] Figures 6A to 6C for Figure 1 A schematic diagram of the architecture of the pixel circuit's driving transistor and light-emitting control transistor.

[0026] Figure 7 This is an example of an automotive display device according to a partial embodiment of the present disclosure.

[0027] List of reference numerals

[0028] 100: Pixel circuit

[0029] 200: Automotive display device

[0030] 220: Base

[0031] 240: Display panel

[0032] 800: Windshield

[0033] 900: Vehicles

[0034] BG1, BG2, BG3: Bottom gate

[0035] Cst: Capacitor

[0036] C1, C2: Output current

[0037] CP1, CP2: Circuit paths

[0038] CCP: Compensation circuit path

[0039] DR: Driving Area

[0040] DA: Data signal

[0041] ED: Light-emitting element

[0042] EM(n), EM(n+1): Emitted signals

[0043] H,L: Logical Levels

[0044] Ic: Compensation current

[0045] NL, SL: Timing

[0046] N1~N5: Nodes

[0047] OVDD: System high voltage

[0048] OVSS: System Low Voltage

[0049] P1, P2, P3, P4, P5, P51, P52: Period

[0050] S1(n), S2(n): Signals

[0051] ST1, ST2, ST3: Architecture

[0052] T1, T2, T3, T4, T5: Transistors

[0053] TD1, TD2: Drive transistors

[0054] TE1, TE2: Light-emitting control transistors

[0055] TG1, TG2, TG3: Top gate

[0056] Vref: Reference voltage

[0057] Vp: Voltage Detailed Implementation

[0058] The embodiments of this disclosure are discussed in detail below. However, it should be understood that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific situations. The discussed and disclosed embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The terms "first," "second," etc., as used herein, do not specifically refer to any order or sequence, but are used only to distinguish components or operations described using the same technical terms.

[0059] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one element or feature and another illustrated in the figures. Besides the orientation depicted in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly. As used herein, “approximately,” “about,” “approximately,” or “substantially” generally refers to within 20%, 10%, or 5% of a given value or range. The numerical quantities given herein are approximate, meaning that the terms “approximately,” “about,” “approximately,” or “substantially” may be conjectured unless explicitly specified.

[0060] Figure 1This is an example of an equivalent circuit of a pixel circuit 100 according to a partial embodiment of the present disclosure. The pixel circuit 100 may include a driving transistor TD1, a driving transistor TD2, transistors T1 to T5, a light-emitting control transistor TE1, a light-emitting control transistor TE2, a light-emitting element ED, and a capacitor Cst. The driving transistors TD1, TD2, TE1, TE2, and T1 to T5 each have a first terminal, a second terminal, and a control terminal (e.g., a gate terminal). When the first terminals of the driving transistors TD1, TD2, TE1, TE2, and T1 to T5 are the drain terminals (source terminals), the second terminals of the driving transistors TD1, TD2, TE1, TE2, and T1 to T5 are the source terminals (drain terminals).

[0061] In some embodiments, the control terminal of driving transistor TD1 is coupled to node N1, and the first terminal of driving transistor TD1 receives the system high voltage OVDD. Driving transistor TD2 is connected in series with driving transistor TD1, wherein the control terminal of driving transistor TD2 is coupled to node N1, and the second terminal of driving transistor TD2 is coupled to node N2. Furthermore, driving transistor TD1 and driving transistor TD2 may have different component characteristics. For example, in this embodiment, the ratio (W / L) of the channel width (W) to the channel length (L) of driving transistor TD1 may be different from the ratio of the channel width to the channel length of driving transistor TD2. In other embodiments, driving transistor TD1 and driving transistor TD2 may have the same component characteristics. For example, the ratio (W / L) of the channel width (W) to the channel length (L) of driving transistor TD1 may be the same as the ratio of the channel width to the channel length of driving transistor TD2.

[0062] In some embodiments, the control terminal of the light-emitting control transistor TE1 receives the light-emitting control signal EM(n+1). The first terminal of the light-emitting control transistor TE1 is coupled to the second terminal of the driving transistor TD1 and the first terminal of the driving transistor TD2. The second terminal of the light-emitting control transistor TE1 is coupled to node N2. The control terminal of the light-emitting control transistor TE2 receives the light-emitting control signal EM(n). The first terminal of the light-emitting control transistor TE2 is coupled to node N2. The light-emitting control signal EM(n+1) is the next-level signal after the light-emitting control signal EM(n).

[0063] In some embodiments, the control terminal of transistor T1 receives the light emission control signal EM(n), the first terminal of transistor T1 receives voltage Vp, and the second terminal of transistor T1 is coupled to node N3. The control terminal of transistor T2 is coupled to node N4, where node N4 is used to receive signal S2(n), the first terminal of transistor T2 is coupled to node N3, and the second terminal of transistor T2 receives data signal DA. The control terminal of transistor T3 is coupled to node N4 to receive signal S2(n), the first terminal of transistor T3 is coupled to node N5, and the second terminal of transistor T2 is coupled to node N1. The control terminal of transistor T4 is coupled to node N4 to receive signal S2(n), the first terminal of transistor T4 is coupled to node N2, and the second terminal of transistor T2 is coupled to node N5. The control terminal of transistor T5 receives signal S1(n), the first terminal of transistor T5 is coupled to node N5, and the second terminal of transistor T5 receives reference voltage Vref.

[0064] In some embodiments, the light-emitting element ED may be composed of a micro light-emitting diode (micro LED). In other embodiments, the light-emitting element ED may be composed of a mini light-emitting diode (mini LED), a light-emitting diode (LED), or other suitable light-emitting diode. A first terminal (e.g., the anode) of the light-emitting element ED is coupled to a second terminal of the light-emitting control transistor TE2, and a second terminal (e.g., the cathode) of the light-emitting element ED receives the system low voltage OVSS.

[0065] In some embodiments, capacitor Cst is disposed between transistor T1 and transistor T3. For example, the first end of capacitor Cst is coupled to node N1, and the second end of capacitor Cst is coupled to node N3.

[0066] Please refer to the above as well. Figure 2 as well as Figures 3A to 3D . Figure 2 for Figure 1 An example of timing SL of pixel circuit 100, wherein timing SL is an example of daytime mode of pixel circuit 100. Figures 3A to 3D for Figure 1 A schematic diagram of the pixel circuit 100 operating at different times P1~P4. (See diagram) Figure 2As shown, the timing SL of the daytime mode includes periods P1 to P4, where period P1 is defined in this disclosure as the pre-reset period, period P2 is defined in this disclosure as the reset period of data input and drive transistors TD1 and TD2, period P3 is defined in this disclosure as the compensation period of the threshold voltage (Vth) of data input and drive transistors TD1 and TD2, and period P4 is defined in this disclosure as the light emission period of the daytime mode. In period P4, since the daytime mode requires high brightness, the enable period of the light emission control signal EM(n+1) and the enable period of the light emission control signal EM(n) can be designed to partially overlap to output a larger current, thereby increasing the light emission brightness of the light-emitting element ED. Furthermore, the start time of the enable period of the light emission control signal EM(n+1) and the start time of the enable period of the light emission control signal EM(n) can be designed to be staggered by a data time (H), where the data time is defined as the time for the pixel circuit 100 to drive a corresponding pixel column in each frame time.

[0067] In detail, such as Figure 2 as well as Figure 3A As shown, during period P1, signal S1(n) is at logic level L (e.g., a low voltage level) to turn on transistor T5. The reference voltage Vref can be transmitted to node N5 via transistor T5. Signal S2(n) is at logic level H (e.g., a low voltage level) to turn off transistors T2, T3, and T4. The light-emitting control signal EM(n) is at logic level H to turn off transistor T1 and the light-emitting control transistor TE2. The light-emitting control signal EM(n+1) is at logic level H to turn off the light-emitting control transistor TE1. In this way, the voltage at node N5 can be pre-reset.

[0068] like Figure 2 as well as Figure 3B As shown, during period P2, signal S1(n) remains at logic level L to turn on transistor T5. Signal S2(n) switches to logic level H to turn on transistors T2, T3, and T4. The reference voltage Vref can be transmitted to node N5 via transistor T5, and then to nodes N1 and N2 via transistors T3 and T4 respectively. The voltage of the data signal DA can be transmitted to node N3 via transistor T2. The light-emitting control signal EM(n) remains at logic level H to turn off transistor T1 and the light-emitting control transistor TE2. The light-emitting control signal EM(n+1) remains at logic level H to turn off the light-emitting control transistor TE1. In this way, the voltage of the data signal DA can be written to node N3, and the voltage of node N1 can be reset to reset the voltage of the control terminals of driving transistors TD1 and TD2.

[0069] like Figure 2 as well as Figure 3C As shown, during period P3, signal S1(n) switches to logic level H to turn off transistor T5. Signal S2(n) remains at logic level L to turn on transistors T2, T3, and T4. The voltage of data signal DA can be continuously transmitted to node N3 via transistor T2. The light emission control signal EM(n) remains at logic level H to turn off transistor T1 and light emission control transistor TE2. The light emission control signal EM(n+1) remains at logic level H to turn off light emission control transistor TE1. At this time, since the voltage of node N1 has not been rewritten with other voltages, it remains at the reference voltage Vref written during period P2. The compensation circuit path CCP from the system high voltage OVDD through driving transistors TD1, TD2, T4, and T3 to node N1 can be turned on. The compensation current Ic can flow through the compensation circuit path CCP, thereby writing the compensation voltage to node N1, wherein the compensation voltage can be the system high voltage OVDD minus the critical voltage. In this way, the voltage of the data signal DA can be written into node N3 to write the data signal DA, and the voltage of node N1 can be compensated to compensate the critical voltage of driving transistors TD1 and TD2.

[0070] like Figure 2 as well as Figure 3DAs shown, during period P4 (i.e., the daytime illumination period), signal S1(n) remains at logic level H to turn off transistor T5. Signal S2(n) switches to logic level H to turn off transistors T2, T3, and T4. The illumination control signal EM(n) switches to logic level L to turn on transistor T1 and the illumination control transistor TE2. Voltage Vp can be written to node N3 via transistor T1. The illumination control signal EM(n+1) switches to logic level L to turn on the illumination control transistor TE1. At this time, voltage Vp can be coupled to node N1 via capacitor Cst. Capacitor Cst can couple the change in its second terminal (i.e., node N3) (i.e., voltage Vp minus the voltage of data signal DA) to node N1 to overwrite the voltage of node N1, where the voltage of node N1 can be the compensation voltage (i.e., system high voltage OVDD minus the critical voltage) plus the change in the second terminal of capacitor Cst. Since the voltage at node N1 is greater than the critical voltages of driving transistors TD1 and TD2, driving transistors TD1 and TD2 can be turned on. Driving transistors TD1 and TD2 can operate in the linear region and saturation region, respectively, where the impedance of driving transistor TD1 is less than the impedance of driving transistor TD2, so that the output current C1 flows through driving transistor TD1 but not through driving transistor TD2. In this way, the circuit path CP1 from the system high voltage OVDD through driving transistor TD1, light-emitting control transistor TE1, light-emitting control transistor TE2, and light-emitting element ED to the system low voltage OVSS can be turned on. And when the enable period of the light-emitting control signal EM(n) is greater than a data time (for example, when the enable period of the light-emitting control signal EM(n) overlaps with the enable period of the light-emitting control signal ED), the output current C1 can flow through the circuit path CP1 to make the light-emitting element ED emit light, where the data time is defined as the time for the pixel circuit 100 to drive a corresponding pixel column in each frame time.

[0071] Please refer to the above as well. Figure 4 , Figure 5A as well as Figure 5B . Figure 4 for Figure 1 An example of timing NL of pixel circuit 100, wherein timing NL is an example of night mode of pixel circuit 100. Figure 5A as well as Figure 5B for Figure 1 The pixel circuit 100 operates in Figure 4A schematic diagram of the time sequence NL, including periods P51 and P52. The time sequence NL of the night mode is similar to that of the time sequence SL of the day mode, except that the time sequence NL of the night mode includes period P5 instead of period P4, wherein period P5 includes period P51, which is defined in this disclosure as the illumination period of the night mode, and period P52, which is defined in this disclosure as the cutoff period of the night mode.

[0072] It is worth mentioning that during period P51 (i.e., the illumination period of night mode), since night mode requires low brightness, the enable period of the illumination control signal EM(n+1) and the enable period of the illumination control signal EM(n) can be designed to not overlap, so as to output a smaller current and thus reduce the brightness of the light-emitting element ED. For example, in this embodiment, the enable period of the illumination control signal EM(n) in period P51 (i.e., the illumination period of night mode) can be designed to be shorter than the enable period of the illumination control signal EM(n) in the illumination period P4 of the daytime mode timing SL (i.e., daytime mode), so that the enable period of the illumination control signal EM(n) does not overlap with the enable period of the illumination control signal EM(n+1), thereby making the illumination period of period P5 (i.e., period P51) shorter than the illumination period of period P4. In other words, the duty cycle of the illumination control signal EM(n) can be reduced to lower the output current and thus reduce the brightness of the light-emitting element ED. In this way, by controlling the output current and the enable period of the light emission control signal EM(n), the problem of needing to reduce the data voltage due to excessive brightness in night mode, which would lead to a deterioration in image quality, can be avoided. In other words, the daytime mode and night mode of the pixel circuit 100 can have the same data voltage (e.g., the voltage of the data signal DA), wherein node N3 is used to receive the data voltage.

[0073] In detail, such as Figure 4 as well as Figure 5AAs shown, during period P51 (i.e., the illumination period of night mode), signal S1(n) remains at logic level H to turn off transistor T5. Signal S2(n) switches to logic level H to turn off transistors T2, T3, and T4. The illumination control signal EM(n) switches to logic level L to turn on transistor T1 and illumination control transistor TE2. Voltage Vp can be written to node N3 via transistor T1. Illumination control signal EM(n+1) remains at logic level H to turn off illumination control transistor TE1. At this time, voltage Vp can be coupled to node N1 via capacitor Cst. Capacitor Cst can couple the change in its second terminal (i.e., node N3) (i.e., voltage Vp minus the voltage of data signal DA) to node N1 to overwrite the voltage of node N1, where the voltage of node N1 can be the compensation voltage (i.e., system high voltage OVDD minus the critical voltage) plus the change in the second terminal of capacitor Cst. Since the voltage at node N1 is greater than the critical voltages of driving transistors TD1 and TD2, driving transistors TD1 and TD2 can be turned on. This allows the circuit path CP2, from the system high voltage OVDD through driving transistors TD1, TD2, TE2, and the light-emitting element ED to the system low voltage OVSS, to be turned on. Furthermore, when the enable period of the light-emitting control signal EM(n) is less than a data time (e.g., when the enable period of the light-emitting control signal EM(n) does not overlap with the enable period of the light-emitting control signal ED), the output current C2 can flow through circuit path CP2 to cause the light-emitting element ED to emit light. The data time is defined as the time during which the pixel circuit 100 drives a corresponding pixel column in each frame time.

[0074] like Figure 4 as well as Figure 5B As shown, during period P52 (i.e., the off period of night mode), signal S1(n) remains at logic level H to turn off transistor T5. Signal S2(n) remains at logic level H to turn off transistors T2, T3, and T4. The light emission control signal EM(n) switches to logic level H to turn off transistor T1 and light emission control transistor TE2. The light emission control signal EM(n+1) switches to logic level L to turn on light emission control transistor TE1. In this way, pixel circuit 100 is turned off.

[0075] Furthermore, it is worth mentioning that the output current C1 in the timing SL of daytime mode is greater than the output current C2 in the timing NL of nighttime mode. Specifically, compared to the output current C2 in the timing NL of nighttime mode, the output current C1 in the timing SL of daytime mode flows only through the driving transistor TD1, which is equivalent to the output current C1 flowing through an equivalent driving transistor with half the channel length. This equivalent driving transistor has a larger channel width to channel length ratio. As can be seen from the transistor output current formula, the output current is proportional to the channel width to channel length ratio. Therefore, the equivalent driving transistor can output a large current, allowing the pixel circuit 100 to output a large current (i.e., output current C1) in daytime mode. Compared to the output current C1 in the timing SL of daytime mode, the output current C2 in the timing NL of nighttime mode flows through both driving transistors TD1 and TD2, which is equivalent to the output current C2 flowing through an equivalent driving transistor with double the channel length. This equivalent driving transistor has a smaller channel width to channel length ratio. As can be seen from the transistor's output current formula, the output current is directly proportional to the ratio of the channel width to the channel length. Therefore, the equivalent driving transistor can output a small current, allowing the pixel circuit 100 to output a small current (i.e., output current C2) in night mode. Thus, compared to the night mode's timing NL, the timing SL in day mode effectively reduces the channel length of the driving transistor, allowing the output current C1 to be greater than the output current C2.

[0076] Furthermore, the magnitudes of the output currents C1 and C2 are independent of the system high voltage OVDD, the critical voltage of driving transistor TD1, and the critical voltage of driving transistor TD2. Specifically, according to the transistor output current formula, the output current is proportional to the voltage difference between the source and gate minus the critical voltage. Taking driving transistor TD1 and output current C1 in daytime mode as an example, the voltage difference between the source (e.g., the first terminal) and gate (e.g., the control terminal) of driving transistor TD1 is the critical voltage of driving transistor TD1 minus the voltage Vp plus the voltage of the data signal DA. From the aforementioned output current formula, it is clear that the output current C1 is proportional to the voltage of the data signal DA minus the voltage Vp, and the output current C1 is independent of the system high voltage OVDD and the critical voltage of driving transistor TD1. Furthermore, the relationship between the output current C2 and the critical voltages of driving transistors TD1 and TD2 can be deduced by analogy, and therefore will not be elaborated further.

[0077] Please refer to the above as well. Figures 6A to 6C They are respectively Figure 1 The schematic diagram of the architecture ST1~ST3 of the pixel circuit 100, including the driving transistor TD1, driving transistor TD2 and light-emitting control transistor TE1.

[0078] like Figure 6A As shown, the ST1 architecture can be designed as a dual-gate structure. For example, in this embodiment, the bottom gate BG1 of the driving transistor TD1 is coupled to the top gate TG1 of the driving transistor TD1, the bottom gate BG2 of the driving transistor TD2 is coupled to the top gate TG2 of the driving transistor TD2, and the bottom gate BG3 of the light-emitting control transistor TE1 is coupled to the top gate TG3 of the light-emitting control transistor TE1.

[0079] like Figure 6B As shown, the architecture ST2 and Figure 6A The architecture is similar to ST1, except that the bottom gate BG2 of the driving transistor TD2 and the bottom gate BG3 of the light-emitting control transistor TE1 are coupled to the top gate TG3 of the light-emitting control transistor TE1. This allows the pixel circuit 100 to have lower brightness in night mode.

[0080] like Figure 6C As shown, the architecture ST2 and Figure 6A The architecture is similar to ST1, except that the bottom gate BG1 of driving transistor TD1, the bottom gate BG2 of driving transistor TD2, and the bottom gate BG3 of light-emitting control transistor TE1 are coupled to the top gate TG3 of light-emitting control transistor TE1. This allows the pixel circuit 100 to have higher brightness in daytime mode.

[0081] It is worth noting that this disclosure addresses problems in automotive applications and proposes a solution (MobilitySolution). Please refer to... Figure 7 . Figure 7 This is an example of a vehicle display device 200 according to a partial embodiment of the present disclosure. The vehicle display device 200 can be applied to a head-up display, but is not limited thereto. The vehicle display device 200 may include a base 220 and a display panel 240. The base 220 may be disposed in the driver's area (DR) of a vehicle 900. The display panel 240 may be disposed on the base 220 for projecting information (e.g., vehicle speed) from a data processing device (not shown) onto a windshield 800, wherein the display panel 240 includes... Figure 1 The pixel circuit 100 shown.

[0082] This disclosure provides a pixel circuit and an automotive display device in some embodiments. By splitting a single driving transistor in the pixel circuit into two driving transistors connected in series, and connecting a next-stage light emission control signal between the series driving transistors, the magnitude of the current in the pixel circuit and the current path through which the current flows can be controlled by the series driving transistors and the next-stage light emission control signal. This allows the pixel circuit to have a daytime mode that requires a larger current and a nighttime mode that requires a smaller current. In this way, the problem of excessive brightness in the nighttime mode due to the use of a larger current in the daytime mode can be avoided.

[0083] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of this application. Those skilled in the art should understand that they can readily use this application as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this application, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this application.

Claims

1. A pixel circuit, comprising: A first driving transistor, wherein a control terminal of the first driving transistor is coupled to a first node, and a first terminal of the first driving transistor receives a system high voltage; A second driving transistor, wherein a control terminal of the second driving transistor is coupled to the first node, and a second terminal of the second driving transistor is coupled to a second node; A first light-emitting control transistor, wherein a control terminal of the first light-emitting control transistor receives a first light-emitting control signal, a first terminal of the first light-emitting control transistor is coupled to a second terminal of the first driving transistor and a first terminal of the second driving transistor, and a second terminal of the first light-emitting control transistor is coupled to the second node; A second light-emitting control transistor, wherein a control terminal of the second light-emitting control transistor receives a second light-emitting control signal, and a first terminal of the second light-emitting control transistor is coupled to the second node; and A light-emitting element, wherein a first terminal of the light-emitting element is coupled to a second terminal of the second light-emitting control transistor, and the second terminal of the light-emitting element receives a system low voltage.

2. The pixel circuit of claim 1, wherein the ratio of the channel width to the channel length of the first driving transistor is different from the ratio of the channel width to the channel length of the second driving transistor.

3. The pixel circuit of claim 1, wherein during a light emission period in a daytime mode, the first driving transistor is turned on, the first light emission control transistor is turned on according to the first light emission control signal, and the second light emission control transistor is turned on according to the second light emission control signal to conduct a first circuit path from the system high voltage through the first driving transistor, the first light emission control transistor, the second light emission control transistor, and the light-emitting element to the system low voltage.

4. The pixel circuit of claim 3, wherein in the daytime mode, the enable period of the first light emission control signal partially overlaps with the enable period of the second light emission control signal, and the start time of the enable period of the first light emission control signal and the start time of the enable period of the second light emission control signal are staggered by a data time, wherein the data time is defined as the time during which the pixel circuit drives a corresponding pixel column in each frame time.

5. The pixel circuit of claim 3, wherein during the illumination period of the daytime mode, when the enable period of the second illumination control signal is greater than a data time, a first output current flows through the first circuit path, wherein the data time is defined as the time during which the pixel circuit drives a corresponding pixel column in each frame time.

6. The pixel circuit of claim 5, wherein during a light emission period in a night mode, both the first driving transistor and the second driving transistor are turned on, the first light emission control transistor is turned off according to the first light emission control signal, and the second light emission control transistor is turned on according to the second light emission control signal to conduct a second circuit path from the system high voltage through the first driving transistor, the second driving transistor, the second light emission control transistor, and the light-emitting element to the system low voltage.

7. The pixel circuit of claim 6, wherein in the night mode, the enable period of the first light emission control signal and the enable period of the second light emission control signal do not overlap.

8. The pixel circuit of claim 6, wherein during the illumination period of the night mode, when the enable period of the second illumination control signal is less than the data time, a second output current flows through the second circuit path.

9. The pixel circuit of claim 8, wherein the first output current is greater than the second output current.

10. The pixel circuit of claim 6, wherein the emission period of the daytime mode is longer than the emission period of the nighttime mode.

11. The pixel circuit of claim 10, wherein the daytime mode and the nighttime mode have the same data voltage, wherein a third node is used to receive the data voltage.

12. The pixel circuit of claim 1, wherein a bottom gate of the first driving transistor is coupled to a top gate of the first driving transistor, a bottom gate of the second driving transistor is coupled to a top gate of the second driving transistor, and a bottom gate of the first light-emitting control transistor is coupled to a top gate of the first light-emitting control transistor.

13. The pixel circuit of claim 1, wherein a bottom gate of the first driving transistor is coupled to a top gate of the first driving transistor, and a bottom gate of the second driving transistor and a bottom gate of the first light-emitting control transistor are coupled to a top gate of the first light-emitting control transistor.

14. The pixel circuit of claim 1, wherein a bottom gate of the first driving transistor, a bottom gate of the second driving transistor, and a bottom gate of the first light-emitting control transistor are coupled to a top gate of the first light-emitting control transistor.

15. A vehicle display device, comprising: A base, located in the driver's area of ​​a vehicle; as well as A display panel is disposed on the base, wherein the display panel includes the pixel circuitry as described in claim 1.

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