A comparator-based single-inductor multiple-output switching converter

Abstract

The application provides a single-inductor multi-output switching converter based on a comparator, aiming at the problems of low conversion efficiency and high control difficulty of the single-inductor multi-output switching converter under a light load condition, directly compares the output voltage with a reference to trigger the switch activity, reduces the switch loss, and is suitable for a light load application scene; the control of the circuit does not need to generate a clock signal for each output, the control circuit is simple, the expansion of the number of inputs and outputs is facilitated, and a stable and efficient solution is provided for a power management module of an electronic system.

Description

Technical Field

[0001] This invention relates to the field of switching power supply technology, and more specifically, to a comparator-based single-inductor multi-output switching converter. Background Technology

[0002] A single-inductor multi-output switching converter is a DC-DC conversion circuit that uses power switching transistors to control the power transfer from the input to multiple outputs. It can provide different constant output voltages and / or output currents at different output terminals. Therefore, a single-inductor multi-output converter can simultaneously power multiple sub-modules or loads in an electronic system while requiring only one external inductor, offering advantages such as small size and high efficiency.

[0003] However, under light load conditions (such as portable applications or energy harvesting), the conversion efficiency of single-inductor multi-output switching converters drops significantly due to the increasing proportion of power losses, especially switching losses and quiescent current losses.

[0004] Currently, the control method for single-inductor multi-output switching converters suitable for light load conditions is mainly the pulse skipping or burst mode control method, such as patent CN 110875730 B. This method detects the output voltage or its voltage division result at each clock edge and compares it directly with a fixed reference voltage. Switching activity only occurs when the output voltage is lower, thus reducing switching losses. However, this method requires a non-overlapping clock signal for each output. When there are many outputs, the clock generation circuit becomes complex, and clock losses are high, making it unacceptable for light load conditions. Furthermore, since the charging determination is only made at the clock edge, the system cannot respond promptly to instantaneous changes in output voltage. In the worst case, when the load jumps upward, the circuit has to wait for a full clock cycle before charging the output, resulting in a large undershoot in the output voltage, affecting the operation of downstream powered modules. Summary of the Invention

[0005] The purpose of this invention is to address the problems of low conversion efficiency and high control difficulty of single-inductor multi-output switching converters under light load conditions. It proposes a comparator-based single-inductor multi-output switching converter that directly compares the output with a reference to trigger switching activity, thereby reducing switching losses and making it suitable for light load applications. The control method of this circuit does not require generating a clock signal for each output, the control circuit is simple, and it is conducive to the expansion of the number of inputs and outputs.

[0006] The technical solution of this invention is:

[0007] In a first aspect, the present invention provides a single-inductor multi-output switching converter, wherein the switching converter realizes single-input multi-output buck control, including a control module and a single inductor located outside the control module, wherein the inductor converts and distributes the input voltage Vbat through the control module, and generates multiple stable voltages Vout1, Vout2...Voutm at the output; wherein the control module includes;

[0008] A power switch group includes input power switches Mp and Mn, and corresponding output power switches Ms1, Ms2...Msm, where m represents the total number of output terminals. One end of each power switch Mp and Mn is connected to the input side of an inductor, the other end of power switch Mp is connected to the input terminal Vbat, and the other end of power switch Mn is grounded. One end of each power switch Ms1, Ms2...Msm is connected to the output side of an inductor, and the other end is connected to the corresponding output terminals Vout1, Vout2...Voutm, respectively.

[0009] Multiple voltage comparators (VCMPs) are used, with the number of VCMPs matching the number of output terminals. The inverting input of each VCMP is connected to its corresponding output terminal Vout via a voltage divider circuit, and the non-inverting input of each VCMP is connected to its corresponding reference voltage Vref. The VCMPs are used to compare the voltage divider signal Vfb of each output terminal with the corresponding reference voltage Vref, and generate a voltage comparison signal vout_low, which is output to the control logic circuit.

[0010] Multiple zero-crossing current detectors IZC are provided, the number of which is consistent with the number of output terminals. The two input terminals of each zero-crossing current detector IZC are respectively coupled to the two ends of the corresponding output terminal power switch Ms. The zero-crossing current detector IZC is used to detect the inductor current crossing zero when the corresponding output terminal Vout discharges, and generates the corresponding current zero-crossing signal zc, which is output to the control logic circuit.

[0011] A peak current detector IPK is provided, with its two input terminals coupled to the two ends of the input-side power switch Mp. The peak current detector IPK is used to detect when the inductor current reaches its peak value and generate a peak current signal pk, which is then output to the control logic circuit.

[0012] and control logic circuitry, which performs the following steps:

[0013] S1. Trigger inductor charging based on the voltage comparison signal vout_low output by the voltage comparator VCMP;

[0014] S2. When the inductor is charging, the peak current detector IPK is used to detect the inductor current through the power switch Mp and trigger the inductor to discharge.

[0015] S3. During inductor discharge, a zero-crossing current detector IZC is used to detect the inductor current through the power switch Ms on the output side; when the inductor current drops to 0, a current zero-crossing signal zc is generated to control all power switches to turn off and end the discharge.

[0016] S4. After the inductor discharges, a sleep mode signal (sleep) is generated based on the voltage comparison signal (vout_low) and the current zero-crossing signal (zc). When the inductor current crosses zero and all output voltages are higher than the reference value, the peak current detector (IPK) and the zero-crossing current detector (IZC) are turned off.

[0017] Further, S1 includes: each voltage comparator VCMP acquires the voltage divider signal Vfb at its corresponding output terminal and compares it with the corresponding reference voltage Vref; when the voltage divider signal Vfb at any output terminal is lower than the corresponding reference voltage Vref, a corresponding voltage comparison signal vout_low is generated, triggering inductor charging, and the input-side power switch Mp and the corresponding output-side power switch Ms are turned on.

[0018] Furthermore, if the voltage divider signals Vfb of multiple output terminals are all lower than the corresponding reference voltage Vref, then according to the preset output priority, it is determined that the inductor will be charged and then discharged by the high-priority output terminal.

[0019] Further, S2 includes: a peak current detector IPK acquires the current passing through the power switch Mp located on the input side of the single inductor and compares it with a preset peak threshold; if the single inductor current reaches the peak threshold, a peak current signal pk is generated to control the power switch Mp to turn off, and the power switch Mn and the corresponding output-side power switch Ms to turn on, so that the single inductor switches from charging to discharging at the corresponding output terminal.

[0020] Further, S4 includes: if the zero-crossing current detector IZC corresponding to the current discharge output terminal of the inductor detects the inductor current crossing zero and generates a corresponding current zero-crossing signal zc, and the voltage divider signal Vfb of the current output terminal is higher than the corresponding reference voltage Vref within a preset time, then a sleep mode signal sleep is generated, and the peak current detector IPK and the zero-crossing current detector IZC are turned off by the sleep mode signal sleep; when the voltage divider signal Vfb of any output terminal is lower than the corresponding reference voltage Vref, the operation of the zero-crossing current detector IZC and the peak current detector IPK is resumed.

[0021] Secondly, the present invention provides a single-inductor multi-output switching converter, which realizes single-input multi-output buck-boost control, including a control module and a single inductor located outside the control module. The inductor converts and distributes the input voltage Vbat through the control module, and generates multiple stable voltages Vout1, Vout2...Voutm at the output terminal; wherein, the control module includes;

[0022] A power switch group includes input power switches Mp and Mn, output power switch Msn, and corresponding power switches Ms1, Ms2...Msm, where m represents the total number of output terminals. One end of each power switch Mp and Mn is connected to the input side of an inductor, the other end of power switch Mp is connected to the input terminal Vbat, and the other end of power switch Mn is grounded. One end of each power switch Msn is connected to the output side of the inductor, and the other end is grounded. One end of each power switch Ms1, Ms2...Msm is connected to the output side of the inductor, and the other end is connected to the corresponding output terminals Vout1, Vout2...Voutm, respectively.

[0023] Multiple voltage comparators (VCMPs) are used, with the number of VCMPs matching the number of output terminals. The inverting input of each VCMP is connected to its corresponding output terminal Vout via a voltage divider circuit, and the non-inverting input of each VCMP is connected to its corresponding reference voltage Vref. The VCMPs are used to compare the voltage divider signal Vfb of each output terminal with the corresponding reference voltage Vref, and generate a voltage comparison signal vout_low, which is output to the control logic circuit.

[0024] Multiple zero-crossing current detectors IZC are provided, the number of which is consistent with the number of output terminals. The two input terminals of each zero-crossing current detector IZC are respectively coupled to the two ends of the corresponding output terminal power switch Ms. The zero-crossing current detector IZC is used to detect the inductor current crossing zero when the corresponding output terminal Vout discharges, and generates the corresponding current zero-crossing signal zc, which is output to the control logic circuit.

[0025] A peak current detector IPK is provided, with its two input terminals coupled to the two ends of the output-side power switch Msn. The peak current detector IPK is used to detect when the inductor current reaches its peak value and generate a peak current signal pk, which is then output to the control logic circuit.

[0026] and control logic circuitry, which performs the following steps:

[0027] S1. Trigger inductor charging based on the voltage comparison signal vout_low output by the voltage comparator VCMP;

[0028] S2. When the inductor is charging, the peak current detector IPK is used to detect the inductor current through the power switch Msn and trigger the inductor to discharge.

[0029] S3. During inductor discharge, a zero-crossing current detector IZC is used to detect the inductor current passing through the power switch Ms on the output side, and a timing module is used for timing.

[0030] If the zero-crossing current detector IZC does not detect the inductor current crossing zero within the set time, the power switch Mp will be turned off and Mn will be turned on after the set time is reached to accelerate the inductor discharge; until the inductor current crossing zero is detected, a current zero-crossing signal zc is generated, and all switches on the output side are turned off to end the discharge.

[0031] If the zero-crossing current detector IZC detects that the inductor current has crossed to zero within the set time, it generates a zero-crossing current signal zc, which controls all switches on the output side to turn off and end the discharge.

[0032] S4. After the inductor discharges, a sleep mode signal (sleep) is generated based on the voltage comparison signal (vout_low) and the current zero-crossing signal (zc). When the inductor current crosses zero and there is no output, the peak current detector (IPK) and the zero-crossing current detector (IZC) are turned off.

[0033] Further, S1 includes: each voltage comparator VCMP acquires the voltage divider signal Vfb at its corresponding output terminal and compares it with the corresponding reference voltage Vref; when the voltage divider signal Vfb at any output terminal is lower than the corresponding reference voltage Vref, a corresponding voltage comparison signal vout_low is generated, triggering inductor charging and power switches Mp and Msn to turn on.

[0034] Furthermore, if the voltage divider signals Vfb of multiple output terminals are all lower than the corresponding reference voltage Vref, then according to the preset output priority, it is determined that the inductor will be charged and then discharged by the high-priority output terminal.

[0035] Further, S2 includes: a peak current detector IPK acquires the current passing through the power switch Msn located on the output side of the single inductor and compares it with a preset peak threshold; if the single inductor current reaches the peak threshold, a peak current signal pk is generated to control the power switch Msn to turn off and the corresponding output side power switch Ms to turn on, so that the single inductor switches from charging to discharging at the corresponding output terminal.

[0036] Further, S4 includes: if the zero-crossing current detector IZC corresponding to the current discharge output terminal of the inductor detects the inductor current crossing zero and generates a corresponding current zero-crossing signal zc, and the voltage divider signal Vfb of the current output terminal is higher than the corresponding reference voltage Vref within a preset time, then a sleep mode signal sleep is generated, and the peak current detector IPK and the zero-crossing current detector IZC are turned off by the sleep mode signal sleep; when the voltage divider signal Vfb of any output terminal is lower than the corresponding reference voltage Vref, the operation of the zero-crossing current detector IZC and the peak current detector IPK is resumed.

[0037] The beneficial effects of this invention are:

[0038] This invention discloses a single-inductor multi-output switching converter. It continuously compares the voltage feedback signals from multiple output terminals with a preset reference voltage to determine whether inductor charging / discharging is required. When charging is needed, the charging switch Mp is turned on, allowing the single inductor to draw energy from the input terminal. When the inductor current reaches a preset peak value, the discharging switch Ms is turned on, allowing the single inductor to discharge to the output terminal. During discharging, the inductor current value is continuously monitored; when the current crosses zero, the discharge is considered complete, and all power switches are turned off. If all voltage comparison results are invalid, the converter enters sleep mode and disables the current comparator.

[0039] This invention enables a single inductor to power multiple output terminals, improving power efficiency, simplifying circuit structure, and further reducing power consumption through sleep mode, making it suitable for portable electronic devices and other scenarios.

[0040] The single-inductor multi-output switching converter proposed in this invention simplifies the circuitry compared to existing control methods, saving area and cost, and facilitating the expansion of the number of inputs and outputs. It triggers switching activity by directly comparing the output with a reference and introduces a sleep signal to reduce losses, making it suitable for light-load applications. The system can respond immediately to load changes, and the output voltage has small overshoot and undershoot, providing a stable and efficient solution for the power management module of electronic systems.

[0041] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0042] The above and other objects, features and advantages of the present invention will become more apparent from the more detailed description of exemplary embodiments of the invention in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the invention.

[0043] Figure 1 A block diagram of a single-inductor multi-output switching converter is shown.

[0044] Figure 2 The control flowchart of a single-inductor multi-output switching converter is shown.

[0045] Figure 3 The circuit diagram of a single-inductor multi-output switching converter for implementing single-input multi-output buck control is shown.

[0046] Figure 4 It shows Figure 3 A schematic diagram of the control logic of the circuit.

[0047] Figure 5 The circuit diagram of a single-inductor multi-output switching converter for implementing single-input multi-output buck-boost control is shown.

[0048] Figure 6 It shows Figure 5 A schematic diagram of the control logic of the circuit.

[0049] Figure 7 A schematic diagram showing the steady-state waveform comparison of a single-input dual-output buck control system is presented.

[0050] Figure 8 This diagram illustrates the comparison of output voltage waveforms when the load on one of the outputs of a switching converter undergoes a sudden change. Detailed Implementation

[0051] Preferred embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0052] The block diagram of the single-inductor multi-output switching converter proposed in this invention is as follows: Figure 1 As shown. The system can support a single DC input, such as 3.7V on the left side of the figure, and use a single off-chip inductor to convert and distribute the energy, generating multiple stable DC voltages at the output, such as 1.8V and 1.3V on the right side of the figure.

[0053] Taking a single-input dual-output system as an example, the control flowchart is as follows: Figure 2 As shown. The circuit's default state is that all switches are off, at which point the inductor current is 0.

[0054] A normally open voltage comparator continuously monitors the voltage dividers Vfb1 and Vfb2 of the two output voltages Vout1 and Vout2. When they fall below their respective reference voltages Vref1 and Vref2, the inductor begins to charge.

[0055] The two output voltages can have a fixed priority order, for example... Figure 2 In this case, Vout1 always has a higher priority than Vout2. The maximum number of consecutive discharges to the same output can also be further constrained.

[0056] When the inductor is charging, a current peak comparator is used to continuously detect the inductor current value. Once the set peak value is reached, the output is discharged.

[0057] When the inductor discharges, a current zero-crossing comparator is used to continuously detect the inductor current value, and it returns to the default state when the current crosses zero.

[0058] This control flow can be easily extended to single-inductor multiple-input multiple-output converters. For multiple-input architectures, it is only necessary to determine which input voltage exceeds a set threshold, and the inductor charging and discharging will then proceed from that input.

[0059] The control circuit proposed in this invention can be applied to various power stage topologies, including buck and buck-boost.

[0060] Example 1

[0061] Figures 3 and 4 show the circuit diagram and control logic schematic of a single-inductor multi-output switching converter to implement single-input multi-output buck control.

[0062] This invention provides a single-inductor multi-output switching converter, which realizes single-input multi-output buck control. It includes a control module and a single inductor located outside the control module. The inductor converts and distributes the input voltage Vbat through the control module, generating multiple stable output voltages Vout1, Vout2...Voutm. The control module includes:

[0063] A power switch group includes input power switches Mp and Mn, and corresponding output power switches Ms1, Ms2...Msm, where m represents the total number of output terminals. One end of each power switch Mp and Mn is connected to the input side of an inductor, the other end of power switch Mp is connected to the input terminal Vbat, and the other end of power switch Mn is grounded. One end of each power switch Ms1, Ms2...Msm is connected to the output side of an inductor, and the other end is connected to the corresponding output terminals Vout1, Vout2...Voutm, respectively.

[0064] Multiple voltage comparators (VCMPs) are used, with the number of VCMPs matching the number of output terminals. The inverting input of each VCMP is connected to its corresponding output terminal Vout via a voltage divider circuit, and the non-inverting input of each VCMP is connected to its corresponding reference voltage Vref. The VCMPs are used to compare the voltage divider signal Vfb of each output terminal with the corresponding reference voltage Vref, and generate a voltage comparison signal vout_low, which is output to the control logic circuit.

[0065] Multiple zero-crossing current detectors IZC are provided, the number of which is consistent with the number of output terminals. The two input terminals of each zero-crossing current detector IZC are respectively coupled to the two ends of the corresponding output terminal power switch Ms. The zero-crossing current detector IZC is used to detect the inductor current crossing zero when the corresponding output terminal Vout discharges, and generates the corresponding current zero-crossing signal zc, which is output to the control logic circuit.

[0066] A peak current detector IPK is provided, with its two input terminals coupled to the two ends of the input-side power switch Mp. The peak current detector IPK is used to detect when the inductor current reaches its peak value and generate a peak current signal pk, which is then output to the control logic circuit.

[0067] and control logic circuitry, which performs the following steps:

[0068] S1. Trigger inductor charging based on the voltage comparison signal vout_low output by the voltage comparator VCMP;

[0069] S2. When the inductor is charging, the peak current detector IPK is used to detect the inductor current through the power switch Mp and trigger the inductor to discharge.

[0070] S3. During inductor discharge, a zero-crossing current detector IZC is used to detect the inductor current through the power switch Ms on the output side; when the inductor current drops to 0, a current zero-crossing signal zc is generated to control all power switches to turn off and end the discharge.

[0071] S4. After the inductor discharges, a sleep mode signal (sleep) is generated based on the voltage comparison signal (vout_low) and the current zero-crossing signal (zc). When the inductor current crosses zero and there is no output, the peak current detector (IPK) and the zero-crossing current detector (IZC) are turned off.

[0072] In one example, S1 includes:

[0073] Each voltage comparator (VCMP) acquires the voltage divider signal Vfb at its corresponding output terminal and compares it with the corresponding reference voltage Vref.

[0074] When the voltage divider signal Vfb at any output terminal is lower than the corresponding reference voltage Vref, a corresponding voltage comparison signal vout_low is generated, triggering inductor charging.

[0075] If the voltage divider signals Vfb of multiple output terminals are all lower than the corresponding reference voltage Vref, then according to the preset output priority, it is determined that the high-priority output terminal will discharge after the inductor is charged, and the number of consecutive discharges to the same output terminal is limited by the control logic circuit.

[0076] In one example, S2 includes:

[0077] The peak current detector IPK acquires the current passing through the power switch Mp located on the single inductor input side and compares it with a preset peak threshold.

[0078] If the current of a single inductor reaches the peak threshold, a peak current signal pk is generated, which controls the power switch Mp to turn off and the corresponding output-side power switch Ms to turn on, so that the single inductor switches from charging to discharging at the corresponding output terminal.

[0079] In one example, S4 includes:

[0080] If the zero-crossing current detector IZC corresponding to the current discharge output terminal of the inductor detects the inductor current crossing zero and generates the corresponding current zero-crossing signal zc, and the voltage divider signal Vfb of the current output terminal is higher than the corresponding reference voltage Vref within a preset time, then a sleep mode signal sleep is generated, and the peak current detector IPK and the zero-crossing current detector IZC are turned off by the sleep mode signal sleep.

[0081] When the voltage divider signal Vfb at any output terminal is lower than the corresponding reference voltage Vref, the zero-crossing current detector IZC and the peak current detector IPK resume operation.

[0082] Example 2

[0083] Figures 5 and 6 show the circuit diagram and control logic schematic of a single-inductor multi-output switching converter to implement single-input multi-output buck-boost control.

[0084] This invention provides a single-inductor multi-output switching converter, which realizes single-input multi-output buck-boost control. It includes a control module and a single inductor located outside the control module. The inductor converts and distributes the input voltage Vbat through the control module, generating multiple stable voltages Vout1, Vout2...Voutm at the output. The control module includes:

[0085] A power switch group includes input power switches Mp and Mn, output power switch Msn, and corresponding power switches Ms1, Ms2...Msm, where m represents the total number of output terminals. One end of each power switch Mp and Mn is connected to the input side of an inductor, the other end of power switch Mp is connected to the input terminal Vbat, and the other end of power switch Mn is grounded. One end of each power switch Msn is connected to the output side of the inductor, and the other end is grounded. One end of each power switch Ms1, Ms2...Msm is connected to the output side of the inductor, and the other end is connected to the corresponding output terminals Vout1, Vout2...Voutm, respectively.

[0086] Multiple voltage comparators (VCMPs) are used, with the number of VCMPs matching the number of output terminals. The inverting input of each VCMP is connected to its corresponding output terminal Vout via a voltage divider circuit, and the non-inverting input of each VCMP is connected to its corresponding reference voltage Vref. The VCMPs are used to compare the voltage divider signal Vfb of each output terminal with the corresponding reference voltage Vref, and generate a voltage comparison signal vout_low, which is output to the control logic circuit.

[0087] Multiple zero-crossing current detectors IZC are provided, the number of which is consistent with the number of output terminals. The two input terminals of each zero-crossing current detector IZC are respectively coupled to the two ends of the corresponding output terminal power switch Ms. The zero-crossing current detector IZC is used to detect the inductor current crossing zero when the corresponding output terminal Vout discharges, and generates the corresponding current zero-crossing signal zc, which is output to the control logic circuit.

[0088] A peak current detector IPK is provided, with its two input terminals coupled to the two ends of the output-side power switch Msn. The peak current detector IPK is used to detect when the inductor current reaches its peak value and generate a peak current signal pk, which is then output to the control logic circuit.

[0089] and control logic circuitry, which performs the following steps:

[0090] S1. Trigger inductor charging based on the voltage comparison signal vout_low output by the voltage comparator VCMP;

[0091] S2. When the inductor is charging, the peak current detector IPK is used to detect the inductor current through the power switch Msn and trigger the inductor to discharge.

[0092] S3. During inductor discharge, a zero-crossing current detector IZC is used to detect the inductor current passing through the power switch Ms on the output side, and a timing module is used for timing.

[0093] If the zero-crossing current detector IZC does not detect the inductor current crossing zero within the set time, the power switch Mp will be turned off and Mn will be turned on after the set time is reached to accelerate the inductor discharge; until the inductor current crossing zero is detected, a current zero-crossing signal zc is generated, and all switches on the output side are turned off to end the discharge.

[0094] If the zero-crossing current detector IZC detects that the inductor current has crossed to zero within the set time, it generates a zero-crossing current signal zc, which controls all switches on the output side to turn off and end the discharge.

[0095] S4. After the inductor discharges, a sleep mode signal (sleep) is generated based on the voltage comparison signal (vout_low) and the current zero-crossing signal (zc). When the inductor current crosses zero and there is no output, the peak current detector (IPK) and the zero-crossing current detector (IZC) are turned off.

[0096] The converter proposed in this invention has the advantage of high efficiency under light load, which is illustrated below by the steady-state waveform of the system.

[0097] The steady-state waveform of the system can be divided into three cases. Taking a single-input dual-output buck converter as an example, the inductor current and output voltage waveforms are as follows: Figure 7 As shown.

[0098] Figure 7 In (a), the load is the lightest, and the voltage comparator can be toggled by a single charge and discharge of the inductor. At this time, the system operates in discontinuous conduction mode, and the sleep state accounts for a relatively high proportion of the operating cycle. As the load current of both outputs increases, two changes occur in the system:

[0099] 1. The output voltage increase from one charge / discharge cycle of the inductor decreases until it can no longer overcome the voltage comparator hysteresis. At this point, multiple charge / discharge cycles of the inductor are required to make the voltage comparator output turn low. Figure 7 (b) in the middle.

[0100] 2. As the switching cycle of each output decreases, the sleep time of the system continuously decreases after the two outputs are superimposed, until there is no sleep state. The system always operates at the boundary between continuous conduction mode and discontinuous conduction mode, corresponding to... Figure 7 (c) This is also the limit of the load that the system can drive.

[0101] It is easy to see that the smaller the load current is before reaching the maximum load, the higher the proportion of the sleep state. In the sleep state, the current comparator does not operate, resulting in very low static power consumption, thus reducing the overall average static power consumption of the system. Simultaneously, thanks to the control method that directly compares the output with a reference to trigger switching activity, the switching frequency of the converter is positively correlated with the load current; the low switching frequency under light loads leads to even lower dynamic losses. In summary, this control method simultaneously reduces both the static and dynamic losses of the converter under light loads, achieving the beneficial effect of improving efficiency under light loads.

[0102] The converter proposed in this invention has the advantage of fast load response speed, which will be illustrated below by the output waveform when the load changes abruptly.

[0103] When the load on one of the converter's outputs undergoes a sudden change, the corresponding output voltage waveform is as follows: Figure 8 As shown.

[0104] Figure 8In the diagram, (a) shows the case of an upward load transition. After the transition, the slope of the output voltage drop immediately increases. Compared to the previous charge / discharge cycle, the output drops to the equivalent threshold kVref of the voltage comparator much faster, as shown by the dashed line in the figure. However, the circuit state does not change immediately; it undergoes a delay Td,on, primarily consisting of comparator and driver circuit delays. This delay is approximately the same as the one during the previous transition, but the output voltage drop slope is now greater, resulting in a lower final voltage ripple trough. During subsequent charge / discharge cycles, the output voltage drops at the same slope, so the voltage trough remains at this point. Thus, the load step does not cause an output undershoot but only a change in the average output value.

[0105] Figure 8 In the diagram, (b) considers the case of a downward load jump. This system monitors the output valley value; charging and discharging will not occur unless the voltage comparator flips. Similar to the previous analysis, after the jump, the output voltage drop slope immediately decreases. Compared to the previous charge / discharge, the output voltage valley value is higher because the voltage drop slope is smaller during the comparator delay. During subsequent charge / discharge processes, the output voltage peak and valley values ​​remain unchanged. Therefore, this load step does not cause output overshoot, but only a change in the output average value.

[0106] In summary, load jumps will hardly cause output spikes or dips. After a load step change, the system can immediately adjust to the next steady state, and the load response speed is very fast.

[0107] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A comparator-based single-inductor multi-output switching converter, characterized in that, The switching converter implements single-input multiple-output buck control, including a control module and a single inductor located outside the control module. The inductor converts and distributes the input voltage Vbat through the control module, generating multiple stable voltages Vout1, Vout2...Voutm at the output. The control module includes: A power switch group includes input power switches Mp and Mn, and corresponding output power switches Ms1, Ms2...Msm, where m represents the total number of output terminals. One end of each power switch Mp and Mn is connected to the input side of an inductor, the other end of power switch Mp is connected to the input terminal Vbat, and the other end of power switch Mn is grounded. One end of each power switch Ms1, Ms2...Msm is connected to the output side of an inductor, and the other end is connected to the corresponding output terminals Vout1, Vout2...Voutm, respectively. Multiple voltage comparators (VCMPs) are used, with the number of VCMPs matching the number of output terminals. The inverting input of each VCMP is connected to its corresponding output terminal Vout via a voltage divider circuit, and the non-inverting input of each VCMP is connected to its corresponding reference voltage Vref. The VCMPs are used to compare the voltage divider signal Vfb of each output terminal with the corresponding reference voltage Vref, and generate a voltage comparison signal vout_low, which is output to the control logic circuit. Multiple zero-crossing current detectors IZC are provided, the number of which is consistent with the number of output terminals. The two input terminals of each zero-crossing current detector IZC are respectively coupled to the two ends of the corresponding output terminal power switch Ms. The zero-crossing current detector IZC is used to detect the inductor current crossing zero when the corresponding output terminal Vout discharges, and generates the corresponding current zero-crossing signal zc, which is output to the control logic circuit. A peak current detector IPK is provided, with its two input terminals coupled to the two ends of the input-side power switch Mp. The peak current detector IPK is used to detect when the inductor current reaches its peak value and generate a peak current signal pk, which is then output to the control logic circuit. and control logic circuitry, which performs the following steps: S1. Trigger inductor charging based on the voltage comparison signal vout_low output by the voltage comparator VCMP; S2. When the inductor is charging, the peak current detector IPK is used to detect the inductor current through the power switch Mp and trigger the inductor to discharge. S3. During inductor discharge, a zero-crossing current detector IZC is used to detect the inductor current through the power switch Ms on the output side; when the inductor current drops to 0, a current zero-crossing signal zc is generated to control all power switches to turn off and end the discharge. S4. After the inductor discharges, a sleep mode signal sleep is generated based on the voltage comparison signal vout_low and the current zero-crossing signal zc. When the inductor current crosses zero and all output voltages are higher than the reference value, the peak current detector IPK and the zero-crossing current detector IZC are turned off. S4 includes: if the zero-crossing current detector IZC corresponding to the current discharge output terminal of the inductor detects the inductor current crossing zero and generates the corresponding current zero-crossing signal zc, and the voltage divider signal Vfb of the current output terminal is higher than the corresponding reference voltage Vref within a preset time, then a sleep mode signal sleep is generated, and the peak current detector IPK and the zero-crossing current detector IZC are turned off by the sleep mode signal sleep; when the voltage divider signal Vfb of any output terminal is lower than the corresponding reference voltage Vref, the operation of the zero-crossing current detector IZC and the peak current detector IPK is resumed.

2. The single-inductor multi-output switching converter as described in claim 1, characterized in that... S1 includes: Each voltage comparator VCMP acquires the voltage divider signal Vfb at its corresponding output terminal and compares it with the corresponding reference voltage Vref. When the voltage divider signal Vfb at any output terminal is lower than the corresponding reference voltage Vref, a corresponding voltage comparison signal vout_low is generated, triggering inductor charging and turning on the input-side power switch Mp and the corresponding output-side power switch Ms.

3. The single-inductor multi-output switching converter as described in claim 2, characterized in that, If the voltage divider signals Vfb of multiple output terminals are all lower than the corresponding reference voltage Vref, then according to the preset output priority, it is determined that the inductor will be charged and then discharged by the high-priority output terminal.

4. The single-inductor multi-output switching converter as described in claim 1, characterized in that... S2 includes: The peak current detector IPK acquires the current passing through the power switch Mp located on the single inductor input side and compares it with a preset peak threshold. If the current of a single inductor reaches the peak threshold, a peak current signal pk is generated, which controls the power switch Mp to turn off, and the power switch Mn and the corresponding output-side power switch Ms to turn on, so that the single inductor switches from charging to discharging at the corresponding output terminal.

5. A comparator-based single-inductor multi-output switching converter, characterized in that, The switching converter implements single-input multi-output buck-boost control, including a control module and a single inductor located outside the control module. The inductor converts and distributes the input voltage Vbat through the control module, generating multiple stable voltages Vout1, Vout2...Voutm at the output. The control module includes: A power switch group includes input power switches Mp and Mn, output power switch Msn, and corresponding power switches Ms1, Ms2...Msm, where m represents the total number of output terminals. One end of each power switch Mp and Mn is connected to the input side of an inductor, the other end of power switch Mp is connected to the input terminal Vbat, and the other end of power switch Mn is grounded. One end of each power switch Msn is connected to the output side of the inductor, and the other end is grounded. One end of each power switch Ms1, Ms2...Msm is connected to the output side of the inductor, and the other end is connected to the corresponding output terminals Vout1, Vout2...Voutm, respectively. Multiple voltage comparators (VCMPs) are used, with the number of VCMPs matching the number of output terminals. The inverting input of each VCMP is connected to its corresponding output terminal Vout via a voltage divider circuit, and the non-inverting input of each VCMP is connected to its corresponding reference voltage Vref. The VCMPs are used to compare the voltage divider signal Vfb of each output terminal with the corresponding reference voltage Vref, and generate a voltage comparison signal vout_low, which is output to the control logic circuit. Multiple zero-crossing current detectors IZC are provided, the number of which is consistent with the number of output terminals. The two input terminals of each zero-crossing current detector IZC are respectively coupled to the two ends of the corresponding output terminal power switch Ms. The zero-crossing current detector IZC is used to detect the inductor current crossing zero when the corresponding output terminal Vout discharges, and generates the corresponding current zero-crossing signal zc, which is output to the control logic circuit. A peak current detector IPK is provided, with its two input terminals coupled to the two ends of the output-side power switch Msn. The peak current detector IPK is used to detect when the inductor current reaches its peak value and generate a peak current signal pk, which is then output to the control logic circuit. and control logic circuitry, which performs the following steps: S1. Trigger inductor charging based on the voltage comparison signal vout_low output by the voltage comparator VCMP; S2. When the inductor is charging, the peak current detector IPK is used to detect the inductor current through the power switch Msn and trigger the inductor to discharge. S3. During inductor discharge, a zero-crossing current detector IZC is used to detect the inductor current passing through the power switch Ms on the output side, and a timing module is used for timing. If the zero-crossing current detector IZC does not detect the inductor current crossing zero within the set time, the power switch Mp will be turned off and Mn will be turned on after the set time is reached to accelerate the inductor discharge; until the inductor current crossing zero is detected, a current zero-crossing signal zc is generated, and all switches on the output side are turned off to end the discharge. If the zero-crossing current detector IZC detects that the inductor current has crossed to zero within the set time, it generates a zero-crossing current signal zc, which controls all switches on the output side to turn off and end the discharge. S4. After the inductor discharges, a sleep mode signal sleep is generated based on the voltage comparison signal vout_low and the current zero-crossing signal zc. When the inductor current crosses zero and all output voltages are higher than the reference value, the peak current detector IPK and the zero-crossing current detector IZC are turned off. S4 includes: if the zero-crossing current detector IZC corresponding to the current discharge output terminal of the inductor detects the inductor current crossing zero and generates the corresponding current zero-crossing signal zc, and the voltage divider signal Vfb of the current output terminal is higher than the corresponding reference voltage Vref within a preset time, then a sleep mode signal sleep is generated, and the peak current detector IPK and the zero-crossing current detector IZC are turned off by the sleep mode signal sleep; when the voltage divider signal Vfb of any output terminal is lower than the corresponding reference voltage Vref, the operation of the zero-crossing current detector IZC and the peak current detector IPK is resumed.

6. The single-inductor multi-output switching converter as described in claim 5, characterized in that... S1 includes: Each voltage comparator VCMP acquires the voltage divider signal Vfb at its corresponding output terminal and compares it with the corresponding reference voltage Vref. When the voltage divider signal Vfb at any output terminal is lower than the corresponding reference voltage Vref, the corresponding voltage comparison signal vout_low is generated, triggering inductor charging and power switches Mp and Msn to turn on.

7. The single-inductor multi-output switching converter as described in claim 6, characterized in that, If the voltage divider signals Vfb of multiple output terminals are all lower than the corresponding reference voltage Vref, then according to the preset output priority, it is determined that the inductor will be charged and then discharged by the high-priority output terminal.

8. The single-inductor multi-output switching converter as described in claim 5, characterized in that S2 include: The peak current detector IPK acquires the current passing through the power switch Msn located on the output side of the single inductor and compares it with a preset peak threshold. If the current of a single inductor reaches the peak threshold, a peak current signal pk is generated, which controls the power switch Msn to turn off and the corresponding output-side power switch Ms to turn on, so that the single inductor switches from charging to discharging at the corresponding output terminal.

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