A linear drive amplifier with high slew rate

Abstract

This application belongs to the field of integrated circuit technology and discloses a high-slew rate linear drive amplifier, including a push-pull current input module, a power consumption control module, and a push-pull output module connected in sequence. The push-pull current input module includes a pull-up current transistor, a pull-down current transistor, a first unidirectional path, a second unidirectional path, and a push-pull current branch. The push-pull current branch includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor. The sources of the pull-up current transistor and the pull-down current transistor are connected. The positive terminal of the first unidirectional path is connected to the drain of the pull-up current transistor, and the negative terminal is connected to the drain of the first NMOS transistor. The positive terminal of the second unidirectional path is connected to the drain of the second PMOS transistor, and the negative terminal is connected to the drain of the pull-down current transistor. This application enables each MOS transistor to always operate in the saturation region, avoiding the decrease in slew rate caused by rapid changes in input current.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a high slew rate linear drive amplifier. Background Technology

[0002] A linear drive amplifier is an electronic component that amplifies an input signal without distortion. It amplifies the input signal by a certain factor while maintaining the same waveform as the input signal in the output signal, ensuring signal quality and reliability.

[0003] As its application areas expand, the requirements for linear drive also increase. However, in the high-voltage domain, low power consumption, high linearity, wide bandwidth, high slew rate, wide input / output range, large drive capability, and stability are mutually restrictive, making it difficult to achieve a good balance between low power consumption, high linearity, wide bandwidth, and high slew rate. Therefore, the technical problem addressed in this application is how to achieve a linear drive amplifier with low power consumption, high linearity, and high slew rate in the high-voltage domain. Summary of the Invention

[0004] This application provides a high slew rate linear drive amplifier that enables each MOSFET to always operate in the saturation region, avoiding the reduction in slew rate caused by rapid changes in input current.

[0005] This application provides a high-slew rate linear drive amplifier, including a push-pull current input module, a power consumption control module, and a push-pull output module connected in sequence. The push-pull current input module includes:

[0006] Pull-up current transistor, pull-down current transistor, first unidirectional path, second unidirectional path, and push-pull current branch;

[0007] The push-pull current branch includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor;

[0008] The source of the pull-up current transistor and the source of the pull-down current transistor are connected; the positive terminal of the first unidirectional path is connected to the drain of the pull-up current transistor, and the negative terminal is connected to the drain of the first NMOS transistor; the positive terminal of the second unidirectional path is connected to the drain of the second PMOS transistor, and the negative terminal is connected to the drain of the pull-down current transistor.

[0009] Furthermore, the push-pull current branch also includes a third NMOS transistor, a fourth NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; the gate of the first NMOS transistor is connected to the drain of the first NMOS transistor and the gate of the third NMOS transistor, respectively; the source of the first NMOS transistor is connected to the drain of the second NMOS transistor; the gate of the second NMOS transistor is connected to the drain of the second NMOS transistor and the gate of the fourth NMOS transistor, respectively; the source of the second NMOS transistor is connected to the source of the first PMOS transistor.

[0010] The gate of the first PMOS transistor is connected to the drain of the first PMOS transistor and the gate of the third PMOS transistor; the drain of the first PMOS transistor is connected to the source of the second PMOS transistor; the gate of the second PMOS transistor is connected to the drain of the second PMOS transistor and the gate of the fourth PMOS transistor; the drain of the second PMOS transistor is grounded.

[0011] Furthermore, the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor; the source of the fourth NMOS transistor is connected to the source of the third PMOS transistor; and the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor.

[0012] The drains of the third NMOS transistor and the fourth PMOS transistor are both connected to the power control module.

[0013] Furthermore, the gate of the pull-up current transistor and the gate of the pull-down current transistor are connected, and are also connected to the source of the second NMOS transistor and the source of the first PMOS transistor; the source of the pull-up current transistor and the source of the pull-down current transistor are connected, and are also connected to the source of the fourth NMOS transistor and the source of the third PMOS transistor.

[0014] Furthermore, the linear drive amplifier also includes a voltage-controlled current source module; the voltage-controlled current source module includes a first current source, a first voltage-controlled current source, a second current source, and a second voltage-controlled current source;

[0015] The input terminals of the first current source and the first voltage-controlled current source are both connected to the power supply voltage; the output terminal of the first current source is connected to the drain of the third NMOS transistor and the output terminal of the first voltage-controlled current source, respectively; the input terminal of the first voltage-controlled current source is also connected to the reference voltage, and the output terminal is connected to the drain of the third NMOS transistor and the power consumption control module, respectively.

[0016] The output terminals of the second current source and the second voltage-controlled current source are both grounded; the input terminal of the second current source is connected to the drain of the fourth PMOS transistor and the input terminal of the second voltage-controlled current source, respectively; the output terminal of the second voltage-controlled current source is also connected to the reference voltage, and the input terminal is connected to the drain of the fourth PMOS transistor and the power consumption control module, respectively.

[0017] Furthermore, the power consumption control module includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a first capacitor, and a second capacitor;

[0018] The fifth NMOS transistor, the fifth PMOS transistor, the positive terminal of the first capacitor, and the gate of the seventh PMOS transistor are all connected to the output terminal of the first voltage-controlled current source of the voltage-controlled current source module; the sixth NMOS transistor, the sixth PMOS transistor, the positive terminal of the second capacitor, and the gate of the seventh NMOS transistor are all connected to the input terminal of the second voltage-controlled current source of the voltage-controlled current source module.

[0019] The source of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor;

[0020] The drain of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor; the gates of the fifth NMOS transistor, the sixth NMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are connected to a limiting voltage.

[0021] The drain of the seventh PMOS transistor and the drain of the seventh NMOS transistor are connected together and connected to the push-pull output module; the source of the seventh PMOS transistor is connected to the power supply voltage; the source of the seventh NMOS transistor is grounded.

[0022] The negative terminals of the first capacitor and the second capacitor are connected together and then connected to the push-pull output module.

[0023] Furthermore, the push-pull output module includes a third voltage-controlled current source, a fourth voltage-controlled current source, an eighth NMOS transistor, a ninth NMOS transistor, an eighth PMOS transistor, and a ninth PMOS transistor;

[0024] The input terminal of the third voltage-controlled current source is connected to the source of the ninth NMOS transistor, the negative terminal of the first capacitor, the negative terminal of the second capacitor, and the output port of the push-pull output module, respectively; the output terminal of the third voltage-controlled current source is connected to the source of the eighth NMOS transistor, the source of the eighth PMOS transistor, and ground, respectively.

[0025] The source of the eighth NMOS transistor is connected to the source of the eighth PMOS transistor, and is also connected to the drain of the seventh PMOS transistor, the drain of the seventh NMOS transistor, the source of the ninth NMOS transistor, and the source of the ninth PMOS transistor; the input terminal of the fourth voltage-controlled current source is connected to the power supply voltage, the source of the eighth NMOS transistor, and the source of the eighth PMOS transistor; the output terminal of the fourth voltage-controlled current source is connected to the negative terminal of the first capacitor, the negative terminal of the second capacitor, and the output port of the push-pull output module.

[0026] The drains of the eighth NMOS transistor and the ninth NMOS transistor are both connected to the power supply voltage;

[0027] The drains of both the eighth and ninth PMOS transistors are grounded.

[0028] Furthermore, the first, second, third, and fourth voltage-controlled current sources are all differentially input GM amplifiers.

[0029] Furthermore, the pull-up current transistor is an NMOS transistor, and the pull-down current transistor is a PMOS transistor.

[0030] Furthermore, both the first unidirectional path and the second unidirectional path are diodes.

[0031] In summary, compared with the prior art, the beneficial effects of the technical solution provided in this application include at least the following:

[0032] This application provides a high slew rate linear drive amplifier. By adding a first unidirectional path and a second unidirectional path to the push-pull current input module, it ensures that the first NMOS transistor, the second NMOS transistor, the first PMOS transistor, and the second PMOS transistor in the push-pull current branch always have current flowing through them. This keeps each MOS transistor working in the saturation region and prevents the first NMOS transistor and the second NMOS transistor from entering the cutoff region due to rapid changes in input, which would otherwise reduce the slew rate. Attached Figure Description

[0033] Figure 1 A block diagram of a high slew rate linear drive amplifier is provided for an exemplary embodiment of this application.

[0034] Figure 2 A circuit schematic of a high slew rate linear drive amplifier is provided as an exemplary embodiment of this application. Detailed Implementation

[0035] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0036] Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0037] Please see Figure 1 This application provides a high-voltage slew rate linear drive amplifier, including a push-pull current input module 100, a power consumption control module 300, and a push-pull output module 400 connected in sequence.

[0038] The push-pull current input module 100 includes: a pull-up current transistor M4, a pull-down current transistor M5, a first unidirectional path D0, a second unidirectional path D1, and a push-pull current branch.

[0039] Please see Figure 2The push-pull current branch includes a first NMOS transistor M6, a second NMOS transistor M7, a first PMOS transistor M8, and a second PMOS transistor M9; the push-pull current branch also includes a third NMOS transistor M10, a fourth NMOS transistor M11, a third PMOS transistor M12, and a fourth PMOS transistor M13.

[0040] Figure 2 Except for D0 and D1, which are new circuit modules added in this application, the rest are existing linear drive amplifier structures.

[0041] Among them, the pull-up current transistor is an NMOS transistor, and the pull-down current transistor is a PMOS transistor.

[0042] Both the first and second unidirectional paths are diodes.

[0043] The source of pull-up current transistor M4 and the source of pull-down current transistor M5 are connected; the positive terminal of the first unidirectional path D0 is connected to the drain of pull-up current transistor M4, and the negative terminal is connected to the drain of the first NMOS transistor M6; the positive terminal of the second unidirectional path D1 is connected to the drain of the second PMOS transistor M9, and the negative terminal is connected to the drain of pull-down current transistor M5.

[0044] The gate of the first NMOS transistor M6 is connected to the drain of the first NMOS transistor M6 and the gate of the third NMOS transistor M10, respectively; the source of the first NMOS transistor M6 is connected to the drain of the second NMOS transistor M7.

[0045] The gate of the second NMOS transistor M7 is connected to the drain of the second NMOS transistor M7 and the gate of the fourth NMOS transistor M11, respectively; the source of the second NMOS transistor M7 is connected to the source of the first PMOS transistor M8.

[0046] The gate of the first PMOS transistor M8 is connected to the drain of the first PMOS transistor M8 and the gate of the third PMOS transistor M12, respectively; the drain of the first PMOS transistor M8 is connected to the source of the second PMOS transistor M9; the gate of the second PMOS transistor M9 is connected to the drain of the second PMOS transistor M9 and the gate of the fourth PMOS transistor M13, respectively; the drain of the second PMOS transistor M9 is grounded.

[0047] The source of the third NMOS transistor M10 is connected to the drain of the fourth NMOS transistor M11; the source of the fourth NMOS transistor M11 is connected to the source of the third PMOS transistor M12; the drain of the third PMOS transistor M12 is connected to the source of the fourth PMOS transistor M13; the drains of the third NMOS transistor M10 and the fourth PMOS transistor M13 are both connected to the power consumption control module 300.

[0048] The gate of pull-up current transistor M4 is connected to the gate of pull-down current transistor M5, and is connected to the source of the second NMOS transistor M7 and the source of the first PMOS transistor M8; the source of pull-up current transistor M4 is connected to the source of pull-down current transistor M5, and is connected to the source of the fourth NMOS transistor M11 and the source of the third PMOS transistor M12.

[0049] This application adds D0 and D1 paths to the push-pull current input module 100. When VIP changes significantly, VFB relies on M4 or M5 to provide pull-up current I2 or pull-down current I4 to quickly follow the changes in VIP. I0 and I1 ensure that the push-pull branches M6, M7, M8, and M9 always operate in the saturation region and avoid entering the cutoff region. When VIP changes slightly, M4 and M5 do not operate, and the current is provided by the push-pull branches M6, M7, M8, and M9. At this time, the current is the sum of I1 and I2 or I0 and I4.

[0050] If D0 and D1 are shorted, when VIP changes significantly, the current supplied by M4 or M5 will be the sum of I1 and I2 or I0 and I4. This causes the push-pull branches M6, M7, M8, and M9 to enter the cutoff region. When VIP changes less, the push-pull branches supply current, so M6, M7, M8, and M9 need more time to establish themselves from the cutoff region to the saturation region, thus reducing the slew rate. Similarly, if D0 and D1 are disconnected, when VIP changes less, the push-pull branches M6, M7, M8, and M9 supply currents of I0 and I4, resulting in a lower slew rate. Therefore, D0 and D1 in this application can prevent the slew rate from decreasing.

[0051] The high slew rate linear drive amplifier provided in the above embodiment ensures that the first NMOS transistor, the second NMOS transistor, the first PMOS transistor, and the second PMOS transistor in the push-pull current input module 100 always have current flowing through them, so that each MOS transistor always works in the saturation region. This prevents the first NMOS transistor and the second NMOS transistor from entering the cutoff region due to rapid changes in the input, which would otherwise reduce the slew rate.

[0052] In some embodiments, see Figure 2 The linear drive amplifier also includes a voltage-controlled current source module 200; the voltage-controlled current source module 200 includes a first current source I5, a first voltage-controlled current source G0, a second current source I6, and a second voltage-controlled current source G1;

[0053] The input terminals of the first current source I5 and the first voltage-controlled current source G0 are both connected to the power supply voltage; the output terminal of the first current source I5 is connected to the drain of the third NMOS transistor M10 and the output terminal of the first voltage-controlled current source G0 respectively; the input terminal of the first voltage-controlled current source G0 is also connected to the reference voltage, and the output terminal is connected to the drain of the third NMOS transistor M10 and the power consumption control module 300 respectively.

[0054] The output terminals of the second current source I6 and the second voltage-controlled current source G1 are both grounded; the input terminal of the second current source I6 is connected to the drain of the fourth PMOS transistor M13 and the input terminal of the second voltage-controlled current source G1, respectively; the output terminal of the second voltage-controlled current source G1 is also connected to the reference voltage, and the input terminal is connected to the drain of the fourth PMOS transistor M13 and the power consumption control module 300, respectively.

[0055] Specifically, the voltage-controlled current source module 200 is newly added to the linear drive amplifier in this application, with the aim of further improving the slew rate. Figure 2 VRH and VRL are reference voltages, ensuring that VGP voltage is around VRH and VGN voltage is around VRL. This keeps current sources I5, I6, and M10, M11, M12, and M13 within their normal operating range, improving linearity and stability. When the input amplitude changes too much or too quickly, VGN or VGP is insufficient to keep up with the amplitude change. When VRH-VGP>0, G0 provides pull-up current; when VGN-VRL>0, G1 provides pull-down current, thereby further increasing the slew rate.

[0056] In some embodiments, the power consumption control module 300 includes a fifth NMOS transistor M14, a sixth NMOS transistor M15, a seventh NMOS transistor M19, a fifth PMOS transistor M16, a sixth PMOS transistor M17, a seventh PMOS transistor M18, a first capacitor CC1, and a second capacitor CC2; the positive terminals of the fifth NMOS transistor M14, the fifth PMOS transistor M16, and the first capacitor CC1, and the gate of the seventh PMOS transistor M18 are all connected to the output terminal of the first voltage-controlled current source G0 of the voltage-controlled current source module 200.

[0057] The positive terminals of the sixth NMOS transistor M15, the sixth PMOS transistor M17, the second capacitor CC2, and the gate of the seventh NMOS transistor M19 are all connected to the input terminal of the second voltage-controlled current source G1 of the voltage-controlled current source module 200; the source of the fifth NMOS transistor M14 and the source of the sixth NMOS transistor M15 are connected.

[0058] The drain of the fifth PMOS transistor M16 is connected to the source of the sixth PMOS transistor M17; the gates of the fifth NMOS transistor M14, the sixth NMOS transistor M15, the fifth PMOS transistor M16, and the sixth PMOS transistor M17 are connected to a limiting voltage.

[0059] The drain of the seventh PMOS transistor M18 and the drain of the seventh NMOS transistor M19 are connected together and connected to the push-pull output module 400; the source of the seventh PMOS transistor M18 is connected to the power supply voltage; the source of the seventh NMOS transistor M19 is grounded.

[0060] The negative terminals of the first capacitor CC1 and the second capacitor CC2 are connected together and then connected to the push-pull output module 400.

[0061] In the above embodiments, the power consumption control module 300 controls power consumption and reduces the impact of the output driver stage bandwidth on the overall bandwidth; VBPS and VBNS are voltage limiting voltages in the high voltage domain to ensure that M16 and M15 work in the low voltage region and reduce chip area; VBPR and VBNR are AB level output static power consumption control voltages.

[0062] In some embodiments, the push-pull output module 400 includes a third voltage-controlled current source G2, a fourth voltage-controlled current source G3, an eighth NMOS transistor M20, a ninth NMOS transistor M21, an eighth PMOS transistor M22, and a ninth PMOS transistor M23.

[0063] The input terminal of the third voltage-controlled current source G2 is connected to the source of the ninth NMOS transistor M21, the negative terminal of the first capacitor CC1, the negative terminal of the second capacitor CC2, and the output port VOUT of the push-pull output module 400, respectively; the output terminal of the third voltage-controlled current source G2 is connected to the source of the eighth NMOS transistor M20, the source of the eighth PMOS transistor M22, and ground, respectively.

[0064] The source of the eighth NMOS transistor M20 is connected to the source of the eighth PMOS transistor M22, and is also connected to the drain of the seventh PMOS transistor M18, the drain of the seventh NMOS transistor M19, the source of the ninth NMOS transistor M21, and the source of the ninth PMOS transistor M23. See details in [link to documentation]. Figure 2 The circuit schematic shows that M21 and M23 are connected by two resistors and two diodes. Near the output terminal, there are also two NMOS transistors and two PMOS transistors.

[0065] It can be assumed that, apart from G2 and G3, the connection method of other components in the push-pull output module 400 is the same as that of a conventional linear drive amplifier. The improvement of this module in this application is the addition of two voltage-controlled current sources, G2 and G3.

[0066] The input terminals of the fourth voltage-controlled current source G3 are connected to the power supply voltage VDDH, the source of the eighth NMOS transistor M20, and the source of the eighth PMOS transistor M22, respectively; the output terminals of the fourth voltage-controlled current source G3 are connected to the negative terminals of the first capacitor CC1, the negative terminals of the second capacitor CC2, and the output port VOUT of the push-pull output module 400, respectively.

[0067] The drains of the eighth NMOS transistor M20 and the ninth NMOS transistor M21 are both connected to the power supply voltage.

[0068] The drains of the eighth PMOS transistor M22 and the ninth PMOS transistor M23 are both grounded.

[0069] The push-pull output module 400 in the above embodiments is used to provide output drive capability. The voltage-controlled current sources G2 and G3 added in this application improve the slew rate and drive capability when the output swing increases.

[0070] In the above embodiments, G0, G1, G2, and G3 voltage-controlled current sources are functional schematics. The specific circuits of the first, second, third, and fourth voltage-controlled current sources can be selected from differential input GM amplifiers.

[0071] In summary, by adding D0, D1, voltage-controlled current source module 200, G2, and G3, this application significantly improves the ratio of bandwidth, slew rate, output range, and power consumption of the linear drive amplifier in the high-voltage region.

[0072] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A high-voltage slew rate linear drive amplifier comprising, in sequence, a push-pull current input module, a power consumption control module and a push-pull output module, characterized in that, The push-pull current input module comprises: a pull-up current transistor, a pull-down current transistor, a first one-way path, a second one-way path and a push-pull current branch; The pull-up current transistor is an NMOS transistor, the pull-down current transistor is a PMOS transistor, the push-pull current branch comprises a first NMOS transistor, a second NMOS transistor, a first PMOS transistor and a second PMOS transistor, and the push-pull current branch further comprises a third NMOS transistor, a fourth NMOS transistor, a third PMOS transistor and a fourth PMOS transistor; The gate of the first NMOS transistor is connected to the drain of the first NMOS transistor and the gate of the third NMOS transistor respectively, and the source of the first NMOS transistor is connected to the drain of the second NMOS transistor; The gate of the second NMOS transistor is connected to the drain of the second NMOS transistor and the gate of the fourth NMOS transistor respectively, and the source of the second NMOS transistor is connected to the source of the first PMOS transistor; The gate of the first PMOS transistor is connected to the drain of the first PMOS transistor and the gate of the third PMOS transistor respectively, and the drain of the first PMOS transistor is connected to the source of the second PMOS transistor; The gate of the second PMOS transistor is connected to the drain of the second PMOS transistor and the gate of the fourth PMOS transistor respectively, the drain of the second PMOS transistor is grounded, the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor is connected to the source of the third PMOS transistor; The drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor, the drain of the third NMOS transistor is connected to the drain of the fourth PMOS transistor, and both are connected to the power consumption control module; The source of the pull-up current transistor is connected to the source of the pull-down current transistor, the positive electrode of the first one-way path is connected to the drain of the pull-up current transistor, and the negative electrode is connected to the drain of the first NMOS transistor; the positive electrode of the second one-way path is connected to the drain of the second PMOS transistor, and the negative electrode is connected to the drain of the pull-down current transistor; The gate of the pull-up current transistor is connected to the gate of the pull-down current transistor, and both are connected to the source of the second NMOS transistor and the source of the first PMOS transistor; the source of the pull-up current transistor is connected to the source of the pull-down current transistor, and both are connected to the source of the fourth NMOS transistor and the source of the third PMOS transistor.

2. The high-voltage slew rate linear drive amplifier of claim 1, wherein, The voltage-controlled current source module further comprises a first current source, a first voltage-controlled current source, a second current source and a second voltage-controlled current source; The input ends of the first current source and the first voltage-controlled current source are connected to a power supply voltage; the output end of the first current source is connected to the drain of the third NMOS transistor and the output end of the first voltage-controlled current source; the input end of the first voltage-controlled current source is further connected to a reference voltage, and the output end is connected to the drain of the third NMOS transistor and the power consumption control module; The output terminals of the second current source and the second voltage-controlled current source are grounded; the input terminals of the second current source are connected to the drain of the fourth PMOS tube and the input terminal of the second voltage-controlled current source respectively; the output terminal of the second voltage-controlled current source is also connected to a reference voltage, and the input terminals are connected to the drain of the fourth PMOS tube and the power consumption control module respectively.

3. The high-voltage slew rate linear drive amplifier of claim 2, wherein, The power consumption control module comprises a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a first capacitor and a second capacitor. The fifth NMOS tube, the fifth PMOS tube, the positive electrode of the first capacitor and the gate of the seventh PMOS tube are all connected to the output terminal of the first voltage-controlled current source of the voltage-controlled current source module. The sixth NMOS tube, the sixth PMOS tube, the positive electrode of the second capacitor and the gate of the seventh NMOS tube are all connected to the input terminal of the second voltage-controlled current source of the voltage-controlled current source module. The source of the fifth NMOS tube and the source of the sixth NMOS tube are connected. The drain of the fifth PMOS tube and the source of the sixth PMOS tube are connected; the gates of the fifth NMOS tube, the sixth NMOS tube, the fifth PMOS tube and the sixth PMOS tube are connected to a voltage limiting voltage. The drain of the seventh PMOS tube and the drain of the seventh NMOS tube are connected and connected to the push-pull output module together; the source of the seventh PMOS tube is connected to a power supply voltage; the source of the seventh NMOS tube is grounded. The negative electrode of the first capacitor and the negative electrode of the second capacitor are connected and connected to the push-pull output module together.

4. The high-voltage slew rate linear drive amplifier of claim 3, wherein, The push-pull output module comprises a third voltage-controlled current source, a fourth voltage-controlled current source, an eighth NMOS tube, a ninth NMOS tube, an eighth PMOS tube and a ninth PMOS tube; the input terminals of the third voltage-controlled current source are connected to the source of the ninth NMOS tube, the negative electrode of the first capacitor, the negative electrode of the second capacitor and the output port of the push-pull output module respectively; the output terminals of the third voltage-controlled current source are connected to the source of the eighth NMOS tube, the source of the eighth PMOS tube and the ground respectively. The source of the eighth NMOS tube and the source of the eighth PMOS tube are connected and connected to the drain of the seventh PMOS tube, the drain of the seventh NMOS tube, the source of the ninth NMOS tube and the source of the ninth PMOS tube. The input terminals of the fourth voltage-controlled current source are connected to the power supply voltage, the source of the eighth NMOS tube and the source of the eighth PMOS tube respectively; the output terminals of the fourth voltage-controlled current source are connected to the negative electrode of the first capacitor, the negative electrode of the second capacitor and the output port of the push-pull output module respectively. The drain of the eighth NMOS tube and the drain of the ninth NMOS tube are both connected to the power supply voltage. The drain of the eighth PMOS tube and the drain of the ninth PMOS tube are both grounded.

5. The high-voltage slew rate linear drive amplifier of claim 4, wherein, The first voltage-controlled current source, the second voltage-controlled current source, the third voltage-controlled current source and the fourth voltage-controlled current source are all differential input GM amplifiers.

6. The high-voltage slew rate linear drive amplifier of claim 1, wherein, The first one-way path and the second one-way path are both diodes. The first one-way path and the second one-way path are both diodes.

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