Back contact cell, photovoltaic module and method for manufacturing back contact cell

Abstract

The application relates to the technical field of photovoltaics, in particular to a back contact cell, a photovoltaic module and a preparation method of the back contact cell. The back contact cell comprises a silicon base, the silicon base comprises a front surface and a back surface; the back surface is sequentially and alternately provided with a plurality of first regions and a plurality of second regions, the first regions and the second regions are isolated from each other through gaps, a first semiconductor layer is arranged on the first regions, a second semiconductor layer is arranged on the second regions, and the conductive types of the second semiconductor layer and the first semiconductor layer are opposite; a dense TCO layer, a porous TCO layer and a metal electrode are sequentially arranged on the first semiconductor layer and / or the second semiconductor layer, and the metal electrode is in contact with the dense TCO layer. The structure is designed by introducing a composite film layer of a dense TCO layer / porous TCO layer, the porous TCO layer is selectively removed in the metal electrode area, the unification of high conductivity, strong antireflection and excellent processability is achieved, and the contradiction between performance and cost of a traditional single TCO layer is effectively solved.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to back contact cells, photovoltaic modules, and methods for preparing back contact cells. Background Technology

[0002] As the photovoltaic industry continues to demand higher battery efficiency and cost control, back contact (BC) battery technology has become an important technical route for achieving high-efficiency crystalline silicon solar cells because it places all electrodes on the back of the battery, completely eliminating the shading loss of the front grid lines.

[0003] In related technologies, a transparent conductive oxide (TCO) layer is typically fabricated on the back side of a back-contact battery to laterally collect charge carriers and connect to the metal electrodes. To balance the conductivity and light management capabilities of the TCO layer, a common approach is to use a single-structure TCO film. One method is to use a dense and highly conductive TCO thin film, but these films have limited anti-reflection effects and contribute insufficiently to improving short-circuit current. Another approach is to increase the thickness of the TCO layer to enhance light utilization, but this not only increases the cost of expensive TCO materials but also makes subsequent TCO patterning processes more difficult. Thicker films require more intense or longer etching processes, narrowing the process window and potentially leading to incomplete etching causing leakage or over-etching that damages the underlying functional film.

[0004] However, the aforementioned single-structure TCO film design makes it difficult to achieve a good balance between key performance characteristics such as high conductivity, high anti-reflection, low cost, and easy patterning, which limits further improvement in back contact battery efficiency and further optimization of manufacturing costs. Summary of the Invention

[0005] Therefore, it is necessary to provide a back contact battery that addresses the problem that the TCO layer in existing back contact batteries cannot simultaneously achieve high conductivity, high anti-reflection properties, and low-cost patterning processes.

[0006] A back contact battery, the back contact battery comprising:

[0007] A silicon substrate, the silicon substrate comprising a front side and a back side;

[0008] The back side is alternately provided with a plurality of first regions and a plurality of second regions, the first regions and the second regions are isolated from each other by gaps, a first semiconductor layer is provided on the first region, and a second semiconductor layer is provided on the second region, the second semiconductor layer and the first semiconductor layer have opposite conductivity types;

[0009] A dense transparent conductive oxide layer, a porous transparent conductive oxide layer, and a metal electrode are sequentially disposed on the first semiconductor layer and / or the second semiconductor layer, wherein the metal electrode is in contact with the dense transparent conductive oxide layer.

[0010] In one embodiment, the thickness of the dense transparent conductive oxide layer is 30 nm-70 nm, and the carrier concentration is 2E+20 cm⁻¹. -3 -5E+20 cm -3 Electron mobility is 25 cm⁻¹ 2 / Vs -30 cm 2 / Vs; the thickness of the porous transparent conductive oxide layer is 5 nm-20 nm.

[0011] In one embodiment, the first semiconductor layer includes an N-type doped polycrystalline silicon layer and a tunneling oxide layer disposed sequentially away from the dense transparent conductive oxide layer; the second semiconductor layer includes a P-type doped polycrystalline silicon layer and an intrinsic amorphous silicon layer disposed sequentially away from the dense transparent conductive oxide layer.

[0012] In one embodiment, the thickness of the N-type doped polysilicon layer is 80 nm-200 nm, and the thickness of the P-type doped polysilicon layer is 8 nm-20 nm.

[0013] A photovoltaic module, the photovoltaic module including the back contact battery.

[0014] A method for preparing a back contact battery, the method comprising the following steps:

[0015] S01. A battery precursor is provided, wherein a plurality of first regions and a plurality of second regions are alternately disposed on the back side of the silicon substrate, the first regions and the second regions are isolated from each other by gaps, a first semiconductor layer is disposed on the first region, and a second semiconductor layer is disposed on the second region, wherein the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer.

[0016] S02, a dense transparent conductive oxide layer and a porous transparent conductive oxide layer are sequentially deposited on the back side of the battery precursor to form a stacked structure;

[0017] S03. The stacked structure is patterned, and in the area corresponding to the reserved metal electrode, part of the porous transparent conductive oxide layer is selectively removed, while the dense transparent conductive oxide layer is retained, and the stacked structure deposited in the gap is removed.

[0018] In one embodiment, step S02 further includes:

[0019] S021. After depositing the dense transparent conductive oxide layer, in-situ annealing is performed in an inert gas atmosphere at a temperature of 160 °C to 240 °C for a time of 10 min to 30 min.

[0020] In one embodiment, in step S03, the laminated structure is patterned using an etching paste printing method.

[0021] In one embodiment, the etching paste printing method includes: applying etching paste to the area corresponding to the reserved metal electrode and the gap using a single screen.

[0022] In one embodiment, the etching paste printing method includes:

[0023] Using a first screen, an etching paste is applied into the gap;

[0024] Using a second screen, etchant is applied to the area corresponding to the reserved metal electrode.

[0025] In one embodiment, the preparation method further includes:

[0026] S04. Print metal electrodes so that the metal electrodes are in direct contact with the dense transparent conductive oxide layer.

[0027] The aforementioned back-contact battery structure achieves a balance between high conductivity, strong anti-reflection properties, and excellent processability by introducing a composite film design of "dense TCO layer / porous TCO layer" and selectively removing the porous TCO layer in the metal electrode region. This structure utilizes the bottom dense TCO layer to ensure efficient lateral charge collection and form a low-resistance contact with the metal electrode, while the top porous TCO layer enhances the light-trapping ability of long-wavelength photons near the back surface. This composite structure balances optical performance and patterning process windows without excessively increasing the film thickness, effectively resolving the contradiction between performance and cost that is difficult to achieve with traditional single TCO layers. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the structure of a back contact battery provided in an embodiment of this application.

[0029] Figure 2 This is a schematic diagram of the structure of a battery precursor provided in one embodiment of this application.

[0030] Figure 3 This is a schematic diagram of the structure of a battery precursor after deposition and stacking, according to an embodiment of this application.

[0031] Figure 4 This is a schematic diagram of the structure of a battery precursor after patterning, provided in one embodiment of this application.

[0032] Figure 5 This is a process flow diagram of a back contact battery manufacturing method provided in an embodiment of this application.

[0033] Reference numerals in the detailed embodiments:

[0034] 10. Silicon substrate; 20. First region; 30. Second region; 40. Gap;

[0035] 21. First semiconductor layer; 31. Second semiconductor layer;

[0036] 211. Dense transparent conductive oxide layer (dense TCO layer); 212. Porous transparent conductive oxide layer (porous TCO layer); 213. Metal electrode;

[0037] 214. N-type doped polycrystalline silicon layer; 215. Tunneling oxide layer;

[0038] 311. P-type doped polycrystalline silicon layer; 312. Intrinsic amorphous silicon layer;

[0039] 100. Battery precursor; 200. Laminated structure. Detailed Implementation

[0040] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0041] In the description of this application, it should be understood that if terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" appear, these terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0042] Furthermore, where the terms "first" and "second" appear, these terms are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, where the term "multiple" appears, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0043] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0044] In this application, unless otherwise expressly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0045] It should be noted that if an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. If an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. If so, the terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this application are for illustrative purposes only and do not represent the only possible implementation.

[0046] See Figure 1 , Figure 1A schematic diagram of the structure of a back contact battery according to an embodiment of this application is shown. The back contact battery provided in one embodiment of this application includes a silicon substrate 10, which includes a front side and a back side. The back side is alternately provided with a plurality of first regions 20 and a plurality of second regions 30, which are isolated from each other by gaps 40. A first semiconductor layer 21 is disposed on the first region 20, and a second semiconductor layer 31 is disposed on the second region 30. The conductivity type of the second semiconductor layer 31 is opposite to that of the first semiconductor layer 21. A dense transparent conductive oxide layer 211 (dense TCO layer 211), a porous transparent conductive oxide layer 212 (porous TCO layer 212), and a metal electrode 213 are sequentially disposed on the first semiconductor layer 21 and / or the second semiconductor layer 31. The metal electrode 213 is in contact with the dense transparent conductive oxide layer 211.

[0047] This back-contact battery achieves synergistic optimization of optical performance, electrical performance, and fabrication feasibility by introducing a stacked structure 200 of "dense TCO layer 211 / porous TCO layer 212". The bottom dense TCO layer 211, with its excellent conductivity, effectively undertakes the lateral transport function of charge carriers, ensuring efficient charge collection; simultaneously, the direct contact interface formed between it and the metal electrode 213 helps reduce contact resistance and improve the fill factor. The porous TCO layer 212 mainly undertakes optical functions; its porous structure effectively reduces light reflection from the back surface and enhances the light-trapping ability of long-wavelength photons near the back surface, thereby improving the battery's short-circuit current density.

[0048] By selectively removing the porous TCO layer 212 in the corresponding region of the metal electrode 213, the metal electrode 213 is made into direct contact with the highly conductive dense TCO layer 211, ensuring the reliability of the ohmic contact. The porous TCO layer 212 retained on both sides of the metal electrode 213 helps maintain the overall anti-reflection effect. Furthermore, completely removing the stacked structure 200 within the gap 40 achieves effective electrical isolation, preventing performance degradation caused by leakage between the first region 20 and the second region 30. This application effectively solves the inherent contradiction between conductivity and anti-reflection properties in traditional single TCO layers without significantly increasing film thickness and material costs, providing a practical technical path for fabricating high-efficiency, high-reliability, and low-cost back-contact solar cells.

[0049] According to some embodiments of this application, the thickness of the dense transparent conductive oxide layer 211 is 30 nm-70 nm, and the carrier concentration is 2E+20 cm⁻¹. -3 -5E+20 cm -3 Electron mobility is 25 cm⁻¹ 2 / Vs -30 cm 2 / Vs. This parameter range is set to ensure that the dense TCO layer 211 has excellent conductivity, effectively undertaking the lateral transport function of charge carriers, reducing series resistance, and thus helping to improve the fill factor and conversion efficiency of the battery. At the same time, this thickness range also takes into account the preparation cost and process feasibility of the film, avoiding material waste and increased deposition time caused by excessive film thickness.

[0050] According to some embodiments of this application, the thickness of the porous transparent conductive oxide layer 212 is 5 nm-20 nm. The relatively thin porous TCO layer 212 mainly undertakes optical functions, and its porous characteristics can effectively reduce light reflection on the back surface and enhance the ability to trap long-wavelength photons. This thickness range optimizes the optical performance of the back of the battery without significantly increasing the overall film thickness and material cost, and achieves enhanced anti-reflection effect. This application forms a stacked structure 200 by combining the dense TCO layer 211 and the porous TCO layer 212 with specific parameters. This design cleverly and synergistically optimizes the electrical and optical performance of the back contact battery. The bottom dense TCO layer 211 ensures efficient charge collection and transport and forms excellent ohmic contact with the metal electrode 213; the porous TCO layer 212 focuses on improving light management capabilities. This tiered functional composite film structure effectively solves the technical problem of traditional single TCO layers being unable to achieve a balance between conductivity and anti-reflection without significantly increasing process complexity and manufacturing cost.

[0051] According to some embodiments of this application, the first semiconductor layer 21 includes an N-type doped polysilicon layer 214 and a tunneling oxide layer 215 disposed sequentially away from the dense transparent conductive oxide layer 211. The tunneling oxide layer 215, as an interface layer in direct contact with the silicon substrate 10, enables efficient tunneling transport of charge carriers and provides excellent chemical passivation to the surface of the silicon substrate 10, effectively reducing the surface recombination rate. The upper N-type doped polysilicon layer 214 not only provides field-effect passivation, further suppressing carrier recombination on the surface, but also serves as the main conductive channel, responsible for collecting and transporting photogenerated electrons. This combination of "tunneling oxide layer 215 + N-type doped polysilicon layer 214" is a classic and reliable solution for achieving efficient electron collection.

[0052] Accordingly, the second semiconductor layer 31 includes a P-type doped polycrystalline silicon layer 311 and an intrinsic amorphous silicon layer 312 disposed sequentially away from the dense transparent conductive oxide layer 211. The intrinsic amorphous silicon layer 312 at the bottom can passivate the interface of the back side of the silicon substrate 10, ensuring the lifetime of holes. The P-type doped polycrystalline silicon layer 311 above it establishes a stable hole collection and transport path. This structure, which combines the excellent passivation characteristics of intrinsic amorphous silicon with the stable conductivity characteristics of P-type doped polycrystalline silicon, is conducive to the effective collection of holes, thus forming a high-performance back contact battery core together with the first semiconductor layer 21.

[0053] By configuring such a refined semiconductor structure containing a passivation layer and a conductive layer for the first region 20 and the second region 30 with opposite conductivity types, electrons and holes can be collected efficiently and with low loss in their respective regions, minimizing recombination losses.

[0054] In one embodiment, the N-type doped polysilicon layer 214 has a thickness of 80 nm–200 nm. This relatively thick design aims to ensure that the layer has sufficiently low lateral resistance, thereby enabling efficient lateral collection and transport of photogenerated electrons and avoiding fill factor loss due to increased series resistance. Simultaneously, this thickness range provides sufficient total doping, contributing to stable field-effect passivation, further improving the passivation quality of the interface, and exhibiting good stability for thermal processes during subsequent fabrication. For the P-type doped polysilicon layer 311, its thickness is 8 nm–20 nm. This thinner design is based on two main considerations: firstly, the thinner thickness facilitates hole tunneling transport and reduces carrier transport resistance; secondly, it effectively weakens the parasitic absorption of long-wavelength photons incident on the back of the battery by the P-type layer, thereby helping to improve the battery's short-circuit current. This design minimizes optical losses while ensuring effective hole collection and necessary conductivity.

[0055] By setting different polysilicon layer thicknesses for the N-type region (first region 20) and the P-type region (second region 30), this embodiment cleverly balances the contradiction between electrical and optical performance. The thicker N-type layer prioritizes the conductivity requirements for electron collection, while the thinner P-type layer focuses on reducing parasitic absorption. This asymmetric thickness design fully considers the differences in the mobility of the two types of carriers and the optical characteristics of materials with different doping types, reflecting considerations for overall performance optimization. This is beneficial for achieving synergistic improvements in parameters such as open-circuit voltage, short-circuit current, and fill factor of the back-contact battery.

[0056] This application also provides a photovoltaic module, the core feature of which is the integration of the aforementioned back-contact cell with a stacked structure 200 and a partitioned semiconductor structure. This photovoltaic module inherits the dual advantages of back-contact cells in optical management and electrical performance. The porous TCO layer 212 effectively reduces light reflection from the back surface and enhances the module's ability to capture long-wavelength light, thereby contributing to an increase in the module's short-circuit current. The underlying dense TCO layer 211 ensures that photogenerated carriers inside the cell can be efficiently collected laterally and led to the circuit, minimizing power loss.

[0057] At the structural level, the individual cell units within the module are connected through an optimized interconnection process. Since all electrodes of the back-contact cells are located on the back side, the shading loss caused by the front-side main grid lines of traditional cells is avoided, significantly increasing the effective light-receiving area of ​​the module. This gridless design, combined with the low series resistance and excellent contact characteristics of the stacked structure 200, facilitates the simultaneous optimization of the module's final output power and fill factor. Therefore, photovoltaic modules based on this back-contact cell structure provide a reliable technical path for achieving higher power density and power generation revenue in photovoltaic products. This application also includes a method for fabricating a back-contact cell, which is further referenced below. Figure 5 , Figure 5 A process flow diagram of a back-contact battery fabrication method is shown. This fabrication method includes the following steps:

[0058] S01. A battery precursor 100 is provided, wherein a plurality of first regions 20 and a plurality of second regions 30 are alternately disposed on the back side of the silicon substrate 10, the first regions 20 and the second regions 30 are isolated from each other by gaps 40, a first semiconductor layer 21 is disposed on the first region 20, and a second semiconductor layer 31 is disposed on the second region 30, wherein the conductivity type of the second semiconductor layer 31 and the first semiconductor layer 21 is opposite.

[0059] S02. A dense transparent conductive oxide layer 211 and a porous transparent conductive oxide layer 212 are sequentially deposited on the back side of the battery precursor 100 to form a stacked structure 200.

[0060] S03. The stacked structure 200 is patterned. In the area corresponding to the reserved metal electrode 213, part of the porous transparent conductive oxide layer 212 is selectively removed, while the dense transparent conductive oxide layer 211 is retained. The stacked structure 200 deposited in the gap 40 is also removed.

[0061] Specifically, continue to combine Figure 2 , Figure 2This is a schematic diagram of a battery precursor according to an embodiment of this application. The back side of the silicon substrate 10 of the battery precursor 100 is provided with alternating first regions 20 and second regions 30, separated by gaps 40. A first semiconductor layer 21 is disposed on the first region 20, and a second semiconductor layer 31 is disposed on the second region 30. The second semiconductor layer 31 and the first semiconductor layer 21 have opposite conductivity types. The structure of this battery precursor 100 lays the foundation for the subsequent formation of a high-performance back-contact battery. By setting alternating first regions 20 and second regions 30 separated by gaps 40 on the back side of the silicon substrate 10, and configuring semiconductor layers with opposite conductivity types, effective spatial separation and independent collection of electrons and holes are achieved. This partitioned design reduces the recombination probability of charge carriers during transport, which is beneficial for improving the open-circuit voltage of the battery. The presence of gaps 40 provides electrical isolation, ensuring that no leakage path is formed between the first regions 20 and the second regions 30 due to the continuous coverage of other film layers, thereby effectively preventing the degradation of battery performance. This physical isolation provides clear boundaries and independent process windows for the subsequent fabrication of semiconductor layers and electrode structures with different functions in their respective regions.

[0062] Furthermore, the first semiconductor layer 21 and the second semiconductor layer 31 can adopt a composite structure including a passivation layer and a conductive layer. For example, the first semiconductor layer 21 may include a tunneling oxide layer 215 and an N-type doped polycrystalline silicon layer 214, and the second semiconductor layer 31 may include an intrinsic amorphous silicon layer 312 and a P-type doped polycrystalline silicon layer 311. This refined layered design enables the battery precursor 100 to achieve excellent conductivity while also achieving high-quality passivation of the back surface of the silicon substrate 10, providing a reliable carrier for the final back contact battery. This structure also fully considers the compatibility of subsequent deposition and patterning processes of the stacked structure 200, ensuring the feasibility and stability of the overall fabrication process.

[0063] Furthermore, this preparation method cleverly and synergistically optimizes the optical and electrical performance of the battery through the stacked structure 200 formed by sequentially depositing a dense TCO layer 211 and a porous TCO layer 212 in step S02. Figure 3 , Figure 3This is a schematic diagram of the structure of the battery precursor 100 after deposition of the stacked structure 200 according to an embodiment of this application. The bottom dense TCO layer 211, with its excellent conductivity, provides an efficient lateral collection path for photogenerated carriers, helping to reduce series resistance and thus improving the battery's fill factor. The top porous TCO layer 212 mainly performs optical functions; its unique porous structure significantly reduces light reflection from the back surface and enhances the ability to trap long-wavelength photons, thereby improving the battery's short-circuit current density. This tiered functional design of "dense conductive layer + porous anti-reflection layer" is beneficial for improving battery performance without significantly increasing the overall film thickness and material cost.

[0064] In one embodiment, step S02 further includes:

[0065] S021. After depositing a dense transparent conductive oxide layer 211, in-situ annealing is performed in an inert gas atmosphere at a temperature of 160 ℃ to 240 ℃ for a time of 10 min to 30 min.

[0066] The in-situ annealing process is a key step in the preparation method, and it has multiple positive effects on improving battery performance. Specifically, the dense TCO layer 211 and the porous TCO layer 212 are preferably prepared by physical vapor deposition (PVD) technology, such as magnetron sputtering. By precisely controlling process parameters such as sputtering power, working gas pressure, substrate temperature, and oxygen / argon flow ratio, a TCO thin film layer with specific crystal orientation, high density, and excellent electrical properties can be obtained. After depositing the dense TCO layer 211, in-situ annealing is immediately performed in an inert gas atmosphere. This annealing process can prevent film oxidation on the one hand, and promote TCO grain growth and optimize grain boundary structure on the other hand, thereby effectively eliminating intrafilm stress and deposition defects.

[0067] More importantly, this heat treatment process has a synergistic optimization effect. Its thermal effect not only improves the microstructure and electrical properties of the newly deposited dense TCO layer 211 itself, but also penetrates the dense TCO layer 211 to produce an effective interface annealing effect on the underlying semiconductor passivation layer (especially the intrinsic amorphous silicon layer 312 in the P-type region). This heat treatment helps passivate dangling bonds at the amorphous silicon / crystalline silicon interface, improves the interface state density, and thus enhances the interface chemical passivation effect.

[0068] By precisely controlling the annealing temperature within the range of 160℃ to 240℃ and holding it for 10 min to 30 min, an optimal balance can be achieved between multiple objectives, including TCO layer densification, improved electrical performance, and enhanced passivation of the underlying interface. This relatively low annealing temperature also avoids the risk of thermal damage to structures such as the underlying ultrathin tunneling oxide layer 215. This in-situ annealing step is tightly integrated with the PVD deposition process, reflecting the synergistic design of the front and rear process steps, and is an important guarantee for achieving high-performance, high-reliability back-contact battery fabrication.

[0069] See Figure 4 , Figure 4 This is a schematic diagram of the battery precursor structure after patterning. It should be noted that the patterning process performed in step S03 is crucial for achieving synergistic performance in this fabrication method. The porous TCO layer 212 is selectively removed from the region corresponding to the reserved metal electrode 213, allowing the subsequently formed metal electrode 213 to directly contact the highly conductive dense TCO layer 211, ensuring excellent ohmic contact and low contact resistance. This is essential for maintaining the battery's fill factor and conversion efficiency. Simultaneously, the porous TCO layer 212 retained on both sides of the metal electrode 213 region continues to perform its anti-reflection function, maintaining the overall optical gain of the back surface. Furthermore, this patterning step completely removes the entire stacked structure 200 deposited in the gap 40 region. This operation achieves necessary electrical isolation between the first region 20 and the second region 30, cutting off leakage channels that could form through continuous TCO film layers. This effectively prevents the decrease in parallel resistance and open-circuit voltage loss caused by inter-region leakage, thereby contributing to improved battery performance and reliability.

[0070] Further, in step S03, the laminated structure 200 is patterned using an etchant printing method. Etchant printing is a selective etching solution that combines high precision and high process compatibility. This method uses screen printing technology to precisely coat a specially formulated chemical etchant onto a predetermined area, followed by a chemical reaction to dissolve and remove the target film layer, thereby achieving the desired patterning. Compared to traditional patterning processes such as vacuum etching or laser ablation, etchant printing does not require a complex vacuum environment or expensive laser equipment; it can be completed in an atmospheric environment, significantly reducing equipment investment and process complexity, making it more suitable for large-scale industrial production.

[0071] Example 1:

[0072] According to some embodiments of this application, the etching paste printing method includes: applying etching paste to the reserved area corresponding to the metal electrode 213 and the gap 40 using a single screen. In this one-step method, a specially designed single screen is used to obtain wider etching paste lines at the gap 40 to thoroughly remove the entire stacked structure 200 in that area, while narrower etching paste lines are obtained in the area corresponding to the metal electrode 213 to selectively remove only the upper porous TCO layer 212. This differentiated paste coating amount design ensures that different etching depths are achieved in different functional areas, thus achieving the dual patterning goals of electrical isolation and electrode contact interface optimization in one step.

[0073] Example 2:

[0074] According to some embodiments of this application, the etching paste printing method includes:

[0075] Using the first screen, apply etching paste within the gap of 40;

[0076] Using a second screen, etchant is applied to the area corresponding to the reserved metal electrode 213.

[0077] This step-by-step printing method achieves precise and differentiated etching control over different functional areas through two independent printing steps. First, a first screen is used specifically for applying etching paste to the gap 40 area. This screen can be designed with a wide aperture and high film thickness to ensure that sufficient etching paste is applied to the gap 40 where the stacked structure 200 needs to be completely removed. Etching at the gap 40 is placed in the first step because this area requires a longer chemical reaction time to completely remove the stacked structure 200. Early coating allows for more sufficient contact time for the etchant, ensuring the complete removal of the stacked structure 200 within the gap 40. Subsequently, a second screen is used to apply etching paste to the area corresponding to the reserved metal electrode 213. This second screen is more finely designed, typically with a narrow aperture and low film thickness, aiming to precisely control the amount and shape of the etching paste application. Its purpose is to selectively remove only the porous TCO layer 212 above the metal electrode 213, while completely preserving the dense TCO layer 211 below. This step-by-step strategy decouples the etching requirements for two different depths and purposes, avoiding over-etching or under-etching problems that may occur when using a single screen due to differences in paste diffusion or reaction kinetics.

[0078] The selective etching in Examples 1 and 2 precisely formed the surface structure of the functional zones: in the region corresponding to the metal electrode 213, only the upper porous TCO layer 212 was removed, allowing the subsequently fabricated metal electrode 213 to directly form a low-resistance ohmic contact with the lower highly conductive dense TCO layer 211, greatly optimizing the longitudinal charge transport; while the porous TCO layers 212 retained on both sides of the electrode continue to perform their excellent anti-reflection function. At the gap 40, all the stacked structures 200 were completely removed, forming a reliable electrical isolation region, effectively preventing leakage between the first region 20 and the second region 30 due to TCO layer bridging, which helps to ensure the open-circuit voltage and fill factor of the battery.

[0079] In one embodiment, the preparation method further includes:

[0080] S04. Print metal electrodes 213 so that the metal electrodes 213 are in direct contact with the dense transparent conductive oxide layer 211. (Continue reading...) Figure 1 , Figure 1 This is a schematic diagram of the structure of the battery with printed metal electrodes in contact with the back.

[0081] In step S04, the metal paste is precisely coated onto the surface of the patterned dense TCO layer 211 using screen printing. Since the porous TCO layer 212 in the electrode area has been precisely removed in the previous patterning process, the paste can directly contact the highly conductive dense TCO layer 211, forming an excellent ohmic contact interface after subsequent curing and photoinjection processes.

[0082] According to some embodiments of this application, the electrode preparation step uses low-temperature conductive pastes such as low-temperature silver paste, silver-coated copper, or silver-coated nickel, and forms a metal electrode pattern by screen printing.

[0083] The back-contact solar cell prepared by the above method successfully achieves a synergistic balance between high conductivity, strong anti-reflection properties, and excellent processability. Its unique stacked structure 200 of "dense TCO layer 211 / porous TCO layer 212" ensures efficient lateral carrier collection and low-resistance ohmic contact while significantly enhancing the light trapping effect on the back surface, thus contributing to increased short-circuit current density. This cell structure systematically solves the core contradiction in traditional back-contact solar cells—the difficulty of balancing optical management and electrical performance—without excessively increasing film thickness and process complexity, providing a reliable technical path for achieving high-efficiency, low-cost solar cells.

[0084] To further illustrate the advantages of the "dense TCO layer 211 / porous TCO layer 212" stacked structure 200 in this application compared with the traditional single TCO film layer, a comparative analysis is now conducted in conjunction with specific film thickness parameters.

[0085] Comparative Example 1

[0086] The back-contact battery provided in Comparative Example 1 has a stacked structure 200 on its back side, wherein the thickness of the dense TCO layer 211 is 52 nm, the thickness of the porous TCO layer 212 is 13 nm, and the total thickness of the stack is 65 nm. After patterning, the porous TCO layer 212 is selectively removed in the region corresponding to the metal electrode 213, while the dense TCO layer 211 is retained, and the stacked structure 200 is completely removed in the gap 40 region.

[0087] Comparative Example 2

[0088] In contrast, Comparative Example 2 uses a single-structure TCO film with a thickness of 65 nm, which combines conductivity and antireflection functions. This back-contact battery underwent annealing under the same conditions as Comparative Example 1, but without patterning.

[0089] The electrical performance data of the back contact batteries prepared in Comparative Example 1 and Comparative Example 2 are shown in Table 1:

[0090] Table 1

[0091]

[0092] By comparing Comparative Example 1 with Comparative Example 2 which uses a single TCO structure, it can be seen that the "dense TCO layer 211 / porous TCO layer 212" stacked structure 200 provided by Comparative Example 1 improves the back reflectivity while enhancing the electrical performance of the back contact battery: the parallel resistance (Rsh) is optimized from 37 Ω to 17 Ω, the series resistance (Rs) is reduced from 1.11 mΩ to 1.05 mΩ, the short-circuit current density (Isc) is increased from 8.024 A / cm² to 8.346 A / cm², the fill factor (FF) is increased from 81.22% to 84.35%, and the final conversion efficiency (Eff) is increased from 25.7% to 26.5%.

[0093] These data demonstrate that by sequentially depositing a dense TCO layer 211 and a porous TCO layer 212 on the first semiconductor layer 21 and / or the second semiconductor layer 31, and selectively removing the porous TCO layer 212 in the corresponding region of the metal electrode 213 through patterning while retaining the dense TCO layer 211, and simultaneously completely removing the stacked structure 200 within the gap 40, the conductivity, anti-reflection properties, and processability of the battery can be synergistically optimized. This structure effectively solves the technical challenge of achieving multiple key performance characteristics simultaneously with a traditional single TCO layer, providing a practical technical path for fabricating high-efficiency, high-reliability back-contact batteries and high-performance photovoltaic modules.

[0094] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0095] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A back-contact battery, characterized in that, The back contact battery includes: A silicon substrate, the silicon substrate comprising a front side and a back side; The back side is alternately provided with a plurality of first regions and a plurality of second regions, the first regions and the second regions are isolated from each other by gaps, a first semiconductor layer is provided on the first region, and a second semiconductor layer is provided on the second region, the second semiconductor layer and the first semiconductor layer have opposite conductivity types; A dense transparent conductive oxide layer, a porous transparent conductive oxide layer, and a metal electrode are sequentially disposed on the first semiconductor layer and / or the second semiconductor layer, wherein the metal electrode is in contact with the dense transparent conductive oxide layer.

2. The back contact battery according to claim 1, characterized in that, The thickness of the dense, transparent conductive oxide layer is 30 nm-70 nm, and the carrier concentration is 2E+20 cm⁻¹. -3 -5E+20 cm -3 Electron mobility is 25 cm⁻¹ 2 / Vs -30 cm 2 / Vs; the thickness of the porous transparent conductive oxide layer is 5 nm-20 nm.

3. The back contact battery according to claim 1, characterized in that, The first semiconductor layer includes an N-type doped polycrystalline silicon layer and a tunneling oxide layer disposed sequentially away from the dense transparent conductive oxide layer; the second semiconductor layer includes a P-type doped polycrystalline silicon layer and an intrinsic amorphous silicon layer disposed sequentially away from the dense transparent conductive oxide layer.

4. The back contact battery according to claim 3, characterized in that, The thickness of the N-type doped polycrystalline silicon layer is 80 nm-200 nm, and the thickness of the P-type doped polycrystalline silicon layer is 8 nm-20 nm.

5. A photovoltaic module, characterized in that, The photovoltaic module includes a back-contact battery as described in any one of claims 1-4.

6. A method for preparing a back-contact battery, characterized in that, The preparation method includes the following steps: S01. A battery precursor is provided, wherein a plurality of first regions and a plurality of second regions are alternately disposed on the back side of the silicon substrate, the first regions and the second regions are isolated from each other by gaps, a first semiconductor layer is disposed on the first region, and a second semiconductor layer is disposed on the second region, wherein the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer. S02, a dense transparent conductive oxide layer and a porous transparent conductive oxide layer are sequentially deposited on the back side of the battery precursor to form a stacked structure; S03. The stacked structure is patterned, and in the area corresponding to the reserved metal electrode, part of the porous transparent conductive oxide layer is selectively removed, while the dense transparent conductive oxide layer is retained, and the stacked structure deposited in the gap is removed.

7. The method for preparing a back contact battery according to claim 6, characterized in that, Step S02 further includes: S021. After depositing the dense transparent conductive oxide layer, in-situ annealing is performed in an inert gas atmosphere at a temperature of 160 °C to 240 °C for a time of 10 min to 30 min.

8. The method for preparing a back contact battery according to claim 6, characterized in that, In step S03, the laminated structure is patterned using an etching paste printing method.

9. The method for preparing a back contact battery according to claim 8, characterized in that, The etching paste printing method includes: using a single screen to apply etching paste to the area corresponding to the reserved metal electrode and the gap.

10. The method for preparing a back contact battery according to claim 8, characterized in that, The etching paste printing method includes: Using a first screen, an etching paste is applied into the gap; Using a second screen, etchant is applied to the area corresponding to the reserved metal electrode.

11. The method for preparing a back contact battery according to claim 6, characterized in that, The preparation method further includes: S04. Print metal electrodes so that the metal electrodes are in direct contact with the dense transparent conductive oxide layer.

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