High-concurrency processor architecture based on instruction-level event structure and scheduling method thereof

Abstract

The application discloses a high-concurrency processor architecture based on an instruction-level event structure and a scheduling method thereof, is based on RISC-V instructions, and defines the stagnation, successful termination, sequential execution, conditional branching and merging operation of a program through a process algebra (PA-ISA) oriented to an instruction set architecture (ISA). On the basis of the PA-ISA, the dependence relationship between instructions in program execution is described through an instruction-level event structure (IES). The instruction-level event structure model is adopted to describe the dependence relationship between instructions in the program, the instruction concurrency is improved, and good expansibility is achieved. The high-concurrency processor architecture based on the IES is combined with an asynchronous circuit, an event triggering is taken as a basic execution advancing mode, the frequency or energy efficiency is improved, the bypass control mechanism in the out-of-order execution is simplified, and the system reliability is improved. The instruction-level event structure is combined with a double-path instruction fetching mechanism, the instruction waste and performance loss are reduced, and the fault tolerance capability under a large-scale instruction fetching strategy is optimized.

Description

Technical Field

[0001] This invention belongs to the field of processor scheduling technology, specifically relating to a high-concurrency processor architecture based on instruction-level event structure and its scheduling method. Background Technology

[0002] As processor performance growth becomes increasingly constrained by the serial bottleneck of the traditional von Neumann architecture, superscalar processors have gradually become one of the mainstream architectures for improving instruction-level parallelism (ILP). By issuing multiple instructions in parallel within a single cycle, superscalar processors can significantly improve throughput. Currently, mainstream commercial processors generally support 6-8 issue widths and rely on complex out-of-order execution engines, register renaming mechanisms, and dynamic scheduling windows to achieve parallelism enhancements.

[0003] However, with the increase in issue width, the hardware complexity of out-of-order scheduling logic increases exponentially. Problems such as limited scheduling window, restricted ROB size, increased cost of inter-instruction dependency detection, increased power consumption, and increased branch prediction failure rate severely restrict the further expansion of instruction parallelism. Current mainstream methods rely on: register renaming tables to avoid data conflicts; age-based issue scheduling; dynamic dependency detection logic to perform multi-way comparisons to determine dependencies for each instruction; and ROB-based result submission and write-back mechanisms to ensure the orderliness of results under out-of-order execution. These mechanisms experience a rapid increase in hardware cost and timing overhead when issue width is further increased to extremely large scalar levels such as 32 or 64 instructions. Furthermore, current mainstream processors are all based on synchronous clock-driven logic, which is difficult to flexibly adapt to complex control paths and diverse data paths. Especially when dealing with large-scale dependency graphs, the synchronous logic faces stringent worst-case latency path constraints.

[0004] Therefore, existing processors have the following shortcomings in instruction scheduling:

[0005] 1. Insufficient ability to express inter-instruction relationships explicitly: Traditional processors use ROB (Reorder Buffer) and scheduling queues to manage instruction dependencies. Essentially, these are based on comparing read and write registers between instructions, which makes it difficult to fully and formally express complex program control and data dependencies. Moreover, they are difficult to extend to higher-concurrency scheduling strategies, increasing the difficulty of verification and debugging.

[0006] 2. Synchronous logic timing bottleneck: Under the unified clock drive, the long path across modules makes it difficult to converge the setup time, which limits the system's main frequency and results in high power consumption;

[0007] 3. Complex bypass path control: To ensure the correctness of out-of-order execution, existing processors need to construct a large number of bypass paths and corresponding bypass control logic. With the increase of superscalar scaling, bypass resources grow exponentially, leading to a significant increase in circuit area and latency, which severely limits the processor's parallelism scaling capability;

[0008] 4. Waste of instruction fetch due to branch prediction errors: In order to improve parallelism, superscalar processors often adopt a strategy of fetching a large number of instructions at once. However, under the traditional single-path prediction mechanism, once a branch prediction error occurs, all these fetched instructions will be invalidated, wasting a lot of bandwidth and energy resources. Summary of the Invention

[0009] To address the problems existing in the above-mentioned background technology, the purpose of this invention is to provide a high-concurrency processor architecture based on instruction-level event structure and its scheduling method.

[0010] To achieve the above objectives, the present invention adopts the following technical solution:

[0011] The high-concurrency processor architecture based on instruction-level event structure uses RISC-V instructions as its foundation. It defines basic operations such as program stalling, successful termination, sequential execution, conditional branching, and merging through Process Algebra Oriented to Instruction Set Architecture (PA-ISA) to describe the execution flow in program blocks. Based on PA-ISA, it describes the dependencies between instructions during program execution through instruction-level event structure (IES).

[0012] IES-based high-concurrency processor architectures include:

[0013] Instruction fetch, decoding, and event structure generation module: The instruction fetching module adopts a multi-round parallel instruction fetching strategy that combines dual-path prediction. After the fetched instructions are decoded, each fetched instruction constructs an IES for out-of-order scheduling or scheduling optimization during execution. Through this mechanism, the processor can simultaneously cover the main branch path and alternative paths in a single instruction fetch cycle, significantly reducing the destructive impact of branch misprediction on instruction supply.

[0014] Branch prediction control module: predicts branch jumps for instruction fetch instructions;

[0015] Event Structure Merging Module: Merges multiple independently constructed small event structures (A ES, B ES, C ES, D ES) into a global IES. During the merging process, the dependencies of each event node are preserved, and cross-structure causal relationships and mutual exclusion conflicts are constructed. This module outputs a unified IES after merging for subsequent scheduling system parsing.

[0016] Buffer scheduling structure: A multi-level buffer scheduling structure is adopted, which drives the scheduling of instructions according to the priority level between events after merging IES. Based on the hierarchical distribution of instructions in IES, they are divided into multi-level buffers for waiting and execution.

[0017] Execution module: Selects the appropriate processing module based on the instruction type for processing, supporting the parallel execution of multiple instructions;

[0018] Memory access module: performs address detection on the address transmitted by the memory management unit and executes the corresponding memory access operation based on the detection result; writes the data transmitted by the execution module to the corresponding memory location according to the address provided by the memory management unit.

[0019] Write-back module: Performs sequential write-back of different types of instructions.

[0020] Furthermore, the basic syntax construction supported by the PA-ISA is as follows:

[0021] inaction(0): indicates that the program does nothing or terminates, equivalent to an empty process with an empty instruction set;

[0022] successful termination (√): This indicates that the program has successfully completed and ended in a certain state, and the instruction set is also empty;

[0023] action-prefix ((i; B), where i∈InstrSet): indicates that after instruction i is executed, program B continues to be executed, corresponding to sequential execution semantics, and the instruction set is {i}∪InstrSet(B);

[0024] choice (B1 + B2): This indicates a conditional selection statement. The program chooses to execute either B1 or B2. It represents a conditional branching structure, and the instruction set is the union of B1 and B2.

[0025] merge (B1 B2): Represents the merging of two program blocks, used to structurally represent the regeneration of the dependencies between the instructions of the two program blocks. The instruction set is the union of B1 and B2, i.e., InstrSet(B1)∪InstrSet(B2).

[0026] Furthermore, the definition of the instruction-level event structure IES is as follows:

[0027] E, an event is defined as a set of instructions in a program;

[0028] #, contradictory relationship, only applies to dynamic branch instructions, inserts a virtual event e' after the jump instruction e;

[0029] The binding relationship is defined as B, J, and R, which represent the instruction sets of dynamic branching, static jumping, and register-dependent instructions, respectively.

[0030] Action tags indicate the instruction type in the instruction set architecture.

[0031] Furthermore, the branch prediction control module includes an instruction fetch channel, a branch prediction module, a correction channel, a branch prediction correction module, and a write-back channel. The instruction fetched through the instruction fetch channel enters the branch prediction module for prediction and outputs the predicted address result. After the prediction is completed, the write-back module sends the instruction with the incorrect address prediction result to the branch prediction correction module through the correction channel for correction. At the same time, the write-back module transmits the address of the next round of instruction fetching through the write-back channel.

[0032] Furthermore, the buffer scheduling structure will coordinate the new instruction buffer and the remaining instruction buffer through control logic. The new instruction buffer is used to store new instructions that participate in IES scheduling after the current batch is parsed, and the remaining instruction buffer is used to store instruction remnants that were not fully scheduled at the moment, and participate in the merging of the next round of IES.

[0033] Furthermore, in the execution module, the execution unit includes two functional units (FU_UNIT), one address generation unit (AGU_UNIT), and one branch jump unit (BRU). Each FU_UNIT contains 8 arithmetic units, 2 multiplication units, and 1 division unit; AGU_UNIT contains 8 address generation units; and the BRU is used to process jump instructions.

[0034] Furthermore, the result output path of the execution module includes a reordering buffer, a bypass, and a memory access unit.

[0035] Furthermore, the memory access module includes an input / output unit, a Load instruction dependency detection module, a Store instruction cache, and an SRAM control unit. Upon address detection, if the address is an input / output type, the corresponding data is directly transmitted to the input / output unit. If the address is not an input / output type, the instruction type is further identified. If it is a Load instruction, address dependency detection is performed by the Load instruction dependency detection module. If it is a Store instruction, the instruction data is preprocessed and temporarily stored in the Store instruction cache. Load instructions retrieve data from different data sources based on the dependency detection results, while Store instructions are temporarily stored in the Store instruction cache. After certain processing, data is written to the SRAM control unit in sequence. Load instructions that need to retrieve data from the SRAM control unit, and some Store instructions specified by the write-back process, trigger the SRAM control module to execute corresponding memory access operations.

[0036] Furthermore, the write-back module includes a preprocessing module, an instruction parsing module, a write-back judgment module, and a write-back control module;

[0037] The preprocessing module is used for instruction preprocessing, and the preprocessed data is stored in the reordering cache;

[0038] The instruction parsing module is used to parse the information of instructions in the reordering cache, and then distribute the write-back instructions for write-back.

[0039] The write-back control module is used to maintain multiple variables controlling the write-back after the instruction is written back and transmit them to the write-back judgment module.

[0040] The write-back judgment module is used to give a comprehensive instruction that can be written back at this time based on the current completion bit and valid bit information.

[0041] This invention further provides a high-concurrency processor scheduling method based on instruction-level event structure. Utilizing a high-concurrency processor architecture based on instruction-level event structure, the instruction execution path establishes communication via an asynchronous handshake protocol among the instruction fetch, decoding, and event structure generation modules, branch prediction control module, event structure merging module, buffer scheduling structure, execution module, memory access module, and write-back module. Each module integrates a local controller, driving local logic operation through a request-response protocol. When data is ready and transmission relationships are satisfied, subsequent modules are automatically triggered, forming an asynchronous pipeline at the functional level. The request-response mechanism transmits data and control signals between modules, ensuring that forwarding operations are only initiated when the receiving module is ready, guaranteeing system consistency. Each instruction is identified at the event granularity, and the causal edges contained in the event structure connect the triggering conditions of each instruction through an asynchronous control chain. Upon completion of the current instruction execution, the ready signal of its directly successor instruction is activated through the chain, achieving a dependency-driven scheduling method.

[0042] Compared with the shortcomings and deficiencies of existing technologies, the present invention has the following beneficial effects:

[0043] 1. A formal structural model, namely the instruction-level event structure model, is adopted to completely and clearly describe the dependencies between instructions in the program, thereby providing the processor with stronger expressive power and scheduling foundation, significantly improving instruction concurrency and possessing good scalability;

[0044] 2. The high-concurrency processor architecture based on IES is combined with asynchronous circuits, and the execution is driven by event triggering, which alleviates the timing bottleneck of synchronous circuits and improves frequency or energy efficiency;

[0045] 3. Simplify the bypass control mechanism in out-of-order execution. By utilizing the execution order relationship defined in the instruction-level event structure, instructions can be executed correctly without additional bypass logic, thereby significantly reducing hardware complexity and power consumption and improving system reliability.

[0046] 4. Introduce an instruction-level event structure combined with a dual-path instruction fetch mechanism. When an error is predicted, the instructions required for the alternative path are retained, reducing instruction waste and performance loss, and optimizing the fault tolerance capability under a large-scale instruction fetch strategy. Attached Figure Description

[0047] Figure 1 This is a diagram of a high-concurrency processor architecture based on IES provided in an embodiment of the present invention;

[0048] Figure 2 This is an architecture diagram of the instruction fetching, decoding, and event structure generation module provided in an embodiment of the present invention;

[0049] Figure 3 This is an architecture diagram of the branch prediction control module provided in an embodiment of the present invention;

[0050] Figure 4 This is an architecture diagram of the event structure merging module and buffer scheduling structure provided in the embodiments of the present invention;

[0051] Figure 5 This is an architecture diagram of the execution module provided in an embodiment of the present invention;

[0052] Figure 6 This is an architecture diagram of the memory access module provided in an embodiment of the present invention;

[0053] Figure 7 This is an architecture diagram of the write-back module provided in an embodiment of the present invention. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0055] This invention proposes a high-concurrency processor architecture and its scheduling method based on instruction-level event structure, starting from program structure and combining it with event structure theory.

[0056] The high-concurrency processor architecture based on instruction-level event structures is based on RISC-V instructions. It uses Process Algebra Oriented to Instruction Set Architecture (PA-ISA) to define basic operations such as program stalling, successful termination, sequential execution, conditional branching, and merging, and to describe the execution flow in program blocks. Based on PA-ISA, instruction-level event structures (IES) are used to describe the dependencies between instructions during program execution.

[0057] 1. Process algebra that adapts to program instruction sequences

[0058] To accurately express the instruction sequence, parallelism, conflicts, and dependencies in a program, this invention first simplifies and extends the traditional process algebra model based on program structure, proposing the PA-ISA model. This model defines the program structure through a set of syntactic construction rules, as shown in Table 1:

[0059] Table 1. PA-ISA Model Syntax Construction Rules

[0060] .

[0061] PA-ISA supports the following basic syntax constructs:

[0062] inaction(0): indicates that the program does nothing or terminates, equivalent to an empty process with an empty instruction set;

[0063] successful termination (√): This indicates that the program has successfully completed and ended in a certain state, and the instruction set is also empty;

[0064] action-prefix ((i; B), where i∈InstrSet): indicates that after instruction i is executed, program B continues to be executed, corresponding to sequential execution semantics, and its instruction set is {i}∪InstrSet(B);

[0065] choice (B1 + B2): This indicates a conditional selection statement. The program chooses to execute one of B1 and B2. It represents a conditional branch structure. Its instruction set is the union of B1 and B2, i.e., InstrSet(B1)∪InstrSet(B2).

[0066] merge (B1 B2): Represents the merging of two program blocks. It is usually used to regenerate the dependencies between the instructions of two program blocks in a structured way. Its instruction set is the union of B1 and B2, i.e., InstrSet(B1)∪InstrSet(B2).

[0067] PA-ISA supports structured composition with dependency information, explicitly representing the dependency logic between instructions and uncovering potential parallel relationships between instructions. The PA-ISA-based modeling approach provides a rigorous structural semantic foundation for the subsequent construction of event structures.

[0068] 2. Instruction-Level Event Structure (IES) for RISC-V Processor Execution Scenarios

[0069] Building upon PA-ISA, this invention further defines a structural model adapted to processor scheduling scenarios—IES. Its core is based on the theory of bound event structures, constructing an instruction-level semantic model oriented towards program execution. IES is an extension of the traditional event structure, defined as follows:

[0070] E, an event is defined as a set of instructions in a program;

[0071] #, contradictory relationship, only applies to dynamic branch instructions, inserts a virtual event e' after the jump instruction e;

[0072] The binding relationship is defined as B, J, and R, which represent the instruction sets of dynamic branching, static jumping, and register-dependent instructions, respectively.

[0073] Action tags indicate the instruction type in the instruction set architecture.

[0074] The introduction of IES enables "explicit structured expression of instruction dependencies," providing hardware with an intuitive and structured basis for scheduling.

[0075] 3. High-concurrency processor architecture based on IES

[0076] Overall architecture as follows Figure 1 As shown, a detailed explanation is given using 32 instructions as an example.

[0077] (1) Fetch, Decode and Event Structure Build module

[0078] A multi-round parallel instruction fetching strategy combining dual-path prediction is employed to mitigate the disruption caused by branch instructions to the instruction fetch process and improve the continuity and fault tolerance of front-end bandwidth in high-scalar processors. The architecture diagram of the instruction fetch, decoding, and event structure generation modules is shown below. Figure 2 As shown, the specific process is as follows:

[0079] First, the instruction fetch module retrieves a total of 32 instructions from the instruction cache in each round, which is completed in 4 fetches, with 8 instructions retrieved each time, and labeled A, B, C, and D respectively:

[0080] A: The 8 instructions fetched sequentially starting from the current program counter PC;

[0081] B: If the branch prediction module identifies a branch instruction in A, then the 8 instructions are fetched based on the target address of the "jump" of that branch;

[0082] C: Corresponding to B, it represents the 8 instructions taken in the branch "sequence" direction;

[0083] D: Based on the branch prediction results, continue to retrieve 8 instructions sequentially from the target PC selected from B or C to continue the predicted path;

[0084] If no branch instruction is detected in any instruction fetch cycle (A, B, C, D), the system will run in sequential instruction fetch mode to reduce unnecessary prediction overhead.

[0085] Then, the four instructions A, B, C, and D are concatenated to form a complete set of 32 instructions (instruction 0, instruction 1, ..., instruction n), which fully covers the branching situation of the current main path and alternative paths, in order to reduce the cost of front-end bubbling caused by prediction errors.

[0086] Finally, the concatenated 32 instructions are sent to the decoder for unified decoding. In the subsequent dependency analyzer, each instruction's corresponding instruction-level event structure (AIES, BIES, CIES, DIES) is independently constructed for A, B, C, and D to facilitate out-of-order scheduling or scheduling optimization during execution. Through this mechanism, the processor can simultaneously cover the main branch path and alternative paths within a single instruction fetch cycle, significantly reducing the destructive impact of branch misprediction on instruction supply.

[0087] (2) Branch Prediction Control Module

[0088] Instruction fetching works by fetching one small round of instructions at a time, for a total of four fetches constituting one large round. After each small round of instructions is fetched, it is sent to the branch prediction module for branch jump prediction. The architecture diagram is as follows: Figure 3As shown, the branch prediction control module includes an instruction fetch channel, a branch prediction module, a correction channel, a branch prediction correction module, and a write-back channel. The Fetch Unit sends a small round of instructions through the Fetch channel (Fetch_ch), which is then entered into the Branch Prediction Unit (Prediction_part) for prediction. The predicted address result is output to the Fetch Unit for the next small round of instruction fetching. After a large round is completed, the Retirement Unit indicates whether the prediction result is correct and sends the address of a new large round of instructions to the Fetch Unit. The correction channels Correction_ch1, Correction_ch2, ​​Correction_ch3, and Correction_ch4 correspond to the four small rounds of instructions A, B, C, and D, respectively. If the prediction is incorrect, these four small rounds of instructions need to be corrected, and they are entered into the Branch Prediction Unit (Correction_part) for correction. In addition, the write-back channel (Retirement termination_ch5) is responsible for passing the address of the next round of instructions to be written back to the Fetch Unit.

[0089] (3) Event Structure Merge and Buffer Scheduling

[0090] Architecture diagram as follows Figure 4As shown, the event structure merging module merges multiple independently constructed small event structures (A ES, B ES, C ES, D ES) into a global IES to support high-concurrency instruction scheduling and execution. During the merging process, the dependencies of each event node are preserved, and causal relationships and mutual exclusion conflicts across structures are constructed. This module outputs a unified IES for subsequent parsing by the scheduling system. The control logic coordinates two types of instruction buffers. The New Instruction Buffer stores new instructions that participate in IES scheduling after parsing in the current batch; the Remainder Buffer stores residual instructions that were not fully scheduled at the moment, which participate in the next round of IES merging. The merged IES structure drives instruction scheduling according to the priority hierarchy among events. All instructions are divided into multi-level buffers for waiting and execution based on their hierarchical distribution in the IES. This invention adopts a four-level buffer scheduling structure (expandable) to represent the scheduling order from the first executable instruction to the last layer of dependent instructions. Instructions do not physically move within the buffers in the IES hierarchy; instead, they are resolved and emitted by the IES-driven hierarchy switching through the Control n Buffers module.

[0091] (4) Execute module

[0092] Architecture diagram as follows Figure 5 As shown, the Execute Unit comprises two functional units (FU_UNIT), one address generation unit (AGU_UNIT), and one branch jump unit (BRU). Each FU_UNIT contains 8 arithmetic units, 2 multiplication units, and 1 division unit; each AGU_UNIT contains 8 address generation units; and the BRU handles jump instructions. When the Level 4 Buffer (used to temporarily store instructions that can be executed in parallel) sends the instruction to the Execute Unit, the Execute Unit selects the appropriate processing module for processing based on the instruction type. Due to the large number of processing modules, the unit supports the parallel execution of multiple instructions. After processing, the output path of the result is divided into several types: some results are directly output to the Reorder Buffer (ROB), while others need to be bypassed or processed further by the Memory Request Unit (LSU).

[0093] (5) Load Store Unit

[0094] Architecture diagram as follows Figure 6As shown, the system includes an Input / Output Unit (IO_Unit), a Load instruction dependency detection module, a Store instruction buffer (Store_Buffer), and an SRAM Control Unit (SRAM Control Unit). Upon receiving the address from the Memory Management Unit (MMU Unit), the LSUUnit immediately initiates address detection logic. If the address is an Input / Output (IO) address, the corresponding data is directly transmitted to the IO_Unit. If it is a non-IO address, the instruction type is further identified. If it is a Load instruction, address dependency detection is performed by the Load instruction dependency detection module. If it is a Store instruction, the instruction data is preprocessed and temporarily stored in the Store instruction buffer. Load instructions retrieve data from different data sources based on the dependency detection results, while Store instructions are temporarily stored in the Store instruction buffer. After certain processing, data is written to the SRAM Control Unit in sequence. Load instructions that need to retrieve data from the SRAM Control Unit, and some Store instructions specified by the write-back process, trigger the SRAM Control Unit to execute the corresponding memory access operation. Data transmitted by the Execute Unit is written to the corresponding memory location according to the address provided by the MMU Unit.

[0095] (6) Write Back Module

[0096] Architecture diagram as follows Figure 7As shown, the system includes a Write-In-Preprocessing module, an Instruction Parse module, a Retire Judge module, and a Retire Control module. The Retire module is responsible for instruction retirement, primarily handling the retirement of seven instruction types: reg, csr, store, load, B-type, jal, and jalr. Before retirement, instructions are executed out of order; to ensure the correctness of the execution results, they must be written sequentially. Therefore, retirement mainly maintains the Retire Buffer (ROB). Before updating the ROB, the data exchanged between the retire module and other modules needs to be preprocessed, mainly for store, load, and jalr instructions. The Write-In-Preprocessing module preprocesses some instructions, and the preprocessed data is stored in the ROB. The ROB mainly consists of a buffer storing instruction information (such as Type_3, Rd_5, PC_32, etc.) and a Complete Buffer (which determines the instructions that can be retireed). The Instruction Parse module parses the information of four instructions in the ROB at a time. Each set of four instructions is parsed into four main categories and seven groups: reg, csr, ST, and branch instructions. Then, the instructions that can be rewritten are distributed for retire dispatch. The Retire Control module maintains several variables controlling the retire process after instruction rewriting, including four rewrite pointers and a flag indicating the next instruction's transmission permission. The information sent by the Instruction Parse module should include jump information and a pointer to the last valid instruction among the four instructions being rewritten. The Retire Control module receives four rewrite pointers and a validity bit from the Retire Judge module. The validity bit indicates whether the rewrite pointer can be used to rewrite instructions. The Retire Judge module, based on the current complete bit and validity bit information, comprehensively determines the instructions that can be rewritten at this point. The rewrite module terminates when a jump instruction is rewritten and a prediction error occurs, or when 32 instructions are rewritten.

[0097] The high-concurrency processor scheduling method based on instruction-level event structure proposed in this invention employs an asynchronous event-driven execution mechanism to achieve efficient instruction scheduling and execution. The introduction of the asynchronous mechanism allows this invention to maintain accurate communication and orderly execution between modules without requiring global clock signal synchronization, thereby reducing power consumption and increasing parallelism. The scheduling method of this invention is implemented using a high-concurrency processor architecture based on instruction-level event structure. The instruction execution path establishes communication through an asynchronous handshake protocol based on the instruction fetch, decoding, and event structure generation modules, branch prediction control module, event structure merging module, buffer scheduling structure, execution module, memory access module, and write-back module. Each module integrates a local controller, which drives local logic operation through a request-response protocol. When data is ready and the transmission relationship is satisfied, subsequent module processing is automatically triggered, forming an asynchronous pipeline at the functional level. The request-response mechanism transmits data and control signals between modules, ensuring that forwarding operations are only initiated when the receiving module is ready, thus guaranteeing system consistency.

[0098] Each instruction is identified at the event level. The causal edges within the event structure connect the triggering conditions of each instruction via an asynchronous control chain. Upon completion of the current instruction, the chain activates the ready signal of its direct successor instruction, achieving a dependency-driven scheduling approach. After instruction execution, some events may not be triggered; these residual events are retained in the RemainderBuffer and then concatenated with the new event structure generated by the next batch of new instructions through the event structure merging module. This concatenation action is also driven by an asynchronous chain; once the previous event structure has completed propagation, the next stage of event structure construction and propagation immediately begins.

[0099] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-concurrency processor system based on an instruction-level event structure, characterized in that, The high-concurrency processor system is based on RISC-V instructions. It uses Process Algebra-Based Interpreter (PA-ISA) to define program pauses, successful terminations, sequential execution, conditional branches, and merging operations, describing the execution flow within a program block. Building upon PA-ISA, it uses Instruction-Level Event Structures (IES) to describe the dependencies between instructions during program execution. The definition of the Instruction-Level Event Structures (IES) is as follows: E, an event is defined as a set of instructions in a program; #, contradictory relationship, only applies to dynamic branch instructions, inserts a virtual event e' after the jump instruction e; The binding relationship is defined as B, J, and R, which represent the instruction sets of dynamic branching, static jumping, and register-dependent instructions, respectively. Action tags indicate the instruction type in the instruction set architecture; IES-based high-concurrency processor systems include: Instruction fetch, decoding, and event structure generation module: The instruction fetching module adopts a multi-round parallel instruction fetching strategy that combines dual-path prediction. After the fetched instructions are decoded, each instruction is used to construct an IES. Branch prediction control module: predicts branch jumps for instruction fetch instructions; Event Structure Merging Module: Merges multiple independently constructed small event structures into a global IES. During the merging process, the dependencies of each event node are preserved, and causal relationships and mutual exclusion conflicts across structures are constructed; the merged IES is then output. Buffer scheduling structure: A multi-level buffer scheduling structure is adopted, which drives the scheduling of instructions according to the priority level between events after merging IES. Based on the hierarchical distribution of instructions in IES, they are divided into multi-level buffers for waiting and execution. Execution module: Selects the appropriate processing module based on the instruction type for processing, supporting the parallel execution of multiple instructions; Memory access module: performs address detection on the address transmitted by the memory management unit and executes the corresponding memory access operation based on the detection result; writes the data transmitted by the execution module to the corresponding memory location according to the address provided by the memory management unit. Write-back module: Performs sequential write-back of different types of instructions.

2. The high-concurrency processor system based on instruction-level event structure as described in claim 1, characterized in that, The basic syntax construction supported by PA-ISA is as follows: inaction(0): indicates that the program does nothing or terminates, equivalent to an empty process with an empty instruction set; successful termination (√): This indicates that the program has successfully completed and ended in a certain state, and the instruction set is also empty; action-prefix ((i; B), where i∈InstrSet): indicates that after instruction i is executed, program B continues to be executed, corresponding to sequential execution semantics, and the instruction set is {i}∪InstrSet(B); choice (B1 + B2): This indicates a conditional selection statement. The program chooses to execute either B1 or B2. It represents a conditional branching structure, and the instruction set is the union of B1 and B2. merge (B1 B2): Represents the merging of two program blocks, used to structurally represent the regeneration of the dependencies between the instructions of the two program blocks. The instruction set is the union of B1 and B2, i.e., InstrSet(B1)∪InstrSet(B2).

3. The high-concurrency processor system based on instruction-level event structure as described in claim 1, characterized in that, The branch prediction control module includes an instruction fetch channel, a branch prediction module, a correction channel, a branch prediction correction module, and a write-back channel. The instruction fetched through the instruction fetch channel enters the branch prediction module for prediction and outputs the predicted address result. After the prediction is completed, the write-back module sends the instruction with the incorrect address result to the branch prediction correction module through the correction channel for correction. At the same time, the write-back module transmits the address of the next instruction fetch through the write-back channel.

4. The high-concurrency processor system based on instruction-level event structure as described in claim 1, characterized in that, The buffer scheduling structure will coordinate the new instruction buffer and the remaining instruction buffer through control logic. The new instruction buffer is used to store the new instructions that participate in IES scheduling after the current batch is parsed, and the remaining instruction buffer is used to store the instruction remnants that were not fully scheduled at the moment and participate in the next round of IES merging.

5. The high-concurrency processor system based on instruction-level event structure as described in claim 1, characterized in that, The execution module includes two functional units FU_UNIT, one address generation unit AGU_UNIT, and one branch jump unit BRU. Each FU_UNIT contains 8 arithmetic units, 2 multiplication units, and 1 division unit; each AGU_UNIT contains 8 address generation units; and the BRU is used to process jump instructions.

6. The high-concurrency processor system based on instruction-level event structure as described in claim 5, characterized in that, The output path of the execution module includes a reordering buffer, a bypass, and a memory access unit.

7. The high-concurrency processor system based on instruction-level event structure as described in claim 1, characterized in that, The memory access module includes an input / output unit, a Load instruction dependency detection module, a Store instruction cache, and an SRAM control unit. Upon address detection, if the address is an input / output type, the corresponding data is directly transmitted to the input / output unit. If the address is not an input / output type, the instruction type is further identified. If it is a Load instruction, address dependency detection is performed by the Load instruction dependency detection module. If it is a Store instruction, the instruction data is preprocessed and temporarily stored in the Store instruction cache. Load instructions retrieve data from different data sources based on the dependency detection results, while Store instructions are temporarily stored in the Store instruction cache. After certain processing, data is written to the SRAM control unit in sequence. Load instructions that need to retrieve data from the SRAM control unit, and some Store instructions specified by the write-back process, trigger the SRAM control module to execute the corresponding memory access operation.

8. The high-concurrency processor system based on instruction-level event structure as described in claim 1, characterized in that, The write-back module includes a preprocessing module, an instruction parsing module, a write-back judgment module, and a write-back control module; wherein: The preprocessing module is used for instruction preprocessing, and the preprocessed data is stored in the reordering cache; The instruction parsing module is used to parse the information of instructions in the reordering cache, and then distribute the write-back instructions for write-back. The write-back control module is used to maintain multiple variables controlling the write-back after the instruction is written back and to transmit them to the write-back judgment module; The write-back judgment module is used to comprehensively provide write-back instructions based on the current completion bit and valid bit information.

9. A high-concurrency processor scheduling method based on instruction-level event structure, characterized in that, The high-concurrency processor system based on instruction-level event structure as described in any one of claims 1-8 is implemented. The instruction execution path establishes communication through an asynchronous handshake protocol based on the instruction fetch, decoding and event structure generation module, branch prediction control module, event structure merging module, buffer scheduling structure, execution module, memory access module, and write-back module. Each module integrates a local controller and drives local logic operation through a request-response protocol. When data is ready and the transmission relationship is satisfied, subsequent module processing is automatically triggered, forming an asynchronous pipeline at the functional level. The request-response mechanism transmits data and control signals between modules. Each instruction is identified at the event granularity. The causal edges contained in the event structure are connected to the triggering conditions of each instruction through an asynchronous control chain. When the current instruction is completed, the ready signal of its direct successor instruction is activated through the link, realizing a dependency-driven scheduling method.

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