Data transmission system, chip and electronic equipment

Abstract

The invention discloses a data transmission system, a chip and electronic equipment, and belongs to the technical field of integrated circuits, and the data transmission system comprises a medium access control layer, a physical coding sub-layer and a physical medium adaptation layer. In a data transmission system of a sending end, a physical coding sub-layer comprises a conversion module; the conversion module is used for performing bit width conversion and clock domain conversion on first sending data sent by the medium access control layer to obtain second sending data, and sending the second sending data to the physical medium adaptation layer; in a data transmission system of a receiving end, a physical coding sub-layer comprises a locking module and a processing module which are electrically connected; the locking module is used for performing data locking on first receiving data sent by the physical medium adaptation layer to obtain second receiving data, and sending the second receiving data to the processing module; and the processing module is used for processing the second receiving data into third receiving data and sending the third receiving data to the medium access control layer.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and particularly relates to a data transmission system, a chip and an electronic device. BACKGROUND

[0002] At a macroscopic level, long-distance interconnection technology and off-chip short-distance interconnection technology are conducive to the formation of a super-large server cluster and a computing center. At a microscopic level, intra-chip interconnection technology with a millimeter order of magnitude is conducive to the production of a chip with more complex functions and greater computing throughput.

[0003] Chip interconnection technology based on the Peripheral Component Interconnect express (PCIe) standard has strong compatibility and universality, and can be used for off-chip long-distance interconnection wiring and intra-chip short-distance packaging interconnection.

[0004] The sending end and the receiving end of the PCIe involve clock domain conversion. However, after the transmission rate is improved and the data coding scheme is changed, the physical layer still uses the old interface due to compatibility problems, for example, the physical layer is still a 20-bit interface. When 32-bit data is transmitted to the physical layer, at least four-tap delay is generated, which leads to unnecessary transmission delay of data in the physical layer transmission, and reduces the data transmission efficiency. SUMMARY

[0005] The purpose of the embodiments of the present application is to provide a data transmission system, a chip and an electronic device, which can solve the problem of unnecessary transmission delay of data through the physical layer conversion, leading to reduced data transmission efficiency.

[0006] In a first aspect, the embodiments of the present application provide a data transmission system, which comprises a medium access control layer, a physical coding sublayer and a physical medium adaptation layer.

[0007] In the data transmission system at the sending end, the physical coding sublayer comprises a conversion module; the conversion module is configured to perform bit width conversion and clock domain conversion on first sending data sent by the medium access control layer to obtain second sending data, and send the second sending data to the physical medium adaptation layer; wherein the ratio of the data bit width of the first sending data to the data bit width of the second sending data is 2N, and N is a positive integer.

[0008] In the data transmission system at the receiving end, the physical coding sublayer comprises a locking module and a processing module electrically connected; the locking module is used for data locking on the first received data sent by the physical medium adaptation layer, so as to determine the starting boundary of a character or a data block in the first received data, obtain second received data, and send the second received data to the processing module; the processing module is used for processing the second received data into third received data, and sending the third received data to the medium access control layer; wherein the ratio of the data bit width of the third received data to the data bit width of the first received data is 2N.

[0009] Optionally, in the data transmission system at the sending end, the conversion module of the physical coding sublayer comprises an encoding unit and an asynchronous conversion unit electrically connected;

[0010] The encoding unit is used for encoding the first sent data sent by the medium access control layer to obtain first encoded data, and sending the first encoded data to the asynchronous conversion unit;

[0011] The asynchronous conversion unit is used for bit width conversion and clock domain conversion on the first encoded data, to obtain the second sent data, and sending the second sent data to the physical medium adaptation layer.

[0012] Optionally, the asynchronous conversion unit comprises an asynchronous immediate first-in-first-out buffer, and the asynchronous immediate first-in-first-out buffer is electrically connected with the encoding unit;

[0013] The asynchronous immediate first-in-first-out buffer is used for converting the first encoded data into second encoded data, converting the clock domain of the second encoded data to the clock domain corresponding to the physical medium adaptation layer, to obtain the second sent data, and sending the second sent data to the physical medium adaptation layer.

[0014] Optionally, the encoding unit comprises a first encoder, and the first encoder is electrically connected with the asynchronous conversion unit;

[0015] The first encoder is used for acquiring 10-bit encoded data according to every 8-bit valid data in the first sent data, to obtain the first encoded data, and sending the first encoded data to the asynchronous conversion unit.

[0016] Optionally, in the data transmission system at the receiving end, the conversion module of the physical coding sublayer comprises a character locking unit, and the processing module comprises a decoding unit, and the decoding unit is electrically connected with the character locking unit;

[0017] The character locking unit is configured to perform character locking on the first received data transmitted by the media access control layer, to determine the starting boundary of the character in the first received data, to obtain to-be-decoded data, to convert the clock domain of the to-be-decoded data to the clock domain corresponding to the decoding unit, to obtain the second received data, and to transmit the second received data to the decoding unit.

[0018] The decoding unit is configured to perform decoding processing on the second received data, to obtain the third received data, and to transmit the third received data to the media access control layer.

[0019] Optionally, the character locking unit comprises an asynchronous locking first-in-first-out buffer, which is electrically connected to the decoding unit.

[0020] The asynchronous locking first-in-first-out buffer is configured to perform 10-bit alignment character locking on the first received data, to obtain the to-be-decoded data, to convert the clock domain of the to-be-decoded data to the clock domain corresponding to the decoding unit, to obtain the second received data, and to transmit the second received data to the decoding unit.

[0021] Optionally, the decoding unit comprises a first decoder, which is electrically connected to the character locking unit.

[0022] The first decoder is configured to obtain 8-bit valid data from each 10-bit encoded data in the second received data, to obtain the third received data, and to transmit the third received data to the media access control layer.

[0023] Optionally, in the data transmission system of the sending end, the conversion module of the physical coding sublayer comprises a synchronous first-in-first-out buffer, which is configured to perform synchronous bit width conversion and clock domain conversion on the first transmitted data, to obtain the second transmitted data, and to transmit the second transmitted data to the physical media adaptation layer.

[0024] Optionally, in the data transmission system of the receiving end, the conversion module of the physical coding sublayer comprises a block locking unit, and the processing module comprises a clock compensation unit, which is electrically connected to the block locking unit.

[0025] The block locking unit is configured to perform block locking on the first received data transmitted by the media access control layer, to determine the starting boundary of the data block in the first received data, to obtain the second received data, and to transmit the second received data to the clock compensation unit.

[0026] The clock compensation unit is configured to convert a clock domain of the second received data to a clock domain corresponding to the medium access control layer, to obtain third received data, and to send the third received data to the medium access control layer.

[0027] Optionally, the block locking unit comprises a block locking buffer, which is electrically connected to the clock compensation unit.

[0028] The block locking buffer is configured to perform block alignment on the first received data to obtain block data, and to send the block data to the clock compensation unit as the second received data.

[0029] Optionally, the clock compensation unit comprises an elastic buffer, which is electrically connected to the block locking unit.

[0030] The elastic buffer is configured to perform clock compensation on the second received data based on clock offset compensation of an ordered set, to obtain the third received data, and to send the third received data to the medium access control layer.

[0031] Optionally, in the data transmission system of the sending end, the physical medium adaptation layer comprises a first physical layer interface, and in the data transmission system of the receiving end, the physical medium adaptation layer comprises a second physical layer interface, and the first physical layer interface and the second physical layer interface are compatible with the high-speed serial computer expansion bus standard.

[0032] In a second aspect, an embodiment of the present application provides a chip, which comprises the data transmission system as described in the first aspect.

[0033] In a third aspect, an embodiment of the present application provides an electronic device, which comprises the chip as described in the second aspect.

[0034] In the embodiment of the present application, for the physical coding sublayer between the medium access control layer and the physical medium adaptation layer in the data transmission system, the conversion module of the physical coding sublayer is configured to receive the first sending data sent by the medium access control layer, to perform bit width conversion and clock domain conversion, and to send the second sending data to the physical medium adaptation layer, and the locking module of the physical coding sublayer is configured to receive the first receiving data sent by the physical medium adaptation layer, to perform data locking on the first receiving data to determine the starting boundary of a character or a data block in the first receiving data, and to send the obtained second receiving data to the processing module, so that the data processing error caused by the misalignment of the boundary of the data can be avoided, the accuracy of data transmission can be improved, the processing module is configured to process the second receiving data into the third receiving data and to send the third receiving data to the medium access control layer. In this way, since the ratio of the data bit width of the first sending data to the data bit width of the second sending data is 2N, and the ratio of the data bit width of the third receiving data to the data bit width of the first receiving data is 2N, N is a positive integer, that is, the data is a power of 2, the bit width of the sending path of the data transmitted from the medium access control layer to the physical medium adaptation layer through the physical coding sublayer is matched, and the bit width of the receiving path of the data transmitted from the physical medium adaptation layer to the medium access control layer through the physical coding sublayer is matched, the transmission delay problem caused by the mismatch of the bit width can be avoided, and the data transmission efficiency of the data transmission system of the sending end and the receiving end can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 is a structural schematic diagram of a data transmission system provided by the embodiment of the present application;

[0036] Figure 2 is one of the structural schematic diagrams of the data transmission system of the sending end provided by the embodiment of the present application;

[0037] Figure 3 is the second structural schematic diagram of the data transmission system of the sending end provided by the embodiment of the present application;

[0038] Figure 4 is one of the structural schematic diagrams of the data transmission system of the receiving end provided by the embodiment of the present application;

[0039] Figure 5 is the second structural schematic diagram of the data transmission system of the receiving end provided by the embodiment of the present application;

[0040] Figure 6 is the third structural schematic diagram of the data transmission system of the sending end provided by the embodiment of the present application;

[0041] Figure 7 is the third structural schematic diagram of the data transmission system of the receiving end provided by the embodiment of the present application;

[0042] Figure 8 Figure 4 is a structural schematic diagram of a data transmission system of a receiving end provided by an embodiment of the present application. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0044] The terms "first", "second", and the like in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second", and the like are generally of a kind and are not limited in number, for example, the first object can be one or at least two. In addition, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / ", generally indicates that the objects before and after are in an "or" relationship.

[0045] Currently, the design and manufacturing of chips at advanced process nodes face two main problems, cost and performance. From a macro perspective, that is, at the level of multi-rack, large-scale cluster, the demand for super-large cluster computing power is rising. With the rapid development of artificial intelligence, big data analysis, cloud computing and the Internet of Things, the demand for computing power is also growing. Super-large cluster computing power has the ability to process massive data, complex calculations and deep learning tasks, and can support large business demands. From a micro perspective, "Moore's Law" and "Dennard Scaling" are gradually slowing down, and the space for transistor channel length to explore below 3 nanometers and 2 nanometers is becoming smaller. For wafer factories, under the condition of a certain transistor density, the larger the wafer, the lower the yield of finished products. In order to control costs, the interconnection within the package is receiving more and more attention.

[0046] From the current development trend, long-distance interconnection technology on the order of meters and short-distance interconnection technology outside the chip on the order of centimeters are conducive to the formation of super-large server clusters and computing centers. Chip-level interconnection technology on the order of millimeters is conducive to making chips with more complex functions and greater computing throughput while controlling costs and yield.

[0047] Figure 1 Figure 1 is a structural schematic diagram of a data transmission system provided by an embodiment of the present application. Figure 1As shown, the data transmission system comprises a media access control layer (MAC), a physical coding sublayer (PCS) and a physical medium attachment layer (PMA);

[0048] In the data transmission system at the sending end, the physical coding sublayer (PCS) comprises a conversion module 101; the conversion module 101 is configured to perform bit width conversion and clock domain conversion on first sending data sent by the media access control layer (MAC) to obtain second sending data, and send the second sending data to the physical medium attachment layer (PMA); wherein the ratio of the data bit width of the first sending data to the data bit width of the second sending data is 2N, and N is a positive integer;

[0049] In the data transmission system at the receiving end, the physical coding sublayer (PCS) comprises a locking module 201 and a processing module 202 connected electrically; the locking module 201 is configured to perform data locking on first receiving data sent by the physical medium attachment layer (PMA) to determine the starting boundary of a character or a data block in the first receiving data, to obtain second receiving data, and send the second receiving data to the processing module 202; the processing module 202 is configured to process the second receiving data into third receiving data, and send the third receiving data to the media access control layer (MAC); wherein the ratio of the data bit width of the third receiving data to the data bit width of the first receiving data is 2N.

[0050] In some embodiments, the data transmission system can be applied to data transmission of a chip interconnection link, which is a channel for data transmission between chips or between different modules in a chip. The data transmission system comprises a media access control layer (MAC), a physical coding sublayer (PCS) and a physical medium attachment layer (PMA), wherein the physical layer can comprise the PCS and PMA layers. In addition, the data transmission system can further comprise a data link layer (DLL), which is responsible for generating a data link layer packet (DLLP) and distributing the DLLP packet and a transaction layer packet (TLP) to the media access control layer (MAC).

[0051] In order to reduce the data transmission delay and improve the data transmission efficiency, the data transmission system provided by the embodiment adopts different data path structures in the physical coding sublayer (PCS) of the sending end and the receiving end to ensure efficient transmission under different data transmission rates. Specifically, the physical coding sublayer (PCS) in the data transmission system of the sending end includes a conversion module 101, and the input interface of the conversion module 101 can be electrically connected with the output interface of the sending module in the medium access control layer (MAC). The physical coding sublayer (PCS) in the data transmission system of the receiving end includes a locking module 201 and a processing module 202, the output interface of the locking module 201 is electrically connected with the input interface of the processing module 202, the input interface of the locking module 201 can be electrically connected with the output interface of the receiving module in the physical medium adaptation layer (PMA), and the output interface of the processing module 202 can be electrically connected with the input interface of the receiving module in the medium access control layer (MAC).

[0052] In some embodiments, the conversion module 101 is configured to convert the data bit width of the first sending data from the output interface of the medium access control layer (MAC) to the input interface of the physical medium adaptation layer (PMA), and convert the sending clock domain of the first sending data to the receiving clock domain of the physical medium adaptation layer (PMA) to obtain second sending data, and send the second sending data to the physical medium adaptation layer (PMA) so that the physical medium adaptation layer (PMA) can correctly receive the second sending data.

[0053] In some embodiments, the ratio of the data bit width of the first sending data to the data bit width of the second sending data is 2N, where N is a positive integer, i.e., the first sending data and the second sending data are both powers of 2, so that the bit width between the medium access control layer (MAC) and the physical medium adaptation layer (PMA) is matched, and the transmission delay between the medium access control layer (MAC) and the physical medium adaptation layer (PMA) is reduced. For example, the data bit width of the first sending data is 32 bits, and the data bit width of the second sending data is 16 bits, so the ratio of the data bit width of the first sending data to the data bit width of the second sending data is 2.

[0054] In some embodiments, the locking module 201 is configured to perform data locking on the first receiving data sent by the physical medium adaptation layer (PMA) to determine the starting boundary of a character or a data block in the first receiving data, so that the first receiving data can be bit-aligned or block-aligned to obtain second receiving data, and the second receiving data is sent to the processing module 202 for further processing by the processing module 202. The processing module 202 is configured to perform decoding, clock compensation, etc. on the second receiving data, convert the third receiving data to the input interface bit width of the medium access control layer (MAC), and convert the second receiving data to the receiving clock domain of the medium access control layer (MAC) to obtain third receiving data.

[0055] The data transmission system of the receiving end is similar to the data transmission system of the sending end, and the ratio of the data bit width of the third received data to the data bit width of the first received data is 2 N, N being a positive integer, that is, the third received data and the first received data are both powers of 2, so that the bit width between the physical media adaptation layer PMA and the medium access control layer MAC is matched, and the transmission delay between the physical media adaptation layer PMA and the medium access control layer MAC is reduced. For example, the data bit width of the first received data is 16 bits, and the data bit width of the third received data is 32 bits, so the ratio of the data bit width of the third received data to the data bit width of the first received data is 2.

[0056] The data transmission system provided by the embodiment can be applied to a low-speed transmission interconnection application scenario, for example, a chip interconnection link using the Gen1 and Gen2 transmission rates of PCIe, or the data transmission system can also be applied to a high-speed transmission interconnection application scenario, for example, a chip interconnection link using the Gen3 and Gen4 transmission rates of PCIe.

[0057] The Gen1 represents the first generation, the Gen1 transmission rate is 2.5 Giga Transfers per second (GT / s), and the encoding mode uses 8 / 10 encoding, that is, 8 bits of valid data are transmitted per 10 bits of encoded data. The transmission rate of Gen2 is 5 GT / s, and the encoding mode uses 8 / 10 encoding, and the encoding efficiency is 80%. Gen3 and Gen4 use a simpler 128 / 130 encoding. For example, the transmission rate of Gen3 is 8 GT / s, and the transmission rate of Gen4 is 16 GT / s.

[0058] In some embodiments, when data is transmitted in the data transmission system, asynchronous clock domain conversion is involved, for example, the clock domains corresponding to the data link layer DLL, the medium access control layer MAC, the physical coding sublayer PCS and the physical media adaptation layer PMA respectively can be different, and the data transmission system of the sending end needs to go through several asynchronous clock domain conversions when transmitting data, and the receiving end is the same. In particular, in a high-speed transmission chip interconnection link, the performance loss caused by the transmission delay across asynchronous clock domains will be greater.

[0059] In the embodiments of the present application, for the physical coding sublayer (PCS) between the medium access control (MAC) layer and the physical medium attachment (PMA) layer in the data transmission system, the conversion module 101 of the physical coding sublayer (PCS) is configured to receive the first sending data sent by the medium access control (MAC) layer, perform bit width conversion and clock domain conversion, and then send the second sending data to the physical medium attachment (PMA) layer, and the locking module 201 of the physical coding sublayer (PCS) is configured to receive the first receiving data sent by the physical medium attachment (PMA) layer, lock the first receiving data, determine the starting boundary of the character or data block in the first receiving data, and send the obtained second receiving data to the processing module 202, so as to avoid data processing errors caused by boundary misplacement of data, improve the accuracy of data transmission, and configure the processing module 202 to process the second receiving data into the third receiving data and send the third receiving data to the medium access control (MAC) layer. In this way, since the ratio of the data bit width of the first sending data to the data bit width of the second sending data is 2N, and the ratio of the data bit width of the third receiving data to the data bit width of the first receiving data is 2N, N is a positive integer, that is, the data is a power of 2, so that the bit width of the sending path of the data from the medium access control (MAC) layer to the physical medium attachment (PMA) layer through the physical coding sublayer (PCS) is matched, and the bit width of the receiving path of the data from the physical medium attachment (PMA) layer to the medium access control (MAC) layer through the physical coding sublayer (PCS) is matched, so that the transmission delay problem caused by the mismatch of the bit width can be avoided, and the data transmission efficiency of the data transmission system of the sending end and the receiving end can be improved.

[0060] In the related art, the data transmission rate is improved from Gen1 and Gen2 to Gen3 and Gen4, and the data encoding method is changed, such as 8 / 10 encoding to 128 / 130 encoding, but the physical layer interface still retains a 20-bit interface, resulting in that under the transmission rate of Gen3 and Gen4, several asynchronous clock domain conversions under the transmission rates of Gen1 and Gen2 are still required, causing great transmission delay of data during sending and receiving, and bringing great performance loss.

[0061] In the data transmission system at the sending end, the conversion module 101 of the physical coding sublayer PCS can be configured as a 32-bit input interface and a 16-bit output interface, so that the conversion module 101 can receive the 32-bit first sending data sent by the medium access control layer MAC through the 32-bit input interface, and send the converted 16-bit second sending data to the physical medium adaptation layer PMA through the 16-bit output interface. Therefore, the 32-bit first sending data can be converted into the 16-bit second sending data through synchronous bit width conversion and clock domain conversion, so as to avoid unnecessary transmission delay caused by bit width mismatch when the data at the sending end is converted in the physical coding sublayer PCS, thereby improving the data transmission efficiency.

[0062] In the data transmission system at the receiving end, the locking module 201 of the physical coding sublayer PCS can be configured as a 16-bit input interface, and the processing module 202 can be configured as a 32-bit output interface, so that the locking module 201 can receive the 16-bit first sending data sent by the physical medium adaptation layer PMA through the 16-bit input interface, and the processing module 202 can send the converted 32-bit third receiving data to the medium access control layer MAC through the 32-bit output interface. Therefore, the 16-bit first receiving data can be converted into the 32-bit third receiving data through synchronous data locking and data processing, so as to avoid unnecessary transmission delay caused by data locking and data processing when the data at the receiving end is converted in the physical coding sublayer PCS, thereby improving the data transmission efficiency.

[0063] Optionally, as shown in Figure 2 In the data transmission system at the sending end, the conversion module 101 of the physical coding sublayer PCS includes an encoding unit 1011 and an asynchronous conversion unit 1012 connected electrically;

[0064] The encoding unit 1011 is configured to encode the first sending data sent by the medium access control layer MAC to obtain first encoded data, and send the first encoded data to the asynchronous conversion unit 1012;

[0065] The asynchronous conversion unit 1012 is configured to convert the first encoded data through bit width conversion and clock domain conversion to obtain second sending data, and send the second sending data to the physical medium adaptation layer PMA.

[0066] In some embodiments, in the application scenario of low-speed transmission interconnection, the conversion module 101 of the physical coding sublayer PCS in the data transmission system of the sending end can include an encoding unit 1011 and an asynchronous conversion unit 1012, and the encoding unit 1011 and the asynchronous conversion unit 1012 are electrically connected. The media access control layer MAC of the data transmission system is used to distribute packet control characters and ordered sets and electrical idle packets to each channel. In this embodiment, the first sending data can include packet control characters and ordered sets and electrical idle packets, etc. The electrical idle packet refers to an electrical idle ordered set or an electrical idle sequence. The electrical idle packet is not a true "packet", but a physical layer control symbol sequence, which is used to indicate that the physical layer link enters a low-power idle state.

[0067] In addition, the maximum parallel data bit width processed by the digital circuit of the physical media adaptation layer PMA during transmission and reception is 16, and the built-in test loop of the physical media adaptation layer PMA and the physical coding sublayer PCS also adopts 16-bit width, so that the built-in test loop and the data bit width of the receiving and transmitting circuits are matched.

[0068] In some embodiments, the encoding unit 1011 is configured to encode the first sending data sent by the media access control layer MAC. The encoding manner of the encoding unit 1011 can be determined according to the data transmission rate in the specific application scenario. For example, the encoding unit 1011 can be configured to have a 32-bit input interface. The 32-bit input interface of the encoding unit 1011 is electrically connected to the 32-bit output interface of the sending module in the media access control layer MAC, so that the encoding unit 1011 can receive the 32-bit first sending data sent by the media access control layer MAC.

[0069] Specifically, in the chip interconnection link with a PCIe transmission rate of 2.5 gigabits per second (Gbps), the encoding manner adopts 8 / 10 encoding, that is, 8-bit valid data is encoded and transmitted per 10 bits. This is only an example and the embodiments of the present application are not limited thereto.

[0070] Optionally, the encoding unit 1011 includes a first encoder, and the first encoder is electrically connected to the asynchronous conversion unit 1012.

[0071] The first encoder is configured to obtain 10-bit encoded data from each 8-bit valid data in the first sending data, obtain first encoded data, and send the first encoded data to the asynchronous conversion unit 1012.

[0072] In some embodiments, the first encoder is an 8 / 10 encoder, i.e., the first encoder adopts an 8 / 10 encoding mode, and specifically, the first encoder encodes each 8-bit valid data in the first sending data into 10-bit encoded data, for example, 32-bit first sending data is encoded by the first encoder to obtain 40-bit first encoded data. In this way, the data transmission system of the sending end can be applied to an interconnection application scenario that adopts an 8 / 10 encoding mode, for example, a chip interconnection link that adopts a Gen1 and Gen2 transmission rate of PCIe, to solve the transmission delay problem in these interconnection application scenarios and improve the data transmission efficiency.

[0073] In this case, the first encoder can be built by a combination of logic circuits, 8-bit valid data is divided into high 3 bits and low 5 bits, the low 5 bits are converted into 6-bit code words, and the high 3 bits are converted into 4-bit code words, and finally the 6-bit and 4-bit results are spliced into 10-bit encoded data. Alternatively, the first encoder can directly implement polynomial operations using an XOR gate and a register to generate redundant bits and append them to the 8-bit valid data to form 10-bit encoded data. This is only an example, and the embodiments of the present application are not limited in this regard.

[0074] In some embodiments, the asynchronous conversion unit 1012 is configured to perform bit width conversion and clock domain conversion on the first encoded data output by the encoding unit 1011, on the one hand, to convert the data bit width of the first encoded data into the input interface bit width of the physical media attachment (PMA), and on the other hand, to convert the first encoded data from the clock domain corresponding to the encoding unit 1011 into the receiving clock domain corresponding to the physical media attachment (PMA), so that the clock domain of the finally obtained second sending data is consistent with the receiving clock domain of the physical media attachment (PMA).

[0075] For example, the asynchronous conversion unit 1012 can be configured to have a 16-bit output interface, and the 16-bit output interface of the asynchronous conversion unit 1012 can be electrically connected to the 16-bit input interface of the sending module in the physical media attachment (PMA), so that the asynchronous conversion unit 1012 can send the 16-bit second sending data obtained by conversion to the physical media attachment (PMA).

[0076] In this case, the sending clock domain of the physical coding sublayer (PCS) and the receiving clock domain of the physical media attachment (PMA) can be matched, and the asynchronous conversion unit 1012 can convert the first encoded data to the sending clock domain of the physical coding sublayer (PCS).

[0077] Optionally, the asynchronous conversion unit 1012 includes an asynchronous immediate first-in-first-out buffer (Async_IMM_FIFO), and the asynchronous immediate first-in-first-out buffer (Async_IMM_FIFO) is electrically connected to the encoding unit 1011.

[0078] The asynchronous immediate first-in-first-out buffer Async_IMM_FIFO is configured to convert the first encoded data into second encoded data, convert a clock domain of the second encoded data into a clock domain corresponding to the physical media attachment PMA, obtain second sending data, and send the second sending data to the physical media attachment PMA.

[0079] In some embodiments, the first encoded data obtained after encoding by the encoding unit 1011 usually has an increased data bit width. For example, the encoding unit 1011 uses an 8 / 10 encoder to encode the 32-bit first sending data into 40-bit first encoded data. The process of converting the first encoded data into the second sending data in the asynchronous immediate first-in-first-out buffer Async_IMM_FIFO involves cross-clock domain conversion. For example, when converting the 40-bit first encoded data into 16-bit second sending data, the clock domain is also upgraded. For example, the clock frequency corresponding to 16-bit data is higher than the clock frequency corresponding to 40-bit data. Higher clock frequency is beneficial to reduce data transmission delay and improve data transmission efficiency.

[0080] In this embodiment, the asynchronous conversion unit 1012 uses the asynchronous immediate first-in-first-out buffer Async_IMM_FIFO. The read and write clock domains of the asynchronous immediate first-in-first-out buffer Async_IMM_FIFO are asynchronous. The asynchronous immediate first-in-first-out buffer Async_IMM_FIFO is used to complete the data bit width conversion of the first encoded data in the cross-clock domain scenario. In addition, the asynchronous immediate first-in-first-out buffer Async_IMM_FIFO has the characteristics of immediate reading and writing. After data is written, it can be read immediately without waiting for synchronization delay. Therefore, the delay can be greatly reduced, and the processing efficiency of the asynchronous conversion unit 1012 can be improved.

[0081] For example, the asynchronous immediate access first-in-first-out buffer can be implemented by using a dual-port random access memory (RAM) and a Gray code counter, or can be implemented by using a register. This is only an example, and the embodiments of the present application are not limited in this regard.

[0082] In the embodiments of the present application, the encoding unit 1011 and the asynchronous conversion unit 1012 are arranged in the physical coding sublayer PCS in the sending end data transmission system. The first sending data sent by the medium access control layer MAC is encoded by the encoding unit 1011 to obtain first encoded data. Then, the asynchronous conversion unit 1012 is used to perform bit width conversion and clock domain conversion on the first encoded data to obtain second sending data. Therefore, the data transmission system can be applied to a chip interconnection link that needs to perform data encoding, the interconnection application scenarios of the data transmission system are expanded, and the versatility of the data transmission system can be improved.

[0083] Figure 3 is a structure diagram of a data transmission system of a sending end provided by an embodiment of the present application. As shown in Figure 3 , the data transmission system of the sending end is composed of a data link layer DLL, a medium access control layer MAC, a physical coding sublayer PCS and a physical medium adaptation layer PMA, and the data transmission system adopts a transmission rate of 2.5 Gbps. The physical coding sublayer PCS includes a first encoder and an asynchronous immediate first-in-first-out buffer Async_IMM_FIFO, and the first encoder is an 8 / 10 encoder.

[0084] As shown in Figure 3 , the data link layer DLL distributes 32-bit DLLP packets and TLP packets to the medium access control layer MAC. The medium access control layer MAC distributes 32-bit first sending data such as packet control characters and ordered sets and electrical idle packets to the physical coding sublayer PCS. The first encoder of the physical coding sublayer PCS receives the 32-bit first sending data and performs 8 / 10 encoding to obtain 40-bit first encoded data and send the first encoded data to the asynchronous immediate first-in-first-out buffer Async_IMM_FIFO. The asynchronous immediate first-in-first-out buffer Async_IMM_FIFO performs bit width conversion and clock domain conversion on the 40-bit first encoded data to obtain 16-bit second sending data and send the second sending data to the physical medium adaptation layer PMA. Wherein, [15:0] represents a data bit width of 16 bits, [31:0] represents a data bit width of 32 bits, and [39:0] represents a data bit width of 40 bits.

[0085] Optionally, as shown in Figure 4 , in the data transmission system of the receiving end, the locking module 201 of the physical coding sublayer PCS includes a character locking unit 2011, and the processing module 202 includes a decoding unit 2021, and the decoding unit 2021 is electrically connected with the character locking unit 2011.

[0086] The character locking unit 2011 is configured to perform character locking on the first receiving data sent by the physical medium adaptation layer PMA to determine the starting boundary of the characters in the first receiving data, obtain to-be-decoded data, convert the clock domain of the to-be-decoded data to the clock domain corresponding to the decoding unit 2021 to obtain second receiving data, and send the second receiving data to the decoding unit 2021.

[0087] The decoding unit 2021 is configured to perform decoding processing on the second receiving data to obtain third receiving data, and send the third receiving data to the medium access control layer MAC.

[0088] In some embodiments, in the application scenario of low-speed transmission interconnection, the lock module 201 of the physical coding sublayer PCS in the data transmission system of the receiving end comprises a character lock unit 2011, and the processing module 202 comprises a decoding unit 2021, which is electrically connected with the character lock unit 2011. The digital circuit of the physical media attachment layer PMA of the data transmission system can complete the clock data recovery algorithm by using 8-bit parallel data, and then perform symbol locking after locking the clock frequency and phase by the phase-locked loop, so as to realize the bit-level synchronization of the received data of the physical media attachment layer PMA, that is, to determine the boundary of a single bit (symbol) in the received data, and obtain first received data.

[0089] In the application scenario of low-speed transmission interconnection, the character lock unit 2011 can perform character locking on the first received data, so as to realize byte / word boundary synchronization, that is, to determine the starting boundary of a "character" or "word" composed of multiple bits in the first received data, and obtain to-be-decoded data. Then, the clock domain of the to-be-decoded data is converted to the clock domain corresponding to the decoding unit 2021, so as to obtain second received data, so that the clock domain of the second received data is consistent with the clock domain corresponding to the decoding unit 2021.

[0090] In some embodiments, the character lock unit 2011 can be configured to have a 16-bit input interface, and the 16-bit input interface of the character lock unit 2011 is electrically connected with the 16-bit output interface of the receiving module in the physical media attachment layer PMA, so that the character lock unit 2011 can receive the 16-bit first received data sent by the physical media attachment layer PMA.

[0091] In some embodiments, the character lock unit 2011 can be configured to have a 16-bit input interface, and the 16-bit input interface of the character lock unit 2011 is electrically connected with the 16-bit output interface of the receiving module in the physical media attachment layer PMA, so that the character lock unit 2011 can receive the 16-bit first received data sent by the physical media attachment layer PMA.

[0092] Optionally, the character lock unit 2011 comprises an asynchronous lock first-in-first-out buffer Async_Lock_FIFO, which is electrically connected with the decoding unit 2021.

[0093] The asynchronous lock first-in-first-out buffer Async_Lock_FIFO is used for performing 10-bit alignment character locking on the first received data to obtain to-be-decoded data, converting the clock domain of the to-be-decoded data to the clock domain corresponding to the decoding unit 2021 to obtain second received data, and sending the second received data to the decoding unit 2021.

[0094] In some embodiments, the data transmission system can be applied to an interconnection application scenario in which the encoding mode adopts 8 / 10 encoding, for example, a chip interconnection link adopting the Gen1 and Gen2 transmission rate of PCIe, and thus 8 / 10 decoding needs to be performed in the decoding unit 2021, and thus 10-bit alignment character locking needs to be performed on the first received data in the character locking unit 2011. For example, 10-bit alignment character locking is performed on the 16-bit first received data, so that the data stream is converted from 16-bit parallel data to 40-bit parallel data, and 40-bit to-be-decoded data is obtained.

[0095] Then, the character locking unit 2011 converts the clock domain of the to-be-decoded data to the clock domain corresponding to the decoding unit 2021, obtains second received data, and sends the second received data to the decoding unit 2021, so that 8 / 10 decoding is performed in the decoding unit 2021. For example, 8 / 10 decoding is performed on the 40-bit to-be-decoded data in the decoding unit 2021, and 32-bit third received data is obtained.

[0096] In some embodiments, the character locking unit 2011 includes an asynchronous locking first-in-first-out buffer Async_Lock_FIFO, which can safely and orderly deliver data between different clock domains, and thus the character locking and clock domain conversion of the first received data can be completed in a cross-clock-domain scenario through the asynchronous locking first-in-first-out buffer Async_Lock_FIFO, which has the advantages of fast speed and low delay, and improves the processing efficiency of the character locking unit 2011.

[0097] For example, the asynchronous locking first-in-first-out buffer Async_Lock_FIFO can be implemented by using a dual-port RAM, double pointers (read pointer / write pointer), a synchronizer chain, and a Gray code encoder. Specifically, the dual-port RAM (or register stack) is used as a storage unit, the write pointer points to the next position to be written, the read pointer points to the next position to be read, the Gray code encoder converts the double pointers into Gray codes and sends them to the synchronizer chain, and the synchronizer chain realizes clock domain synchronization. Alternatively, the asynchronous immediate access first-in-first-out buffer can be implemented by using a register. Here, only an example is given, and the embodiments of the present application are not limited in this regard.

[0098] In some embodiments, the decoding unit 2021 is configured to decode the second received data transmitted by the character locking unit 2011 to obtain third received data. The decoding manner of the decoding unit 2021 in this embodiment can be determined according to the data transmission speed in a specific application scenario. For example, the decoding unit 2021 can be configured to have a 32-bit output interface. The output interface of the decoding unit 2021 is electrically connected to a 32-bit input interface of a receiving module in a medium access control layer (MAC), so that the decoding unit 2021 can transmit 32-bit third received data to the medium access control layer (MAC).

[0099] Specifically, in a chip interconnection link with a PCIe transmission rate of 2.5 gigabits per second (Gbps), the encoding manner adopts 8 / 10 encoding. Therefore, the decoding unit 2021 of the physical coding sublayer (PCS) in the receiving end data transmission system needs to perform 8 / 10 decoding, and then transmit the decoded third received data to the medium access control layer (MAC). This is only an example, and the embodiments of the present application are not limited thereto.

[0100] Optionally, the decoding unit 2021 comprises a first decoder, and the first decoder is electrically connected to the character locking unit 2011.

[0101] The first decoder is configured to obtain 8-bit valid data from every 10-bit encoded data in the second received data to obtain the third received data, and transmit the third received data to the medium access control layer (MAC).

[0102] In some embodiments, the first decoder can be an 8 / 10 decoder, that is, the first decoder adopts an 8 / 10 decoding manner. Specifically, the first decoder obtains 8-bit valid data from every 10-bit encoded data in the second received data.

[0103] For example, the second received data is subjected to character locking and clock domain conversion in the character locking unit 2011. The data bit width of the second received data is 40 bits. After the 8 / 10 decoder decodes the 40-bit second received data, 32-bit decoded data is obtained as the 32-bit third received data in this embodiment.

[0104] In this way, the data transmission system at the receiving end can be applied to an interconnection application scenario in which the encoding manner adopts 8 / 10 encoding, such as a chip interconnection link with a PCIe Gen1 and Gen2 transmission rate. The transmission delay problem in these interconnection application scenarios can be solved, and the data transmission efficiency can be improved.

[0105] The first decoder can refer to the circuit structure of the first encoder, and is built by combining logic circuits and registers to implement the decoding logic required by the first decoder. This is only an example, and the embodiments of the present application are not limited thereto.

[0106] In this embodiment, by setting a character locking unit 2011 and a decoding unit 2021 in the Physical Coding Sublayer (PCS) of the data transmission system at the receiving end, the character locking unit 2011 can perform character locking and clock domain conversion on the first received data of the Physical Media Adaptor (PMA) to obtain the second received data. Then, the decoding unit 2021 can perform decoding processing on the second received data to obtain the third received data. This allows the data transmission system to be applied to chip interconnect links that require data decoding, expands the interconnection application scenarios of the data transmission system, and enhances the versatility of the data transmission system.

[0107] Figure 5 This is a second schematic diagram of a receiving end data transmission system provided in an embodiment of this application. For example... Figure 5 As shown, the data transmission system at the receiving end consists of a data link layer (DLL), a media access control layer (MAC), a physical coding sublayer (PCS), and a physical media adaptation layer (PMA). This data transmission system uses a transmission rate of 2.5 Gbps. The physical coding sublayer (PCS) includes an asynchronously locked first-in-first-out buffer (Async_Lock_FIFO) and a first decoder, which is an 8 / 10 decoder.

[0108] like Figure 5 As shown, the Physical Media Adaptor (PMA) layer sends 16 bits of the first received data to the Async_Lock_FIFO asynchronous lock-in-first-out (AFIFO) buffer in the Physical Coding Sublayer (PCS). The AFIFO performs 10-bit aligned character locking and clock domain conversion to obtain 40 bits of the second received data, which is then sent to the first decoder. The first decoder performs 8 / 10 decoding to obtain 32 bits of the third received data, which is then sent to the Media Access Control (MAC) layer. Here, [15:0] indicates a data width of 16 bits, and [31:0] indicates a data width of 32 bits.

[0109] In some embodiments, in the application scenario of high-speed transmission interconnection, the conversion module 101 of the physical coding sublayer PCS in the data transmission system of the sending end can be configured to have a 32-bit input interface, the 32-bit input interface of the conversion module 101 can be electrically connected with a 32-bit output interface of a sending module in the medium access control layer MAC, so that the conversion module 101 can receive 32-bit first sending data sent by the medium access control layer MAC. In addition, the conversion module 101 can be configured to have a 16-bit output interface, and the 16-bit output interface of the conversion module 101 can be electrically connected with a 16-bit input interface of a sending module in the physical media adaptation layer PMA, so that the conversion module 101 can send 16-bit second sending data obtained by conversion to the physical media adaptation layer PMA. The application scenario of high-speed transmission interconnection may, for example, be a chip interconnection link with a transmission rate of 20.0 gigabits per second (Gbps) of PCIe, which is only an example and is not limited in the embodiments of the present application.

[0110] In some embodiments, since the maximum parallel data bit width processed by the digital circuit of the physical media adaptation layer PMA in the embodiments when sending and receiving is 16, the 32-bit first sending data needs to be converted in bit width, and the clock domain conversion needs to be performed in the conversion module 101 due to the cross-clock domain. In the embodiments, the conversion module 101 performs 32-bit to 16-bit bit width conversion and clock domain conversion on the first sending data to obtain 16-bit second sending data, and sends the second sending data to the physical media adaptation layer PMA. The sending clock domain of the physical coding sublayer PCS and the receiving clock domain of the physical media adaptation layer PMA can be matched, and the conversion module 101 can convert the first sending data to the sending clock domain of the physical coding sublayer PCS to obtain 16-bit second sending data.

[0111] Optionally, in the data transmission system of the sending end, the conversion module 101 of the physical coding sublayer PCS includes a synchronous first-in-first-out buffer Sync_FIFO, which is configured to perform synchronous bit width conversion and clock domain conversion on the first sending data to obtain second sending data, and send the second sending data to the physical media adaptation layer PMA.

[0112] In some embodiments, in the application scenario of high-speed transmission interconnection, since the ratio of the data bit width of the first sending data to the data bit width of the second sending data is 2N, and the data is a power of 2, the data transmission does not need complex clock domain conversion and data bit width conversion when passing through the physical coding sublayer PCS.

[0113] The conversion module 101 can employ a synchronous first-in-first-out (FIFO) buffer (Sync_FIFO) to reduce transmission latency and improve data transmission efficiency. For example, the Sync_FIFO buffer can be implemented based on registers and read / write pointer counters, or it can be implemented using a dual-port RAM and read / write pointers. This is merely an example, and the embodiments of this application do not impose limitations.

[0114] In this embodiment, by setting a synchronous first-in-first-out buffer Sync_FIFO in the conversion module 101 of the physical coding sublayer (PCS) in the data transmission system at the transmitting end, synchronous bit width conversion and clock domain conversion are performed on the first transmitted data. This eliminates the need for complex clock domain conversion and data bit width conversion, thereby improving processing efficiency, reducing transmission latency, and thus improving data transmission efficiency.

[0115] Figure 6 This is the third schematic diagram of a data transmission system for a transmitting end provided in this application embodiment, as shown below. Figure 6 As shown, the data transmission system at the transmitting end consists of a data link layer (DLL), a media access control layer (MAC), a physical coding sublayer (PCS), and a physical media adaptation layer (PMA). This data transmission system uses a transmission rate of 20.0 Gbps. The physical coding sublayer (PCS) includes a synchronization first-in-first-out (FIFO) buffer (Sync_FIFO).

[0116] like Figure 6 As shown, the data link layer (DLL) distributes 32-bit DLLP packets and TLP packets to the media access control layer (MAC). The MAC then distributes the packet control character, ordered set, and electrical idler packet (32-bit first transmission data) to the physical coding sublayer (PCS). The PCS's synchronization first-in-first-out buffer (Sync_FIFO) receives the 32-bit first transmission data and performs bit-width and clock domain conversion to obtain 16-bit second transmission data, which is then sent to the physical media adapter layer (PMA). Here, [15:0] indicates a data width of 16 bits, and [31:0] indicates a data width of 32 bits.

[0117] Optionally, such as Figure 7 As shown, in the data transmission system at the receiving end, the locking module 201 of the physical coding sublayer PCS includes a block locking unit 2012, and the processing module 202 includes a clock compensation unit 2022. The clock compensation unit 2022 is electrically connected to the block locking unit 2012.

[0118] The block locking unit 2012 is used to perform block locking on the first received data sent by the Media Access Control (MAC) layer to determine the starting boundary of the data block in the first received data, obtain the second received data, and send the second received data to the clock compensation unit 2022.

[0119] The clock compensation unit 2022 is configured to perform clock frequency compensation on the second received data to obtain third received data, and send the third received data to a medium access control layer (MAC).

[0120] In some embodiments, in a high-speed transmission interconnection application scenario, the lock module 201 of the physical coding sublayer (PCS) of the data transmission system at the receiving end includes a block lock unit 2012, the processing module 202 includes a clock compensation unit 2022, and the clock compensation unit 2022 is electrically connected to the block lock unit 2012. The digital circuit of the physical medium attachment (PMA) layer of the data transmission system can complete a clock data recovery algorithm using 8-bit parallel data, and perform symbol locking after locking the clock frequency and phase using a phase-locked loop, to achieve bit-level synchronization of the received data of the PMA, that is, to determine the boundary of a single bit (symbol) in the received data, to obtain first received data. For example, the high-speed transmission interconnection application scenario uses a chip interconnection link with a transmission rate of 20.0 Gbps according to PCIe, which is only an example and is not limited in the embodiments of the present application.

[0121] In some embodiments, the block lock unit 2012 can be configured to have a 16-bit input interface, and the 16-bit input interface of the block lock unit 2012 is electrically connected to a 16-bit output interface of a receiving module in the PMA, so that the block lock unit 2012 can receive the 16-bit first received data sent by the PMA. The block lock of the 16-bit first received data is performed on the basis of the symbol lock of the PMA, that is, the symbol clock is recovered to ensure the accuracy of the sampling point through the symbol lock of the PMA, and then the block lock is performed in the block lock unit 2012 of the PCS.

[0122] Optionally, the block lock unit 2012 includes a block lock buffer Block_Lock_Buffer, and the block lock buffer Block_Lock_Buffer is electrically connected to the clock compensation unit 2022.

[0123] The block lock buffer Block_Lock_Buffer is configured to perform block alignment on the first received data to obtain block data, and send the block data to the clock compensation unit 2022 as second received data.

[0124] In some embodiments, the block lock unit 2012 includes a block lock buffer Block_Lock_Buffer. Block lock refers to data block level synchronization of the first received data, that is, identifying the start boundary of the data block in the first received data to achieve block alignment, such as identifying the frame header, synchronization word, frame tail, etc. of the data block, preventing the receiving end from causing data parsing errors due to boundary misalignment, and improving the accuracy of data transmission.

[0125] In some embodiments, the block lock buffer Block_Lock_Buffer identifies the start boundary of the data block in the first received data, and achieves block alignment through data buffering and realignment. The block lock buffer Block_Lock_Buffer can cache the input data until a valid block boundary is detected, and recombine the first received data into a boundary-aligned output block, thereby converting the first received data into block data, referred to as second received data in this embodiment. The block lock buffer Block_Lock_Buffer sends the second received data to the clock compensation unit 2022, where clock frequency compensation is performed.

[0126] For example, the block lock buffer Block_Lock_Buffer can be implemented using a shift register and a sliding window detector, or the block lock buffer Block_Lock_Buffer can be implemented using a dual-port RAM and a dynamic pointer. This is only an example and the embodiments of the present application are not limited in this regard.

[0127] In some embodiments, the clock compensation unit 2022 can compensate the clock frequency of the second received data based on the clock skew compensation ordered set, eliminate the clock frequency skew of the second received data, and make the clock domain of the obtained third received data match the clock domain corresponding to the medium access control layer MAC.

[0128] For example, the clock skew compensation ordered set can be a SKIP ordered set (SKIP Ordered Set). The SKIP ordered set is a special data packet structure used for clock skew compensation in the PCIe protocol, and its main function is to solve the data transmission error problem caused by the clock frequency inconsistency between the sending end and the receiving end. This is only an example and the embodiments of the present application are not limited in this regard.

[0129] In some embodiments, the clock compensation unit 2022 can be configured to have a 32-bit input interface and a 32-bit output interface, the 32-bit input interface of the clock compensation unit 2022 is electrically connected to the 32-bit output interface of the block locking unit 2012, and the 32-bit output interface of the clock compensation unit 2022 is electrically connected to the 32-bit input interface of the receiving module in the medium access control layer MAC, so that the clock compensation unit 2022 can receive the 32-bit second receiving data sent by the block locking unit 2012, complete the clock frequency compensation conversion of the second receiving data to obtain 32-bit third receiving data, and then send the third receiving data to the medium access control layer MAC.

[0130] Optionally, the clock compensation unit 2022 includes an elastic buffer Elastic_Buffer, which is electrically connected to the block locking unit 2012.

[0131] The elastic buffer Elastic_Buffer is configured to compensate the second receiving data based on the clock skew compensation ordered set to obtain third receiving data, and send the third receiving data to the medium access control layer MAC.

[0132] In some embodiments, the clock compensation unit 2022 includes an elastic buffer Elastic_Buffer. The elastic buffer Elastic_Buffer can realize clock domain conversion by transferring data from the clock domain of the sending end to the clock domain of the receiving end, and can also compensate for the slight frequency deviation between the reference clock of the sending end and the reference clock of the receiving end to realize frequency compensation.

[0133] In some embodiments, the elastic buffer Elastic_Buffer is configured to compensate the second receiving data based on the clock skew compensation ordered set to obtain third receiving data, which can reduce the transmission delay. For example, the elastic buffer Elastic_Buffer can complete the clock frequency compensation by using the SKIP ordered set, which is a special control symbol defined by the protocol, such as COM-SKP-SKP-SKP in PCIe. The elastic buffer Elastic_Buffer can realize clock frequency compensation by dynamically inserting or deleting SKP symbols.

[0134] For example, the elastic buffer Elastic_Buffer can be implemented by using a dual-port RAM, or the elastic buffer Elastic_Buffer can be implemented by using a shift register and a multiplexer (MUX). Here, only an example is given, and the embodiments of the present application are not limited in this regard.

[0135] In this embodiment, by setting a block locking unit 2012 and a clock compensation unit 2022 in the Physical Coding Sublayer (PCS) of the data transmission system at the receiving end, the block locking unit 2012 can perform block locking on the first received data sent by the Media Access Control (MAC) layer to determine the starting boundary of the data block in the first received data. The resulting second received data is then sent to the clock compensation unit 2022, which performs clock frequency compensation on the second received data and sends the resulting third received data to the MAC layer. This improves the accuracy of data transmission, reduces transmission latency, and thus increases data transmission efficiency.

[0136] Figure 8 This is the fourth schematic diagram of a receiving end data transmission system provided in the embodiments of this application, as shown below. Figure 8 As shown, the data transmission system at the receiving end consists of a data link layer (DLL), a media access control layer (MAC), a physical coding sublayer (PCS), and a physical media adaptation layer (PMA). This data transmission system uses a transmission rate of 20.0 Gbps. The physical coding sublayer (PCS) includes a block-locked buffer (Block_Lock_Buffer) and an elastic buffer (Elastic_Buffer).

[0137] like Figure 8 As shown, the Physical Media Adaptor (PMA) layer sends the 16-bit first received data to the Block Lock Buffer (Block_Lock_Buffer) in the Physical Coding Sublayer (PCS). Block alignment is performed in the Block Lock Buffer to obtain the 32-bit second received data, which is then sent to the Elastic Buffer. Clock frequency compensation is performed in the Elastic Buffer to obtain the 32-bit third received data, which is then sent to the Media Access Control (MAC) layer. Here, [31:0] indicates a data width of 32 bits, and [15:0] indicates a data width of 16 bits.

[0138] In the related art, in the scenario of a chip interconnection link, a chip interconnection technology based on NVLink can be used for long-distance interconnection between GPUs (Graphics Processing Units), and can be used for PCB (Printed Circuit Board) integration, MCM (Multi Chip Module) integration, and wafer-level integration. However, in the first to third generations of NVLink, the electrical interface of the physical layer only supports the NVLink standard, and the fourth generation of NVLink-c2c is compatible with the electrical interfaces of Ethernet and IB. For a CPU (Central Processing Unit) that does not support the electrical standard of the NVLink interface, a PCIe interface needs to be used to implement interconnection with the GPU, which makes the data transmission speed between the CPU and the GPU a performance bottleneck.

[0139] Optionally, in the data transmission system at the sending end, the physical media adaptation layer PMA includes a first physical layer interface, and in the data transmission system at the receiving end, the physical media adaptation layer PMA includes a second physical layer interface, and the first physical layer interface and the second physical layer interface are compatible with the high-speed serial computer expansion bus standard.

[0140] The data transmission system provided by the embodiments of the present application can be compatible with the PCIe interface of the high-speed serial computer expansion bus standard. Specifically, in the data transmission system at the sending end, the physical media adaptation layer PMA includes a first physical layer interface, and the first physical layer interface is compatible with the high-speed serial computer expansion bus standard, that is, the first physical layer interface can be a PIPE (Physical Interface for PCI Express) interface. Similarly, in the data transmission system at the receiving end, the physical media adaptation layer PMA includes a second physical layer interface, and the second physical layer interface is compatible with the high-speed serial computer expansion bus standard, that is, the second physical layer interface can be a PIPE interface.

[0141] In this way, the data transmission system provided by the embodiments of the present application can be applied to a PCIe chip interconnection link, for example, applied to data transmission between a CPU and a GPU, and can reduce transmission delay while being compatible with the PCIe interface, has higher data transmission efficiency compared with a traditional PCIe sending end and receiving end interface, and has stronger universality compared with a chip interconnection technology based on NVLink.

[0142] The embodiment of the present application realizes the delay reduction of the clock domain conversion and the data bit width conversion between the link layer and the physical layer by improving the overall architecture of the data transmission system of the sending end and the receiving end. In the electrically friendly and good signal transmission quality package internal interconnection environment, the interconnection link training and establishment process can be directly performed at a high clock frequency, the transmission delay of the link can be reduced, and the data transmission efficiency can be improved.

[0143] The embodiment of the present application provides a chip, which comprises the data transmission system of the foregoing embodiment.

[0144] The chip has the same advantages as the data transmission system of the foregoing embodiment in the related art, which will not be described here.

[0145] The embodiment of the present application provides an electronic device, which comprises the chip of the foregoing embodiment.

[0146] The electronic device has the same advantages as the data transmission system of the foregoing embodiment in the related art, which will not be described here.

[0147] It should be noted that, in this document, the term "comprising" or "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes the elements inherent to such process, method, article or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of another identical element in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the method and device in the embodiment of the present application is not limited to the order of performing the functions shown or discussed, but can also include performing the functions in a substantially simultaneous manner or in a reverse order, for example, the described method can be performed in an order different from that described, and various steps can also be added, omitted or combined. In addition, the features described with reference to certain examples can be combined in other examples.

[0148] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above-described specific embodiments, and the above-described specific embodiments are only illustrative, not limiting, and those skilled in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope protected by the claims.

Claims

1. A data transmission system, characterized by The data transmission system comprises a medium access control layer, a physical coding sublayer and a physical medium adaptation layer; In the data transmission system at the sending end, the physical coding sublayer comprises a conversion module; the conversion module is configured to perform bit width conversion and clock domain conversion on first sending data sent by the medium access control layer to obtain second sending data, and send the second sending data to the physical medium adaptation layer; wherein a ratio of a data bit width of the first sending data to a data bit width of the second sending data is 2N, N being a positive integer; In the data transmission system at the receiving end, the physical coding sublayer comprises a locking module and a processing module electrically connected; the locking module is configured to perform data locking on first receiving data sent by the physical medium adaptation layer to determine a starting boundary of a character or a data block in the first receiving data, to obtain second receiving data, and send the second receiving data to the processing module; the processing module is configured to process the second receiving data into third receiving data, and send the third receiving data to the medium access control layer; wherein a ratio of a data bit width of the third receiving data to a data bit width of the first receiving data is 2N.

2. The data transmission system of claim 1, wherein, In the data transmission system at the sending end, the conversion module of the physical coding sublayer comprises an encoding unit and an asynchronous conversion unit electrically connected; The encoding unit is configured to encode the first sending data sent by the medium access control layer to obtain first encoded data, and send the first encoded data to the asynchronous conversion unit; The asynchronous conversion unit is configured to perform bit width conversion and clock domain conversion on the first encoded data to obtain the second sending data, and send the second sending data to the physical medium adaptation layer.

3. The data transmission system of claim 2, wherein, The asynchronous conversion unit comprises an asynchronous immediate first-in-first-out buffer electrically connected with the encoding unit; The asynchronous immediate first-in-first-out buffer is configured to convert the first encoded data into second encoded data, convert a clock domain of the second encoded data to a clock domain corresponding to the physical medium adaptation layer to obtain the second sending data, and send the second sending data to the physical medium adaptation layer.

4. The data transmission system of claim 2, wherein, The encoding unit comprises a first encoder electrically connected with the asynchronous conversion unit; The first encoder is configured to obtain 10-bit encoded data from every 8-bit valid data in the first sending data to obtain the first encoded data, and send the first encoded data to the asynchronous conversion unit.

5. The data transmission system according to any of claims 1-4, characterized in that, In the data transmission system at the receiving end, the locking module of the physical coding sublayer comprises a character locking unit, and the processing module comprises a decoding unit electrically connected with the character locking unit; The character locking unit is configured to perform character locking on the first received data transmitted by the physical medium adaptation layer, to determine the starting boundary of the character in the first received data, to obtain to-be-decoded data, to convert the clock domain of the to-be-decoded data to the clock domain corresponding to the decoding unit, to obtain the second received data, and to transmit the second received data to the decoding unit. The decoding unit is configured to perform decoding processing on the second received data, to obtain the third received data, and to transmit the third received data to the medium access control layer.

6. The data transmission system of claim 5, wherein, The character locking unit comprises an asynchronous locking first-in-first-out buffer, which is electrically connected to the decoding unit. The asynchronous locking first-in-first-out buffer is configured to perform 10-bit alignment character locking on the first received data, to obtain the to-be-decoded data, to convert the clock domain of the to-be-decoded data to the clock domain corresponding to the decoding unit, to obtain the second received data, and to transmit the second received data to the decoding unit.

7. The data transmission system of claim 5, wherein, The decoding unit comprises a first decoder, which is electrically connected to the character locking unit. The first decoder is configured to obtain 8-bit valid data from each 10-bit encoded data in the second received data, to obtain the third received data, and to transmit the third received data to the medium access control layer.

8. The data transmission system of claim 1, wherein, In the data transmission system of the sending end, the conversion module of the physical coding sublayer comprises a synchronous first-in-first-out buffer, which is configured to perform synchronous bit width conversion and clock domain conversion on the first transmitted data, to obtain the second transmitted data, and to transmit the second transmitted data to the physical medium adaptation layer.

9. The data transmission system of claim 1 or 8, wherein In the data transmission system of the receiving end, the locking module of the physical coding sublayer comprises a block locking unit, and the processing module comprises a clock compensation unit, which is electrically connected to the block locking unit. The block locking unit is configured to perform block locking on the first received data transmitted by the medium access control layer, to determine the starting boundary of the data block in the first received data, to obtain the second received data, and to transmit the second received data to the clock compensation unit. The clock compensation unit is configured to perform clock frequency compensation on the second received data, to obtain the third received data, and to transmit the third received data to the medium access control layer.

10. The data transmission system of claim 9, wherein, The block locking unit comprises a block locking buffer, which is electrically connected to the clock compensation unit. The block locking buffer is configured to perform block alignment on the first received data, to obtain block data, and to transmit the block data as the second received data to the clock compensation unit.

11. The data transmission system of claim 9, wherein, The clock compensation unit comprises an elastic buffer, which is electrically connected to the block locking unit. The elastic buffer is configured to perform clock frequency compensation on the second received data based on clock deviation compensation of an in-order set, to obtain the third received data, and to transmit the third received data to the medium access control layer.

12. The data transmission system of claim 1, wherein, In the data transmission system at the sending end, the physical medium attachment layer comprises a first physical layer interface, and in the data transmission system at the receiving end, the physical medium attachment layer comprises a second physical layer interface, the first physical layer interface and the second physical layer interface being compatible with the high-speed serial computer expansion bus standard.

13. A chip, characterized by The chip comprises the data transmission system according to any one of claims 1-12.

14. An electronic device, comprising: The electronic device comprises the chip according to claim 13.

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