Method and system for virtual-real combination simulation verification of CPU and FPGA
By combining CPU simulation models with FPGA acceleration hardware, the problems of low simulation verification efficiency and poor consistency in existing technologies are solved, achieving efficient and accurate simulation verification, reducing the risk of FPGA code rewriting, and shortening the delivery cycle.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- VISION MICROSYST (SHANGHAI) CO LTD
- Filing Date
- 2025-11-07
- Publication Date
- 2026-06-02
AI Technical Summary
In existing technologies, simulation verification methods for CPU+FPGA heterogeneous architectures are inefficient and prone to errors, making it difficult to guarantee the functional consistency between the model and the source code, resulting in reduced credibility of simulation results and increased integration risks.
By creating a CPU simulation model and loading a binary executable file, FPGA code is deployed using FPGA-accelerated hardware. Connection relationships are dynamically configured and call interfaces are converted into network interfaces to match the running speed for simulation verification.
It improves the efficiency and reliability of simulation verification, reduces the risk of FPGA code rewriting, shortens the delivery cycle, and ensures the accuracy and consistency of simulation results.
Smart Images
Figure CN121072425B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of hardware simulation and collaborative verification technology, specifically relating to a method and system for virtual-real combined simulation verification of CPU and FPGA. Background Technology
[0002] In embedded system design, the heterogeneous architecture of "CPU+FPGA" has become a common choice to meet the demands of high-performance computing. Corresponding simulation and verification techniques are crucial. Currently, simulation of this architecture typically employs software simulation of FPGA logic, including manually writing C / C++ models or converting existing FPGA code to C / C++. However, when the FPGA logic becomes complex, these methods reveal significant shortcomings: manual conversion is labor-intensive and prone to introducing errors during the conversion process, leading to inconsistencies between the software model and the original hardware design, severely limiting the efficiency and reliability of verification.
[0003] Therefore, the core problems faced by existing technologies are: firstly, manual conversion is inefficient and prone to errors, becoming a bottleneck in the development process; secondly, it is difficult to guarantee the functional consistency between the model and the source code, which reduces the credibility of simulation results and introduces integration risks. These problems together result in the current verification methods being insufficient in both accuracy and efficiency, and there is an urgent need for a solution that can automatically and accurately realize the docking of FPGA hardware logic to software models.
[0004] Patent document CN120529032A discloses a real-time video processing system based on Anlu FPGA. This system includes an SD card, an Anlu FPGA board, and an HDMI display. The SD card stores raw video data in Bayer format. The Anlu FPGA board includes an FPGA side and an ARM side. The FPGA side includes an SD card read / write control module, an image buffer FIFO module, a Bayer to RGB converter module, a 7-in-1 image processing module, an SDRAM read / write control module, and an HDMI display control module. The connections between these modules are as follows: the first four modules are connected sequentially; the SDRAM read / write control module is connected to the Bayer to RGB converter module, the 7-in-1 image processing module, and the HDMI display control module, respectively. The ARM side includes a Cortex... M0 processor core, AHBLite The interconnect data bus and peripheral interfaces are sequentially connected between modules; the Anlu FPGA board performs all video processing functions; and the processed video is output to the HDMI display. This solution offers good video processing performance, low resource consumption, high flexibility, strong stability, low hardware cost, and 100% domestically produced hardware. However, it does not reduce the risk of problems introduced by code rewriting, nor does it improve simulation verification efficiency or shorten the delivery cycle.
[0005] This technical problem urgently needs to be solved. Summary of the Invention
[0006] To address the shortcomings of existing technologies, the purpose of this invention is to provide a method and system for virtual-real combined simulation verification of CPU and FPGA.
[0007] A CPU and FPGA virtual-real combined simulation verification method provided by the present invention includes:
[0008] S1: Create a CPU simulation model and load the CPU-side binary executable file;
[0009] Step S2: Based on the CPU simulation model, deploy FPGA code using FPGA acceleration hardware;
[0010] Step S3: Dynamically configure the connection relationship and connection interface between the CPU simulation model and the FPGA hardware, and convert the FPGA code calling interface into network interface for sending and receiving.
[0011] Step S4: Match the CPU simulation model with the running speed of the FPGA acceleration hardware, and then run the external test equipment to obtain the test results.
[0012] Preferably, the FPGA acceleration hardware is an FPGA acceleration server; the FPGA acceleration server includes an FPGA array acceleration board; the FPGA array acceleration board includes a VU13P core board;
[0013] The FPGA array acceleration board is connected to a physical standalone machine;
[0014] The external interfaces of the FPGA acceleration server include PXIE, GTH, LVDS, GPIO, and SMA.
[0015] The FPGA acceleration server converts network protocol packets into protocols within the physical standalone machine; the protocols within the physical standalone machine include: GTH, LVDS, and EMIF;
[0016] In step S2, FPGA code is deployed using an FPGA array acceleration board.
[0017] Preferably, the interface between the CPU simulation model and the FPGA acceleration server is an Ethernet interface, and it is connected to a 10 Gigabit Ethernet network; the external interface of the physical unit is an SMA intermediate frequency signal; the digital terminal of the physical unit is an AD / DA digital timing interface, which is connected to the Ethernet interface of the FPGA acceleration server through an LVDS digital timing interface.
[0018] Preferably, in step S3, the network interface is an Ethernet interface; the Ethernet interface is converted by the FPGA acceleration hardware into a timing interface corresponding to the physical unit; the timing interface of the physical unit is determined according to the internal protocol of the physical unit, i.e., dynamically configured; the timing interface includes an LVDS timing interface.
[0019] Preferably, in step S4, the CPU simulation model and the FPGA acceleration hardware are synchronized using the clock signal provided by DDS.
[0020] A CPU and FPGA virtual-real combined simulation verification system according to the present invention includes:
[0021] Module M1: Creates a CPU simulation model and loads the CPU-side binary file;
[0022] Module M2: Based on the CPU simulation model, FPGA code is deployed through FPGA acceleration hardware.
[0023] Module M3: Dynamically configures the connection relationship and interface between the CPU simulation model and the FPGA hardware, and converts the FPGA code calling interface into network interface for sending and receiving.
[0024] Module M4: Matches the CPU simulation model with the running speed of the FPGA acceleration hardware, and then runs external test equipment to obtain test results.
[0025] Preferably, the FPGA acceleration hardware is an FPGA acceleration server; the FPGA acceleration server includes an FPGA array acceleration board; the FPGA array acceleration board includes a VU13P core board;
[0026] The FPGA array acceleration board is connected to a physical standalone machine;
[0027] The external interfaces of the FPGA acceleration server include PXIE, GTH, LVDS, GPIO, and SMA.
[0028] The FPGA acceleration server converts network protocol packets into protocols within the physical standalone machine; the protocols within the physical standalone machine include: GTH, LVDS, and EMIF;
[0029] In module M2, FPGA code is deployed via an FPGA array acceleration board.
[0030] Preferably, the interface between the CPU simulation model and the FPGA acceleration server is an Ethernet interface, and it is connected to a 10 Gigabit Ethernet network; the external interface of the physical unit is an SMA intermediate frequency signal; the digital terminal of the physical unit is an AD / DA digital timing interface, which is connected to the Ethernet interface of the FPGA acceleration server through an LVDS digital timing interface.
[0031] Preferably, in module M3, the network interface is an Ethernet interface; the Ethernet interface is converted by the FPGA acceleration hardware into a timing interface corresponding to the physical unit; the timing interface of the physical unit is determined according to the internal protocol of the physical unit, i.e., dynamically configured; the timing interface includes an LVDS timing interface.
[0032] Preferably, in module M4, the CPU simulation model and the FPGA acceleration hardware are synchronized using a clock signal provided by DDS.
[0033] Compared with the prior art, the present invention has the following beneficial effects:
[0034] 1. This invention uses digital simulation CPU technology to ensure that the binary program running on the CPU is directly loaded, ensuring that the CPU side is consistent with the real hardware, saving hardware costs, and allowing development and debugging to be carried out before the real hardware is available, thus improving delivery efficiency.
[0035] 2. This invention uses general-purpose FPGA acceleration hardware to directly load FPGA code, which reduces the risk of functional deviation caused by FPGA code rewriting, reduces the time and manpower consumption of FPGA code rewriting, shortens the verification cycle, and improves delivery efficiency.
[0036] 3. This invention ensures relatively consistent simulation timing through hardware and software coordinated adjustment and data caching technology, improves the credibility and correctness of joint verification, and effectively supports the simulation and deduction of the system. Attached Figure Description
[0037] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:
[0038] Figure 1 This is a schematic diagram of the system structure provided by the present invention;
[0039] Figure 2 This is a schematic diagram of the FPGA acceleration hardware structure provided by the present invention;
[0040] Figure 3 This is a schematic diagram illustrating the usage process of the present invention. Detailed Implementation
[0041] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.
[0042] For CPU+FPGA simulation scenarios, digital CPU modeling is currently the most common approach, implemented through manual coding or by converting FPGA code into C / C++ code. However, for complex FPGA logic functions, rewriting this code is labor-intensive and cannot guarantee the consistency of the rewritten code's functionality.
[0043] Using a CPU and FPGA virtual-real simulation verification system can effectively solve this problem. It uses a digital CPU to load the CPU binary program and a general-purpose FPGA hardware acceleration device to directly load the FPGA, maintaining consistency between the CPU and FPGA sides with the hardware. This reduces the risk of problems introduced by code rewriting, improves the credibility of test verification, reduces the coding and functional test verification time of FPGA to C / C++, improves simulation verification efficiency, and shortens the delivery cycle.
[0044] A CPU and FPGA virtual-real combined simulation verification method provided by the present invention includes:
[0045] Step 1: Use a domestically developed digital simulation platform to model the hardware board system on the CPU side and directly load the CPU-side binary executable file.
[0046] Specifically, step 1 includes the following steps:
[0047] Step 1.1: Based on the actual CPU hardware board structure diagram, select the corresponding instruction set, SOC target board, and peripheral interfaces through a graphical digital simulation environment platform to complete the digital CPU construction;
[0048] Step 1.2: Based on the hardware operating parameters, set the corresponding operating configuration parameters in the digital simulation component;
[0049] Step 1.3: Load the CPU-side binary executable file to the specified path and switch to operation mode, waiting for the execution control command.
[0050] The loading of the CPU-side binary executable file simulates the user object code program running on the CPU. The purpose of this operation is to make the simulation consistent with the real hardware.
[0051] Step 2: Use general-purpose FPGA acceleration hardware, i.e., FPGA acceleration hardware, to complete the deployment of FPGA code.
[0052] Step 2 includes the following steps:
[0053] Step 2.1: General-purpose FPGA acceleration hardware. The basic main chip adopts the VU13P ultra-large scale FPGA. Multiple VU13P are used as the basic chips to form FPGA array acceleration boards. Several FPGA array acceleration boards form a general-purpose FPGA acceleration server. The external interface of the general-purpose FPGA acceleration server is 10 Gigabit Ethernet, which can be connected to other standard server networks.
[0054] Step 2.2: The external interface is a 10 Gigabit Ethernet, which can interact with other servers. The internal interface can be flexibly configured by the FPGA logic to convert the 10 Gigabit Ethernet interface into an internal interface.
[0055] Step 2.3: Use the DDS protocol to interact with the digital CPU using network transmission protocol packets. General-purpose FPGA acceleration hardware can flexibly convert network protocol packets.
[0056] Step 2.4: The FPGA converts the received network protocol packets into its own internal protocols, such as GTH, LVDS, EMIF, etc.
[0057] Specifically, step 2.4 includes the following steps:
[0058] Step 2.4.1: The external interfaces of the general FPGA acceleration hardware include Ethernet, PXIE, GTH, LVDS, GPIO and SMA.
[0059] Step 2.4.2: Provide a network interface that can be connected to the server network port of the CPU simulation system to enable communication with other servers.
[0060] Step 2.4.3: Provide a PXIE interface for connection to a general-purpose FPGA acceleration hardware chassis baseboard, enabling communication or cascading with other boards; provide a GTH interface for communication with other standalone and general-purpose FPGA boards; provide an LVDS interface for communication with other standalone and general-purpose FPGA boards; provide a GPIO interface for communication with other standalone and general-purpose FPGA boards; and provide an SMA interface, reserved for connection to intermediate frequency signals, which can be connected to physical devices.
[0061] Step 2.5: Select the appropriate number of FPGA boards to complete the deployment of the FPGA code;
[0062] Step 2.6: The interface between the general-purpose FPGA acceleration hardware and the digital CPU simulation system is designed as an Ethernet interface, using the DDS protocol to directly connect to different digital CPU simulation systems. The external interface of the physical unit is the SMA intermediate frequency signal, and its digital end is the AD / DA digital timing signal. It connects to the physical unit FPGA through the LVDS digital timing interface, requiring conversion between the Ethernet interface and the LVDS interface.
[0063] Step 3: Referring to the actual hardware connection relationship between the CPU and FPGA, use the FPGA connection configuration software to convert the FPGA code call interface into a network interface for sending and receiving.
[0064] Step 3 includes the following steps:
[0065] Step 3.1: Referring to the actual hardware connection relationship between the CPU and FPGA, open the FPGA connection configuration software to complete the dynamic connection configuration of FPGA to FPGA and FPGA to CPU, which is converted into a network interface; that is, flexibly configure the communication interface between the CPU and FPGA according to the actual hardware connection, so as to facilitate the reuse of different hardware configurations.
[0066] Specifically, FPGA connection configuration software provides multiple connection configurations that can dynamically adjust the connections between FPGA simulation hardware and between FPGA simulation hardware and CPU based on connection interfaces and connection relationships, so that a single FPGA hardware can simulate user scenarios with multiple connection forms.
[0067] Step 3.2: The built-in interface conversion program can complete the conversion from interface data to network data according to the configuration;
[0068] Step 3.3: The general-purpose FPGA acceleration hardware sets a corresponding equal-multiplier reduction operating frequency based on the difference between the FPGA running speed and the simulation CPU running speed, and caches the FPGA running result data to perform equivalent simulation time synchronization adjustment; specifically, the ratio between the simulation CPU running speed and the FPGA hardware simulation speed is calculated based on the ratio, and the FPGA hardware is set to run at a reduced speed to achieve a matching simulation time for the entire system.
[0069] As an example, the clock signal provided by DDS is used to match and synchronize the operating speed of the CPU simulation model and the FPGA acceleration hardware.
[0070] Step 3.4: After the data is processed by the FPGA, it is sent to the corresponding digitized CPU via DDS using the data conversion function;
[0071] Step 3.5: The general-purpose FPGA acceleration hardware is adapted to access the Ethernet interface. After interface conversion processing, it is converted into the corresponding timing interface inside the FPGA. Data interaction is performed with the standalone FPGA program deployed in the general-purpose FPGA acceleration board through this timing interface.
[0072] Step 4: Run the co-simulation control software to complete the co-simulation of the CPU-side software and the FPGA code.
[0073] Step 4 includes the following steps:
[0074] Step 4.1: Complete the operation control of the digital CPU and general-purpose FPGA acceleration hardware through the encapsulated unified control interface;
[0075] Step 4.2: Use the DDS clock synchronization mechanism to complete the timing control of the simulation collaborative operation, match the running speed of the FPGA acceleration hardware with the running speed of the digital CPU, and ensure the relative timing uniformity of the simulation operation; specifically, DDS clock refers to receiving and controlling the waiting or running of the simulation object by providing synchronization signals through DDS.
[0076] Step 4.3: Run external testing equipment to complete test stimulus injection, test data monitoring, and test result analysis.
[0077] The present invention also provides a CPU and FPGA virtual-real combined simulation verification system. The CPU and FPGA virtual-real combined simulation verification system can be implemented by executing the process steps of the CPU and FPGA virtual-real combined simulation verification method. That is, those skilled in the art can understand the CPU and FPGA virtual-real combined simulation verification method as a preferred embodiment of the CPU and FPGA virtual-real combined simulation verification system.
[0078] A CPU and FPGA virtual-real combined simulation verification system according to the present invention includes:
[0079] Module M1: Creates a CPU simulation model and loads the CPU-side binary file;
[0080] Module M2: Based on the CPU simulation model, FPGA code is deployed through FPGA acceleration hardware.
[0081] Module M3: Dynamically configures the connection relationship and interface between the CPU simulation model and the FPGA hardware, and converts the FPGA code calling interface into network interface for sending and receiving.
[0082] Module M4: Matches the CPU simulation model with the running speed of the FPGA acceleration hardware, and then runs external test equipment to obtain test results.
[0083] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units of this invention function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.
[0084] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.
Claims
1. A method for virtual-real combination simulation and verification of a CPU and an FPGA, characterized in that, include: Step S1: Create a CPU simulation model and load the CPU-side binary executable file; Step S2: Based on the CPU simulation model, deploy FPGA code using FPGA acceleration hardware; Step S3: Dynamically configure the connection relationship and connection interface between the CPU simulation model and the FPGA hardware, and convert the FPGA code calling interface into network interface for sending and receiving. Step S4: Match the CPU simulation model with the running speed of the FPGA acceleration hardware, and then run the external test equipment to obtain the test results; In step S3, the network interface is an Ethernet interface; The Ethernet interface is converted into a timing interface corresponding to the physical unit by the FPGA acceleration hardware; the timing interface of the physical unit is determined according to the internal protocol of the physical unit, that is, dynamically configured; the timing interface includes the LVDS timing interface. In step S4, the CPU simulation model and the FPGA acceleration hardware are synchronized using the clock signal provided by DDS. The FPGA acceleration hardware is the FPGA acceleration server; The FPGA acceleration server includes an FPGA array acceleration board; the FPGA array acceleration board includes a VU13P core board; The FPGA array acceleration board is connected to a physical standalone machine; The external interfaces of the FPGA acceleration server include PXIE, GTH, LVDS, GPIO, and SMA. The FPGA acceleration server converts network protocol packets into protocols within the physical standalone machine; the protocols within the physical standalone machine include: GTH, LVDS, and EMIF; In step S2, FPGA code is deployed using an FPGA array acceleration board; The interface between the CPU simulation model and the FPGA acceleration server is an Ethernet interface, and it is connected to a 10 Gigabit Ethernet network. The external interface of the physical unit is an SMA intermediate frequency signal. The digital terminal of the physical unit is an AD / DA digital timing interface, which is connected to the Ethernet interface of the FPGA acceleration server through an LVDS digital timing interface.
2. A CPU and FPGA virtual-real combination simulation verification system, characterized in that, include: Module M1: Creates a CPU simulation model and loads the CPU-side binary file; Module M2: Based on the CPU simulation model, FPGA code is deployed through FPGA acceleration hardware. Module M3: Dynamically configures the connection relationship and interface between the CPU simulation model and the FPGA hardware, and converts the FPGA code calling interface into network interface for sending and receiving. Module M4: Matches the CPU simulation model with the running speed of the FPGA acceleration hardware, and then runs external test equipment to obtain test results; In module M3, the network interface is an Ethernet interface; The Ethernet interface is converted into a timing interface corresponding to the physical unit by the FPGA acceleration hardware; the timing interface of the physical unit is determined according to the internal protocol of the physical unit, that is, dynamically configured; the timing interface includes the LVDS timing interface. In module M4, the CPU simulation model and the FPGA acceleration hardware are synchronized using the clock signal provided by DDS. The FPGA acceleration hardware is the FPGA acceleration server; The FPGA acceleration server includes an FPGA array acceleration board; the FPGA array acceleration board includes a VU13P core board; The FPGA array acceleration board is connected to a physical standalone machine; The external interfaces of the FPGA acceleration server include PXIE, GTH, LVDS, GPIO, and SMA. The FPGA acceleration server converts network protocol packets into protocols within the physical standalone machine; the protocols within the physical standalone machine include: GTH, LVDS, and EMIF; In module M2, FPGA code is deployed via an FPGA array acceleration board; The interface between the CPU simulation model and the FPGA acceleration server is an Ethernet interface, and it is connected to a 10 Gigabit Ethernet network. The external interface of the physical unit is an SMA intermediate frequency signal. The digital terminal of the physical unit is an AD / DA digital timing interface, which is connected to the Ethernet interface of the FPGA acceleration server through an LVDS digital timing interface.