A design method of non-temperature-sensitive adaptive bias circuit for GaAs HBT process

Abstract

The application discloses a GaAs HBT process non-temperature-sensitive self-adaptive bias circuit design method, and relates to the technical field of analog integrated circuits.The method is based on a self-adaptive bias circuit system, which comprises a bias mirror module, a temperature compensation module and a port stabilization module.The bias mirror module is used for generating and stably providing the bias current required by the base of a main power amplifier tube HBT0.The temperature compensation module is used for compensating the base-emitter junction voltage changes caused by temperature and input power to keep the bias point stable.The port stabilization module is used for bypassing radio frequency leakage, shaping the bias port impedance and inhibiting the bias point disturbance, and the base bias current of the main power amplifier tube HBT0 is provided through the mirror branch, the mirror working point is stabilized through the port shaping, and the base-emitter junction voltage changes caused by temperature and power are offset through the potential compensation branch, so that the stability of Vbe0 and the bias current is kept in the full-temperature and full-input-power dynamic range, and the linearity and efficiency are improved.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, specifically to a non-temperature-sensitive adaptive bias circuit design method using GaAs HBT technology. Background Technology

[0002] Gallium arsenide (GaAs) substrates have lower thermal conductivity than silicon. GaAs HBT power amplifiers are prone to self-heating under high power density, causing the HBT base-emitter junction voltage Vbe to decrease with temperature and input power. This bias point drift leads to a decrease in transconductance, which in turn causes gain compression and phase distortion, resulting in overall efficiency and linearity degradation. Traditional passive voltage divider biasing cannot adaptively compensate for Vbe changes caused by self-heating and large-signal rectification, making it difficult to balance temperature drift suppression with large- and small-signal consistency.

[0003] Existing non-temperature-sensitive adaptive bias circuits exhibit bias point drift with temperature and input power, resulting in inconsistent transconductance and causing AM-AM and AM-PM distortion and efficiency degradation. Passive voltage divider bridges lack adaptive capability and cannot dynamically compensate for Vbe declines, making it difficult to maintain stable bias for the power amplifier under different operating conditions. RF leakage entering the bias branch may alter the port impedance, further amplifying temperature drift and distortion risks. Therefore, designing a non-temperature-sensitive adaptive bias circuit using GaAs HBT technology is essential. Summary of the Invention

[0004] The purpose of this invention is to provide a non-temperature-sensitive adaptive bias circuit design method for GaAs HBT process, so as to solve the problems mentioned in the background art.

[0005] To address the aforementioned technical problems, this invention provides the following technical solution: a non-temperature-sensitive adaptive bias circuit design method for GaAs HBT technology. This method is based on an adaptive bias circuit system, which includes a bias mirror module, a temperature compensation module, and a port stabilization module. The bias mirror module is used to generate and stably provide the bias current required by the base of the main power amplifier transistor HBT0. The temperature compensation module is used to equivalently compensate for the base-emitter junction voltage changes caused by temperature and input power to maintain bias point stability. The port stabilization module is used to bypass RF leakage, shape the bias port impedance, and suppress bias point disturbances.

[0006] According to the above technical solution, the bias mirroring module includes:

[0007] The reference and current limiting branches Vref and R1 are connected to the base of HBT1 via a signal to provide a mirror reference and current limiting;

[0008] The mirror drive branch HBT1, its collector and emitter are electrically connected to the bias network and output mirror current to the base of HBT0;

[0009] The ballast and shaping branch R3 is connected in series in the emitter circuit of HBT1 to limit the mirror current during temperature rise and to cooperate with port shaping.

[0010] The temperature compensation module includes:

[0011] The potential compensation branches HBT2 and HBT3 are equivalent to series diodes, which are connected across the mirror control node to achieve compensation by changing the on-potential with temperature.

[0012] The current-limiting and stabilizing branch R2 is connected to the potential compensation branches HBT2 and HBT3 to limit the operating area and stabilize the compensation amount;

[0013] The port stabilization module includes:

[0014] The RF bypass branch C1 is connected to the base of HBT1 to ground to discharge the stable RF leakage VB;

[0015] The port impedance shaping branch C2 is connected in parallel with R3 and connected to the bias port to form the target input impedance and extend the bandwidth.

[0016] According to the above technical solution, the following steps are included:

[0017] S1. Based on GaAs HBT process and power amplifier stage specifications, determine the bias current range, Vbe stability target, temperature and input power coverage range of the main amplifier HBT0, and obtain the starting parameters of mirror, compensation and ballast by calibrating the Vbe-Ib characteristics under extreme conditions through simulation and prototype.

[0018] S2. Establish reference and current limiting branches to determine R1 and generate a stable mirror bias; introduce ballast resistor R3 at the emitter of HBT1 and connect the mirror output to the base of HBT0 to form the bias main link and complete the mirror closed loop.

[0019] S3. Select HBT2, HBT3 and R2 to form a potential compensation branch and set R3 in conjunction to effectively cancel out the Vbe drift caused by temperature rise and large signal, lock the base point potential and bias current, and achieve consistency of small and large signal transconductance.

[0020] S4. Configure bypass capacitor C1 according to the device's self-tuning frequency and use C2 and R3 in parallel to shape the bias port impedance. Then perform DC+RF joint simulation and parasitic verification. If the performance does not meet the requirements, optimize R1, R2, R3, and C2 in small steps and re-verify.

[0021] S5. Verify bias stability, linearity, and broadband stability across the entire temperature and input power range. After fine-tuning the parameters, solidify the size ratios of R1, R2, R3, C1, C2, and HBT2, HBT3. Output the BOM, layout, and test specifications to form a mass production design package.

[0022] According to the above technical solution, S1 specifically refers to:

[0023] S1-1. Based on the GaAs HBT process library and power amplifier stage design goals, determine the bias current range, Vbe stability target, temperature and input power coverage range of HBT0 under small and large signals, and give the reference potential, tolerance and stability constraints of the bias network.

[0024] S1-2. Through simulation or rapid testing of prototypes, calibrate the Vbe-Ib characteristics and mirror operating point under extreme conditions of low and high temperatures and large and small signals to obtain the starting parameters for subsequent mirroring, compensation and ballasting.

[0025] According to the above technical solution, S2 specifically refers to:

[0026] S2-1. Set up the reference source and current-limiting branch according to the formula. Calculate R1, where Vref is the reference voltage of the bias circuit. This is the base voltage of HBT1. This refers to the base-emitter quiescent current of the HBT2. This refers to the base-emitter quiescent current of the HBT1. Given the collector-emitter static current of HBT2, based on the general relationship between mirror current and base-emitter junction voltage, and combined with the bias node potential balance and temperature margin constraints, the bias range of mirror-driven HBT1 is determined so that the mirror chain is stable in the target temperature range.

[0027] S2-2. Add an initial value to the ballast resistor R3 in the emitter circuit of HBT1 for current limiting and stabilization during heat rise and large signals. R3 is set according to... Estimate and coordinate with mirror parameters, where This is the base voltage of HBT1. The maximum base bias current of HBT0 during operation was determined through simulation. Then, the drive current that HBT1 needs to provide to HBT0 is obtained; the mirror output is connected to the base of HBT0 through the bias network to form the bias main link.

[0028] According to the above technical solution, S3 specifically refers to:

[0029] S3-1. Based on the drift law of Vbe caused by temperature and input power, HBT2 and HBT3 are selected to form a potential compensation branch, which is an equivalent series diode structure. The area and ratio are based on BTI experience, and then combined with the potential relationship and resistance formula. Calculate R2 and the critical node potential to obtain a preliminary match of the compensation amount;

[0030] S3-2. A compensation branch is added to the mirror baseline to effectively cancel out the Vbe shift caused by temperature rise or large signals; together with R3, the base point potential and bias current are adjusted to ensure that the transconductance of small and large signals meets the index and a stable bias point is obtained.

[0031] According to the above technical solution, S4 specifically refers to:

[0032] S4-1. Based on the self-tuning frequency of HBT1, select bypass capacitor C1 to prioritize the return of RF leakage to ground and stabilize the base potential; select C2 according to the target bias port impedance and frequency band requirements and connect it in parallel with R3 for shaping to achieve broadband stability and backfeed suppression.

[0033] S4-2. Perform DC+RF co-simulation and layout parasitic verification on the connected bias network to check the Vbe stability, mirror current drift, port impedance and backfeed under the temperature range and power coverage. If the target is not met, call back R1, R2, R3, C2 and return to S2 and S3 for small-step optimization until the key indicators converge.

[0034] According to the above technical solution, S5 specifically refers to:

[0035] S5-1. Retest bias point stability, linearity and efficiency across the entire temperature and input power dynamic range, including startup, thermal shock, AM, PM consistency and broadband stability verification; fine-tune compensation and ballast values ​​as necessary.

[0036] S5-2, solidify the size ratios of R1, R2, R3, C1, C2 and HBT2, HBT3, output BOM and layout constraints, target values ​​of bias port impedance and test specifications, forming a mass-producible design flow package.

[0037] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: The present invention proposes a non-temperature-sensitive adaptive bias circuit design method and circuit based on a mirror current source structure: the mirror branch provides the base bias current of the main power amplifier tube HBT0, the ballast and port shaping stabilize the mirror operating point, and the potential compensation branch effectively cancels the base junction voltage changes caused by temperature and power, thereby maintaining the stability of Vbe0 and bias current in the entire temperature and full input power dynamic range, and improving linearity and efficiency;

[0038] By using mirrored bias and potential compensation coupling, the bias point exhibits self-compensation characteristics in response to temperature and input power changes, significantly reducing Vbe0 and bias current drift. The transconductance of large and small signals remains consistent, reducing AM-AM and AM-PM distortion and maintaining power amplifier efficiency and output quality. C1 bypasses RF leakage, and C2-R3 shapes the port impedance, improving the broadband stability of the bias branch and reducing RF backfeed disturbance to the bias point. Clear selection and calculation procedures are provided for each key component (HBT1, 2, 3, R1, 2, 3, C1, 2), facilitating layout implementation and mass production expansion under GaAs HBT technology. Attached Figure Description

[0039] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0040] Figure 1 This is a schematic diagram of the non-temperature-sensitive adaptive bias circuit structure and its equivalent structure of the present invention;

[0041] Figure 2 This is a schematic diagram of the circuit design process of the present invention. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] Please see Figure 1 and Figure 2 The present invention provides a technical solution: a non-temperature-sensitive adaptive bias circuit design method for GaAs HBT process. The method is based on the operation of an adaptive bias circuit system, which includes a bias mirror module, a temperature compensation module, and a port stabilization module. The bias mirror module is used to generate and stably provide the bias current required by the base of the main power amplifier tube HBT0. The temperature compensation module is used to perform equivalent compensation for the base-emitter junction voltage change caused by temperature and input power to maintain the bias point stability. The port stabilization module is used to bypass RF leakage, shape the bias port impedance, and suppress bias point disturbances.

[0044] The bias mirroring module includes:

[0045] The reference and current limiting branches Vref and R1 are connected to the base of HBT1 via a signal to provide a mirror reference and current limiting;

[0046] The mirror drive branch HBT1, its collector and emitter are electrically connected to the bias network and output mirror current to the base of HBT0;

[0047] The ballast and shaping branch R3 is connected in series in the emitter circuit of HBT1 to limit the mirror current during temperature rise and to cooperate with port shaping.

[0048] The temperature compensation module includes:

[0049] The potential compensation branches HBT2 and HBT3 are equivalent to series diodes, which are connected across the mirror control node to achieve compensation by changing the on-potential with temperature.

[0050] The current-limiting and stabilizing branch R2 is connected to the potential compensation branches HBT2 and HBT3 to limit the operating area and stabilize the compensation amount;

[0051] The port stabilization module includes:

[0052] The RF bypass branch C1 is connected to the base of HBT1 to ground to discharge the stable RF leakage VB;

[0053] The port impedance shaping branch C2 is connected in parallel with R3 and connected to the bias port to form the target input impedance and extend the bandwidth;

[0054] Includes the following steps:

[0055] S1. Based on GaAs HBT process and power amplifier stage specifications, determine the bias current range, Vbe stability target, temperature and input power coverage range of the main amplifier HBT0, and obtain the starting parameters of mirror, compensation and ballast by calibrating the Vbe-Ib characteristics under extreme conditions through simulation and prototype.

[0056] S2. Establish reference and current limiting branches to determine R1 and generate a stable mirror bias; introduce ballast resistor R3 at the emitter of HBT1 and connect the mirror output to the base of HBT0 to form the bias main link and complete the mirror closed loop.

[0057] S3. Select HBT2, HBT3 and R2 to form a potential compensation branch and set R3 in conjunction to effectively cancel out the Vbe drift caused by temperature rise and large signal, lock the base point potential and bias current, and achieve consistency of small and large signal transconductance.

[0058] S4. Configure bypass capacitor C1 according to the device's self-tuning frequency and use C2 and R3 in parallel to shape the bias port impedance. Then perform DC+RF joint simulation and parasitic verification. If the performance does not meet the requirements, optimize R1, R2, R3, and C2 in small steps and re-verify.

[0059] S5. Verify bias stability, linearity and broadband stability across the entire temperature and input power range. After fine-tuning the parameters, solidify the size ratios of R1, R2, R3, C1, C2 and HBT2, HBT3. Output the BOM, layout and test specifications to form a mass production design package.

[0060] S1 specifically refers to:

[0061] S1-1. Based on the GaAs HBT process library and power amplifier stage design goals, determine the bias current range, Vbe stability target, temperature and input power coverage range of HBT0 under small and large signals, and give the reference potential, tolerance and stability constraints of the bias network.

[0062] S1-2. Through simulation or rapid testing of prototypes, calibrate the Vbe-Ib characteristics and mirror operating point under extreme conditions of low and high temperatures and large and small signals to obtain the starting parameters for subsequent mirroring, compensation and ballasting.

[0063] S2 specifically refers to:

[0064] S2-1. Set up the reference source and current-limiting branch according to the formula. Calculate R1, where Vref is the reference voltage of the bias circuit. This is the base voltage of HBT1. This refers to the base-emitter quiescent current of the HBT2. This refers to the base-emitter quiescent current of the HBT1. Given the collector-emitter static current of HBT2, based on the general relationship between mirror current and base-emitter junction voltage, and combined with the bias node potential balance and temperature margin constraints, the bias range of mirror-driven HBT1 is determined so that the mirror chain is stable in the target temperature range.

[0065] S2-2. Add an initial value to the ballast resistor R3 in the emitter circuit of HBT1 for current limiting and stabilization during heat rise and large signals. R3 is set according to... Estimate and coordinate with mirror parameters, where This is the base voltage of HBT1. The maximum base bias current of HBT0 during operation was determined through simulation. Then, the drive current that HBT1 needs to provide to HBT0 is obtained; the mirror output is connected to the base of HBT0 through the bias network to form the bias main link;

[0066] S3 specifically refers to:

[0067] S3-1. Based on the drift law of Vbe caused by temperature and input power, HBT2 and HBT3 are selected to form a potential compensation branch, which is an equivalent series diode structure. The area and ratio are based on BTI experience, and then combined with the potential relationship and resistance formula. Calculate R2 and the critical node potential to obtain a preliminary match of the compensation amount;

[0068] S3-2. A compensation branch is added to the mirror baseline to effectively cancel out the Vbe shift caused by temperature rise or large signals; the base point potential and bias current are adjusted in conjunction with R3 to ensure that the transconductance of small and large signals meets the index and a stable bias point is obtained.

[0069] S4 specifically refers to:

[0070] S4-1. Based on the self-tuning frequency of HBT1, select bypass capacitor C1 to prioritize the return of RF leakage to ground and stabilize the base potential; select C2 according to the target bias port impedance and frequency band requirements and connect it in parallel with R3 for shaping to achieve broadband stability and backfeed suppression.

[0071] S4-2. Perform DC+RF co-simulation and layout parasitic verification on the connected bias network to check Vbe stability, mirror current drift, port impedance and backfeed under temperature range and power coverage. If the target is not met, call back R1, R2, R3, C2 and return to S2 and S3 for small-step optimization until the key indicators converge.

[0072] S5 specifically refers to:

[0073] S5-1. Retest bias point stability, linearity and efficiency across the entire temperature and input power dynamic range, including startup, thermal shock, AM, PM consistency and broadband stability verification; fine-tune compensation and ballast values ​​as necessary.

[0074] S5-2, solidify the size ratios of R1, R2, R3, C1, C2 and HBT2, HBT3, output BOM and layout constraints, target values ​​of bias port impedance and test specifications, forming a mass-producible design flow package.

[0075] This invention proposes a non-temperature-sensitive adaptive bias circuit design method and circuit based on a mirror current source structure: the mirror branch provides the base bias current of the main power amplifier tube HBT0, the ballast and port shaping stabilize the mirror operating point, and the potential compensation branch effectively cancels the base junction voltage changes caused by temperature and power, thereby maintaining the stability of Vbe0 and bias current in the entire temperature and input power dynamic range, and improving linearity and efficiency.

[0076] By using mirrored bias and potential compensation coupling, the bias point exhibits self-compensation characteristics in response to temperature and input power changes, significantly reducing Vbe0 and bias current drift. The transconductance of large and small signals remains consistent, reducing AM-AM and AM-PM distortion and maintaining power amplifier efficiency and output quality. C1 bypasses RF leakage, and C2-R3 shapes the port impedance, improving the broadband stability of the bias branch and reducing RF backfeed disturbance to the bias point. Clear selection and calculation procedures are provided for each key component (HBT1, 2, 3, R1, 2, 3, C1, 2), facilitating layout implementation and mass production expansion under GaAs HBT technology.

[0077] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0078] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A non-temperature-sensitive adaptive bias circuit design method for GaAs HBT process, characterized in that: This method is based on an adaptive bias circuit system, which includes a bias mirror module, a temperature compensation module, and a port stabilization module. The bias mirror module is used to generate and stably provide the bias current required by the base of the main power amplifier tube HBT0. The temperature compensation module is used to equivalently compensate for the base-emitter junction voltage changes caused by temperature and input power to maintain the bias point stability. The port stabilization module is used to bypass RF leakage, shape the bias port impedance, and suppress bias point disturbances. The bias mirroring module includes: The reference and current limiting branches Vref and R1 are connected to the base of HBT1 via a signal to provide a mirror reference and current limiting; The mirror drive branch HBT1, its collector and emitter are electrically connected to the bias network and output mirror current to the base of HBT0; The ballast and shaping branch R3 is connected in series in the emitter circuit of HBT1 to limit the mirror current during temperature rise and to cooperate with port shaping. The temperature compensation module includes: The potential compensation branches HBT2 and HBT3 are equivalent to series diodes, which are connected across the mirror control node to achieve compensation by changing the on-potential with temperature. The current-limiting and stabilizing branch R2 is connected to the potential compensation branches HBT2 and HBT3 to limit the operating area and stabilize the compensation amount; The port stabilization module includes: The RF bypass branch C1 is connected to the base of HBT1 to ground to discharge the stable RF leakage VB; The port impedance shaping branch C2 is connected in parallel with R3 and connected to the bias port to form the target input impedance and extend the bandwidth.

2. The non-temperature-sensitive adaptive bias circuit design method for GaAs HBT process according to claim 1, characterized in that: Includes the following steps: S1. Based on GaAs HBT process and power amplifier stage specifications, determine the bias current range, Vbe stability target, temperature and input power coverage range of the main amplifier HBT0, and obtain the starting parameters of mirror, compensation and ballast by calibrating the Vbe-Ib characteristics under extreme conditions through simulation and prototype. S2. Establish reference and current limiting branches to determine R1 and generate a stable mirror bias; introduce ballast resistor R3 at the emitter of HBT1 and connect the mirror output to the base of HBT0 to form the bias main link and complete the mirror closed loop. S3. Select HBT2, HBT3 and R2 to form a potential compensation branch and set R3 in conjunction to effectively cancel out the Vbe drift caused by temperature rise and large signal, lock the base point potential and bias current, and achieve consistency of transconductance between small and large signals. S4. Based on the device's self-tuning frequency, configure the bypass capacitor C1 and use C2 and R3 in parallel to shape the bias port impedance. Then, perform DC+RF joint simulation and parasitic verification. If the indicators are not met, perform small-step optimizations and reviews using R1, R2, R3, and C2. S5. Verify bias stability, linearity, and broadband stability across the entire temperature and input power range. After fine-tuning the parameters, solidify the size ratios of R1, R2, R3, C1, C2, and HBT2, HBT3. Output the BOM, layout, and test specifications to form a mass production design package.

3. The non-temperature-sensitive adaptive bias circuit design method for GaAs HBT process according to claim 2, characterized in that: Specifically, S1 is: S1-1. Based on the GaAs HBT process library and power amplifier stage design goals, determine the bias current range, Vbe stability target, temperature and input power coverage range of HBT0 under small and large signals, and give the reference potential, tolerance and stability constraints of the bias network. S1-2. Through simulation or rapid testing of prototypes, calibrate the Vbe-Ib characteristics and mirror operating point under extreme conditions of low and high temperatures and large and small signals to obtain the starting parameters for subsequent mirroring, compensation and ballasting.

4. The non-temperature-sensitive adaptive bias circuit design method for GaAs HBT process according to claim 3, characterized in that: Specifically, S2 is: S2-1. Set up the reference source and current-limiting branch according to the formula. Calculate R1, where Vref is the reference voltage of the bias circuit. This is the base voltage of HBT1. This refers to the base-emitter quiescent current of the HBT2. This refers to the base-emitter quiescent current of the HBT1. Given the collector-emitter static current of HBT2, based on the general relationship between mirror current and base-emitter junction voltage, and combined with the bias node potential balance and temperature margin constraints, the bias range of mirror-driven HBT1 is determined to ensure the stability of the mirror chain in the target temperature range. S2-2. Add an initial value to the ballast resistor R3 in the emitter circuit of HBT1 for current limiting and stabilization during heat rise and large signals. R3 is set according to... Estimate and coordinate with mirror parameters, where This is the base voltage of HBT1. The maximum base bias current of HBT0 during operation was determined through simulation. Then, the drive current that HBT1 needs to provide to HBT0 is obtained; the mirror output is then connected to the bias network. The base of HBT0 forms the main bias link, which is the base bias voltage of HBT0. This is the base bias voltage of HBT1.

5. The non-temperature-sensitive adaptive bias circuit design method for GaAs HBT process according to claim 4, characterized in that: Specifically, S3 is: S3-1. Based on the drift characteristics of Vbe caused by temperature and input power, HBT2 and HBT3 are selected to form a potential compensation branch, which is an equivalent series diode structure. The initial values ​​of its effective area and the area ratio between the two are determined based on BTI design experience, and then combined with the potential relationship and resistance formula. Calculate R2 and the critical node potential to obtain a preliminary match of the compensation amount. This is the base voltage of HBT2. This is the base bias current of HBT2; S3-2. A compensation branch is added to the mirror baseline to effectively cancel out the Vbe shift caused by temperature rise or large signals; together with R3, the base point potential and bias current are adjusted to ensure that the transconductance of small and large signals meets the index and a stable bias point is obtained.

6. The non-temperature-sensitive adaptive bias circuit design method for GaAs HBT process according to claim 5, characterized in that: Specifically, S4 is: S4-1. Based on the self-tuning frequency of HBT1, select bypass capacitor C1 to prioritize the return of RF leakage to ground and stabilize the base potential; select C2 according to the target bias port impedance and frequency band requirements and connect it in parallel with R3 for shaping to achieve broadband stability and backfeed suppression. S4-2. Perform DC+RF co-simulation and layout parasitic verification on the connected bias network to check the Vbe stability, mirror current drift, port impedance and backfeed under the temperature range and power coverage. If the target is not met, call back R1, R2, R3, C2 and return to S2 and S3 for small-step optimization until the key indicators converge.

7. The non-temperature-sensitive adaptive bias circuit design method for GaAs HBT process according to claim 6, characterized in that: Specifically, S5 is: S5-1. Retest bias point stability, linearity and efficiency across the entire temperature and input power dynamic range, including startup, thermal shock, AM, PM consistency and broadband stability verification; fine-tune compensation and ballast values ​​as necessary. S5-2, solidify the size ratios of R1, R2, R3, C1, C2 and HBT2, HBT3, output BOM and layout constraints, target values ​​of bias port impedance and test specifications, forming a design flow package that can be mass-produced.

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