Unified three-level real-time simulation method based on modal mapping

Abstract

The invention provides a unified three-level real-time simulation method based on modal mapping, and the method comprises the steps: building a unified three-level model which comprises three equivalent switches which can be independently controlled, and are respectively corresponding to three operation modes of positive electrode output, midpoint output and negative electrode output; carrying out discretization processing on the unified three-level model based on a differential modeling method, and carrying out modeling on a switch state by adopting a constant admittance model; mapping control signals of a plurality of switches in the original three-level topological structure into three paths of control input of a unified three-level model; obtaining an electrical quantity simulation result by using a simple EMTP resolving method; an intermediate calculation result obtained through simulation is transmitted into a circuit reflection module, and electrical quantities are split and combined and are restored into actual output of each measurement point. The method has the advantages of being high in modeling universality, high in calculation efficiency, low in hardware resource occupation and the like, and is suitable for scenes such as power electronic simulation and control strategy verification.

Description

Technical Field

[0001] This invention belongs to the field of real-time simulation technology of power electronic systems, and particularly relates to a unified three-level real-time simulation method based on modal mapping. Background Technology

[0002] With the large-scale integration of new energy sources and the increasing frequency of power electronic devices, modern power systems place higher demands on the modeling accuracy and control reliability of power electronic converters. To fully verify the stability of control strategies and system-level operational performance before actual equipment deployment, real-time simulation technology for power electronic systems has become a core supporting tool. This technology can accurately reproduce the dynamic behavior of power electronic devices under various operating conditions with microsecond or even nanosecond time steps, and is widely used in engineering processes such as control algorithm verification, fault ride-through testing, and hardware-in-the-loop (HIL) experiments.

[0003] In practical engineering applications, three-level inverters are widely deployed in medium-voltage converters, new energy grid-connected systems, and flexible DC transmission due to their advantages such as high output voltage waveform quality and low switching losses. Common three-level topologies include NPC (neutral-point clamped), ANPC (active neutral-point clamped), and T-type three-level structures. Although these topologies differ in structural form and control strategy, their operating states can be abstracted into three typical modes: positive (P), neutral (O), or negative (N) output. However, current simulation modeling methods mostly rely on independent modeling of the topology structure itself, lacking a unified modeling and solution architecture. This results in poor model versatility, low development efficiency, and difficulty in adapting to the unified deployment requirements of large-scale multi-topology systems.

[0004] To improve simulation efficiency and meet the deployment requirements of parallel platforms such as FPGAs, discrete circuit modeling (ADC) methods based on constant admittance models are currently widely used. This method equates power electronic switches to specific impedance branches in their on / off states, simplifying the computation process and offering good programmability and real-time performance. However, at the instant of device switching between on and off, this type of model often exhibits deviations from the actual device behavior, easily generating non-physical virtual power losses, which are particularly significant in high-frequency and high-speed switching simulations, weakening simulation accuracy. Although some scholars have proposed mitigating this problem through compensation sources and initialization corrections, these often lead to increased model complexity, enhanced parameter dependence, and even increased consumption of FPGA resources, affecting system feasibility. Summary of the Invention

[0005] The purpose of this invention is to provide a unified three-level real-time simulation method based on modal mapping, which aims to solve the problems of complex modeling, poor topology adaptability, and significant virtual power loss of three-level inverters in real-time simulation.

[0006] This invention is implemented as follows: a unified three-level real-time simulation method based on modal mapping, the method comprising the following steps:

[0007] Step S1: Establish a unified three-level model, which includes three independently controllable equivalent switches, corresponding to the three operating modes of positive output, midpoint output and negative output respectively;

[0008] Step S2: Discretize the unified three-level model based on the differential modeling method, and model the switching state using the constant admittance model;

[0009] Step S3: Map the control signals of multiple switches in the original three-level topology to three control inputs of a unified three-level model;

[0010] Step S4: Numerical calculation of the unified three-level model is performed using the simplified EMTP solution method to obtain the electrical quantity simulation results;

[0011] Step S5: The intermediate calculation results obtained from the simulation are fed into the circuit inverse mapping module. This module decomposes and combines the electrical quantities according to the current control state and the internal structural relationship of the model, and restores them to the actual output of each measurement point in the original topology.

[0012] A further technical solution of the present invention is that the unified three-level model is adapted to NPC, ANPC and T-type three-level inverter structures.

[0013] A further technical solution of the present invention is: in step S1, the conduction of each switch represents the system being in the corresponding modal state.

[0014] A further technical solution of the present invention is: in step S2, a differential modeling strategy based on the ADC idea is adopted to discretize the dynamic element into a time-domain differential expression, and the on state of the switching device is equivalent to a parallel structure of inductor and resistor, and the off state is equivalent to a series structure of capacitor and resistor.

[0015] A further technical solution of the present invention is as follows: In step S3, the switch control signal in the original three-level topology is input to the control mapping conversion module. The module normalizes the multiple control inputs in the topology into three control signals required by the unified three-level model according to the conduction combination relationship of the control signals, and drives the switch units representing different operating modes in the unified three-level model respectively.

[0016] A further technical solution of the present invention is as follows: In step S4, after the mapping is completed, the unified three-level model performs differential modeling calculations under control input, and adopts a simplified EMTP numerical solution method to output the key electrical quantities under the corresponding mode: through i temp (t)=j a(t)+j s (t) Calculate the intermediate current, through i n (t)=-A·i temp (t) Calculate the node injection current, through Calculate the node voltage using v b (t)=A T ·v n (t) Calculate the branch voltage using i b (t)=Y b ·v b (t)+i temp (t) Calculate the branch current using j a (t+Δt)=α·Y b v b (t)+β·i b (t) Update the accompanying current source, where i temp For intermediate current, Y b For the admittance of each branch, Y n Let v be the nodal admittance matrix. b For branch voltage, i n Inject current into the node, j s As an independent current source, j a Let α and β be the associated current sources of each branch, α and β be the branch coefficients, and A be the node-branch correlation matrix. After decoupling the above calculation steps, the simplified EMTP numerical solution steps can be obtained:

[0017] i temp (t)=j a (t)+j s (t)

[0018] v m (t)-M1·i temp (t)

[0019] i b (t)=M2·i temp (t)

[0020] j a (t+△t)=(α+β)·i b (t)-α·j a (t)

[0021] In the formula, v m For the observed voltage vector, M1 and M2 are constant coefficient matrices.

[0022] A further technical solution of the present invention is: it also includes step S6: deploying steps S1-S5 on an FPGA platform, the solution process adopts a pipeline structure, the mathematical operations are completed by the DSP resources in the FPGA, and the control mapping and anti-mapping logic is completed within a single cycle.

[0023] A further technical solution of the present invention is as follows: The numerical solution process of the unified three-level model adopts a pipeline structure, which schedules and executes key steps of electrical quantity update and state advancement in sequence and in segments. The matrix-vector dot product calculation involved in the differential modeling process is completed by the multiply-accumulate architecture inside the FPGA. First, a row of matrix data and corresponding vector data are read from the on-chip memory. Then, the product of each element pair is calculated in parallel by multiple multipliers. Next, these products are accumulated through an adder tree or a serial accumulator to obtain the dot product result of the row, and the result is written to the output register or buffer.

[0024] The beneficial effects of this invention are: 1. Strong modeling uniformity: By standardizing the structural differences of different three-level topologies through runtime modal abstraction, the modeling logic is unified and the structure is reused, which significantly improves the versatility and deployment efficiency of the model;

[0025] 2. High solution accuracy: The ADC differential model combines modal prediction and error correction to effectively suppress virtual power loss;

[0026] 3. Low implementation cost: No complex compensation network is required, and the mapping logic can be embedded into existing FPGA architectures at low cost;

[0027] 4. High deployment efficiency: The computational architecture is adapted to pipelined computation, making it suitable for HIL platforms and multi-core parallel environments;

[0028] 5. Wide topology adaptability: Applicable to mainstream three-level inverters such as NPC, ANPC, and T-type, facilitating industrial promotion. Attached Figure Description

[0029] Figure 1 This is the main flowchart of the present invention;

[0030] Figure 2 This invention provides the solution framework for a unified three-level real-time simulation method based on modal mapping.

[0031] Figure 3 This is the differential modeling process of the circuit components and the three-level ADC of this invention;

[0032] Figure 4 This describes the hardware implementation method of the present invention on an FPGA. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0034] Figure 1 This invention illustrates a unified three-level real-time simulation method based on modal mapping, the method comprising the following steps:

[0035] Step S1: Establish a unified three-level model, which includes three independently controllable equivalent switches, corresponding to the three operating modes of positive output, midpoint output and negative output respectively;

[0036] Step S2: Discretize the unified three-level model based on the differential modeling method, and model the switching state using the constant admittance model;

[0037] Step S3: Map the control signals of multiple switches in the original three-level topology to three control inputs of a unified three-level model;

[0038] Step S4: Numerical calculation of the unified three-level model is performed using the simplified EMTP solution method to obtain the electrical quantity simulation results;

[0039] Step S5: The intermediate calculation results obtained from the simulation are fed into the circuit inverse mapping module. This module decomposes and combines the electrical quantities according to the current control state and the internal structural relationship of the model, and restores them to the actual output of each measurement point in the original topology.

[0040] Preferably, the unified three-level model is adapted to NPC, ANPC, and T-type three-level inverter structures.

[0041] Preferably, in step S1, the conduction of each switch represents the system being in the corresponding modal state.

[0042] Preferably, in step S2, a differential modeling strategy based on the ADC concept is adopted to discretize the dynamic element into a time-domain differential expression. The on-state of the switching device is equivalent to a parallel structure of an inductor and a resistor, and the off-state is equivalent to a series structure of a capacitor and a resistor.

[0043] Preferably, in step S3, the switch control signal in the original three-level topology is input to the control mapping conversion module. The module normalizes the multiple control inputs in the topology into three control signals required for the unified three-level model according to the conduction combination relationship of the control signals, and drives the switch units representing different operating modes in the unified three-level model respectively.

[0044] Preferably, in step S4, after mapping is completed, the unified three-level model performs differential modeling calculations under control input, and uses a simplified EMTP numerical solution method to output the key electrical quantities under the corresponding mode: through itemp (t)=j a (t)+j s (t) Calculate the intermediate current, through i n (t)=-A·i temp (t) Calculate the node injection current, through Calculate the node voltage using v b (t)=A T ·v n (t) Calculate the branch voltage using i b (t)=Y b ·v b (t)+i temp (t) Calculate the branch current using j a (t+Δt)=α·Y b v b (t)+β·i b (t) Update the accompanying current source, where i temp For intermediate current, Y b For the admittance of each branch, Y n Let v be the nodal admittance matrix. b For branch voltage, i n Inject current into the node, j s As an independent current source, j a Let α and β be the associated current sources of each branch, α and β be the branch coefficients, and A be the node-branch correlation matrix. After decoupling the above calculation steps, the simplified EMTP numerical solution steps can be obtained:

[0045] i temp (t)=j a (t)+j s (t)

[0046] v m (t)=M1·i temp (t)

[0047] i b (t)=M2·i temp (t)

[0048] j a (t+△t)=(α+β)·i b (t)-α·j a (t)

[0049] In the formula, v m For the observed voltage vector, M1 and M2 are constant coefficient matrices.

[0050] Preferably, the method further includes step S6: deploying steps S1-S5 on an FPGA platform, the solution process adopts a pipeline structure, the mathematical operations are completed by the DSP resources in the FPGA, and the control mapping and demapping logic is completed within a single cycle.

[0051] Preferably, the numerical solution process of the unified three-level model adopts a pipeline structure, which schedules and executes key steps of electrical quantity update and state advancement in sequence. The matrix-vector dot product calculation involved in the differential modeling process is completed by the multiply-accumulate architecture inside the FPGA. First, a row of matrix data and corresponding vector data are read from the on-chip memory. Then, the product of each element pair is calculated in parallel by multiple multipliers. Next, these products are accumulated through an adder tree or serial accumulator to obtain the dot product result of the row, and the result is written to the output register or buffer.

[0052] This invention provides a unified three-level real-time simulation method based on modal mapping. This method establishes a general modeling and solving architecture applicable to various three-level topologies such as NPC, ANPC, and T-type by running a unified modal abstraction, ADC differential model reconstruction, and mapping mechanism optimization. It has the characteristics of high precision, low resource consumption, and strong compatibility.

[0053] This invention first abstracts the output state of a three-level inverter into three typical operating modes: P (positive output), O (neutral output), and N (negative output). For each mode, a circuit structure independently controlled by a single equivalent switch is constructed, and the operating state abstraction is completed with a unified current path and node configuration. Based on this, the corresponding electrical behavior equations are established using an ADC (Associated Discrete Circuit) differential model, and an optimal admittance parameter selection mechanism is adopted to ensure good stability and accuracy in the simulation process.

[0054] During simulation, the system identifies the current operating mode in real time based on the conduction logic and control signals of the devices in the three-level topology, and maps it to the corresponding modal circuit structure. This mode determination is not only used to select the solution path, but also assists in predicting the expected steady-state response of the circuit, providing a reference value for the initial error correction mechanism in the model, thereby effectively suppressing virtual power loss that may occur during switching and improving simulation stability. The modal mapping and reverse mapping process fully utilizes the idle DSP modules and logic gate resources in the FPGA, efficiently completing the structure mapping and result restoration without adding extra matrix solving logic burden, ensuring minimal overall system resource consumption.

[0055] This invention, based on unified modal abstraction, ADC differential model construction, and efficient FPGA deployment, enables real-time simulation modeling and calculation of various three-level topologies. The implementation process is described in detail below with reference to the accompanying drawings.

[0056] In this invention, the design of a unified three-level ADC differential model is the core step in the modeling process. Firstly, independent of specific three-level topologies, a standardized three-modal circuit structure is proposed. This structure consists of three switches, such as... Figure 2 In this model, S1, S2, and S3 correspond to three typical operating states: P (positive output), O (neutral output), and N (negative output). The conduction of each switch represents the system being in the corresponding modal state, thus forming a concise three-level equivalent topology with clear physical meaning and independent current paths. This model does not depend on the arrangement and control method of the devices in a specific topology, but rather completes the structural abstraction through a unified modal circuit framework, ensuring that the model has good structural independence and universal adaptability.

[0057] Based on this, to achieve high-speed, low-error real-time modeling of this unified topology, this invention adopts a differential modeling strategy based on the ADC concept, discretizing dynamic components such as inductors and capacitors into time-domain differential expressions. For example... Figure 3 As shown, taking inductance as an example, its definition is: Implicit Euler difference Where i L U represents the inductor current. L Let L represent the inductor voltage, L represent the inductance, and Δt represent the step size. The discrete expression can be obtained as follows: Further define admittance coefficient With historical current term i L_history (t)=i L (t-Δt), the final inductor current can be expressed as i L (t)=Y L ·u L (t)+i L_history (t). Where Y L i represents the equivalent admittance of the inductor branch. L_history This represents the historical current source of the inductor branch. In this invention, the switching behavior is modeled as an improved constant admittance branch: the on-state of the switching device is equivalent to a parallel structure of an inductor and a resistor, and the off-state is equivalent to a series structure of a capacitor and a resistor. For example... Figure 3 As shown, its implicit Euler difference result is Where Y s j represents the equivalent admittance of the switching branch. a This represents the accompanying current source of the switching branch. Compared to the traditional L / C switch modeling method, this improved constant admittance model provides a clearer equivalent branch definition between the on and off states, and effectively suppresses virtual power loss while maintaining modeling accuracy, thus improving numerical stability and energy conservation. Figure 3The following illustrates the differential modeling process of a unified three-level circuit, using the intermediate equivalent switch S2 as an example. Its current and output voltage expressions are as follows:

[0058] Where I2 is the current in branch 2, I o with U o Let k1 and k2 represent the output current and voltage, respectively, and k1 and k2 be the coefficients of the switching differential model. The convergence rate of the system parameters under different parameter conditions can be calculated based on the pole distribution. The selection of the admittance parameters for each branch is optimized in conjunction with typical operating conditions, ensuring that the model possesses good dynamic response performance while guaranteeing simulation convergence.

[0059] After completing the construction of the unified three-level ADC differential model, in order to enable the model to adapt to different types of three-level topologies and achieve an accurate correspondence between the simulation results and the original system state, this invention designs a mapping module and an anti-mapping module as the interface logic between the unified model and the actual system.

[0060] like Figure 2 As shown, the switch control signals in the original three-level topology are first input to the control mapping conversion module. This module, based on the conduction combination relationship of the control signals, normalizes the multiple control inputs in the topology into three control signals required for the unified model, which then drive the switch units representing different operating modes in the unified model. Taking switch S1 as an example, its control positive output mode P, under constraints... Under these conditions, switch S1 is controlled by actual control signals s1 and s2: S1 = s1∧s2. After mapping is completed, the unified model performs differential modeling calculations under this control input and uses the simplified EMTP numerical solution method to output key electrical quantities such as node voltage and current under the corresponding mode.

[0061] i temp (t)=j a (t)+j s (t) — Calculate the intermediate current

[0062] i n (t)=-A·i temp (t) — Calculate the node injection current

[0063] — Calculate node voltage

[0064] v b (t)=A T ·v n (t)——Calculate the branch voltage

[0065] i b (t)=Y b ·v b (t)+itemp (t)——Calculate the branch current

[0066] j a (t+Δt)=α·Y b v b (t)+β·i b (t)——Update the accompanying current source

[0067] In the formula, i temp For intermediate current, Y b For the admittance of each branch, Y n Let v be the nodal admittance matrix. b For branch voltage, i n Inject current into the node, j s As an independent current source, j a Let α and β be the associated current sources of each branch, α and β be the branch coefficients, and A be the node-branch correlation matrix.

[0068] After decoupling the above calculation steps, a simplified EMTP numerical solution step can be obtained.

[0069] i temp (t)=j a (t)+j s (t)

[0070] v m (t)=M1·i temp (t)

[0071] i b (t)=M2·i temp (t)

[0072] j a (t+Δt)=(α+β)·i b (t)-α·j a (t)

[0073] In the formula, v m For the observed voltage vector, M1 and M2 are constant coefficient matrices.

[0074] Subsequently, the intermediate calculation results obtained from the simulation are fed into the circuit inverse mapping module. This module decomposes and combines the electrical quantities according to the current control state and the internal structural relationships of the model, and restores them to the actual outputs of each measurement point in the original topology, such as branch voltage, output current, and switch node status, thereby completing the complete simulation of the original system.

[0075] To achieve efficient deployment of the unified three-level simulation method proposed in this invention on the FPGA platform, the system design process fully incorporates the structural characteristics of the FPGA, and performs parallel optimization and resource scheduling on the solution process and key modules.

[0076] When the unified three-level simulation method proposed in this invention is implemented on an FPGA platform, the design focuses on real-time performance and resource efficiency. For example... Figure 4 As shown, the numerical solution process of the unified three-level model adopts a pipelined structure. Leveraging the parallel computing advantages of FPGAs, key steps such as electrical quantity updates and state progression are scheduled sequentially and executed in segments, improving overall computational throughput. The matrix-vector dot product calculations involved in differential modeling are completed by the FPGA's internal multiply-accumulate (MAC) architecture. First, a row of matrix data and its corresponding vector data are read from on-chip memory. Then, multiple multipliers calculate the product of each element pair in parallel. These products are then accumulated through an adder tree or serial accumulator to obtain the dot product result for that row, which is then written to an output register or buffer. This process is pipelined continuously, processing one row of data per cycle to achieve efficient fixed-cycle solution capability. In terms of resource allocation, DSP computing units and register resources are rationally scheduled and reused, concentrating intensive operations such as multiplication and addition to hardware multiply-accumulate units, reducing redundant logic consumption and improving execution efficiency.

[0077] The mapping and demapping module has a simple structure and clear control logic. It can be embedded in the idle logic area of ​​the main solution process and use the idle computing resources under the current timing to complete the control signal conversion and simulation output restoration. Its processing delay is less than one cycle and does not affect the main path solution.

[0078] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A unified three-level real-time simulation method based on modal mapping, characterized in that, The method comprises the following steps: Step S1: establishing a unified three-level model, which comprises three independently controllable equivalent switches corresponding to three operating modes of positive output, midpoint output and negative output; Step S2: discretizing the unified three-level model based on a difference modeling method, and modeling the switch state by using a constant admittance model; Step S3: mapping the control signals of the multiple switches in the original three-level topology structure to the three-way control input of the unified three-level model; Step S4: performing numerical calculation on the unified three-level model by using a simple EMTP calculation method, and obtaining the simulation results of the electrical quantities; Step S5: inputting the intermediate calculation results obtained in the simulation into a circuit reflection mapping module, which splits and combines the electrical quantities according to the current control state and the internal structure relationship of the model, and restores the actual output of each measurement point in the original topology structure.

2. The modal mapping based unified three-level real-time simulation method according to claim 1, characterized in that, The unified three-level model is suitable for NPC, ANPC and T-type three-level inverter structures.

3. The modal mapping based unified three-level real-time simulation method according to claim 1, wherein, In step S1, the conduction of each switch represents the corresponding mode state of the system.

4. The modal mapping based unified three-level real-time simulation method according to claim 1, wherein, In step S2, a difference modeling strategy based on the ADC idea is adopted to discretize the dynamic elements into time domain difference expressions, and the conduction state of the switch device is equivalent to the parallel structure of inductance and resistance, and the off state is equivalent to the series structure of capacitance and resistance.

5. The modal mapping based unified three-level real-time simulation method according to claim 1, wherein, In step S3, the switch control signal in the original three-level topology is input into the control mapping conversion module, and the module normalizes the multiple control inputs in the topology structure into three control signals required by the unified three-level model according to the conduction combination relationship of the control signal, and drives the switch units representing different operating modes in the unified three-level model.

6. The modal mapping based unified three-level real-time simulation method according to claim 1, wherein, In step S4, after mapping is completed, the unified three-level model is subjected to differential modeling calculation under control input, and a simple EMTP numerical solution method is adopted to output key electrical quantities under corresponding modes: through i temp (t) = j a (t) + j s (t) intermediate current is calculated, through i n (t) = -A i temp (t) node injection current is calculated, through v b (t) = A T v n (t) branch voltage is calculated, through i b (t) = Y b v b (t) + i temp (t) branch current is calculated, through j a (t + Δt) = α Y b v b (t) + β i b (t) accompanying current source is updated, wherein i temp is intermediate current, Y b is branch admittance, Y n is node admittance matrix, v b is branch voltage, i n is node injection current, j s is independent current source, j a is accompanying current source of each branch, and α and β are branch coefficients. A is node-branch association matrix. After decoupling of the above calculation steps, a simple EMTP numerical solution step is obtained: i temp (t) = j a (t) + j s (t) v m (t) = M1 · i temp (t) i b (t) = M2- i temp (t) j a (t + At) = (a + b) - i b (t) - a - j a (t) where v m M1 and M2 are constant coefficient matrices for the observation voltage vector.

7. The modal mapping based unified three-level real-time simulation method according to claim 1, wherein, Step S6: deploying steps S1-S5 on an FPGA platform, the calculation process adopts a pipeline structure, the mathematical operation is completed by the DSP resource in the FPGA, and the control mapping and reflection mapping logic are processed in a single cycle.

8. The modal mapping based unified three-level real-time simulation method according to claim 7, characterized in that, The numerical solution process of the unified three-level model adopts a pipeline structure, the electrical quantity update and state promotion key steps are sequentially scheduled and executed, the matrix-vector dot product calculation involved in the difference modeling process is completed by the multiply-add architecture in the FPGA, first, a row of matrix data and corresponding vector data are read from the on-chip memory, then the products of each element pair are calculated in parallel through multiple multipliers, then the products are accumulated through an addition tree or a serial accumulator to obtain the dot product result of the row, and the result is written to the output register or buffer.

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