A hardware circuit for real-time image edge enhancement filtering

Abstract

The application discloses a kind of hardware circuits of real-time image edge enhancement filter, the circuit includes input interface module, cache control module, guide filter operation module and bypass selection module.Input interface module obtains the video stream signal containing original pixel data;Cache control module generates N×N pixel array with current pixel as center using multi-stage line cache and synchronous delay;Guide filter operation module converts RGB pixel into guide image, and based on the linear regression calculation of local covariance and variance, output filtered central pixel data;Bypass selection module selects output original or filtered pixel data according to enable signal.The circuit of the present application implements guide filter with full hardware architecture, without CPU / GPU participation, with the advantages of less resource occupation, low power consumption, extremely low delay and excellent image edge retention effect, suitable for high real-time video display system.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits and image processing technology, and in particular to a hardware circuit for real-time image edge enhancement filtering. BACKGROUND

[0002] In high refresh rate display application scenarios, such as smartphone screens, computer monitors, and game console video outputs, the real-time processing capability of image data is extremely demanding. In order to overcome the limitation of transmission bandwidth, the video sending end usually compresses the image data. Although compression effectively reduces the data transmission load, after decompression at the receiving end, the image quality often suffers considerable loss. Especially at a higher compression ratio, this quality loss is more pronounced, specifically manifested as image edge blurring, loss of fine details, and enhancement of unpleasant jagged artifacts.

[0003] In the prior art, a common method to improve such image quality problems is to use software for post-processing at the receiving end. Specifically, a complex image filtering and enhancement algorithm is executed by the central processing unit or the graphics processing unit of the system, the decompressed full-frame image data is calculated, and the optimized image is output. However, this software-based processing method has several inherent drawbacks:

[0004] First, the image processing process needs to significantly occupy the computing resources of the CPU or GPU, which in processing high-resolution, high-frame-rate video streams, will bring a heavy computational burden to the system, which may affect the execution efficiency of other parallel tasks.

[0005] Second, the software algorithm usually needs to buffer the complete frame of image data in the memory during execution, which not only causes additional memory bandwidth occupation, but also brings considerable storage chip overhead, which is not conducive to system cost control.

[0006] Third, due to the sequential nature of software processing and the requirement of full-frame buffering, the processing flow will introduce considerable computational delay. This delay is unacceptable in high real-time requirement application scenarios (such as high-speed games, virtual reality), which may cause the asynchronization between picture display and user operation.

[0007] Finally, a large amount of data transfer and floating-point operation will cause the system power consumption to increase significantly, which is contrary to the urgent need for low-power design of mobile devices and portable electronic products.

[0008] Therefore, there is an urgent need for an innovative technical solution that can perform high-quality edge enhancement filtering on video streams at the receiving end, while overcoming the above-mentioned software solution defects in resource occupation, storage overhead, processing delay, and system power consumption. SUMMARY

[0009] To address the technical problems existing in the background art, this invention proposes a hardware circuit for real-time image edge enhancement filtering.

[0010] In a first aspect, the present invention proposes a hardware circuit for real-time image edge enhancement filtering, comprising:

[0011] The input interface module is used to acquire the input video stream signal, which includes frame synchronization signal, line synchronization signal, data valid signal and raw pixel data.

[0012] The buffer control module is used to generate and output an N×N pixel array centered on the current pixel based on the raw pixel data in the video stream signal, where N is an odd number greater than 1;

[0013] The guided filtering operation module is used to obtain an N×N pixel array, perform guided filtering calculations on the center pixel in the N×N pixel array, and output the filtered center pixel data.

[0014] The bypass selection module is connected to the input interface module and the guided filtering operation module, respectively. It is used to acquire the original pixel data, the filtered center pixel data and the enable signal in the video stream signal, and select one of the original pixel data and the filtered center pixel data as the final video stream pixel data according to the enable signal.

[0015] Preferably, the cache control module includes:

[0016] The synchronization delay unit is used to acquire the original pixel data, delay the original pixel data for multiple clock cycles, and output a horizontal pixel window containing M consecutive pixels, where M is an integer greater than 1.

[0017] The timing generation unit is used to acquire vertical resolution parameters and horizontal resolution parameters, and generate row count signals, column count signals, delayed frame synchronization signals, delayed row synchronization signals, and delayed data valid signals;

[0018] The RAM data path unit includes K cascaded single-row RAMs for caching the raw pixel data line by line. In the RAM data path unit, the data written to the first-level RAM is the raw pixel data, and the data read out is used as the data written to the second-level RAM. The subsequent RAMs are cascaded in sequence, and finally output the cached K consecutive rows of image data.

[0019] The address control unit is used to uniformly generate and distribute read address signals and write address signals for all K single-row RAMs in the RAM data path unit;

[0020] The cache control module combines the horizontal pixel window data output by the synchronization delay unit with the continuous K rows of image data output by the RAM data path unit to form and output an N×N pixel array.

[0021] Preferably, the guided filtering operation module specifically includes:

[0022] The guide image conversion unit is used to obtain the current center pixel data from the N×N pixel array, and convert the red, green and blue components in the center pixel data into single-channel guide image data through integer operations;

[0023] The filtering calculation unit is used to acquire the guide image data, the original channel pixel data in the N×N pixel array, and the smoothing factor parameter. Within the window defined by the N×N pixel array, it calculates the local mean, local covariance, and local variance of the guide image data and the original channel pixel data, and combines the smoothing factor parameter to output the filtered center pixel data through linear regression calculation.

[0024] Preferably, in the guided filtering operation module, for image boundary regions that cannot form a complete N×N pixel array, the guided filtering operation module uses the center original pixel data of the N×N pixel array obtained from the cache control module to fill all the missing pixel positions in the N×N pixel array to form a complete, computable virtual N×N pixel array, and performs guided filtering calculation on the center pixel of the virtual N×N pixel array.

[0025] Preferably, in the guide image conversion unit, the conversion formula for converting the center pixel data into single-channel guide image data is as follows:

[0026] y×8192=R×2449+G×4809+B×934;

[0027] Where y is the single-channel guide image data; R is the red component of the center pixel data; G is the green component of the center pixel data; and B is the blue component of the center pixel data.

[0028] Preferably, in the filtering calculation unit, the linear regression calculation performed by the filtering calculation unit is based on the following mathematical relationship:

[0029] ;

[0030] Where I represents the raw pixel data of the input channel; y represents the guide image data of a single channel; The mean of the product of the image data and the raw pixel data of the input channel within the window; To guide the mean of image data within the window; This is the mean of the raw pixel data of the input channel within the window; This is the mean of the squared image data within the window; is the smoothing factor parameter; O is the filtered center pixel data.

[0031] Preferably, in the bypass selection module, when the enable signal is in an invalid state, the bypass selection module outputs the raw pixel data from the input interface module; when the enable signal is in an active state, the bypass selection module outputs the filtered center pixel data from the guided filtering operation module.

[0032] Preferably, the size of the N×N pixel array is configured by the filter window radius parameter, and at least 3×3, 5×5 or 7×7 pixel arrays are supported.

[0033] Secondly, the present invention proposes an image edge enhancement method, applied to a hardware circuit for real-time image edge enhancement filtering as described in any of the preceding claims, the method comprising:

[0034] S1. Acquire the input video stream signal, the video stream signal including frame synchronization signal, line synchronization signal, data valid signal and raw pixel data;

[0035] S2. Generate and output an N×N pixel array centered on the current pixel based on the original pixel data, where N is an odd number greater than 1;

[0036] S3. Perform guided filtering calculation on the center pixel in the N×N pixel array and output the filtered center pixel data;

[0037] S4. Based on the valid state of the enable signal, select either the original pixel data or the filtered center pixel data as the final video stream pixel data.

[0038] Thirdly, the present invention provides an image display device, including a display screen and a video processing circuit, wherein the video processing circuit includes a hardware circuit for real-time image edge enhancement filtering as described in any one of the above.

[0039] The hardware circuit for real-time image edge enhancement filtering proposed in this invention implements the guided filtering algorithm through dedicated hardware circuitry, completely eliminating reliance on general-purpose processor computing resources and significantly reducing system computational burden and overall power consumption. Its streaming processing architecture eliminates the need to cache complete frame images, greatly reducing storage overhead and achieving extremely low processing latency, perfectly meeting the stringent requirements of high real-time display systems. The unique boundary pixel processing mechanism effectively avoids distortion in image edge regions, ensuring the overall quality and integrity of the output image. The integer approximation operation and pipelined multiplication and division units employed greatly optimize hardware resource utilization and computational efficiency while maintaining algorithm accuracy. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the circuit architecture of a hardware circuit for real-time image edge enhancement filtering proposed in this invention.

[0041] Figure 2 This is a schematic diagram of the circuit architecture of one embodiment of the hardware circuit for real-time image edge enhancement filtering proposed in this invention.

[0042] Figure 3 This is a schematic diagram of the buffer control module of the hardware circuit for real-time image edge enhancement filtering proposed in this invention;

[0043] Figure 4 This is a schematic diagram of one embodiment of the guided filtering operation module of the hardware circuit for real-time image edge enhancement filtering proposed in this invention.

[0044] Figure 5 This is a schematic diagram of one embodiment of the filtering calculation unit of the hardware circuit for real-time image edge enhancement filtering proposed in this invention. Detailed Implementation

[0045] Reference Figures 1-5 The present invention proposes a hardware circuit for real-time image edge enhancement filtering, comprising:

[0046] The input interface module is used to acquire the input video stream signal, which includes frame synchronization signal, line synchronization signal, data valid signal and raw pixel data.

[0047] The buffer control module is used to generate and output an N×N pixel array centered on the current pixel based on the raw pixel data in the video stream signal, where N is an odd number greater than 1.

[0048] In this embodiment, the cache control module includes:

[0049] The synchronization delay unit is used to acquire the original pixel data, delay the original pixel data for multiple clock cycles, and output a horizontal pixel window containing M consecutive pixels, where M is an integer greater than 1.

[0050] Specifically, the synchronization delay unit performs timing delay processing on the input raw pixel data. The input raw pixel data includes a 24-bit RGB signal, which contains a red (R), green (G), and blue (B) component. The synchronization delay unit operates under the drive of a clock signal and outputs the input signal after delaying it by one clock cycle. Through this delay operation, the RGB signal is made time-synchronized with data from other RAMs, thereby ensuring aligned output in subsequent outputs and guaranteeing the synchronization and stability of the data in the pipeline structure.

[0051] The timing generation unit is used to acquire vertical resolution parameters and horizontal resolution parameters, and generate row count signals, column count signals, delayed frame synchronization signals, delayed row synchronization signals, and delayed data validity signals.

[0052] The RAM data path unit includes K cascaded single-row RAMs for caching the raw pixel data line by line. In the RAM data path unit, the data written to the first-level RAM is the raw pixel data, and the data read out is used as the data written to the second-level RAM. The subsequent RAMs are cascaded in sequence, and finally output the cached K consecutive rows of image data.

[0053] The address control unit is used to uniformly generate and distribute read address signals and write address signals for all K single-row RAMs in the RAM data path unit;

[0054] The cache control module combines the horizontal pixel window data output by the synchronization delay unit with the continuous K rows of image data output by the RAM data path unit to form and output an N×N pixel array.

[0055] The guided filtering operation module is used to obtain an N×N pixel array, perform guided filtering calculations on the center pixel in the N×N pixel array, and output the filtered center pixel data.

[0056] like Figure 1As shown, in addition to the input and output video stream signals, the circuit also includes a clock signal i_vclk, a reset signal i_rstn, and several configuration register input signals, including the vertical resolution parameter i_vactive, the horizontal resolution parameter i_hactive, the guided filter window radius parameter i_guide_radius, the smoothing factor parameter i_smooth_value, and the module enable signal i_enable. When the module is not enabled, i.e., i_enable is in an invalid state, the circuit output is directly connected to the input signal, thus putting the circuit in a bypass state. Regarding the module's workflow, the above parameters are first configured through the register interface. When the i_enable signal is set to valid, the circuit starts and enters the working state.

[0057] like Figure 1 and Figure 2 As shown, the buffer control module is used to buffer and manage the single-frame data of the input video stream to meet the pixel array processing requirements of the guided filtering algorithm. The size of the pixel neighborhood is determined by the input parameter i_guide_radius configuration. In this embodiment, the guided filtering algorithm is based on a 3×3, 5×5, or 7×7 pixel neighborhood for operation.

[0058] Specifically, the size of the N×N pixel array is configured through the filter window radius parameter, and at least 3×3, 5×5 or 7×7 pixel arrays are supported.

[0059] In this embodiment, the guided filtering operation module specifically includes:

[0060] The guide image conversion unit is used to obtain the current center pixel data from the N×N pixel array and convert the red, green and blue components in the center pixel data into single-channel guide image data through integer operations.

[0061] In this embodiment, the conversion formula for converting center pixel data into single-channel guide image data in the guide image conversion unit is as follows:

[0062] y×8192=R×2449+G×4809+B×934;

[0063] Where y is the single-channel guide image data; R is the red component of the center pixel data; G is the green component of the center pixel data; and B is the blue component of the center pixel data.

[0064] The filtering calculation unit is used to acquire the guide image data, the original channel pixel data in the N×N pixel array, and the smoothing factor parameter. Within the window defined by the N×N pixel array, it calculates the local mean, local covariance, and local variance of the guide image data and the original channel pixel data, and combines the smoothing factor parameter to output the filtered center pixel data through linear regression calculation.

[0065] In this embodiment, the linear regression calculation performed by the filtering calculation unit is based on the following mathematical relationship:

[0066] ;

[0067] Where I represents the raw pixel data of the input channel; y represents the guide image data of a single channel; The mean of the product of the image data and the raw pixel data of the input channel within the window; To guide the mean of image data within the window; This is the mean of the raw pixel data of the input channel within the window; This is the mean of the squared image data within the window; is the smoothing factor parameter; O is the filtered center pixel data.

[0068] Specifically, in the above formula, the molecule part Represents the local covariance, the denominator part This represents the combination of local variance and a smoothing factor. Through calculation using this linear regression form, input pixels can be adaptively weighted according to the guided image features, effectively achieving edge preservation and noise suppression. In the specific circuit implementation, this part of the logic operation is completed through integer arithmetic units such as addition, subtraction, and pipelined multiplication and division, supporting efficient data processing. With the above hardware architecture, the guided filtering operation module can perform edge-preserving filtering while ensuring real-time image processing, reducing computational resource consumption and improving the system's engineering feasibility.

[0069] Specifically, in the guided filtering operation module, for image boundary regions that cannot form a complete N×N pixel array, the guided filtering operation module uses the center original pixel data of the N×N pixel array obtained from the cache control module to fill all the missing pixel positions in the N×N pixel array to form a complete and computable virtual N×N pixel array, and performs guided filtering calculation on the center pixel of the virtual N×N pixel array.

[0070] The bypass selection module is connected to the input interface module and the guided filtering operation module, respectively. It is used to acquire the original pixel data, the filtered center pixel data and the enable signal in the video stream signal, and select one of the original pixel data and the filtered center pixel data as the final video stream pixel data according to the enable signal.

[0071] Specifically, in the bypass selection module, when the enable signal is in an invalid state, the bypass selection module outputs the raw pixel data from the input interface module; when the enable signal is in an active state, the bypass selection module outputs the filtered center pixel data from the guided filtering operation module.

[0072] In this embodiment, the circuit obtains the enable signal through a D flip-flop. The enable signal pos_vsync of the D flip-flop is obtained by sampling the rising edge of the input signal i_vsync.

[0073] Example 1

[0074] In this embodiment, specifically in terms of hardware implementation, to obtain a pixel array of the corresponding size, it is necessary to additionally cache the preceding 2, 4, or 6 rows of image pixels based on the real-time input of the current row of data. Therefore, this embodiment sets up 6 RAMs in the cache control module, each capable of caching a single row of pixels, to ensure that a pixel matrix that meets the algorithm's requirements can be output. Figure 2 As shown, the input video image data is distributed by the buffer control module and sequentially written to six cascaded single-row RAM blocks. When the number of buffer rows reaches a preset threshold (determined by the parameter i_guide_radius), the buffer control module begins to continuously output the corresponding pixel array to the guided filtering operation module to perform guided filtering calculations. The filtered pixel data is then output to the bypass selection module, which determines whether the output video image data is the original input pixel data or the filtered center pixel data based on the state of the enable signal i_enable.

[0075] like Figure 3 As shown in the diagram, the internal structure of the cache control module can be divided into four parts:

[0076] Synchronization delay unit sync_delay: where sync_delay_n (n=1~7) is used to delay the input signal by n clock cycles to obtain pixel input values ​​for seven consecutive clock cycles, thus corresponding to seven consecutive pixels of the video stream input.

[0077] The timing generation unit, timing_gen, is mainly composed of counter logic. Its function is to generate row count signal o_vdecnt and column count signal o_hdecnt based on the input image row number parameter i_vactive and the number of pixels per row parameter i_hactive, and output video synchronization signals o_vsync, o_hsync, and o_de delayed by two clock cycles.

[0078] RAM data path unit: The input signal rd_data1 is the raw pixel data, which is used as the write data wr_data2 input to RAM2; simultaneously, the read data rd_data2 from RAM2 is used as the write data wr_data3 from RAM3, and so on, with the output of the previous stage RAM serving as the write input to the next stage RAM. Through this step-by-step write and read method, the six RAMs sequentially complete the buffering of consecutive rows of data, thereby obtaining six consecutive rows of pixels in the current frame.

[0079] Address control unit: Figure 3 The read address signal rd_addr and write address signal wr_addr of the RAM are uniformly generated and distributed by the cache control module, thereby ensuring the timing consistency and data integrity of the cache. At this point, the cache control module forms a pixel array window of o_pixel[7×7] at the output end. This window contains the current pixel row input in real time and the previous row pixel data obtained from the cache. This pixel array serves as the input for subsequent guided filtering algorithms, thereby achieving edge preservation and smoothing enhancement of the image.

[0080] Figure 4 This is a schematic diagram of the guided filtering operation module in this embodiment. This module mainly consists of a guided image conversion unit and a filtering calculation unit, as shown below. Figure 4 As shown, the guided image conversion unit is composed of multiple synchronous delay units and multiple gate devices.

[0081] The filtering calculation unit is the logical calculation part of the guided filtering algorithm. The input video stream, after passing through the buffer control module, outputs a pixel array to the filtering calculation unit for filtering calculation processing, and outputs the filtered pixel data filter_pixel[23:0]. Simultaneously, the filtering calculation unit also outputs a set of corner_pixel[23:0] to represent the pixel value at the top left corner of the current pixel array. It should be noted that the guided filtering algorithm only processes the center pixels of the pixel array. For example, when the selected array is 3×3, only the pixel located at position [2,2] in the array is filtered; the remaining boundary pixels are not filtered. Therefore, for the boundary pixels of the image, since a complete 3×3 (or 5×5, 7×7) processing window cannot be formed, this embodiment uses the original pixel value at the corresponding position of the input image for replacement output, i.e., corner_pixel is used as the boundary fill value. For 5×5 or 7×7 arrays, only the center pixels of the array are processed, and the pixels in the image boundary area are compensated in the above manner, such as... Figure 4 As shown in the bottom right corner.

[0082] Furthermore, the output signal o_de of the guided filtering operation module is the output pixel validity signal, used to indicate whether the current output pixel is valid; filter_en is the filter validity signal, used to indicate whether the current output pixel has been processed by the filtering calculation unit. When the filter validity signal filter_en is valid, the output of o_pixel is the filtered filter_pixel; when the filter validity signal filter_en is invalid, the output of o_pixel is the original input corner_pixel.

[0083] Figure 5 This is an internal structure diagram of the filtering calculation unit. Taking a 7×7 RGB pixel array as an example (3×3 and 5×5 are also supported), each channel performs filtering calculations independently.

[0084] The filtering calculation unit mainly consists of two parts: the guide image conversion subunit `guide_image_exchange` and the export filter subunit `guide_filter_form`. The guide image conversion subunit `guide_image_exchange` converts the input color image into a guide image. This part performs the RGB to grayscale conversion according to the following weighted formula:

[0085] y=R×0.299+G×0.587+B×0.114;

[0086] To save hardware resources and avoid floating-point operations, this embodiment approximates the formula by integerization. Specifically, each input component is shifted left by 12 bits before calculation and then right by 12 bits after calculation. This approach significantly reduces the size of the hardware multiplier while maintaining calculation accuracy, thus improving circuit implementation efficiency. The approximate formula is as follows:

[0087] y×8192=R×2449+G×4809+B×934.

[0088] The function of the export filter subunit guide_filter_form is to generate the center pixel data of the corresponding channel after filtering based on the input raw channel pixel data I, guide image data y, and smoothing parameter i_smooth_value.

[0089] Reference Figures 1-5 The present invention proposes an image edge enhancement method, applied to a hardware circuit for real-time image edge enhancement filtering as described above, the method comprising:

[0090] S1. Acquire the input video stream signal, which includes frame synchronization signal, line synchronization signal, data valid signal and raw pixel data;

[0091] S2. Generate and output an N×N pixel array centered on the current pixel based on the original pixel data, where N is an odd number greater than 1;

[0092] S3. Perform guided filtering calculation on the center pixel in the N×N pixel array and output the filtered center pixel data;

[0093] S4. Based on the valid state of the enable signal, select either the original pixel data or the filtered center pixel data as the final video stream pixel data.

[0094] Reference Figures 1-5 The present invention proposes an image display device, including a display screen and a video processing circuit, wherein the video processing circuit includes a hardware circuit for real-time image edge enhancement filtering as described above.

[0095] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A hardware circuit for real-time image edge enhancement filtering, characterized in that, include: The input interface module is used to acquire the input video stream signal, which includes frame synchronization signal, line synchronization signal, data valid signal and raw pixel data. The buffer control module is used to generate and output an N×N pixel array centered on the current pixel based on the raw pixel data in the video stream signal, where N is an odd number greater than 1; The guided filtering operation module is used to obtain an N×N pixel array, perform guided filtering calculations on the center pixel in the N×N pixel array, and output the filtered center pixel data. The bypass selection module is connected to the input interface module and the guided filtering operation module, respectively. It is used to acquire the original pixel data, the filtered center pixel data and the enable signal in the video stream signal, and select one of the original pixel data and the filtered center pixel data as the final video stream pixel data according to the enable signal. Specifically, the guided filtering operation module includes: The guide image conversion unit is used to obtain the current center pixel data from the N×N pixel array, and convert the red, green and blue components in the center pixel data into single-channel guide image data through integer operations; The filtering calculation unit is used to acquire the guide image data, the original channel pixel data in the N×N pixel array, and the smoothing factor parameter. Within the window defined by the N×N pixel array, it calculates the local mean, local covariance, and local variance of the guide image data and the original channel pixel data, and combines the smoothing factor parameter to output the filtered center pixel data through linear regression calculation.

2. The hardware circuit for real-time image edge enhancement filtering according to claim 1, characterized in that, The cache control module includes: The synchronization delay unit is used to acquire the original pixel data, delay the original pixel data for multiple clock cycles, and output a horizontal pixel window containing M consecutive pixels, where M is an integer greater than 1. The timing generation unit is used to acquire vertical resolution parameters and horizontal resolution parameters, and generate row count signals, column count signals, delayed frame synchronization signals, delayed row synchronization signals, and delayed data valid signals; The RAM data path unit includes K cascaded single-row RAMs for caching the raw pixel data line by line. In the RAM data path unit, the data written to the first-level RAM is the raw pixel data, and the data read out is used as the data written to the second-level RAM. The subsequent RAMs are cascaded in sequence, and finally output the cached K consecutive rows of image data. The address control unit is used to uniformly generate and distribute read address signals and write address signals for all K single-row RAMs in the RAM data path unit; The cache control module combines the horizontal pixel window data output by the synchronization delay unit with the continuous K rows of image data output by the RAM data path unit to form and output an N×N pixel array.

3. The hardware circuit for real-time image edge enhancement filtering according to claim 1, characterized in that, In the guided filtering operation module, for image boundary regions that cannot form a complete N×N pixel array, the guided filtering operation module uses the center original pixel data of the N×N pixel array obtained from the cache control module to fill all the missing pixel positions in the N×N pixel array to form a complete and computable virtual N×N pixel array, and performs guided filtering calculation on the center pixel of the virtual N×N pixel array.

4. The hardware circuit for real-time image edge enhancement filtering according to claim 1, characterized in that, In the guide image conversion unit, the conversion formula for converting the center pixel data into single-channel guide image data is as follows: ； Where y is the single-channel guide image data; R is the red component of the center pixel data; G is the green component of the center pixel data; and B is the blue component of the center pixel data.

5. The hardware circuit for real-time image edge enhancement filtering according to claim 1, characterized in that, In the filtering calculation unit, the linear regression calculation performed by the filtering calculation unit is based on the following mathematical relationship: ； Where I represents the raw pixel data of the input channel; y represents the guide image data of a single channel; The mean of the product of the image data and the raw pixel data of the input channel within the window; To guide the mean of image data within the window; This is the mean of the raw pixel data of the input channel within the window; To guide the mean of the squared image data within the window; is the smoothing factor parameter; O is the filtered center pixel data.

6. The hardware circuit for real-time image edge enhancement filtering according to claim 1, characterized in that, In the bypass selection module, when the enable signal is in an invalid state, the bypass selection module outputs the raw pixel data from the input interface module; when the enable signal is in an active state, the bypass selection module outputs the filtered center pixel data from the guided filtering operation module.

7. The hardware circuit for real-time image edge enhancement filtering according to claim 1, characterized in that, The size of the N×N pixel array is configured by the filter window radius parameter, and at least 3×3, 5×5 or 7×7 pixel arrays are supported.

8. An image edge enhancement method, applied to the hardware circuit of real-time image edge enhancement filtering as described in any one of claims 1-7, characterized in that, The method includes: S1. Acquire the input video stream signal, the video stream signal including frame synchronization signal, line synchronization signal, data valid signal and raw pixel data; S2. Generate and output an N×N pixel array centered on the current pixel based on the original pixel data, where N is an odd number greater than 1; S3. Perform guided filtering calculation on the center pixel in the N×N pixel array and output the filtered center pixel data; S4. Based on the valid state of the enable signal, select either the original pixel data or the filtered center pixel data as the final video stream pixel data.

9. An image display device, comprising a display screen and a video processing circuit, characterized in that, The video processing circuit includes the hardware circuit for real-time image edge enhancement filtering as described in any one of claims 1 to 7.

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