A non-volatile semiconductor memory array and a method of in-memory logic operation thereof

Abstract

The application provides a non-volatile semiconductor memory array and a method for in-memory logic operation. In the array, a row of memory cells shares a word line, a column of memory cells shares a bit line and a storage gate lead, the source terminals of every two columns of memory cells are interconnected and connected to the same source lead CSL, and the end of each CSL is provided with a sensitive amplifier SA controlled by an enabling signal. One of the memory cells in every two columns has a substrate split, or the cell is replaced by a DCC cell. The method includes pre-writing, pre-charging, charging and discharging estimation, and judgment and result writing. The input and output are the storage states of different memory cells. The charging and discharging of the parasitic capacitor on the source lead when the memory cell is opened are detected as the input, and the SA is used to make a logic judgment and complete the writing. In one operation, any two-input logic except XOR and XNOR can be realized, and the logic result can be directly used as a logic input to realize cascading. The logic operation has many types, few steps, low difficulty and high efficiency.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor, memory, and CMOS hybrid integrated circuit technology, and more specifically, to a non-volatile semiconductor memory array and its in-memory logic operation method. Background Technology

[0002] With the development of information technology and the increase in data volume and computing power demand, the speed of accessing and transferring data in computer memory has become far slower than the processing speed of the processor, and this difference is gradually widening; the power consumption of accessing memory is also far greater than the power consumption of computing. The traditional von Neumann architecture (i.e., storage and computation are separated) faces the memory wall and power wall, which are becoming bottlenecks limiting further improvements in its computing power and energy efficiency. In-memory computing technology combines storage and computing units into one, performing in-situ computation within the memory array. Compared with the von Neumann architecture, it can reduce data transfer, lower energy consumption, and increase computational parallelism, making it a highly promising computing architecture. In-memory logic technology implements digital logic operations within the memory array and is an important component of in-memory computing architecture.

[0003] In-memory logic, where both inputs and outputs are in memory states, can be directly cascaded within the memory array without requiring the results to be read as voltages or undergo input-output conversion. This type of in-memory logic is one of the most promising. It is typically implemented using emerging non-volatile semiconductor memory devices such as resistive random access memory (RRAM), phase-change memory (PCM), and magnetoresistive memory (MRAM). Its inputs and outputs are both device resistance values. The voltage difference across the output device is controlled by a voltage divider based on the resistance values ​​of the input devices, thus affecting the resistance of the output device and completing the logic operation. Typical technologies include implied (IMP) logic and MAGIC logic based on RRAM. However, the types of logic that can be implemented in the array are often very limited. Logic operations that cannot be implemented in a single operation are constructed by combining implementable logic; for example, implementing XOR logic in RRAM-based IMP in-memory logic requires four IMP operations. This leads to an increase in the number of logic operation steps, increased area overhead, and more complex logic synthesis, resulting in reduced computational efficiency. Summary of the Invention

[0004] This invention proposes a non-volatile semiconductor memory array and its in-memory logic operation method. Its input and output are both storage states of different memory cells. The input is detected by the charging and discharging of parasitic capacitance on the Common Source Line (CSL) when the memory cell is turned on, and the logic judgment is made and the writing is completed by using a sense amplifier (SA). It can realize 14 kinds of two-input logic operations, excluding XOR and XNOR, in a single operation in the array, reducing the difficulty of logic synthesis and improving the computational efficiency.

[0005] The technical solution of the present invention is as follows:

[0006] A non-volatile semiconductor memory array comprises an array of memory cells arranged in a repeating pattern along the horizontal and vertical axes. Each memory cell is composed of a ferroelectric field-effect transistor with a split-gate structure. The split-gate ferroelectric field-effect transistor has a control gate and a storage gate, wherein the storage gate is located at the drain end with a ferroelectric layer below it, and the control gate is located at the source end without a ferroelectric layer below it. The source ends of every two columns of memory cells in the same row are interconnected and connected to the same source lead CSL. The drain ends of the memory cells are connected to the bit line BL, and memory cells in the same column share a single BL. The control gate of each row of memory cells... The memory cells in each column are connected by word lines (WL), with each column sharing a single WL. The memory gates of each column are connected by memory gate leads (ML), with each column sharing a single ML. Each column is equipped with a sensitive amplifier (SA) at its end, and all sensitive amplifiers are controlled by a single sensitive amplifier enable signal (SA_enable). In every two columns, one memory cell has a substrate partition, meaning it does not share a substrate with the other cells and can perform substrate erase operations independently. Each column is equipped with a pre-charge circuit to charge the column to a specific voltage value.

[0007] Furthermore, the memory cell is modified to consist of a transistor and a conventional single-gate ferroelectric field-effect transistor connected in series, wherein the single-gate ferroelectric field-effect transistor corresponds to the memory gate and is located on the bit line BL side, while the transistor corresponds to the control gate and is located on the source lead CSL side.

[0008] Furthermore, in the aforementioned non-volatile semiconductor memory array, the memory cells with substrate partitions in every two columns are replaced with negation cells DCC. The negation cells also have substrate partitions. The negation cell DCC consists of a transistor and a ferroelectric field-effect transistor connected in series. The ferroelectric field-effect transistor corresponds to the memory gate and is located on the bit line BL side, while the transistor corresponds to the control gate and is located on the source lead CSL side. The connection node between the two is connected to the other end of the sensitive amplifier SA through another transistor. The negation cell selection signal DCC Select controls the switching of the transistor. When DCC Select is low and WL where DCC is located is high, the source of the ferroelectric field-effect transistor in DCC is connected to CSL; otherwise, its source is connected to the other end of SA, i.e., the result after CSL is negated.

[0009] Furthermore, the transistor is an N-type field-effect transistor.

[0010] On the other hand, the present invention also proposes an in-memory logic operation method on the above-mentioned non-volatile semiconductor memory array. In the non-volatile semiconductor memory array, in every two columns of memory cells interconnected at the source ends and sharing a source lead CSL, two non-substrate-divided memory cells in the same row are selected as logic input memory cells for the logic operation, denoted as A and B from left to right. A substrate-divided memory cell or a NOT cell DCC is selected as the logic output memory cell for the logic operation, denoted as C. The method includes the following steps:

[0011] The first step is to apply a write voltage to the substrate electrode of C to prewrite C as '0'.

[0012] The second step is to start the pre-charge circuit on the CSL where C is located, and pre-charge the parasitic capacitance of the CSL until the CSL has a specified voltage value. When performing NOT, NAND, OR, implied, and reverse implied logic operations, the pre-charge target voltage value is lower than the SA judgment threshold. When performing cloning, AND, OR, implied NOT, and reverse implied NOT logic operations, the pre-charge target voltage value is higher than the SA judgment threshold.

[0013] The third step is to turn off the pre-charge circuit, apply a gating voltage to WL where A and B are located to open the control gates of A and B, and apply a specific voltage (high level or low level) to BL where A and B are located. After holding for a specific time, WL and BL are restored to low level. At this time, if A or B stores a '1' state, the voltage on the corresponding BL will charge or discharge the parasitic capacitance of CSL, causing the CSL voltage to change gradually over time, and perform the estimation operation.

[0014] The fourth step is to set SA_Enable to a high level to enable SA. At the same time, a write voltage is applied to BL and ML where C is located, and a gating voltage is applied to WL where C is located to enable the control gate of C. When SA is enabled, a CSL voltage greater than the SA judgment threshold will cause SA to set CSL, i.e., the source of C, to a high level, so that C cannot be written and remains in the '0' state of pre-writing. Conversely, a CSL voltage less than the SA judgment threshold will cause SA to set CSL, i.e., the source of C, to a low level, so that C is written to the '1' state.

[0015] Furthermore, in the third step of the above steps, when performing OR and AND operations, both A and B are at a low level in BL; when performing NOR and NAND operations, both A and B are at a high level in BL; when performing implied, reverse implied, implied NOT, and reverse implied NOT logic, one of A and B is at a high level and the other is at a low level in BL; the holding time of the voltage pulse depends on the type of logic operation. When performing AND and NAND logic, the holding time is shorter, and the CSL voltage only exceeds the SA judgment threshold when A and B units are turned on at the same time and form two charging and discharging paths. When performing other logic operations, the holding time is longer, and one or more charging and discharging paths are sufficient to make the CSL voltage exceed the SA judgment threshold.

[0016] Furthermore, when performing in-memory logic operations on the aforementioned non-volatile semiconductor memory array including the NOT cell DCC using the aforementioned in-memory logic operation method, the first step of the in-memory logic operation method remains unchanged. In the second step, when performing NOT, NAND, NOR, implied, and reverse implied logic operations, a pre-charge voltage higher than the SA judgment threshold is used instead, while the remaining logic operations remain unchanged. In the third step, the NOT, NAND, NOR, implied, and reverse implied operations determine the BL voltage and hold time according to the cloning, AND, OR, implied NOT, and reverse implied NOT logic, respectively. The first step is to perform the initial valuation, while the rest of the logic operations remain unchanged. In the fourth step, when performing NOT, NAND, NOR, implication, and reverse implication logic operations, the gating voltage is no longer applied to WL of the NOT unit C, but to DCCSelect. The source of the ferroelectric field-effect transistor in C is connected to the other end of SA. Its voltage value after SA is turned on is the result of the CSL voltage passing through the inverter. If CSL is eventually high, the source is low, and C is written to the '1' state. Otherwise, C remains in the '0' state. The rest of the logic operations remain unchanged.

[0017] Furthermore, in the in-memory logic operation method, the SA judgment threshold is half of the power supply voltage.

[0018] The technical effects of this invention are as follows:

[0019] (1) This invention can realize any two-input logic except XOR and XNOR in one operation. The logic result can be directly used as logic input to realize cascading without input-output conversion. It can also be operated in parallel in the entire array, with high parallelism. Moreover, if multiple WLs can be enabled at the same time, it also has the potential to realize multi-input logic. Compared with traditional cascaded in-memory logic, it can realize more types of logic, reduce the average number of logic operation steps, reduce the difficulty of logic synthesis, and increase computational efficiency.

[0020] (2) The state of the storage unit used as logical input does not change during the logical operation process described in this invention. It is a non-destructive operation and does not require read-write.

[0021] (3) The present invention makes little modification to the memory array circuit. The circuit structure is similar to that of a ferroelectric field effect transistor array used only for storage. The area increment is small and the storage density is high. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the non-volatile semiconductor memory array structure in this invention;

[0023] Figure 2 This is a schematic diagram of the non-volatile semiconductor memory array structure with NOT cells in this invention;

[0024] Figure 3 This is a schematic diagram of the in-memory logic operation steps in this invention;

[0025] Figure 4 This is a schematic diagram of the in-memory logic operation steps with NOT in this invention;

[0026] Figure 5 This is a schematic diagram illustrating the implementation principle of the in-memory logic in this invention. Detailed Implementation

[0027] The present invention will be further clearly and completely described below with reference to the accompanying drawings and specific embodiments.

[0028] The non-volatile semiconductor memory array structure of the present invention is as follows: Figure 1As shown, an array of memory cells is arranged in a repeating pattern along the horizontal and vertical axes. Each memory cell can be composed of a ferroelectric field-effect transistor with a split-gate structure. Each ferroelectric field-effect transistor has a control gate and a storage gate. The storage gate is located at the drain end with a ferroelectric layer underneath, while the control gate is located at the source end without a ferroelectric layer underneath. The remaining components are similar to those of a conventional ferroelectric field-effect transistor. The source ends of every two columns of memory cells are interconnected and connected to the same source lead (CSL). The drain ends of the memory cells are connected to the bit line (BL), and memory cells in the same column share a single BL. The control gate of each row of memory cells is connected by a word line (WL), and memory cells in the same row share a single WL. The storage gates of each column of memory cells are connected by a storage gate lead (ML), and memory cells in the same column share a single ML. Each CSL is equipped with a sensitive amplifier (SA) at its end, and all sensitive amplifiers are controlled by a single sensitive amplifier enable signal (SA_enable). One memory cell in every two columns has a substrate split; this cell does not share a substrate with the other cells and can perform substrate erase operations independently. Each CSL is equipped with a pre-charge circuit that can charge the CSL to a specific voltage value; the pre-charge circuit and its control signals are omitted in the array structure diagram for clarity.

[0029] Optionally, the memory cell of the present invention can also be composed of a transistor and a conventional single-gate ferroelectric field-effect transistor connected in series, or other similar structures. The single-gate ferroelectric field-effect transistor corresponds to the memory gate and is located on the bit line BL side, while the transistor corresponds to the control gate and is located on the source lead CSL side.

[0030] Optionally, such as Figure 2 As shown, this invention employs an array structure with dual-contact cells (DCCs) to achieve better performance in band-NOT logic. Each pair of columns in the array contains substrate-divided memory cells serving as negation cells. Each negation cell consists of a transistor on the CSL side and a ferroelectric field-effect transistor on the BL side connected in series. The connection point between the two is connected to the other end of the SA via another transistor. The negation cell select signal (DCC Select) controls the switching of this transistor. The negation cell also features substrate division. When DCC Select is low and WL (where DCC is located) is high, the source of the ferroelectric field-effect transistor in DCC is connected to the CSL; conversely, its source is connected to the other end of the SA, i.e., the result after negation of the CSL. The remaining components of this array are similar to... Figure 1 The arrays shown are the same.

[0031] One method of operating on in-memory logic is as follows: Figure 3 As shown. A and B refer to the storage units used as inputs, while C refers to the storage unit used as the logic output. If using... Figure 1The array structure shown represents a memory cell with substrate partitioning; if using Figure 2 In the array structure shown, C is the negation cell. A and B should be located in the same row and on the same CSL.

[0032] The first step is to apply a write voltage to the C substrate electrode alone to prewrite C as '0'.

[0033] The second step is to activate the pre-charge circuit on the CSL where C is located, and pre-charge the parasitic capacitance of the CSL until the CSL has a specified voltage value (V). CSL =V pre When performing NOT, NAND, OR, implied, and reverse implied logic operations, the pre-charge target voltage value is lower than the SA judgment threshold. When performing cloning, AND, OR, implied NOT, and reverse implied NOT logic operations, the pre-charge target voltage value is higher than the SA judgment threshold.

[0034] The third step is to disable the pre-charge circuit, apply a gating voltage to WL at points A and B to open the control gates of A and B, and apply a specific voltage (high or low level) to BL at points A and B. After holding this voltage for a specific time, WL and BL are returned to low level. During OR and AND operations, both BL at points A and B are applied low level; during NOR and NAND operations, both BL at points A and B are applied high level; during implication, inverse implication, implication NOT, and inverse implication NOT logic, one BL at point A and B is applied high level, and the other is applied low level. For example... Figure 5 As shown, the holding time of the voltage pulse depends on the type of logic operation. During AND and NAND logic operations, the holding time is shorter; the CSL voltage only exceeds the SA threshold when cells A and B are simultaneously activated, forming two charging / discharging paths. For other logic operations, the holding time is longer; one or more charging / discharging paths are sufficient for the CSL voltage to exceed the SA threshold. At this time, if A or B stores a '1' state, the voltage on BL will charge or discharge the parasitic capacitance of CSL, causing the CSL voltage to gradually change over time, thus performing an estimation operation. The formula for this step in the figure reflects the CSL voltage (V... CSL The relationship between V and time, where V A V B These refer to the voltage values ​​of the voltage lines where A and B are located, respectively, and C. A G B These refer to the equivalent conductance between the source and drain of memory cells A and B at this time.

[0035] The fourth step is to set SA_enable high to enable SA, simultaneously applying a write voltage to BL and ML where C is located, and applying a gating voltage to WL where C is located to enable the control gate of C. When SA is enabled, if the CSL voltage (V... CSL The voltage is greater than the SA threshold, which is half of the power supply voltage (V). DD / 2), SA will set the source of CSL, i.e., C, to a high level (V'). CSL =V DD If there is insufficient voltage difference between the storage gate and channel of C to change the polarization state of the ferroelectric layer, C cannot be written to and remains in the pre-written '0' state. Conversely, if the CSL voltage is less than the SA judgment threshold (half of the power supply voltage), the SA will set the CSL, i.e., the source of C, to a low level (V'). CSL =0), since the voltage drop at the drain of C is mainly on the drain side of the channel, the voltage in the C channel is close to the source voltage, i.e., low level. The voltage difference between its storage gate and the channel is close to the write voltage, which is sufficient to change the polarization state of the ferroelectric layer, and C is written to the '1' state. During the writing of C, the control gates of other storage cells that share ML and BL with C are not opened, so the channel is only connected to the drain and separated from the source, and its voltage is close to the drain voltage. Since the voltage applied to the drain, i.e., BL, is equal to that of ML, the voltage difference across the ferroelectric layer of these storage cells is very small, and the state is almost unaffected. Therefore, the crosstalk of the in-memory logic operation can be ignored.

[0036] Optionally, the SA (Self-Assessment) threshold can be set to other values, rather than being limited to half the power supply voltage. This example uses a threshold of half the power supply voltage.

[0037] It should be noted that, in Figure 3 Used Figure 2 The array structure shown is used as an example, while using Figure 1 The array structure shown can achieve the same function by following the same steps, without exceeding the scope of the present invention.

[0038] Optionally, use Figure 2 When performing logical operations on the array structure shown, the NOT, NAND, NOR, implication, and inverse implication logic can be implemented in a different way to achieve better performance. The specific steps are as follows: Figure 4 As shown. The first step remains unchanged. In the second step, when performing NOT, NAND, NOR, implication, and reverse implication logic operations, a pre-charge voltage (V) higher than the SA judgment threshold is used instead. pre The rest remains unchanged. In the third step, the NOT, NAND, NOR, implied, and reverse implied logic determine the BL voltage and hold time according to the clone, AND, OR, implied NOT, and reverse implied NOT logic, respectively, and perform estimation. In the fourth step, the gating voltage is no longer applied to WL of the NOT unit C, but to DCC Select. The source of the ferroelectric field-effect transistor in C is connected to the other end of SA. Its voltage value after SA is turned on is equivalent to the result of CSL voltage passing through the inverter. If CSL is eventually high, the source is low, and C is written to the '1' state; otherwise, C remains in the '0' state. Figure 4 The meaning of the Chinese formula and Figure 3 Same as above.

[0039] The specific implementation principles of each logical operation are as follows: Figure 5 As shown in the figure, the CSL voltage changes over time during the estimation and judgment phases under different input conditions. In AND and OR logic, the pre-charge voltage (V) pre ) higher than the SA judgment threshold (V) DD / 2), BL is connected to low level (V A =V B =0), when A or B is stored in the '1' state, CSL discharges during the evaluation phase. The discharge speed is faster when both A and B are '1' than when only one is '1'. If an appropriate evaluation time (t) is set... AND This ensures that the CSL voltage drops below the SA judgment threshold only when both A and B are '1', in which case the final state of C is AAND B. If this estimation time (t) is extended... OR If either A or B is '1', the CSL voltage can drop below the SA judgment threshold, then the final state of C is AORB. The principle of data cloning / copying is the same as AND and OR.

[0040] Similarly, in NAND and NOR logic, if the precharge voltage is lower than the SA threshold, BL is connected to a high level (V). A =V B =V DD A or B charges CSL during the valuation phase while storing the '1' state. This can be achieved by setting different valuation times (t). NAND or t NOR This ensures that CSL is sufficiently charged only when both A and B are '1', implementing NAND logic, and also ensures that the CSL voltage is above the SA judgment threshold when only one of them is '1', implementing NOR logic. The principle of data negation is the same as NAND and NOR. In addition, as explained above, NAND, NOR, and negation can all be implemented using DCC.

[0041] In the implied (IMP) logic, if the pre-charge voltage is less than the SA judgment threshold, a high level (V) is applied to the BL where A is located during the evaluation phase. A =V DD When BL is located at B, a low level (V) is applied. B =0); When A is '1', CSL is charged, and when B is '1', CSL is discharged. When both A and B are '1', the charging and discharging currents almost cancel each other out, and the CSL voltage changes very little. Therefore, CSL can only be effectively charged to a voltage higher than the SA judgment threshold when A is '1' and B is '0', so that C can be written as '1'. In other cases, C remains '0'. By swapping A and B, we get the inverse implication (CIMP) logic.

[0042] Similarly, when the pre-charge voltage is greater than the SA judgment threshold and the bit line voltages (V) of A and B are... A V B When these are interchanged, implied NOT (NIMP) and inverse implied NOT (C-NIMP) logic can be implemented respectively. Furthermore, both logics can also be implemented using DCC.

[0043] To implement XOR logic, first execute the IMP logic to set C to AIMPB. Then, without pre-writing, execute the CIMP logic. If A is '0' and B is '1', write C to '1'; otherwise, C retains AIMP B. Thus, C eventually becomes '1' when A and B are different, otherwise C retains the pre-written '0'. XNOR can be similarly constructed from AND and NAND, or obtained by negating XOR in the DCC unit.

[0044] It should be noted that, Figure 5 The CSL voltage change shown in the diagram is only illustrated in terms of direction; the actual CSL voltage change process is different. Figure 5 The differences are as follows, but the direction of change and the relative rate of change are the same. Figure 5 It matches the Chinese standard.

[0045] If the voltage conditions described above are applied simultaneously to multiple sets of CSL, ML, and BL in the array, multiple sets of inputs can be processed simultaneously within the same row, i.e., multiple logic operations can be executed in parallel. The types of logic operations executed in parallel are the same, and each CSL, i.e., each pair of storage cells, corresponds to a set of input-output combinations. The operating principle and effect of each pair of storage cells are the same as described above, and will not be detailed here.

[0046] The above images and text descriptions all use ferroelectric field-effect transistors with split-gate structures as storage cells, and the transistors are N-type field-effect transistors. However, changing the specific structure of the storage cell or the type of transistor does not exceed the scope of this invention. For example, charge-capture memories such as flash memory are also possible.

[0047] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.

Claims

1. A non-volatile semiconductor memory array, comprising an array of memory cells arranged repeatedly along a horizontal and vertical direction, wherein each memory cell is composed of a ferroelectric field-effect transistor with a split-gate structure, the ferroelectric field-effect transistor having a control gate and a storage gate respectively, wherein the storage gate is located at the drain end and has a ferroelectric layer below it, and the control gate is located at the source end and has no ferroelectric layer below it; characterized in that, The source terminals of every two columns of memory cells in the same row are interconnected and connected to the same source lead CSL, and the drain terminals of the memory cells are connected to the bit line BL. Memory cells in the same column share one BL. The control gate of each row of memory cells is connected by the word line WL, and memory cells in the same row share one WL. The memory gate of each column of memory cells is connected by the memory gate lead ML, and memory cells in the same column share one ML. Each CSL is equipped with a sensitive amplifier SA at its end, and all sensitive amplifiers are controlled by a sensitive amplifier enable signal SA_enable. In every two columns of memory cells, one memory cell has a substrate partition and does not share a substrate with the other memory cells. Each CSL is equipped with a pre-charge circuit to charge the CSL to a specific voltage value.

2. The non-volatile semiconductor memory array as described in claim 1, characterized in that, The memory cell is changed to be composed of a transistor and a conventional single-gate ferroelectric field-effect transistor connected in series. The single-gate ferroelectric field-effect transistor corresponds to the memory gate and is located on the bit line BL side, while the transistor corresponds to the control gate and is located on the source lead CSL side.

3. The non-volatile semiconductor memory array as described in claim 1 or 2, characterized in that, In the array, the memory cells with substrate partitions in every two columns are replaced with NOT cells DCC. The NOT cells also have substrate partitions. The NOT cell DCC consists of a transistor and a ferroelectric field-effect transistor connected in series. The ferroelectric field-effect transistor corresponds to the memory gate and is located on the bit line BL side, while the transistor corresponds to the control gate and is located on the source lead CSL side. The connection node between the two is connected to the other end of the sensitive amplifier SA through another transistor. The NOT cell selection signal DCC Select controls the switching of the transistor.

4. The non-volatile semiconductor memory array as described in claim 3, characterized in that, The transistor is an N-type field-effect transistor.

5. A method for in-memory logic operation on a non-volatile semiconductor memory array as described in any one of claims 1, 2, 3, or 4, characterized in that, In the non-volatile semiconductor memory array, in every two columns of memory cells interconnected at the source and sharing a single source lead CSL, two non-substrate-divided memory cells in the same row are selected as logic input memory cells for logic operations, denoted as A and B from left to right. A substrate-divided memory cell or a NOT cell DCC is selected as the logic output memory cell for logic operations, denoted as C. The method includes the following steps: The first step is to apply a write voltage to the substrate electrode of C to prewrite C as '0'. The second step is to start the pre-charge circuit on the CSL where C is located, and pre-charge the parasitic capacitance of the CSL until the CSL has a specified voltage value. When performing NOT, NAND, OR, implied, and reverse implied logic operations, the pre-charge target voltage value is lower than the SA judgment threshold. When performing cloning, AND, OR, implied NOT, and reverse implied NOT logic operations, the pre-charge target voltage value is higher than the SA judgment threshold. The third step is to turn off the pre-charge circuit, apply a gating voltage to WL where A and B are located to open the control gates of A and B, and apply a specific voltage (high level or low level) to BL where A and B are located. After holding for a specific time, WL and BL are restored to low level. At this time, if A or B stores a '1' state, the voltage on the corresponding BL will charge or discharge the parasitic capacitance of CSL, causing the CSL voltage to change gradually over time, thus performing the estimation operation. The fourth step is to set SA_enable to a high level to enable SA. At the same time, a write voltage is applied to BL and ML where C is located, and a gating voltage is applied to WL where C is located to enable the control gate of C. When SA is enabled, a CSL voltage greater than the SA judgment threshold will cause SA to set CSL, i.e., the source of C, to a high level, so that C cannot be written and remains in the '0' state of pre-writing. Conversely, a CSL voltage less than the SA judgment threshold will cause SA to set CSL, i.e., the source of C, to a low level, so that C is written to the '1' state.

6. The in-memory logic operation method as described in claim 5, characterized in that, In the third step of the method, when performing OR or AND operations, both A and B are at a low level in BL; when performing NOR or NAND operations, both A and B are at a high level in BL; when performing implied, reverse implied, implied NOT, or reverse implied NOT logic, one of A and B is at a high level and the other is at a low level in BL. The holding time of the voltage pulse depends on the type of logic operation. When performing AND or NAND logic, the holding time is short, and the CSL voltage exceeds the SA judgment threshold only when A and B units are turned on at the same time and form two charging and discharging paths. When performing other logic operations, the holding time is long, and one or more charging and discharging paths are sufficient to make the CSL voltage exceed the SA judgment threshold.

7. The in-memory logic operation method as described in claim 6, characterized in that, When performing in-memory logic operations on the non-volatile semiconductor memory array as described in claim 3, the first step of the in-memory logic operation method remains unchanged. In the second step, when performing NOT, NAND, NOR, implied, and reverse implied logic operations, a pre-charge voltage higher than the SA judgment threshold is used instead, while the remaining logic operations remain unchanged. In the third step, the NOT, NAND, NOR, implied, and reverse implied logic operations determine the BL voltage and hold time according to the clone, AND, OR, implied NOT, and reverse implied NOT logic respectively, and perform estimation, while the remaining logic operations remain unchanged. In the fourth step, when performing NOT, NAND, NOR, implied, and reverse implied logic operations, the gating voltage is no longer applied to WL of the NOT cell C, but to DCC Select, connecting the source of the ferroelectric field-effect transistor in C to the other end of SA. Its voltage value after SA is turned on is the result of the CSL voltage passing through the inverter. If CSL is ultimately high, the source is low, and C is written to the '1' state; otherwise, C remains in the '0' state. The remaining logic operations remain unchanged.

8. The in-memory logic operation method as described in any one of claims 5, 6, or 7, characterized in that, The SA (Self-Assessment) threshold is half of the power supply voltage.

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