Clock signal frequency conversion circuit, chip and electronic device

Abstract

The present disclosure relates to a clock signal frequency conversion circuit, a chip and an electronic device, the clock signal frequency conversion circuit comprising: a delay chain module configured to obtain a reference clock signal, delay the reference clock signal to generate a plurality of same-frequency clock signals with different phases; and a signal extraction and output module coupled to the delay chain module, configured to receive the plurality of same-frequency clock signals, extract a plurality of signal segments from the plurality of same-frequency clock signals according to received configuration information, and obtain and output a frequency conversion clock signal associated with the configuration information according to the extracted plurality of signal segments. The present disclosure achieves the purpose of reducing the delay in the clock signal frequency conversion process, and the purpose of fine-grained frequency conversion of the clock signal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a clock signal frequency conversion circuit, a chip and an electronic device. BACKGROUND

[0002] In modern integrated circuits, a PLL (Phase Lock Loop) is an important core technology for realizing high-quality clock generation, frequency synthesis and synchronization, and the frequency conversion of the PLL is a key means for realizing high performance, high stability and high flexibility of frequency control. A frequency divider is a basic module for realizing multi-frequency output and feedback control in the PLL. The PLL and the frequency divider work together to support the efficient operation of the complex clock system inside the chip and integrated circuit.

[0003] In the related art, the frequency conversion of the PLL is achieved by changing the feedback coefficient of the PLL through the frequency divider to change the output clock frequency of the PLL after locking, but the clock frequency relocking of the PLL takes a long time, for example, the clock frequency relocking of the PLL may take tens of microseconds when the output clock frequency of the PLL is in the order of kHz to MHz. The long time consumption of the clock frequency relocking may not meet the demand of fast response of high-frequency clock, and in addition, during the clock frequency relocking, the output clock frequency of the PLL is very unstable, which may easily cause timing problems and lead to the crash of the integrated circuit or chip.

[0004] In the related art, there is also a means for realizing the frequency conversion of the clock signal by using the delay control of the timer, which usually introduces a large delay due to the use of the timer. SUMMARY

[0005] Therefore, the present disclosure provides a clock signal frequency conversion circuit, a chip and an electronic device to reduce the delay in the clock signal frequency conversion process and realize fine-grained frequency conversion of the clock signal.

[0006] The technical solution of the present disclosure is implemented as follows:

[0007] According to an aspect of an embodiment of the present disclosure, a clock signal frequency conversion circuit is provided, comprising:

[0008] a delay chain module configured to obtain a reference clock signal and delay the reference clock signal to generate a plurality of same-frequency clock signals with different phases;

[0009] a signal extraction and output module coupled to the delay chain module, configured to receive the plurality of same-frequency clock signals, extract a plurality of signal segments from the plurality of same-frequency clock signals according to received configuration information, and obtain and output a frequency conversion clock signal associated with the configuration information according to the extracted plurality of signal segments.

[0010] In a possible implementation, the delay chain module comprises:

[0011] a plurality of delay units, the plurality of delay units being connected in series to form the delay chain module, wherein a clock signal output end of a previous delay unit is coupled to a clock signal input end of a next delay unit between two adjacent delay units connected in series, and a clock signal input end of a first delay unit in the plurality of delay units receives the reference clock signal;

[0012] wherein the output end of each delay unit generates a same-frequency clock signal with a different phase.

[0013] In a possible implementation, the delay chain module further comprises:

[0014] a flip-flop, the clock signal input end of the first delay unit receives the reference clock signal through the flip-flop, wherein a clock signal input end of the flip-flop receives the reference clock signal, and the clock signal input end of the first delay unit is coupled to an output end of the flip-flop.

[0015] In a possible implementation, the signal extraction and output module comprises:

[0016] a plurality of signal extraction sub-modules, the plurality of signal extraction sub-modules being coupled to the delay chain module, and the plurality of signal extraction sub-modules respectively receiving one of the plurality of same-frequency clock signals one by one, each signal extraction sub-module being configured to extract a signal segment from the received same-frequency clock signal according to configuration information received thereby;

[0017] a signal combination and output sub-module, the signal combination and output sub-module being coupled to the plurality of signal extraction sub-modules, configured to receive the signal segments extracted by the plurality of signal extraction sub-modules, and combine the received signal segments to obtain and output the variable-frequency clock signal.

[0018] In a possible implementation, the signal extraction sub-module comprises:

[0019] an enable signal generation unit, the enable signal generation unit being coupled to the delay chain module, configured to receive the same-frequency clock signal and configuration information, and generate an enable signal according to the received same-frequency clock signal and configuration information;

[0020] an AND gate unit, two input ends of the AND gate unit being respectively coupled to the enable signal generation unit and the delay chain module, configured to receive the same-frequency clock signal and the enable signal, and obtain the signal segment according to the same-frequency clock signal and the enable signal.

[0021] In a possible implementation, the enable signal generation unit comprises:

[0022] a count comparison sub-unit, coupled to the delay chain module, configured to receive the same-frequency clock signal and configuration information, count the period of the same-frequency clock signal based on the configuration information, and generate the enable signal when the count reaches a count value required by the configuration information.

[0023] In a possible implementation, the signal combination output sub-module comprises:

[0024] a plurality of input OR gates, each input of the plurality of input OR gates being coupled to each of the signal extraction sub-modules, configured to receive the signal segments extracted by the plurality of signal extraction sub-modules, and output the frequency-converted clock signal at the output of the plurality of input OR gates.

[0025] In a possible implementation, the signal combination output sub-module comprises:

[0026] a plurality of cascaded OR gate units, each input of a primary plurality of OR gate units of the plurality of cascaded OR gate units being coupled to each of the signal extraction sub-modules, an output of a previous OR gate unit of two adjacent OR gate units of the plurality of cascaded OR gate units being coupled to an input of a subsequent OR gate unit, the number of the subsequent OR gate unit being less than the number of the previous OR gate unit, and the number of the plurality of cascaded OR gate units being one, an output of a final OR gate unit of the plurality of cascaded OR gate units outputting the frequency-converted clock signal.

[0027] In a possible implementation, the clock signal frequency conversion circuit further comprises:

[0028] a configuration unit, coupled to the signal extraction output module, configured to generate the configuration information.

[0029] In a possible implementation, the clock signal frequency conversion circuit further comprises:

[0030] a phase-locked loop circuit, coupled to the delay chain module, configured to generate the reference clock signal.

[0031] According to another aspect of the embodiments of the present disclosure, a chip is provided, which employs the clock signal frequency conversion circuit according to any one of the above.

[0032] According to another aspect of the embodiments of the present disclosure, an electronic device is provided, which comprises the chip according to the above.

[0033] It can be seen from the above scheme that the clock signal frequency conversion circuit of the present disclosure can be used in the clock circuit design in the integrated circuit. It has the characteristics of high clock frequency adjustment precision. By using the clock signal frequency conversion circuit, chip and electronic device of the present disclosure, the adjustment step of the frequency conversion clock signal can be controlled in a very small range, even reaching the MHz level, and fine adjustment of the MHz level can be realized. Among them, the smaller the delay of the delay unit in the delay chain module to the clock signal, the more the number of delay units, and the more dense the layout, the smaller the granularity of the adjustable clock signal step, so that the required clock frequency can be obtained flexibly and accurately within the set clock range.

[0034] In addition, the clock signal frequency conversion circuit of the present disclosure also has the advantage of fast response speed. Compared with the clock frequency division or frequency multiplication mechanism of the related art, the clock signal frequency conversion circuit of the present disclosure helps to improve the adjustment speed of the frequency conversion clock signal. The related art usually relies on a timer for delay control, and then the trigger signal takes effect. This way will introduce a large delay due to the timer. The clock signal frequency conversion circuit of the present disclosure can be implemented in a full hardware manner, and the response process is almost delay-free, so that the real-time performance and efficiency of clock adjustment can be greatly improved. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 is a clock signal frequency conversion circuit schematic diagram according to an illustrative embodiment;

[0036] Figure 2 is a structure schematic diagram of a signal extraction submodule according to an illustrative embodiment;

[0037] Figure 3 is a timing schematic diagram of a certain same frequency clock signal and an enable signal and a signal segment associated with the same frequency clock signal according to an illustrative embodiment;

[0038] Figure 4A is an application scenario structure schematic diagram of a delay chain module using ten levels of delay according to an illustrative embodiment;

[0039] Figure 4B is an application scenario structure schematic diagram of a signal extraction output module using ten-way extraction signal segments according to an illustrative embodiment;

[0040] Figure 5 is a signal timing schematic diagram of an application scenario of a delay chain module using ten levels of delay according to an illustrative embodiment. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical scheme and advantages of the present disclosure clearer, the following will make a further detailed description of the present disclosure with reference to the drawings and examples.

[0042] It should be noted that the terms "first", "second", and the like in the description and claims of the present disclosure and the above drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0043] As used in the description and claims of the present disclosure, "coupled (or connected)" can refer to any direct or indirect connection means, for example, a first device is coupled (or connected) to a second device, which should be interpreted as the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means.

[0044] As described above, in the related art, the frequency conversion of the PLL is achieved by changing the feedback coefficient of the PLL through the frequency divider to change the output clock frequency of the PLL after locking, but the clock frequency relocking of the PLL takes a long time, so the long time consumption of the clock frequency relocking can not meet the demand of the high-frequency clock for fast response, and during the clock frequency relocking, the output clock frequency of the PLL is very unstable, which can easily cause timing problems and lead to the crash of the integrated circuit or chip. At the same time, the means of using the timer for delay control to achieve the frequency conversion of the clock signal usually introduces a large delay due to the use of the timer.

[0045] In addition, the means of using the timer for delay control to achieve the frequency conversion of the clock signal usually has a large granularity for the frequency conversion of the clock signal, and it is difficult to achieve fine adjustment of the frequency of the clock signal, and it is usually only suitable for large-scale adjustment of the basic clock frequency, but it is difficult to perform small-range correction of the clock signal.

[0046] Therefore, the embodiments of the present disclosure provide a clock signal frequency conversion circuit, a chip and an electronic device, which first change the phase of a reference clock signal to obtain a plurality of same-frequency signals with different phases, then pick up the required clock signal edge from the same-frequency signals with different phases according to the required output clock frequency, so as to constitute the required frequency conversion clock signal, achieve the purpose of reducing the delay in the clock signal frequency conversion process, and achieve the purpose of fine-grained frequency conversion of the clock signal.

[0047] Figure 1 is a clock signal frequency conversion circuit schematic diagram according to an illustrative embodiment, as shown in Figure 1As shown, the clock signal frequency conversion circuit mainly includes a delay chain module 1 and a signal extraction and output module 2. The delay chain module 1 is used to acquire a reference clock signal and delay it to generate multiple clock signals with different phases at the same frequency. The signal extraction and output module 2, coupled to the delay chain module 1, receives the multiple clock signals at the same frequency, extracts multiple signal segments from them according to the received configuration information, and obtains and outputs a frequency conversion clock signal associated with the configuration information based on the extracted signal segments.

[0048] The clock signal frequency conversion circuit of this embodiment delays the reference clock signal through the delay chain module 1 to generate multiple clock signals with different phases at the same frequency. Since the reference clock signal is transmitted in real time in the delay chain module 1, the multiple clock signals with different phases at the same frequency are also generated in real time. In this process, there is no delay caused by PLL relocking or timer delay control. Furthermore, since the multiple clock signals with different phases at the same frequency are generated in real time, the signal extraction output module 2 extracts multiple signal segments from the multiple clock signals at the same frequency in real time. Consequently, the frequency conversion clock signal obtained based on the extracted multiple signal segments is also generated in real time. Therefore, in the process from the reference clock signal to the obtained frequency conversion clock signal, the clock signal frequency conversion circuit of this embodiment does not produce delays caused by PLL relocking or timer delay control, thereby helping to reduce the delay in the clock signal frequency conversion process. Meanwhile, because the clock signal frequency conversion circuit of this embodiment uses the delay chain module 1 to generate multiple clock signals with different phases, the phase difference (or phase adjustment step size) between the multiple clock signals with the same frequency can be adjusted or set within a very small range. Based on this, the frequency difference between the frequency conversion clock signal obtained by extracting multiple signal segments and the reference clock signal can be even smaller, thereby achieving the purpose of high clock frequency adjustment accuracy. Therefore, the clock signal frequency conversion circuit of this embodiment can achieve the purpose of flexibly and accurately obtaining the required clock frequency within the set clock range.

[0049] like Figure 1 As shown in the illustrative embodiment, in order to obtain multiple clock signals with different phases at the same frequency, the delay chain module 1 includes multiple delay units 11. The multiple delay units 11 are connected in series to form the delay chain module 1, wherein, between two adjacent delay units 11 connected in series, the preceding delay unit 11 (e.g., ...) Figure 1 The clock signal output terminal of the left delay unit 11 in two adjacent delay units 11 is coupled to the next stage delay unit 11 (e.g., Figure 1 The clock signal input terminal of the right delay unit 11 in two adjacent delay units 11, and the first stage delay unit 11 in multiple delay units 11 (e.g.Figure 1 The clock signal input end of the leftmost delay unit 11 among all the delay units 11 receives a reference clock signal. The output ends of the respective delay units 11 respectively generate same-frequency clock signals with different phases.

[0050] In order to eliminate clock jitter and glitches and improve the stability of the delay chain module 1, as shown in the illustrative embodiment, the delay chain module 1 further comprises a flip-flop 12. The clock signal input end of the first-stage delay unit 11 (for example, the leftmost delay unit 11 among all the delay units 11) receives the reference clock signal through the flip-flop 12, wherein the clock signal input end of the flip-flop 12 receives the reference clock signal, and the clock signal input end of the first-stage delay unit 11 is coupled to the output end of the flip-flop 12. Figure 1 Figure 1 In order to eliminate clock jitter and glitches and improve the stability of the delay chain module 1, as shown in the illustrative embodiment, the delay chain module 1 further comprises a flip-flop 12. The clock signal input end of the first-stage delay unit 11 (for example, the leftmost delay unit 11 among all the delay units 11) receives the reference clock signal through the flip-flop 12, wherein the clock signal input end of the flip-flop 12 receives the reference clock signal, and the clock signal input end of the first-stage delay unit 11 is coupled to the output end of the flip-flop 12.

[0051] In the illustrative embodiment, the flip-flop 12 is composed of a D flip-flop and an inverter. The clock signal input end of the D flip-flop receives the reference clock signal, the input end of the inverter is coupled to the positive output end (Q end) of the D flip-flop, the output end of the inverter is coupled to the input end (D end) of the D flip-flop, and the clock signal input end of the first-stage delay unit 11 is coupled to the positive output end (Q end) of the D flip-flop.

[0052] In the illustrative embodiment, the flip-flop 12 comprises a D flip-flop. The clock signal input end of the D flip-flop receives the reference clock signal, the input end (D end) of the D flip-flop is coupled to the inverted output end (non-Q end) of the D flip-flop, and the clock signal input end of the first-stage delay unit 11 is coupled to the positive output end (Q end) of the D flip-flop.

[0053] As shown in the illustrative embodiment, in order to obtain a variable-frequency clock signal based on a plurality of same-frequency clock signals, in the illustrative embodiment, the signal extraction output module 2 comprises a signal extraction sub-module 21 and a signal combination output sub-module 22. The signal extraction sub-module 21 is multiple, the multiple signal extraction sub-modules 21 are coupled to the delay chain module 1, and the multiple signal extraction sub-modules 21 respectively receive one-to-one a plurality of same-frequency clock signals. Each signal extraction sub-module 21 is used to extract a signal segment from the received same-frequency clock signal according to the configuration information received thereby. The signal combination output sub-module 22 is coupled to the multiple signal extraction sub-modules 21, used to receive the signal segments extracted by the multiple signal extraction sub-modules 21, and combine the received signal segments to obtain and output a variable-frequency clock signal. Figure 1

[0054] The structure of the signal extraction sub-module according to an illustrative embodiment is shown in the structural diagram of the signal extraction sub-module, as shown in the illustrative embodiment, Figure 2 Figure 2 ​​As shown, in an exemplary embodiment, the signal extraction sub-module 21 comprises an enable signal generation unit 211 and an AND gate unit 212. The enable signal generation unit 211 is coupled to the delay chain module 1 for receiving the same frequency clock signal and the configuration information, and generating the enable signal according to the received same frequency clock signal and the configuration information. The two inputs of the AND gate unit 212 are coupled to the enable signal generation unit 211 and the delay chain module 1 respectively for receiving the same frequency clock signal and the enable signal, and obtaining the signal segment according to the same frequency clock signal and the enable signal.

[0055] Further, in order to generate the enable signal according to the received same frequency clock signal and the configuration information, as shown, Figure 2 As shown, in an exemplary embodiment, the enable signal generation unit 211 comprises a count comparison sub-unit 2111. The count comparison sub-unit 2111 is coupled to the delay chain module 1 for receiving the same frequency clock signal and the configuration information, counting the period of the same frequency clock signal based on the configuration information, and generating the enable signal when the count reaches the count value required by the configuration information. In an exemplary embodiment, the configuration information at least comprises a count threshold, which can be configured in a CCR (Capture / Compare Register) of the count comparison sub-unit 2111 for example. In an exemplary embodiment, the configuration information can further comprise at least one of a reset signal (RST) and an enable signal (EN). The reset signal is used to clear the count of the count comparison sub-unit 2111. The enable signal is used to enable the operation of the count comparison sub-unit 2111. When the enable signal is valid (e.g. the enable signal is high), the count comparison sub-unit 2111 operates to count the period of the same frequency clock signal, and generates the enable signal when the count reaches the count threshold. When the enable signal is invalid (e.g. the enable signal is low), the count comparison sub-unit 2111 stops operating, and in an exemplary embodiment, only outputs a low signal when the count comparison sub-unit 2111 stops operating.

[0056] Figure 3 is a timing diagram of a certain same frequency clock signal, and the enable signal and the signal segment associated with the same frequency clock signal according to an exemplary embodiment. As shown, Figure 3 and in combination with Figure 2 As shown, for a certain same frequency clock signal, the count comparison sub-unit 2111 receives the same frequency clock signal and the configuration information, wherein the configuration information is used to set the count threshold. The count comparison sub-unit 2111 counts the period of the received same frequency clock signal, and generates the enable signal when the count reaches the count threshold (i.e. the count reaches the count value required by the configuration information). In an exemplary embodiment, the enable signal is high, for example, Figure 3As shown, the counting threshold is 5. The counting comparison subunit 2111 performs periodic counting on the received same-frequency clock signal. When the count reaches 5, that is, when the same-frequency clock signal reaches the 5th cycle, an enable signal is generated.

[0057] In an illustrative embodiment, the counting comparison subunit 2111 can count cyclically, and the maximum value of the count can exceed the counting threshold. In a specific embodiment, the maximum value of the count can be, for example, 9, and the minimum value can be, for example, 0. After counting from 0 to 9, the counting comparison subunit 2111 starts counting from 0 again. Taking a counting threshold of 5 as an example, an enable signal is generated each time the counting comparison subunit 2111 counts to 5.

[0058] In an illustrative embodiment, when the count in the counting comparison subunit 2111 exceeds the counting threshold, the generation of the enable signal (low level) is stopped.

[0059] like Figure 2 , Figure 3 As shown, a clock signal generated by the delay chain module 1 is sent to a counting comparison subunit 2111. The clock signal is used as the clock signal (CK signal) of the counting comparison subunit 2111 and is input to the counting comparison subunit 2111. In the illustrative embodiment, the relevant parameters (i.e., the configuration information of the counting comparison subunit 2111) of the counting comparison subunit 2111 can be set by the MCU (microcontroller). The parameters include a reset signal, an enable signal, and a counting threshold. The counting threshold can be stored in the CCR of the output comparison counting subunit of the counting comparison subunit 2111. When the count value of the counting comparator subunit 2111 is equal to the counting threshold (i.e., the value stored in CCR), the counting comparator subunit 2111 outputs an effective level (high level) as the enable signal of the subsequent AND gate unit 212 (i.e., input to one input terminal of the subsequent AND gate unit 212). When the count value of the counting comparator subunit 2111 is not equal to (e.g., less than or greater than) the counting threshold, the counting comparator subunit 2111 outputs an invalid level (low level) to the subsequent AND gate unit 212.

[0060] To obtain and output a frequency-converted clock signal from multiple extracted signal segments, in an illustrative embodiment, the signal combination output submodule 22 may include a multi-input OR gate. Each input of the multi-input OR gate is coupled to each signal extraction submodule 21 to receive the signal segments extracted by the multiple signal extraction submodules 21 and output the frequency-converted clock signal at the output of the multi-input OR gate.

[0061] In order to obtain and output the variable frequency clock signal according to the extracted multiple signal segments, in an illustrative embodiment, the signal combination output sub-module 22 comprises a plurality of cascaded OR gate units. Each input end of the primary plurality of OR gate units in the plurality of cascaded OR gate units is respectively coupled to each signal extraction sub-module 21, between two adjacent levels of OR gate units in the plurality of cascaded OR gate units, the output end of the former level of OR gate units is coupled to the input end of the latter level of OR gate units, and the number of the latter level of OR gate units is less than the number of the former level of OR gate units, and the last OR gate unit in the plurality of cascaded OR gate units is one, and the output end of the last OR gate unit outputs the variable frequency clock signal.

[0062] In the case of obtaining and outputting the variable frequency clock signal according to the extracted multiple signal segments by using the above two ways, i.e., the multi-input OR gate or the plurality of OR gate units, when any one of the signal extraction sub-modules 21 sends out a signal segment, i.e., outputs the corresponding signal segment. Based on the configuration information received by each signal extraction sub-module 21 (each count comparison sub-unit 2111), each signal extraction sub-module 21 (each count comparison sub-unit 2111) can in turn send out its own signal segment to the signal combination output sub-module 22. These signal segments can be equally spaced in time sequence. In this way, the signal combination output sub-module 22 can output these signal segments which can be equally spaced in time sequence in turn through its multi-input OR gate or the plurality of OR gate units, forming a variable frequency clock signal.

[0063] In an illustrative embodiment, the signal segment is a high-level signal, and the duration of the high-level signal is half a period of the reference clock signal.

[0064] In an illustrative embodiment, in order to realize the setting of the configuration information, in an illustrative embodiment, the clock signal variable frequency circuit can further comprise a configuration unit. The configuration unit is coupled to the signal extraction output module 2 and is used to generate configuration information. The configuration unit can exist in the form of software or hardware.

[0065] The clock signal variable frequency circuit of the embodiments of the present disclosure can realize fine tuning of the frequency of the clock signal, and the clock signal can be generated by a phase-locked loop. Based on this, in an illustrative embodiment, the clock signal variable frequency circuit of the embodiments of the present disclosure can further comprise a phase-locked loop circuit. The phase-locked loop circuit is coupled to the delay chain module 1 and is used to generate a reference clock signal.

[0066] The clock signal variable frequency circuit of the embodiments of the present disclosure will be described below in combination with a specific application scenario.

[0067] Figure 4A is a structure schematic diagram of an application scenario of a delay chain module using ten levels of delay according to an illustrative embodiment, Figure 4BFigure 1 is a schematic diagram of an application scenario of a signal extraction output module employing a ten-channel extracted signal segment according to an illustrative embodiment.

[0068] As Figure 4AAs shown, in this application scenario, the delay chain module 1 includes a D flip-flop DFF, an inverter INV, a first-stage delay unit Dlc01, a second-stage delay unit Dlc02, a third-stage delay unit Dlc03, a fourth-stage delay unit Dlc04, a fifth-stage delay unit Dlc05, a sixth-stage delay unit Dlc06, a seventh-stage delay unit Dlc07, an eighth-stage delay unit Dlc08, a ninth-stage delay unit Dlc09, and a tenth-stage delay unit Dlc10. The clock input terminal ck of the D flip-flop DFF receives a reference clock signal Base CLK, which can be generated by a phase-locked loop circuit in a previous stage. The input terminal and the output terminal of the inverter INV are coupled to the Q terminal and the D terminal of the D flip-flop DFF, respectively, to form a T flip-flop. The first-stage delay unit Dlc01 to the tenth-stage delay unit Dlc10 have the same structure. The input terminal of the first-stage delay unit Dlc01 is coupled to the Q terminal of the D flip-flop DFF, the input terminal of the second-stage delay unit Dlc02 is coupled to the output terminal of the first-stage delay unit Dlc01, the input terminal of the third-stage delay unit Dlc03 is coupled to the output terminal of the second-stage delay unit Dlc02, the input terminal of the fourth-stage delay unit Dlc04 is coupled to the output terminal of the third-stage delay unit Dlc03, the input terminal of the fifth-stage delay unit Dlc05 is coupled to the output terminal of the fourth-stage delay unit Dlc04, the input terminal of the sixth-stage delay unit Dlc06 is coupled to the output terminal of the fifth-stage delay unit Dlc05, the input terminal of the seventh-stage delay unit Dlc07 is coupled to the output terminal of the sixth-stage delay unit Dlc06, the input terminal of the eighth-stage delay unit Dlc08 is coupled to the output terminal of the seventh-stage delay unit Dlc07, the input terminal of the ninth-stage delay unit Dlc09 is coupled to the output terminal of the eighth-stage delay unit Dlc08, and the input terminal of the tenth-stage delay unit Dlc10 is coupled to the output terminal of the ninth-stage delay unit Dlc09. Furthermore, the output terminal of the first-stage delay unit Dlc01 generates a first same-frequency clock signal Clk01, the output terminal of the second-stage delay unit Dlc02 generates a second same-frequency clock signal Clk02, the output terminal of the third-stage delay unit Dlc03 generates a third same-frequency clock signal Clk03, the output terminal of the fourth-stage delay unit Dlc04 generates a fourth same-frequency clock signal Clk04, the output terminal of the fifth-stage delay unit Dlc05 generates a fifth same-frequency clock signal Clk05, the output terminal of the sixth-stage delay unit Dlc06 generates a sixth same-frequency clock signal Clk06, the output terminal of the seventh-stage delay unit Dlc07 generates a seventh same-frequency clock signal Clk07, the output terminal of the eighth-stage delay unit Dlc08 generates an eighth same-frequency clock signal Clk08, the output terminal of the ninth-stage delay unit Dlc09 generates a ninth same-frequency clock signal Clk09, and the output terminal of the tenth-stage delay unit Dlc10 generates a tenth same-frequency clock signal Clk10.The output terminal of the 10th delay unit Dlc10 generates a 10th same-frequency clock signal Clk10. The 1st delay unit Dlc01 to the 10th delay unit Dlc10 are of the same structure, and the 1st same-frequency clock signal Clk01 to the 10th same-frequency clock signal Clk10 are of the same frequency and different phases. Since the 1st delay unit Dlc01 to the 10th delay unit Dlc10 are of the same structure, the phase difference between the same-frequency clock signals generated by any two adjacent delay units 11 in the delay chain is equal, that is, the phase difference between the 1st same-frequency clock signal Clk01 and the 2nd same-frequency clock signal Clk02, the phase difference between the 2nd same-frequency clock signal Clk02 and the 3rd same-frequency clock signal Clk03, and the phase difference between the 9th same-frequency clock signal Clk09 and the 10th same-frequency clock signal Clk10 are all equal, or in other words, the delay of the 2nd same-frequency clock signal Clk02 relative to the 1st same-frequency clock signal Clk01, the delay of the 3rd same-frequency clock signal Clk03 relative to the 2nd same-frequency clock signal Clk02, and the delay of the 10th same-frequency clock signal Clk10 relative to the 9th same-frequency clock signal Clk09 are all equal. In the embodiment of the present disclosure, this equal phase difference or equal delay can also be referredally be referred to as a step.

[0069] As Figure 4B and in combination Figure 1As shown, in this application scenario, the signal extraction output module 2 includes ten signal extraction sub-modules 21 and a signal combination output sub-module 22, and the signal combination output sub-module 22 is in the form of a plurality of cascaded OR cell units. Among them, the ten signal extraction sub-modules include a first signal extraction sub-module, a second signal extraction sub-module, a third signal extraction sub-module, a fourth signal extraction sub-module, a fifth signal extraction sub-module, a sixth signal extraction sub-module, a seventh signal extraction sub-module, an eighth signal extraction sub-module, a ninth signal extraction sub-module, and a tenth signal extraction sub-module. Among them, the first signal extraction sub-module includes a first enable signal generation unit EGU01 and a first AND gate unit AND01, the second signal extraction sub-module includes a second enable signal generation unit EGU02 and a second AND gate unit AND02, the third signal extraction sub-module includes a third enable signal generation unit EGU03 and a third AND gate unit AND03, the fourth signal extraction sub-module includes a fourth enable signal generation unit EGU04 and a fourth AND gate unit AND04, the fifth signal extraction sub-module includes a fifth enable signal generation unit EGU05 and a fifth AND gate unit AND05, the sixth signal extraction sub-module includes a sixth enable signal generation unit EGU06 and a sixth AND gate unit AND06, the seventh signal extraction sub-module includes a seventh enable signal generation unit EGU07 and a seventh AND gate unit AND07, the eighth signal extraction sub-module includes an eighth enable signal generation unit EGU08 and an eighth AND gate unit AND08, the ninth signal extraction sub-module includes a ninth enable signal generation unit EGU09 and a ninth AND gate unit AND09, and the tenth signal extraction sub-module includes a tenth enable signal generation unit EGU10 and a tenth AND gate unit AND10.

[0070] As Figure 4B and in combination Figure 4A and Figure 1As shown, in the 1st signal extraction sub-module, the 1st enable signal generation unit EGU01 is coupled to the output terminal of the 1st stage delay unit Dlc01 in the delay chain module 1 to receive the 1st same frequency clock signal Clk01, and the 1st signal extraction sub-module receives the 1st configuration information CFG01 (the 1st configuration information CFG01 can be derived from a configuration unit, for example, and the configuration signal line is coupled to the configuration unit) through a configuration signal line, the 1st enable signal generation unit EGU01 is used to receive the 1st same frequency clock signal Clk01 and the 1st configuration information CFG01, and generate the 1st enable signal EN01 according to the 1st same frequency clock signal Clk01 and the 1st configuration information CFG01; in the 2nd signal extraction sub-module, the 2nd enable signal generation unit EGU02 is coupled to the output terminal of the 2nd stage delay unit Dlc02 in the delay chain module 1 to receive the 2nd same frequency clock signal Clk02, and the 2nd signal extraction sub-module receives the 2nd configuration information CFG02 through a configuration signal line, the 2nd enable signal generation unit EGU02 is used to receive the 2nd same frequency clock signal Clk02 and the 2nd configuration information CFG02, and generate the 2nd enable signal EN02 according to the 2nd same frequency clock signal Clk02 and the 2nd configuration information CFG02; and so on, the 3rd enable signal generation unit EGU03 receives the 3rd same frequency clock signal Clk03 and the 3rd configuration information CFG03 and generates the 3rd enable signal EN03, the 4th enable signal generation unit EGU04 receives the 4th same frequency clock signal Clk04 and the 4th configuration information CFG04 and generates the 4th enable signal EN04, the 5th enable signal generation unit EGU05 receives the 5th same frequency clock signal Clk05 and the 5th configuration information CFG05 and generates the 5th enable signal EN05, the 6th enable signal generation unit EGU06 receives the 6th same frequency clock signal Clk06 and the 6th configuration information CFG06 and generates the 6th enable signal EN06, the 7th enable signal generation unit EGU07 receives the 7th same frequency clock signal Clk07 and the 7th configuration information CFG07 and generates the 7th enable signal EN07, the 8th enable signal generation unit EGU08 receives the 8th same frequency clock signal Clk08 and the 8th configuration information CFG08 and generates the 8th enable signal EN08, the 9th enable signal generation unit EGU09 receives the 9th same frequency clock signal Clk09 and the 9th configuration information CFG09 and generates the 9th enable signal EN09, and the 10th enable signal generation unit EGU10 receives the 10th same frequency clock signal Clk10 and the 10th configuration information CFG10 and generates the 10th enable signal EN10.

[0071] As Figure 4BAs shown, the first enable signal generating unit EGU01 includes a first count comparison subunit CNT01 coupled to the output terminal of the first delay unit Dlc01 in the delay chain module 1 to receive the first same frequency clock signal Clk01 and the first count comparison subunit CNT01 receives the first configuration information CFG01 through the configuration signal line, the first count comparison subunit CNT01 counts the period of the first same frequency clock signal Clk01, generates the first enable signal EN01 (so that the first enable signal EN01 is valid) when the count reaches the count value required by the first configuration information CFG01, and does not generate the first enable signal EN01 (so that the first enable signal EN01 is invalid) when the count does not reach or exceeds the count value required by the first configuration information CFG01; the second enable signal generating unit EGU02 includes a second count comparison subunit CNT02 coupled to the output terminal of the second delay unit Dlc02 in the delay chain module 1 to receive the second same frequency clock signal Clk02 and the second count comparison subunit CNT02 receives the second configuration information CFG02 through the configuration signal line, the second count comparison subunit CNT02 counts the period of the second same frequency clock signal Clk02, generates the second enable signal EN02 (so that the second enable signal EN02 is valid) when the count reaches the count value required by the second configuration information CFG02, and does not generate the second enable signal EN022 (so that the second enable signal EN02 is invalid) when the count does not reach or exceeds the count value required by the second configuration information CFG02; by analogy, the third enable signal generating unit EGU03 includes a third count comparison subunit CNT03, the third count comparison subunit CNT03 counts the period of the third same frequency clock signal Clk03, generates the third enable signal EN03 (so that the third enable signal EN03 is valid) when the count reaches the count value required by the third configuration information CFG03, and does not generate the third enable signal EN03 (so that the third enable signal EN03 is invalid) when the count does not reach or exceeds the count value required by the third configuration information CFG03; the fourth enable signal generating unit EGU04 includes a fourth count comparison subunit CNT04, the fourth count comparison subunit CNT04 counts the period of the fourth same frequency clock signal Clk04, generates the fourth enable signal EN04 (so that the fourth enable signal EN04 is valid) when the count reaches the count value required by the fourth configuration information CFG04, and does not generate the fourth enable signal EN04 (so that the fourth enable signal EN04 is invalid) when the count does not reach or exceeds the count value required by the fourth configuration information CFG04.The 5th enable signal generating unit EGU05 includes a 5th counting comparison sub-unit CNT05 which counts the period of the 5th same frequency clock signal Clk05, generates the 5th enable signal EN05 (makes the 5th enable signal EN05 valid) when the count reaches the count value required by the 5th configuration information CFG05, and does not generate the 5th enable signal EN05 (makes the 5th enable signal EN05 invalid) when the count does not reach or exceeds the count value required by the 5th configuration information CFG05; the 6th enable signal generating unit EGU06 includes a 6th counting comparison sub-unit CNT06 which counts the period of the 6th same frequency clock signal Clk06, generates the 6th enable signal EN06 (makes the 6th enable signal EN06 valid) when the count reaches the count value required by the 6th configuration information CFG06, and does not generate the 6th enable signal EN06 (makes the 6th enable signal EN06 invalid) when the count does not reach or exceeds the count value required by the 6th configuration information CFG06; the 7th enable signal generating unit EGU07 includes a 7th counting comparison sub-unit CNT07 which counts the period of the 7th same frequency clock signal Clk07, generates the 7th enable signal EN07 (makes the 7th enable signal EN07 valid) when the count reaches the count value required by the 7th configuration information CFG07, and does not generate the 7th enable signal EN07 (makes the 7th enable signal EN07 invalid) when the count does not reach or exceeds the count value required by the 7th configuration information CFG07; the 8th enable signal generating unit EGU08 includes an 8th counting comparison sub-unit CNT08 which counts the period of the 8th same frequency clock signal Clk08, generates the 8th enable signal EN08 (makes the 8th enable signal EN08 valid) when the count reaches the count value required by the 8th configuration information CFG08, and does not generate the 8th enable signal EN08 (makes the 8th enable signal EN08 invalid) when the count does not reach or exceeds the count value required by the 8th configuration information CFG08; the 9th enable signal generating unit EGU09 includes a 9th counting comparison sub-unit CNT09 which counts the period of the 9th same frequency clock signal Clk09, generates the 9th enable signal EN09 (makes the 9th enable signal EN09 valid) when the count reaches the count value required by the 9th configuration information CFG09, and does not generate the 9th enable signal EN09 (makes the 9th enable signal EN09 invalid) when the count does not reach or exceeds the count value required by the 9th configuration information CFG09.The 10th enable signal generating unit EGU10 comprises a 10th count comparison sub-unit CNT10, which counts the period of the 10th same frequency clock signal Clk10, and generates the 10th enable signal EN10 (so that the 10th enable signal EN10 is valid) when the count reaches the count value required by the 10th configuration information CFG10, and does not generate the 10th enable signal EN10 (so that the 10th enable signal EN10 is invalid) when the count does not reach or exceeds the count value required by the 10th configuration information CFG10.

[0072] As shown in Figure 4B and in combination with Figure 4A The two input terminals of the 1st AND gate unit AND01 are coupled to the output terminals of the 1st enable signal generating unit EGU01 and the 1st stage delay unit Dlc01 in the delay chain module 1 respectively, so as to receive the 1st same frequency clock signal Clk01 and the 1st enable signal EN01, and obtain the 1st signal segment Seg_clk01 according to the 1st same frequency clock signal Clk01 and the 1st enable signal EN01; the two input terminals of the 2nd AND gate unit AND02 are coupled to the output terminals of the 2nd enable signal generating unit EGU02 and the 2nd stage delay unit Dlc02 in the delay chain module 1 respectively, so as to receive the 2nd same frequency clock signal Clk02 and the 2nd enable signal EN02, and obtain the 2nd signal segment Seg_clk02 according to the 2nd same frequency clock signal Clk02 and the 2nd enable signal EN02; in the same way, the 3rd AND gate unit AND03 obtains the 3rd signal segment Seg_clk03 according to the 3rd same frequency clock signal Clk03 and the 3rd enable signal EN03; the 4th AND gate unit AND04 obtains the 4th signal segment Seg_clk04 according to the 4th same frequency clock signal Clk04 and the 4th enable signal EN04; the 5th AND gate unit AND05 obtains the 5th signal segment Seg_clk05 according to the 5th same frequency clock signal Clk05 and the 5th enable signal EN05; the 6th AND gate unit AND06 obtains the 6th signal segment Seg_clk06 according to the 6th same frequency clock signal Clk06 and the 6th enable signal EN06; the 7th AND gate unit AND07 obtains the 7th signal segment Seg_clk07 according to the 7th same frequency clock signal Clk07 and the 7th enable signal EN07; the 8th AND gate unit AND08 obtains the 8th signal segment Seg_clk08 according to the 8th same frequency clock signal Clk08 and the 8th enable signal EN08; the 9th AND gate unit AND09 obtains the 9th signal segment Seg_clk09 according to the 9th same frequency clock signal Clk09 and the 9th enable signal EN09; and the 10th AND gate unit AND10 obtains the 10th signal segment Seg_clk10 according to the 10th same frequency clock signal Clk10 and the 10th enable signal EN10.

[0073] Based on the above description, for one of the first to tenth count comparison sub-units CNT01 to CNT10, after the corresponding received same frequency clock signal is pulled high, the corresponding AND gate unit outputs a valid high level at the next rising edge of the same frequency clock signal, and the high level is pulled low (to form a signal segment) when the corresponding received same frequency clock signal is pulled low. For example, for the first count comparison sub-unit CNT01, after the received first same frequency clock signal Clk01 is pulled high, the corresponding first AND gate unit AND01 outputs a valid high level at the next rising edge of the first same frequency clock signal Clk01, and the high level is pulled low (to form the first signal segment Seg_clk01) when the received first same frequency clock signal Clk01 of the first count comparison sub-unit CNT01 is pulled low.

[0074] As shown in Figure 4B , in the signal combination output sub-module 22, the specific connection mode of the cascaded multiple OR gate units ORcell can include multiple modes, for example Figure 4B As shown in the figure, the first signal segment Seg_clk01 and the second signal segment Seg_clk02 are input into a primary OR gate unit ORcell, the third signal segment Seg_clk03 and the fourth signal segment Seg_clk04 are input into a primary OR gate unit ORcell, the fifth signal segment Seg_clk05 and the sixth signal segment Seg_clk06 are input into a primary OR gate unit ORcell, the seventh signal segment Seg_clk07 and the eighth signal segment Seg_clk08 are input into a primary OR gate unit ORcell, the ninth signal segment Seg_clk09 and the tenth signal segment Seg_clk10 are input into a primary OR gate unit ORcell, the output end of each two OR gate units ORcell in the primary OR gate units ORcell is connected to the two input ends of a secondary OR gate unit ORcell, and so on, until there is only one OR gate unit ORcell in the last stage, and the OR gate unit ORcell in the last stage outputs the converted clock signal Converted_CLK.

[0075] Figure 5 is a signal timing diagram of an application scenario of a delay chain module using ten levels of delay according to an illustrative embodiment. As Figure 5 and in combination with Figure 4A , Figure 4BAs shown, the reference clock signal Base CLK is sequentially passed through the 1st stage delay unit Dlc01 to the 10th stage delay unit Dlc10 to obtain the 1st same frequency clock signal Clk01 to the 10th same frequency clock signal Clk10, and the same time is sequentially delayed, the step length of the delay between any adjacent two same frequency clock signals is equal, or it can also be said that the phase difference between any adjacent two same frequency clock signals is equal.

[0076] In this application scenario, it is assumed that the counting starts from 0, and the maximum value of the counting is 9, that is, each signal extraction submodule 21 (each counting comparison subunit 2111) counts 10 cycles, and when the counting value reaches 9, the counting starts from 0 again.

[0077] The 1st configuration information CFG01 sets the counting threshold of the 1st signal extraction submodule (the 1st counting comparison subunit CNT01) to 0, that is, the 1st configuration information CFG01 configures the 1st signal extraction submodule (the 1st counting comparison subunit CNT01) to generate an enable signal when the clock period of the 1st same frequency clock signal Clk01 reaches 0 (that is, the 0th period, associated with the 0th period of the reference clock signal Base CLK); the 2nd configuration information CFG02 sets the counting threshold of the 2nd signal extraction submodule (the 2nd counting comparison subunit CNT02) to 1, that is, the 2nd configuration information CFG02 configures the 2nd signal extraction submodule (the 2nd counting comparison subunit CNT02) to generate an enable signal when the clock period of the 2nd same frequency clock signal Clk02 reaches 1 (that is, the 1st period, associated with the 1st period of the reference clock signal Base CLK); and so on. The 10th configuration information CFG10 sets the counting threshold of the 10th signal extraction submodule (the 10th counting comparison subunit CNT10) to 9, that is, the 10th configuration information CFG10 configures the 10th signal extraction submodule (the 10th counting comparison subunit CNT10) to generate an enable signal when the clock period of the 10th same frequency clock signal Clk10 reaches 9 (that is, the 9th period, associated with the 9th period of the reference clock signal Base CLK).

[0078] Based on this, the 1st enable signal EN01 enables the output of the 1st signal segment Seg_clk01 when the clock period of the 1st same frequency clock signal Clk01 reaches 0, the 2nd enable signal EN02 enables the output of the 2nd signal segment Seg_clk02 when the clock period of the 2nd same frequency clock signal Clk02 reaches 1, the 3rd enable signal EN03 enables the output of the 3rd signal segment Seg_clk03 when the clock period of the 3rd same frequency clock signal Clk03 reaches 2, the 4th enable signal EN04 enables the output of the 4th signal segment Seg_clk04 when the clock period of the 4th same frequency clock signal Clk04 reaches 3, the 5th enable signal EN05 enables the output of the 5th signal segment Seg_clk05 when the clock period of the 5th same frequency clock signal Clk05 reaches 4, the 6th enable signal EN06 enables the output of the 6th signal segment Seg_clk06 when the clock period of the 6th same frequency clock signal Clk06 reaches 5, the 7th enable signal EN07 enables the output of the 7th signal segment Seg_clk07 when the clock period of the 7th same frequency clock signal Clk07 reaches 6, the 8th enable signal EN08 enables the output of the 8th signal segment Seg_clk08 when the clock period of the 8th same frequency clock signal Clk08 reaches 7, the 9th enable signal EN09 enables the output of the 9th signal segment Seg_clk09 when the clock period of the 9th same frequency clock signal Clk09 reaches 8, and the 10th enable signal EN10 enables the output of the 10th signal segment Seg_clk10 when the clock period of the 10th same frequency clock signal Clk10 reaches 9.

[0079] Because the 2nd same frequency clock signal Clk02 has a one-step delay compared to the 1st same frequency clock signal Clk01, the 2nd signal segment Seg_clk02 (high level) has an additional one-step delay in addition to being delayed by one period compared to the 1st signal segment Seg_clk01 (high level), so the time (one period of the converted clock signal Converted CLK) between the start time of the 1st signal segment Seg_clk01 and the start time of the 2nd signal segment Seg_clk02 is extended by one step compared to one period of the reference clock signal Base CLK. Similarly, it can be seen that each period of the converted clock signal Converted CLK is extended by one step compared to one period of the reference clock signal Base CLK, thus realizing frequency reduction of the reference clock signal Base CLK. Furthermore, the delay step can be set in a small range, such as a preset fine adjustment step range, by the setting of the delay unit 11, thus realizing fine control of the frequency reduction of the reference clock signal and fine adjustment of the frequency of the clock signal.

[0080] In the illustrative embodiment, the signal segment refers to a segment of high level signal extracted from the same frequency clock signal, and if the signal segment and low level of other time segments are integrated, the signal segment and low level of other time segments can constitute a narrow pulse signal that changes periodically. For example Figure 5 In the illustration, the first signal segment Seg clk01 is a segment of high level signal in the output signal of the first signal extraction submodule.

[0081] It should be noted that, Figure 5 Only for the purpose of illustrating the relevant timing relationship segment, and for the purpose of clearly presenting this feature, the timing is illustrative and not actual, Figure 5 The timing shown may not exist in reality, and the delay in reality may be very subtle, so the embodiment of the present disclosure can realize fine and fine-grained frequency conversion adjustment of the clock signal.

[0082] In the illustrative embodiment, according to different designs, the implementation of at least one of the delay chain module 1 and the signal extraction output module 2 can be a combination of multiple hardware (hardware), firmware (firmware), software (software, i.e. program).

[0083] In the form of hardware, at least one of the delay chain module 1 and the signal extraction output module 2 can be implemented on the logic circuit of the integrated circuit (integrated circuit), for example, the related functions of at least one of the delay chain module 1 and the signal extraction output module 2 can be implemented in one or more hardware controllers (hardware controller), microcontrollers (Microcontroller), hardware processors (hardware processor), microprocessors (Microprocessor), application-specific integrated circuits (Application-Specific Integrated Circuit, ASIC), digital signal processors (Digital Signal Processor, DSP), field programmable logic gate arrays (Field Programmable Gate Array, FPGA), central processing units (Central Processing Unit, CPU) or other processing units Various logic blocks, modules and circuits. The related functions of at least one of the delay chain module 1 and the signal extraction output module 2 can be implemented as hardware circuits, such as various logic blocks, modules and circuits in integrated circuits, using hardware description languages (hardware description languages, such as Verilog HDL or VHDL) or other suitable programming languages.

[0084] In software or firmware form, the functions of at least one of the delay chain module 1 and the signal extraction and output module 2 can be implemented as programming codes. For example, at least one of the delay chain module 1 and the signal extraction and output module 2 is implemented using a general programming language (e.g., C, C++, or assembly language) or other suitable programming language. The programming codes can be recorded, stored in a "non-transitory machine-readable storage medium". In some embodiments, the non-transitory machine-readable storage medium includes, for example, a semiconductor memory and / or a storage device. An electronic device (e.g., a CPU, a hardware controller, a microcontroller, a hardware processor, or a microprocessor) can read and execute the programming codes from the non-transitory machine-readable storage medium, thereby implementing the functions of at least one of the delay chain module 1 and the signal extraction and output module 2.

[0085] In illustrative embodiments, the clock signal conversion circuit according to the present disclosure is applicable to a SoC chip, etc., where the SoC chip can be any one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), a NPU (Neural network Processing Unit), a DPU (Deep learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Unit).

[0086] In illustrative embodiments, a chip is also provided, which employs (includes) the clock signal conversion circuit according to any one of the above embodiments.

[0087] In illustrative embodiments, an electronic device is also provided, which includes the chip according to the above.

[0088] In the running process of the clock signal frequency conversion circuit, the chip and the electronic device, because the reference clock signal is continuously present, the plurality of same frequency clock signals generated by the delay chain module are also continuously and stably present, in the process of obtaining the frequency conversion clock signal from the plurality of same frequency clock signals by the signal extraction and output module, the frequency conversion clock signal relocking time is only affected by the circuit delay change of the signal extraction and output module, and the signal extraction and output module does not have the alignment process in multiple dimensions such as phase, frequency, charge, voltage and noise as required by the negative feedback closed loop cycle of the PLL, but obtains the frequency division clock signal according to the extracted signal segment, so the relocking time of the PLL frequency division process is saved, therefore, the frequency conversion response speed of the clock signal is improved, and the frequency conversion granularity of the frequency conversion clock signal is finer.

[0089] The clock signal frequency conversion circuit can be used for clock circuit design in an integrated circuit. The clock signal frequency conversion circuit has the characteristics of high clock frequency adjustment precision. By using the clock signal frequency conversion circuit, the chip and the electronic device, the adjustment step of the frequency conversion clock signal can be controlled in a very small range, even reaching the MHz level, and fine adjustment of the MHz level can be realized. The smaller the delay of the delay unit in the delay chain module to the clock signal, the more the number of delay units, and the more dense the layout, the smaller the granularity of the adjustable clock signal step, so that the required clock frequency can be obtained flexibly and accurately within the set clock range.

[0090] In addition, the clock signal frequency conversion circuit has the advantage of fast response speed. Compared with the clock frequency division or frequency multiplication mechanism of the related art, the clock signal frequency conversion circuit helps to improve the adjustment speed of the frequency conversion clock signal. The related art usually relies on a timer for delay control, and then the trigger signal takes effect, which introduces a large delay due to the timer. The clock signal frequency conversion circuit can be implemented in a full hardware manner, and the response process is almost delay-free, so that the real-time performance and efficiency of clock adjustment can be greatly improved.

[0091] The above only describes the preferred embodiments of the present disclosure and does not limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A clock signal frequency conversion circuit, characterized by comprising: include: The delay chain module is used to acquire a reference clock signal and delay the reference clock signal to generate multiple clock signals with different phases at the same frequency. The signal extraction and output module, coupled to the delay chain module, is used to receive the multiple synchronous clock signals, extract multiple signal segments from the multiple synchronous clock signals according to the received configuration information, and obtain and output a frequency-converted clock signal associated with the configuration information based on the extracted multiple signal segments. The signal extraction output module includes a signal extraction submodule, which is a plurality of signal extraction submodules. The plurality of signal extraction submodules are coupled to the delay chain module. The plurality of signal extraction submodules receive the plurality of same-frequency clock signals one-to-one. Each signal extraction submodule is used to extract a signal segment from the received same-frequency clock signal according to the configuration information it receives. The configuration information is used to set a counting threshold, which is set in the capture / compare register of the signal extraction submodule.

2. The clock signal conversion circuit of claim 1, wherein, The delay chain module includes: The delay unit is a plurality of delay units, which are connected in series to form the delay chain module. In the case of two adjacent delay units connected in series, the clock signal output terminal of the previous delay unit is coupled to the clock signal input terminal of the next delay unit. The clock signal input terminal of the first delay unit among the plurality of delay units receives the reference clock signal. Each of the delay units generates a clock signal with a different phase at the same frequency at its output terminal.

3. The clock signal frequency conversion circuit according to claim 2, characterized in that, The delay chain module further includes: A toggle trigger is provided, wherein the clock signal input terminal of the first-stage delay unit receives the reference clock signal through the toggle trigger, wherein the clock signal input terminal of the toggle trigger receives the reference clock signal, and the clock signal input terminal of the first-stage delay unit is coupled to the output terminal of the toggle trigger.

4. The clock signal frequency conversion circuit according to claim 1, characterized in that, The signal extraction and output module further includes: A signal combination output submodule is coupled to multiple signal extraction submodules and is used to receive signal segments extracted by the multiple signal extraction submodules, combine the received signal segments to obtain and output the frequency conversion clock signal.

5. The clock signal frequency conversion circuit according to claim 4, characterized in that, The signal extraction submodule includes: An enable signal generation unit is coupled to the delay chain module and is used to receive the same frequency clock signal and configuration information, and generate an enable signal according to the received same frequency clock signal and configuration information. An AND gate unit, wherein the two input terminals of the AND gate unit are respectively coupled to the enable signal generation unit and the delay chain module, is used to receive the same frequency clock signal and the enable signal, and obtain the signal segment based on the same frequency clock signal and the enable signal.

6. The clock signal frequency conversion circuit according to claim 5, characterized in that, The enable signal generation unit includes: A counting comparison subunit, coupled to the delay chain module, is used to receive the same-frequency clock signal and configuration information, count the period of the same-frequency clock signal based on the configuration information, and generate the enable signal when the count reaches the count value required by the configuration information.

7. The clock signal frequency conversion circuit according to claim 4, characterized in that, The signal combination output submodule includes: A multi-input OR gate, wherein each input terminal of the multi-input OR gate is coupled to each of the signal extraction sub-modules, for receiving signal segments extracted by the multiple signal extraction sub-modules, and outputting the frequency conversion clock signal at the output terminal of the multi-input OR gate.

8. The clock signal frequency conversion circuit according to claim 4, characterized in that, The signal combination output submodule includes: A series of cascaded OR gate units, wherein the input terminals of the primary OR gate units in the series of cascaded OR gate units are respectively coupled to each of the signal extraction submodules, and between two adjacent OR gate units in the series of cascaded OR gate units, the output terminal of the previous OR gate unit is coupled to the input terminal of the next OR gate unit, and the number of the next OR gate units is less than the number of the previous OR gate units. The final OR gate unit in the series of cascaded OR gate units is a single unit, and the output terminal of the final OR gate unit outputs the frequency conversion clock signal.

9. The clock signal frequency conversion circuit according to claim 1, characterized in that, The clock signal frequency conversion circuit also includes: A configuration unit, coupled to the signal extraction and output module, is used to generate the configuration information.

10. The clock signal frequency conversion circuit according to claim 1, characterized in that, The clock signal frequency conversion circuit also includes: A phase-locked loop circuit, coupled to the delay chain module, is used to generate the reference clock signal.

11. A chip, characterized in that, The clock signal frequency conversion circuit as described in any one of claims 1 to 10 is adopted.

12. An electronic device, characterized in that, Including the chip as described in claim 11.

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