High-precision low-delay successive approximation analog-to-digital converter based on sampling noise elimination

Abstract

The invention provides a high-precision low-delay successive approximation analog-to-digital converter based on sampling noise elimination, and the analog-to-digital converter comprises a main capacitor group which generates an original combined signal according to an original sampling signal and primary sampling noise in a secondary sampling stage; the pre-quantization capacitor bank is used for driving a bottom plate switch of the pre-quantization capacitor bank according to the detection control signal, switching a capacitor weight through a weight control signal to execute pre-quantization operation on the original combined signal and outputting a swing suppression signal; the novel sampling noise elimination module is used for receiving the swing suppression signal, performing gain amplification, generating a purification amplification signal, detecting the differential swing of the original combined signal in real time, and generating a detection control signal and a pre-quantization code according to the differential swing; the successive approximation quantization module is used for generating a main quantization code and a weight control signal according to the purification and amplification signal in a quantization stage; and the digital processing module is used for fusing the pre-quantized code and the main quantized code to obtain a final digital code. And the energy efficiency and the conversion precision of analog signal conversion are obviously improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog-to-digital converters, in particular to a high-precision low-latency successive approximation analog-to-digital converter based on sampling noise cancellation. BACKGROUND

[0002] Analog-to-digital converters (ADCs) as the core interface devices connecting the physical world and digital circuits play an irreplaceable role in modern electronic systems. With the increasing demand for data acquisition accuracy and real-time performance in medical electronics, industrial automation, automotive electronics and other fields, the demand for high-precision, low-latency ADCs is becoming increasingly urgent. Successive approximation register (SAR) ADCs have become the mainstream technology choice in medium-to-high-precision, medium sampling rate scenarios due to their simple structure, low power consumption and high energy efficiency. However, with the further improvement of application scenarios on ADC performance, how to achieve higher precision while maintaining low latency has become a key challenge for SAR ADC technology development.

[0003] To meet the demand for high precision, existing SAR ADCs usually suppress sampling thermal noise by increasing the size of the input sampling capacitor to improve the effective resolution. In addition, to solve the noise coupling problem caused by the increase in capacitor size, some technologies introduce a sampling noise cancellation mechanism, which adds a pre-amplification stage to the traditional SAR ADC structure, stores noise during the sampling stage, and cancels noise by signal cancellation during the quantization stage. This kind of technology tries to balance the capacitor size and noise performance by dynamically adjusting the equivalent noise contribution of the sampling capacitor.

[0004] However, the existing sampling noise cancellation technology still has significant defects. First, the pre-amplification stage needs to work continuously during the sampling and quantization stages, and its static power consumption significantly offsets the power consumption benefits brought by noise cancellation, resulting in limited overall energy efficiency improvement. Second, due to the difference in amplification time of the input signal between the sampling stage and the quantization stage, limited by the bandwidth of the amplifier, the completeness of noise cancellation cannot be guaranteed. In addition, the input signal and the sampling noise need to be amplified by the same operational amplifier before storage, and the limited output swing of the operational amplifier forces the noise storage time to be compressed, resulting in weakened attenuation effect of the noise storage capacitor. More seriously, when the input signal swing difference is large, the deterioration of the linearity of the operational amplifier will further exacerbate the amplification error, making the noise cancellation effect fluctuate significantly in different sampling periods, which is difficult to meet the stability requirements of high-precision scenarios. SUMMARY

[0005] In order to solve the above problems existing in the prior art, the application provides a high-precision low-latency successive approximation type analog-digital converter based on sampling noise elimination.

[0006] The technical problem to be solved by the application is solved by the following technical scheme: The application provides a high-precision low-latency successive approximation type analog-digital converter based on sampling noise elimination, which comprises a sampling module, a new type sampling noise elimination module, a digital-analog conversion capacitor array module, a successive approximation quantization module and a digital processing module. The sampling module is used for sampling an input analog signal to a main capacitor group of the digital-analog conversion capacitor array module in a sampling stage, so as to generate an original sampling signal and accompanying first sampling noise. The digital-analog conversion capacitor array module comprises a main capacitor group and a pre-quantization capacitor group. The pre-quantization capacitor group is used for driving a bottom switch of the pre-quantization capacitor group according to the detection control signal, and performing a pre-quantization operation on the original combined signal through a weight control signal to output a swing suppression signal. The new type sampling noise elimination module is used for receiving the swing suppression signal and performing gain amplification, generating a purified amplification signal, and detecting a differential swing of the original combined signal in real time, so as to generate the detection control signal and a pre-quantization code according to the differential swing. The successive approximation quantization module is used for generating a main quantization code and a weight control signal according to the purified amplification signal in a quantization stage. The digital processing module is used for fusing the pre-quantization code and the main quantization code to obtain a final digital code.

[0007] The application provides a high-precision low-latency successive approximation type analog-to-digital converter based on sampling noise cancellation, comprising a sampling module, a new type of sampling noise cancellation module, a digital-to-analog conversion capacitor array module, a successive approximation quantization module and a digital processing module; the sampling module is used for sampling an input analog signal to a main capacitor group of the digital-to-analog conversion capacitor array module in a sampling stage to generate an original sampling signal and accompanying first sampling noise; the digital-to-analog conversion capacitor array module comprises the main capacitor group and a pre-quantization capacitor group; the main capacitor group is used for generating an original combined signal according to the original sampling signal and the first sampling noise in a second sampling stage; the pre-quantization capacitor group is used for driving a self bottom switch according to a detection control signal and performing a pre-quantization operation on the original combined signal through a weight control signal to output a swing suppression signal; the new type of sampling noise cancellation module is used for receiving the swing suppression signal and performing gain amplification to generate a purified amplification signal and real-time detect a differential swing of the original combined signal to generate a detection control signal and a pre-quantization code according to the differential swing; the successive approximation quantization module is used for generating a main quantization code and the weight control signal according to the purified amplification signal in a quantization stage; and the digital processing module is used for fusing the pre-quantization code and the main quantization code to obtain a final digital code. In the application, the new type of sampling noise cancellation module and the pre-quantization capacitor group are introduced to effectively solve the high static power consumption problem caused by the continuous work of a preamplifier in the prior art, and meanwhile, the problem of incomplete noise cancellation caused by the amplification time difference and the bandwidth limitation of an operational amplifier is avoided. In addition, the swing suppression signal is generated by performing swing suppression processing on the original combined signal through the pre-quantization capacitor group in the second sampling stage, so that the influence of the output swing limitation of the operational amplifier on the decay effect of the noise storage capacitor is reduced. Secondly, the adaptability of the system to the swing change of the input signal is improved by real-time detecting the differential swing of the original combined signal and dynamically generating the detection control signal and the pre-quantization code, the amplification error fluctuation caused by the deterioration of the linearity of the operational amplifier is alleviated, the stability and precision of the noise cancellation effect are significantly enhanced, and the demand of high precision and high energy efficiency scene is met. In summary, the successive approximation type analog-to-digital converter provided by the application significantly improves the energy efficiency and conversion precision of analog signal conversion.

[0008] The application will be further described in detail below with reference to the drawings and examples. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A structure schematic diagram of a high-precision low-latency successive approximation type analog-to-digital converter based on sampling noise cancellation provided by the application is shown; Figure 2 A structure schematic diagram of a FIA dynamic amplifier is exemplarily shown; Figure 3 A structure schematic diagram of a digital-to-analog conversion capacitor array module is exemplarily shown; Figure 4A structural schematic diagram of the novel sampling noise cancellation module is shown exemplarily. Figure 5 A working timing of the high-precision low-latency successive approximation type analog-digital converter based on sampling noise cancellation is provided for the embodiment of the present application. DETAILED DESCRIPTION

[0010] The present application will be further described in detail below in combination with specific embodiments, but the embodiments of the present application are not limited thereto.

[0011] In order to improve the energy efficiency and conversion precision of analog signal conversion, the embodiment of the present application provides a high-precision low-latency successive approximation type analog-digital converter based on sampling noise cancellation. Figure 1 A structural schematic diagram of the high-precision low-latency successive approximation type analog-digital converter based on sampling noise cancellation is provided for the embodiment of the present application, as shown in the figure, comprising: a sampling module, a novel sampling noise cancellation module, a digital-analog conversion capacitor array module, a successive approximation quantization module, and a digital processing module. Figure 1 The sampling module is used for sampling the input analog signal to the main capacitor group of the digital-analog conversion capacitor array module in a sampling stage, to generate an original sampling signal and an accompanying first sampling noise. The digital-analog conversion capacitor array module contains a main capacitor group and a pre-quantization capacitor group: the main capacitor group is used for generating an original combined signal according to the original sampling signal and the first sampling noise in a second sampling stage; The pre-quantization capacitor group is used for driving its bottom switch according to a detection control signal, and performing a pre-quantization operation on the original combined signal through a weight control signal to output a swing suppression signal; The novel sampling noise cancellation module is used for receiving the swing suppression signal and performing gain amplification, to generate a purified amplification signal, and to detect the differential swing of the original combined signal in real time, to generate a detection control signal and a pre-quantization code according to the differential swing. The successive approximation quantization module is used for generating a main quantization code and a weight control signal according to the purified amplification signal in a quantization stage. The digital processing module is used for fusing the pre-quantization code and the main quantization code to obtain a final digital code.

[0012] ​The embodiment of the present application provides a high-precision low-latency successive approximation analog-to-digital converter based on sampling noise cancellation, a capacitor and a switch (a sampling noise cancellation module) are added between an FIA dynamic amplifier and a latch for storing and eliminating sampling noise, wherein a first-stage pre-amplification stage adopts a dynamic floating inverting amplifier (FIA dynamic amplifier), and a detection and quantization submodule is added before the pre-amplification stage. The dynamic floating inverting amplifier only works in the sampling stage and the quantization stage, avoids generation of static current, greatly improves current utilization, and reduces FIA dynamic amplifier power consumption. In addition, a static operational amplifier in a traditional sampling noise cancellation module is in a long-pass state, sampling noise signals are inconsistent in the build time of the secondary sampling stage and the quantization stage, and due to limited operational amplifier bandwidth, the sampling noise cannot be completely eliminated. The dynamic floating inverting amplifier can control working time, the gain thereof is directly related to time, the secondary sampling time and the quantization time are matched by setting an amplifier switch clock, the sampling noise build problem is improved, and the noise cancellation effect is improved. In the sampling noise storage stage, when a top plate voltage of a digital-to-analog conversion capacitor array exceeds a predetermined threshold value of the detection and quantization submodule, a control signal is generated through digital logic to perform partial pre-quantization, the input signal swing of the amplifier in the sampling noise storage stage is reduced, the amplifier is prevented from being saturated in the secondary sampling stage, the size of the secondary sampling signal is controlled within a certain range, amplifier errors caused by too large input signal swing difference in different sampling periods are suppressed, and in addition, the amplifier gain limitation is reduced, the working time of the amplifier can be prolonged, equivalent input noise caused by the sampling noise cancellation capacitor is reduced, and the energy efficiency of the high-precision low-latency successive approximation analog-to-digital converter is improved.

[0013] In addition, in the embodiment, the digital-to-analog conversion capacitor array is designed as two parts, namely a main capacitor group and a pre-quantization capacitor group. The main capacitor group is used for normal quantization, and the other part of the pre-quantization capacitor group is used for the pre-quantization stage. In the sampling and quantization process, only the main capacitor group performs sampling and quantization operations; and the pre-quantization capacitor group remains in a reset state in the first stage of sampling, and then configures its working state according to a detection control signal generated by the detection and quantization submodule in the secondary sampling stage.

[0014] Optionally, the novel sampling noise cancellation module comprises the FIA dynamic amplifier, the sampling noise cancellation capacitor, the detection and quantization submodule, and the latch. The input terminal of the sampling module is connected to the input analog signal Vin. The input terminal of the digital-to-analog converter capacitor array module is connected to the output terminal of the sampling module, the output terminal of the successive approximation quantization module, and the output terminal of the detection quantization submodule, respectively. The output terminal of the digital-to-analog converter capacitor array module is connected to the input terminal of the FIA ​​dynamic amplifier and the input terminal of the detection quantization submodule, respectively. The output terminal of the FIA ​​dynamic amplifier is connected to the input terminal of the sampling noise cancellation capacitor, the output terminal of the sampling noise cancellation capacitor is connected to the input terminal of the latch, and the output terminal of the latch is connected to the input terminal of the successive approximation quantization module. The output terminals of the successive approximation quantization module and the detection quantization submodule are both connected to the input terminal of the signal fusion module. The output terminal of the signal fusion module is connected to the external output terminal Dout.

[0015] Specifically, in this embodiment, the FIA ​​dynamic amplifier serves as a pre-amplification stage, remaining in a reset state before the sampling noise storage stage, with no static power consumption. The second stage is a StrongARM latch. A capacitor C2 and its bottom plate control switch (capacitor C2 and its bottom plate control switch together constitute the sampling noise cancellation capacitor) are added between the pre-amplification stage and the latch. The sampling noise cancellation capacitor is related to the first sampling noise voltage. The voltage stored on C2 is used for offset cancellation; the second sampling noise voltage associated with C2. The gain is attenuated by the preamplifier. After sampling, the digital-to-analog converter capacitor array module enters the sampling noise storage stage. At this time, the FIA ​​amplifier is turned on by clock control, and the first sampling noise voltage of the digital-to-analog converter capacitor array module is... The input analog signal is simultaneously amplified by the amplifier and stored on capacitor C2; this stage is also the secondary sampling stage. To prevent saturation of the FIA ​​dynamic amplifier, the input signal swing needs to be controlled and the secondary sampling time reduced. This limits the gain of the FIA ​​dynamic amplifier, reducing the noise attenuation effect of kT / C2. Therefore, a detection and quantization submodule is used to detect the swing of the input signal (original combined signal). When the differential swing exceeds a preset threshold, a detection control signal is generated to control the capacitor base switch of the digital-to-analog converter capacitor array module for pre-quantization, reducing the input signal swing. As a result, the operating time of the FIA ​​dynamic amplifier can be extended, the gain limitation can be relaxed, the noise cancellation effect of the sampling noise cancellation capacitor is improved, and the power consumption is significantly reduced due to the use of a dynamic amplifier as a pre-amplification stage.

[0016] Optionally, the sampling module is specifically used to sample the input analog signal to the main capacitor bank through the bottom plate sampling method of the gate voltage bootstrap switch during the first sampling stage.

[0017] Figure 2 An exemplary schematic diagram of an FIA dynamic amplifier is shown. Figure 2As shown, the FIA ​​dynamic amplifier includes: switch S11, switch S12, switch S13, switch S14, and capacitor C. RES Capacitor C N Capacitor C P NMOS transistor M1, NMOS transistor M2, PMOS transistor M3 and PMOS transistor M4; One end of switch S11 is connected to capacitor C RES The upper plate is connected; the other end of switch S11 is connected to the power supply voltage VDD or the first connection terminal VS+ formed by the source of PMOS transistor M4 and the source of PMOS transistor M3; capacitor C RES The lower plate is connected to one end of switch S12; the other end of switch S12 is grounded or connected to the second connection terminal VS- formed by the source of NMOS transistor M1 and the source of NMOS transistor M2; the sources of PMOS transistor M3 and PMOS transistor M4 are connected to each other; the gate of PMOS transistor M4 and the gate of NMOS transistor M1 are both connected to the positive terminal voltage V of the upper plate of the digital-to-analog converter capacitor array module. IP Connected; the drain of PMOS transistor M4, the drain of NMOS transistor M1, and capacitor C. N The upper plate and one end of switch S13 are connected to each other to form the third connection terminal V. OUTIN The gates of both PMOS transistor M3 and NMOS transistor M2 are connected to the negative terminal voltage V of the upper-level board of the digital-to-analog converter capacitor array module. IN Connected; the drain of PMOS transistor M3, the drain of NMOS transistor M2, and capacitor C. P The upper plate and one end of switch S14 are connected to each other to form the fourth connection terminal V. OUTP The other ends of both switch S13 and switch S14 are connected to the common-mode voltage V. CM Connected; Capacitor C N The lower plate and capacitor C P The lower plates are all grounded.

[0018] Figure 3 An exemplary schematic diagram of a digital-to-analog converter capacitor array module is shown. For example... Figure 3 As shown, the main capacitor bank includes: the MSB segment capacitor bank and the LSB segment capacitor bank; the pre-quantization capacitor bank includes: capacitor C pq The MSB segment capacitor bank includes: capacitor C a Capacitor C dm Capacitor C m Capacitor C 2m Capacitor C 4m Capacitor C 8m Capacitor C 16m Capacitor C' 16m Capacitor C32m and capacitor C 64m ; the LSB segment capacitor group comprises: capacitor C 32u , capacitor C' 32u , capacitor C 16u , capacitor C 8u , capacitor C 4u , capacitor C' 4u , capacitor C 2u , capacitor C u and capacitor C d1 ; capacitor C dm , capacitor C m , capacitor C 2m , capacitor C 4m , capacitor C 8m , capacitor C 16m , capacitor C' 16m , capacitor C 32m and capacitor C 64m together constitute a capacitor group C1; the right plate of capacitor C a is connected with the upper plate of capacitor C dm , capacitor C m , capacitor C 2m , capacitor C 4m , capacitor C 8m , capacitor C 16m , capacitor C' 16m , capacitor C 32m and capacitor C 64m and capacitor C pq ; the left plate of capacitor C a is connected with the upper plate of capacitor C 32u , capacitor C' 32u , capacitor C 16u , capacitor C 8u , capacitor C 4u , capacitor C' 4u , capacitor C 2u , capacitor C u and capacitor C d1 ; in a first sampling stage and a second sampling stage, the lower plate of capacitor C dm , capacitor C m , capacitor C 2m , capacitor C 4m , capacitor C 8m , capacitor C 16m , capacitor C' 16m , capacitor C 32m and capacitor C 64m is connected with a sampling module through a gate voltage bootstrap switch;32u , capacitor C 32u , capacitor C 16u , capacitor C 8u , capacitor C 4u , capacitor C 4u , capacitor C 2u , capacitor C u , capacitor C d1 , capacitor C CM , capacitor C dm , capacitor C m , capacitor C 2m , capacitor C 4m , capacitor C 8m , capacitor C 16m , capacitor C 16m , capacitor C 32m , capacitor C 64m , capacitor C 32u , capacitor C 32u , capacitor C 16u , capacitor C 8u , capacitor C 4u , capacitor C 4u , capacitor C 2u , capacitor C u , capacitor C d1 , capacitor C , capacitor C pq , capacitor C pq , capacitor C

[0019] , capacitor C 2m , capacitor C 4m , capacitor C 8m , capacitor C 16m , capacitor C 16m , capacitor C 32m , capacitor C 64m , capacitor C m , capacitor C 32u , capacitor C 32u , capacitor C 16u , capacitor C 8u , capacitor C 4u , capacitor C 4u , capacitor C 2u , capacitor C u , capacitor C

[0020] Figure 4 A schematic diagram of the novel sampling noise cancellation module is shown as an example. For example... Figure 4 As shown, the sampling noise cancellation capacitor includes: capacitor C2 and switch S2; the FIA ​​dynamic amplifier includes: switch S1 and pre-amplification stage; When switch S1 is open, the first sampling noise is stored in capacitor bank C1. When switch S2 is open, the first sampling noise is stored in capacitor C2. Noise cancellation is achieved by canceling the first sampling noise in capacitor bank C1 and capacitor C2.

[0021] Alternatively, the gain function of the FIA ​​dynamic amplifier can be expressed as: ; in, express The integral gain of the FIA ​​dynamic amplifier at that time. express The voltage change at the first connection terminal VS+ or the second connection terminal VS- at a given time. Indicates the weak inverse slope factor. Indicates thermal voltage. Indicates capacitance C N or capacitor C P The capacitance value, Indicates capacitance The capacitance value.

[0022] Optionally, a novel sampling noise cancellation module is used to receive the swing suppression signal and amplify its gain to generate a cleaned amplified signal, and to detect the differential swing of the original combined signal in real time, generating a detection control signal and a pre-quantization code based on the differential swing, including: The FIA ​​dynamic amplifier receives the swing suppression signal output from the digital-to-analog converter capacitor array, generates a purified amplified signal through dynamic gain amplification, and stores it in the sampling noise cancellation capacitor; at the same time, the detection quantization submodule and latch detect the differential swing of the original combined signal in real time, and generates a detection control signal and pre-quantization code when the differential swing exceeds a preset threshold. Among them, the detection control signal is used to drive the base plate switch of the pre-quantized capacitor bank, dynamically compressing the swing of the original combined signal.

[0023] The overall operation process of a high-precision, low-delay successive approximation analog-to-digital converter based on sampling noise cancellation provided by this invention is as follows: The sampling module uses a bottom plate sampling method with a gate voltage bootstrap switch and a capacitor switching scheme based on common-mode feedback voltage (Vcm-Based timing) to sample the input analog signal onto capacitor bank C1 of the digital-to-analog converter capacitor array module before the FIA ​​dynamic amplifier. After the top plate switch S1 is opened, the digital-to-analog converter capacitor array module completes the sampling.

[0024] A new sampling noise cancellation module, a noise storage capacitor C2 and its bottom plate control switch S2 are added between the FIA dynamic amplifier and the latch, when S1 is open, S2 is still closed, the first sampling noise related to the DAC capacitor array module is stored on C2 as a mismatch cancellation, the second noise kT / C2 related to C2 is attenuated by the FIA dynamic amplifier gain, reducing the capacitor value without introducing large noise. The first sampling noise voltage It can be regarded as a small step signal appearing at the input of the preamplifier, which is gradually amplified by the FIA dynamic amplifier over time.

[0025] In the case of using a static amplifier as a preamplifier stage, for a single-pole preamplifier with a time constant of τ, the first sampling noise voltage The response in the second sampling stage Can be expressed as: ; Where, G is the gain of the FIA dynamic amplifier, T is the sampling time of capacitor C2, i.e. the second sampling time, And the input end Cancel out, and finally get the input reference noise residual voltage Is: ; Where, V is the first sampling noise voltage introduced by capacitor group C1 in the DAC capacitor, B is the Boltzmann constant, T is the Kelvin temperature.

[0026] In the case of using FIA dynamic amplifier as preamplifier stage, its The response in the second sampling stage And the response in the quantization stage Can be expressed as: ; ; Where, T is the amplification time of the FIA dynamic amplifier during the second sampling, T is the amplification time of the FIA dynamic amplifier in each quantization period, and the final input reference noise residual voltage Is: ; Because of the static op-amp long-pass working mode and the limited bandwidth, the sampling noise cannot be completely established in the second sampling stage, resulting in incomplete elimination of the first sampling noise. The bandwidth of the op-amp needs to be increased to improve the sampling noise elimination effect, which leads to greater power consumption and reduces the effect of the sampling noise elimination technology. The FIA dynamic amplifier periodically works in each quantization cycle as a pre-amplifier stage by controlling the amplification time through the clock. Because of the difference between the input signals of the amplifier in the second sampling stage and the quantization stage, the best noise elimination effect can be achieved by optimization. .

[0027] The sampling noise introduced by the noise storage capacitor C2 will be attenuated by the gain of the amplifier. The final equivalent input noise power , where is the gain of the FIA dynamic amplifier, and is the sampling noise power introduced by the noise storage capacitor C2.

[0028] In order to reduce the equivalent input noise introduced by the noise storage capacitor C2, the gain of the FIA dynamic amplifier needs to be increased by prolonging the amplification time. However, too long amplification time may cause the FIA dynamic amplifier to saturate and deteriorate the linearity. Therefore, the detection quantization technology is adopted to detect the input signal of the pre-amplifier during the sampling stage of the noise storage capacitor C2. If the input signal exceeds the predetermined threshold voltage, the detection control signal is generated by digital logic to control the bottom switch of the threshold weight capacitor Ckr in the pre-quantization capacitor, reducing the top plate voltage and thus reducing the input signal swing. At this time, due to the reduction of the input swing of the pre-amplifier, the sampling time of the capacitor C2 can be increased. At the same time, the input swing of the FIA dynamic amplifier is reduced, and the gain limitation is reduced, which improves the sampling noise attenuation effect of the capacitor C2.

[0029] In the quantization stage, the FIA dynamic amplifier and the latch compare the differential voltage of the upper plate of the digital-to-analog conversion capacitor array, and outputs the comparison result to the successive approximation quantization module. The successive approximation quantization module generates a weight control signal to control the digital-to-analog conversion capacitor array to realize the process of successive approximation, and outputs the main quantization code. In this process, the first sampling noise will be eliminated on the right side of the noise storage capacitor C2.

[0030] The digital code processing stage includes: the digital processing module fuses the pre-quantization code Doutr and the main quantization code Dout1 to generate the final code value Dout.

[0031] Figure 5 ​​​The working timing of the high-precision low-latency successive approximation analog-to-digital converter based on sampling noise cancellation proposed for the embodiments of the application is as follows: in the input signal sampling stage: when switches S1 and S2 are both high, capacitor C1 samples the input analog signal, and the remaining pre-quantization capacitors remain in the reset state. At the moment when S1 is disconnected, the sampling value and the sampling noise are locked on C1, at this time S2 remains closed, and the system enters the C2 sampling stage (i.e. the second sampling stage) immediately. At the same time, the detection quantization submodule starts to work, and the voltage at the input end of the FIA dynamic amplifier is monitored in real time. If the voltage exceeds a certain threshold, a detection control signal is generated to drive the corresponding weight capacitor to perform a pre-quantization operation. The core purpose is to control the input signal swing of the operational amplifier in the second sampling stage to avoid the saturation of the amplifier and the generation of nonlinearity. In the subsequent quantization stage, the amplification time of the FIA is controlled by the clock to make the noise establishment condition of this stage match the stored noise in the second sampling stage, so as to achieve the best noise cancellation effect and generate a normal quantization code value Dout1. Finally, the overall code value is obtained by processing the two code values by the successive approximation quantization module.

[0032] The embodiment of the present application provides a high-precision low-latency successive approximation type analog-to-digital converter based on sampling noise cancellation, comprising a sampling module, a new type of sampling noise cancellation module, a digital-to-analog conversion capacitor array module, a successive approximation quantization module and a digital processing module; the sampling module is used for sampling an input analog signal to a main capacitor group of the digital-to-analog conversion capacitor array module in a sampling stage to generate an original sampling signal and accompanying first sampling noise; the digital-to-analog conversion capacitor array module comprises the main capacitor group and a pre-quantization capacitor group; the main capacitor group is used for generating an original combined signal according to the original sampling signal and the first sampling noise in a second sampling stage; the pre-quantization capacitor group is used for driving a self bottom switch according to a detection control signal and performing a pre-quantization operation on the original combined signal through a weight control signal to output a swing suppression signal; the new type of sampling noise cancellation module is used for receiving the swing suppression signal and performing gain amplification to generate a purified amplification signal and real-time detect a differential swing of the original combined signal to generate the detection control signal and a pre-quantization code according to the differential swing; the successive approximation quantization module is used for generating a main quantization code and the weight control signal according to the purified amplification signal in a quantization stage; and the digital processing module is used for fusing the pre-quantization code and the main quantization code to obtain a final digital code. In the embodiment of the present application, the new type of sampling noise cancellation module and the pre-quantization capacitor group are introduced to effectively solve the high static power consumption problem caused by the continuous work of a preamplifier in the prior art, and meanwhile, the problem of incomplete noise cancellation caused by the amplification time difference and the operational amplifier bandwidth limitation is avoided. In addition, the swing suppression signal is generated by performing swing suppression processing on the original combined signal through the pre-quantization capacitor group in the second sampling stage, so that the influence of the operational amplifier output swing limitation on the noise storage capacitor decay effect is reduced. Secondly, the adaptability of the system to the swing change of the input signal is improved by real-time detecting the differential swing of the original combined signal and dynamically generating the detection control signal and the pre-quantization code, the amplification error fluctuation caused by the operational amplifier linearity deterioration is alleviated, the stability and precision of the noise cancellation effect are significantly enhanced, and the demand of high-precision and high-energy efficiency scenes is met. In summary, the successive approximation type analog-to-digital converter provided by the embodiment of the present application significantly improves the energy efficiency and conversion precision of analog signal conversion.

[0033] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the present specification.

[0034] Although the present application has been described in connection with the embodiments thereof with reference to the drawings, it will be apparent to those skilled in the art that various changes in form and details can be made therein without departing from the scope of the application as set forth in the appended claims. In the description of the specification, the word "comprising" does not exclude the presence of other elements or steps than those listed and "a" or "an" does not exclude a plurality, but "plurality" means two or more unless otherwise stated. Furthermore, various features of the following embodiments can be combined with each other, unless specifically stated otherwise.

[0035] The above description is further to the present application in connection with specific preferred embodiments, and cannot be deemed to limit the specific implementation of the present application to these descriptions. For those skilled in the art, some simple deductions or replacements can be made without departing from the concept of the present application, and all of them shall be deemed to fall within the protection scope of the present application.

Claims

1. A high-precision low-latency successive approximation analog-to-digital converter based on sampling noise cancellation, characterized by, The application relates to a sampling module, a novel sampling noise elimination module, a digital-analog conversion capacitor array module, a successive approximation quantization module and a digital processing module. The sampling module is used for sampling an input analog signal to a main capacitor group of the digital-analog conversion capacitor array module in a first sampling stage to generate an original sampling signal and accompanying first sampling noise. The digital-analog conversion capacitor array module comprises a main capacitor group and a pre-quantization capacitor group; the main capacitor group is used for generating an original combined signal according to the original sampling signal and the first sampling noise in a second sampling stage; the pre-quantization capacitor group is used for driving a bottom plate switch of the pre-quantization capacitor group according to a detection control signal, switching a capacitor weight control signal to perform a pre-quantization operation on the original combined signal, and outputting a swing suppression signal. The novel sampling noise elimination module is used for receiving the swing suppression signal, performing gain amplification, generating a purified amplification signal, and detecting a differential swing of the original combined signal in real time to generate the detection control signal and a pre-quantization code. The successive approximation quantization module is used for generating a main quantization code and the weight control signal according to the purified amplification signal in a quantization stage. The digital processing module is used for fusing the pre-quantization code and the main quantization code to obtain a final digital code. The novel sampling noise elimination module comprises an FIA dynamic amplifier, a sampling noise elimination capacitor, a detection quantization sub-module and a latch. An input end of the sampling module is connected with the input analog signal Vin, input ends of the digital-analog conversion capacitor array module are respectively connected with output ends of the sampling module, output ends of the successive approximation quantization module and output ends of the detection quantization sub-module, an output end of the digital-analog conversion capacitor array module is connected with an input end of the FIA dynamic amplifier and an input end of the detection quantization sub-module, an output end of the FIA dynamic amplifier is connected with an input end of the sampling noise elimination capacitor, an output end of the sampling noise elimination capacitor is connected with an input end of the latch, an output end of the latch is connected with an input end of the successive approximation quantization module, output ends of the successive approximation quantization module and the detection quantization sub-module are connected with an input end of the signal fusion, and an output end of the signal fusion is connected with an external output end Dout.

2. The high-precision low-latency successive approximation analog-to-digital converter based on sampling noise cancellation according to claim 1, characterized in that, The sampling module is specifically used for sampling the input analog signal to the main capacitor group through a bottom plate sampling method of a gate voltage bootstrap switch in the first sampling stage. The sampling noise elimination capacitor comprises a capacitor C2 and a switch S2, and the FIA dynamic amplifier comprises a switch S1 and a pre-amplification stage.

3. The high-precision low-latency successive approximation analog-to-digital converter based on sampling noise cancellation according to claim 1, characterized in that, When the switch S1 is disconnected, the first sampling noise is stored on the capacitor group C1, when the switch S2 is disconnected, the first sampling noise is stored on the capacitor C2, and the first sampling noise in the capacitor group C1 and the capacitor C2 is offset to eliminate noise.

4. The high-precision low-latency successive approximation analog-to-digital converter based on sampling noise cancellation according to claim 2, characterized in that, The FIA dynamic amplifier comprises a switch S11, a switch S12, a switch S13, a switch S14, a capacitor C RES , a capacitor C N , a capacitor C P , an NMOS transistor M1, an NMOS transistor M2, a PMOS transistor M3 and a PMOS transistor M4. One end of the switch S11 is connected with the upper plate of the capacitor C RES ; the other end of the switch S11 is connected with the power voltage VDD or the first connection end VS+ composed of the source of the PMOS transistor M4 and the source of the PMOS transistor M3; the lower plate of the capacitor C RES is connected with one end of the switch S12; the other end of the switch S12 is grounded or connected with the second connection end VS- composed of the source of the NMOS transistor M1 and the source of the NMOS transistor M2; the sources of the PMOS transistor M3 and the PMOS transistor M4 are connected with each other; the gate of the PMOS transistor M4 and the gate of the NMOS transistor M1 are connected with the upper plate positive voltage V IP of the digital-to-analog conversion capacitor array module; the drain of the PMOS transistor M4, the drain of the NMOS transistor M1, the upper plate of the capacitor C N and one end of the switch S13 are connected with each other to form the third connection end V OUTIN ; the gate of the PMOS transistor M3 and the gate of the NMOS transistor M2 are connected with the upper plate negative voltage V IN of the digital-to-analog conversion capacitor array module; the drain of the PMOS transistor M3, the drain of the NMOS transistor M2, the upper plate of the capacitor C P and one end of the switch S14 are connected with each other to form the fourth connection end V OUTP ; the other end of the switch S13 and the other end of the switch S14 are connected with the common mode voltage V CM ; the lower plate of the capacitor C N and the lower plate of the capacitor C P are grounded.

5. The high-precision low-latency successive approximation analog-to-digital converter based on sampling noise cancellation according to claim 2, characterized in that, The main body capacitor group comprises: an MSB section capacitor group and an LSB section capacitor group; the pre-quantization capacitor group comprises: capacitors C pq ; the MSB section capacitor group comprises: capacitors C a , C dm , C m , C 2m , C 4m , C 8m , C 16m , C' 16m , C 32m and C 64m ; the LSB section capacitor group comprises: capacitors C 32u , C' 32u , C 16u , C 8u , C 4u , C' 4u , C 2u , C u and C d1 ; capacitor C dm , capacitor C m , capacitor C 2m , capacitor C 4m , capacitor C 8m , capacitor C 16m , capacitor C' 16m , capacitor C 32m , and capacitor C 64m together constitute a capacitor group Cl; The right plate of the capacitor C a is connected to the upper plate of the capacitor C dm , the capacitor C m , the capacitor C 2m , the capacitor C 4m , the capacitor C 8m , the capacitor C 16m , the capacitor C' 16m , the capacitor C 32m , the capacitor C 64m , and the capacitor C pq , respectively. The left plate of the capacitor C a is connected with the upper plate of the capacitor C 32u , the capacitor C' 32u , the capacitor C 16u , the capacitor C 8u , the capacitor C 4u , the capacitor C' 4u , the capacitor C 2u , the capacitor C u and the capacitor C d1 respectively. In the first sampling stage and the second sampling stage, the lower plate of the capacitor C dm , the capacitor C m , the capacitor C 2m , the capacitor C 4m , the capacitor C 8m , the capacitor C 16m , the capacitor C' 16m , the capacitor C 32m , and the capacitor C 64m is connected to the sampling module through a gate voltage bootstrap switch; the lower plate of the capacitor C 32u , the capacitor C' 32u , the capacitor C 16u , the capacitor C 8u , the capacitor C 4u , the capacitor C' 4u , the capacitor C 2u , the capacitor C u , and the capacitor C d1 is connected to the common mode signal V CM ; in the quantization stage, the lower plate of the capacitor C dm , the capacitor C m , the capacitor C 2m , the capacitor C 4m , the capacitor C 8m , the capacitor C 16m , the capacitor C' 16m , the capacitor C 32m , the capacitor C 64m , the capacitor C 32u , the capacitor C' 32u , the capacitor C 16u , the capacitor C 8u , the capacitor C 4u , the capacitor C' 4u , the capacitor C 2u , the capacitor C u , and the capacitor C d1 is connected to the output terminal of the successive approximation quantization module. The upper plate of the capacitor C pq is also connected with the input end of the FIA dynamic amplifier; the lower plate of the capacitor C pq is connected with the output end of the detection and quantization sub-module.

6. The high-precision low-latency successive approximation analog-to-digital converter based on sampling noise cancellation according to claim 5, characterized in that, The gain function of the FIA dynamic amplifier is represented as ​ 7. The high-precision low-latency successive approximation analog-to-digital converter based on sampling noise cancellation according to claim 5, characterized in that, ​ ； wherein, represents represents the integral gain value of the FIA dynamic amplifier at the time point t, represents represents the voltage variation amount of the first connection terminal VS+ or the second connection terminal VS- at the time point t, represents a weak reverse type slope factor, represents a thermal voltage, represents a capacitance C N or a capacitance C P value.

8. The high-precision low-latency successive approximation analog-to-digital converter based on sampling noise cancellation according to claim 2, characterized in that, The novel sampling noise cancellation module is used for receiving the swing suppression signal and performing gain amplification, generating a purified amplification signal, and detecting a differential swing of the original combined signal in real time, and generating the detection control signal and a pre-quantization code according to the differential swing, and comprises: The FIA dynamic amplifier receives the swing suppression signal output by the digital-to-analog conversion capacitor array, generates the purified amplification signal through dynamic gain amplification, and stores the purified amplification signal to the sampling noise cancellation capacitor; at the same time, the detection quantization sub-module and the latch detect the differential swing of the original combined signal in real time, and generate the detection control signal and the pre-quantization code when the differential swing exceeds a preset threshold. The detection control signal is used for driving the bottom plate switch of the pre-quantization capacitor group, and dynamically compressing the swing of the original combined signal.

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