Improved partial parallel structure decoder and decoding method thereof

Abstract

The invention discloses an improved partial parallel structure decoder and a decoding method thereof, and relates to the technical field of wireless communication and digital signal processing. The system comprises a confidence coefficient message storage unit which is used for alternately storing update information of variable nodes and check nodes by using a single-port storage space and reducing storage resource requirements; the parallelism degree optimization unit comprises a variable node processing module and a check node processing module, a pipelined cascade comparator network is integrated in the check node processing module, and the check node processing module is used for achieving extreme value comparison of multiple input data and accelerating check node information processing; and the control unit is used for dynamically starting and stopping alternate iteration of the variable node processing unit and the check node processing unit and monitoring the maximum number of iterations. The partially parallel structure decoder provided by the invention is suitable for LDPC decoders under the conditions of various code lengths and code rates, the throughput rate of the decoder can be improved, and the storage complexity can be reduced.

Description

Technical Field

[0001] This invention relates to the fields of wireless communication and digital signal processing technology, specifically to an improved partially parallel decoder and its decoding method. Background Technology

[0002] With the rapid development of modern communication technologies, the demand for data communication has experienced explosive growth. In digital communication systems, signals are highly susceptible to various interference factors during transmission, such as noise interference and signal fading. These interferences can lead to data transmission errors, severely impacting communication quality and reliability. Channel coding, as a key technology for ensuring reliable data transmission, is becoming increasingly important.

[0003] Low-density parity-check codes (LDPCs) have been widely used in the field of communications in recent years due to their excellent error-correcting performance. As LDPC code theory matures, the implementation and application of high-performance LDPC codes has become a key research focus in this field.

[0004] LDPC decoding algorithms are mainly divided into two categories: hard-decision and soft-decision. Hard-decision decoding algorithms use simple bit information transmission for decoding, such as the bit-flipping algorithm. This type of algorithm is only suitable for binary symmetric channels (BSC) and has poor computational performance, but its computational and algorithmic complexity are relatively low. However, in modern communication scenarios, the requirements for decoding performance are increasing, and hard-decision algorithms can hardly meet the needs. Therefore, soft-decision algorithms have become the mainstream.

[0005] The main reference indicators for the hardware implementation of LDPC codes include throughput, decoding latency, hardware resource consumption, coding gain, power consumption, and flexibility. These characteristics are somewhat contradictory: increasing parallelism can improve throughput but increases hardware resource consumption; increasing the number of iterations can improve decoding performance but increases decoding latency; high-speed circuit design increases system power consumption. Therefore, designing a good hardware architecture requires balancing these indicators, with the ideal goal of achieving the highest possible throughput with the least possible resource consumption and performance loss.

[0006] Currently, LDPC decoders mainly employ three architectures: serial, partially parallel, and fully parallel. The degree of parallelism in a decoder significantly impacts hardware resource consumption and decoding throughput. Fully parallel LDPC decoders typically offer the highest decoding throughput, but they consume more resources, have complex layout and routing, and experience routing congestion between processing nodes, resulting in high implementation complexity. Serial decoders require the fewest hardware resources, but their low decoding throughput makes them unsuitable for high-speed data transmission requirements. Summary of the Invention

[0007] The purpose of this invention is to provide an improved partially parallel decoder and its decoding method, which improves the throughput of LDPC codes and reduces hardware resource consumption by increasing parallelism and improving memory unit design.

[0008] According to a first aspect of the present invention, in order to achieve the above-mentioned objective, the present invention provides the following technical solution: an improved partially parallel structure decoder, comprising:

[0009] The confidence message storage unit is used to alternately store the update information of variable nodes and verification nodes using a single-port storage space, thereby reducing the storage resource requirements.

[0010] The parallelism optimization unit includes a variable node processing module and a check node processing module. The variable node processing module and the check node processing module adopt a parallel partitioning strategy based on the granularity of cyclic shift sub-blocks to further divide the original M×M submatrix into M / 4×M / 4 cyclic shift blocks, which is used to improve the column parallelism and row parallelism of the decoder.

[0011] The verification node processing module integrates a pipelined cascaded comparator network to realize extreme value comparison of multiple input data and accelerate the processing of verification node information.

[0012] The control unit is used to dynamically start and stop the alternating iteration of the variable node processing unit and the verification node processing unit, and to monitor the maximum number of iterations.

[0013] Furthermore, the confidence message storage unit includes several dual-port RAMs, each RAM corresponding to the position of "1" in the verification matrix, and supports parallel reading and writing by row / column through a cyclic shift address mapping method, and only needs to store one copy of node information to meet the requirements of alternating updates of variable nodes and verification nodes.

[0014] Furthermore, the specific implementation method of the parallelism optimization unit is as follows:

[0015] The M×M submatrix in the parity check matrix is ​​decomposed into multiple M / 4×M / 4 cyclic shift blocks;

[0016] Using the cyclic shift block as a parallel processing unit, a decoding structure with row parallelism and column parallelism is constructed.

[0017] Furthermore, the variable node processing module includes multiple parallel variable node update sub-units, and the verification node processing module includes multiple parallel verification node update sub-units. Both of them use M / 4×M / 4 cyclic shift blocks as the smallest processing granularity to achieve partial parallel decoding of the CCSDS standard near-ground communication LDPC code.

[0018] Furthermore, the cascaded comparator network in the verification node processing module includes:

[0019] The absolute value of the input data is compared in a multi-stage pipeline, with each comparator outputting the minimum and second-minimum values.

[0020] Calculate the global symbolic product using a sign bit XOR circuit;

[0021] Multiply the minimum or second minimum value by a normalization factor of 0.75 and output the result.

[0022] Furthermore, the control module includes a state machine, which contains at least four states: idle, initialization, decoding, and output. By monitoring whether the verification equation is satisfied and whether the current iteration count has reached a preset upper limit, the module determines whether to terminate the iteration early and output the decoding result.

[0023] The monitoring and verification equation is H*C T =0, if H*C T =0, then the decoding is complete.

[0024] According to a second aspect of the present invention, the present invention provides a decoding method for an improved partially parallel structure decoder, which uses an improved partially parallel structure decoder described in the first aspect for decoding and employs a normalized minimum sum decoding algorithm, the specific process of which is as follows:

[0025] (1) Channel initial message:

[0026] r ji =0

[0027] q i =L(P i )

[0028] (2) Verify the external information passed from the node to the variable node:

[0029]

[0030] (3) External information passed from the variable node to the verification node:

[0031]

[0032] (4) Decoding decision: After iteration, the posterior probability of the variable node is:

[0033]

[0034] Therefore, the posterior probability is greater than 0, so v i The judgment is 0, otherwise the judgment is 1;

[0035] In the formula, l maxThe maximum number of iterations is given by q in the l-th iteration. ij The verification node information is r ji The posterior probability information is q i ;

[0036] Does the information sequence y obtained after the judgment satisfy H*C? T =0, if H*C T = 0, then the decoding is complete; otherwise, H*C is not satisfied. T If the value is 0, then check if the current iteration count has reached l. max If the target is not reached, continue iterating; if the target has been reached... max Then the decoding is complete.

[0037] This invention has at least the following beneficial effects:

[0038] 1. This invention refines the decoding parallelism from the original M×M submatrix granularity to the M / 4×M / 4 cyclic shift block granularity, increasing column parallelism by 4 times and row parallelism by 4 times. Under the same clock frequency, the decoding throughput is increased by approximately 4 times, meeting the requirements of high-speed data transmission.

[0039] 2. This invention utilizes the characteristic of "alternating updates of verification nodes and variable nodes" to alternately store two types of node information in a single storage space, thereby reducing the number of intermediate message storage devices by about 50% and significantly reducing chip area and power consumption.

[0040] 3. This invention uses a pipelined cascaded comparator network to compress the calculation of the minimum / second smallest input value of 3 / 6 to 5 clock cycles, which significantly shortens the critical path compared to the traditional serial structure, and the overall decoding delay decreases linearly with the number of iterations.

[0041] 4. The partially parallel architecture in this invention achieves a good trade-off between resources and performance, avoiding the wiring congestion caused by full parallelism and the low speed caused by serial processing; at the same time, the normalized minimum sum algorithm replaces the complex lookup table with sign-comparison operations, further simplifying the circuit implementation.

[0042] 5. The present invention uses a 128×128 cyclic shift block as the basic unit, and can adapt to quasi-cyclic LDPC codes with different code lengths and code rates through parameter configuration, so as to achieve multi-standard compatibility on the same hardware platform and reduce development and maintenance costs.

[0043] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the decoder described in this invention;

[0045] Figure 2 This is a schematic diagram of the verification matrix structure in this invention;

[0046] Figure 3 This is a schematic diagram of the pipelined cascaded comparator network in this invention. Detailed Implementation

[0047] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0048] Example 1:

[0049] Please see Figures 1-3 This invention provides a technical solution: an improved partially parallel decoder, comprising:

[0050] The confidence message storage unit is used to alternately store the update information of variable nodes and verification nodes using a single-port storage space, thereby reducing the storage resource requirements.

[0051] The parallelism optimization unit includes a variable node processing module (VNP) and a check node processing module (CNP). The VNP and CNP adopt a parallel partitioning strategy based on cyclic shift sub-block granularity to further divide the original M×M submatrix into M / 4×M / 4 cyclic shift blocks to improve the column parallelism and row parallelism of the decoder.

[0052] The verification node processing module integrates a pipelined cascaded comparator network to realize extreme value comparison of multiple input data and accelerate the processing of verification node information.

[0053] The control unit is used to dynamically start and stop the alternating iteration of the variable node processing unit and the verification node processing unit, and to monitor the maximum number of iterations.

[0054] Regarding the technical solution of this embodiment, the confidence message storage unit includes several dual-port RAMs, each RAM corresponding to the position of "1" in the verification matrix, and supports parallel reading and writing by row / column through a cyclic shift address mapping method, and only needs to store one copy of node information to meet the requirements of alternating updates of variable nodes and verification nodes;

[0055] Specifically, VNP and CNP require intermediate information storage to transmit and store decoded information. All intermediate information storage units together form the confidence message storage unit. In fact, the position and number of variable nodes and check nodes correspond one-to-one with the position and number of non-zero elements in the check matrix. The storage unit needs to save the updated node information and support reading by row / column. Since the two types of node updates alternate (the variable nodes remain unchanged when the check nodes are updated, and vice versa), only one storage space needs to be allocated for the "1" positions in the check matrix to alternately store the update information of the two types of nodes. This design can reduce the storage complexity by half.

[0056] The original storage unit needs to store checksum variable node information for two check matrix dimensions. However, the storage unit designed based on the alternating storage design and the characteristics of the cyclic shift structure can reduce the storage space by half. Therefore, for the LDPC decoder of (2048, 1024) code, only 60 dual-port RAM memories are needed. The split cyclic matrix is ​​used as the address to ensure that the node value corresponding to each non-zero element can be updated simultaneously.

[0057] Regarding the technical solution of this embodiment, the specific implementation method of the parallelism optimization unit is as follows:

[0058] The M×M submatrix in the parity check matrix is ​​decomposed into 4 M / 4×M / 4 cyclic shift blocks;

[0059] Using cyclic shift blocks as parallel processing units, a decoding structure with row parallelism of 12 and column parallelism of 20 is constructed.

[0060] Specifically, Figure 2 The parity-check matrix (PCM) for the (2048, 1024) LDPC code is 1536 × 2560. Matrix elements have only two values: 0 and 1. The positions with values ​​of 1 converge to form the diagonal lines in the diagram, while the positions with values ​​of 0 form the blank areas. Figure 2 It can be seen that the parity check matrix is ​​composed of 15 parity submatrices of size 512×512, with 3 rows and 5 columns. These parity submatrices contain the superposition of zero matrices, identity matrices or cyclic shift matrices. The existing decoder parallelism design scheme is based on the 512×512 dimension of the parity submatric block to divide the parity check matrix, that is, a scheme with 5 column parallelism and 3 row parallelism.

[0061] The parity check matrix consists of a 512×512 parity check matrix, which is composed of multiple permutation matrices Π superimposed. By observing each permutation matrix Π, it can be seen that it is composed of four cyclic blocks. That is, the 512×512 permutation matrix Π is composed of four 128×128 cyclic shift blocks. Therefore, based on the 128×128 cyclic blocks as the partitioning principle, a design scheme with 20 column parallelism and 12 row parallelism can be obtained. Compared with the parallelism partitioning based on the parity submatrix, the parallelism is improved by 4 times.

[0062] Regarding the technical solution of this embodiment, the variable node processing module includes 20 parallel variable node update subunits (VNU), and the verification node processing module includes 12 parallel verification node update subunits (CNU). Both of them use a 128×128 cyclic shift block as the smallest processing granularity to achieve partial parallel decoding of the CCSDS standard near-ground communication LDPC code.

[0063] It should be further explained that the core function of the verification node processing module is to complete the iterative update of the verification node information. The specific implementation path is as follows:

[0064] For data other than the current node, first calculate the product of their sign bits, and at the same time extract the minimum absolute value of these data. Then multiply the above two results by the correction factor 0.75 respectively.

[0065] In the parity check matrix, the number of non-zero data in a row is called the "row weight", and the number of non-zero data in a column is called the "column weight". For the entire 1 / 2 bit rate parity check matrix, it can be seen from the parity check matrix structure diagram that the first M rows of the parity check matrix, i.e., rows 1-512, have a weight of 3, and the last 2M rows, i.e., rows 513-1536, have a weight of 6. Therefore, the CNU unit needs to be designed with two types of inputs: 3 and 6.

[0066] The key to this module design lies in finding the minimum and second-smallest values ​​among 3 / 6 data points. While the traditional serial comparison structure saves resources, it is time-consuming. Therefore, this embodiment designs a novel comparator structure, employing a pipelined design method to accelerate the computation process. A pipeline partition is performed after each comparison calculation to ensure timing requirements, resulting in a network latency of 5 clock cycles. Ultimately, the comparison operation is completed in just 5 clock cycles, shortening the computation time. The 6-input comparator structure is as follows... Figure 3 As shown.

[0067] It should be further explained that the Variable Node Update Processing Unit (VNP) receives the output parity node information and, based on the variable node update calculation formula, sums the variable node initialization information with all parity information in the corresponding column of the parity matrix except for the current node, thus updating the variable node information. According to the structural characteristics of the parity matrix H, the VNP is designed with 20 parallel-working sub-units (VNUs), each responsible for updating the data at one column of node positions simultaneously, efficiently processing the non-zero element positions in each column of the parity matrix.

[0068] Regarding the technical solution of this embodiment, the control module includes a state machine, which contains at least four states: idle, initialization, decoding, and output. It determines whether to terminate the iteration early and output the decoding result by monitoring whether the verification equation is satisfied and whether the current iteration count has reached a preset upper limit. The monitoring verification equation is H*C. T =0, if H*C T =0, then the decoding is complete;

[0069] Specifically, the core function of the control module is to monitor the operating status of VNP and CNP during the decoding process, thereby determining the start-up timing of each processing unit. It also needs to detect whether the decoder has reached the preset maximum number of iterations. Its specific workflow is as follows:

[0070] When symbol information is not transmitted to the decoder, the control module is in an idle state. When symbol information begins to be transmitted, the control module switches from the idle state to the initialization state. In this state, the control module sends a signal to control the decoder to receive the decoded information and store it in the corresponding memory. When a frame of data is received, the control module switches from the initialization state to the decoding state. At this time, the control VNP and CNP start working and continuously monitor their working status until the decoding is completed.

[0071] In summary, such as Figure 1 As shown, the decoder works as follows:

[0072] First, data reception begins. Quantized information is received from the external source and stored in the received information memory. Once a 2048-bit frame is full, the process moves to the variable node processing unit for initialization. Next, iterative decoding begins. Starting with the variable node processing module (VNP), information is transmitted to the verification node processing unit (CNP) for calculation, and then returned to the VNP. Each VNP calculation completes one iteration. During this process, since the variable nodes are already initialized, the verification node processing module directly updates the information stored in the intermediate memory for the first iteration. Afterward, the variable node processing module reads data from the intermediate memory, and the VNU submodule updates the variable node values ​​to complete the iteration. Finally, codeword decision output occurs. The iteration ends, and a hard decision is made on the confidence information updated by the VNP to obtain a binary sequence, which is then verified. If the verification is successful, the iteration ends early, the decoding result is output, and the next frame of data begins processing. If the verification fails, the next iteration begins, continuing until the maximum number of iterations is reached.

[0073] Example 2:

[0074] According to a second aspect of the present invention, the present invention provides a decoding method for an improved partially parallel structure decoder, which uses an improved partially parallel structure decoder described in the first aspect for decoding and employs a normalized minimum sum decoding algorithm, the specific process of which is as follows:

[0075] (1) Channel initial message:

[0076] r ji =0

[0077] q i =L(P i )

[0078] (2) Verify the external information passed from the node to the variable node:

[0079]

[0080] (3) External information passed from the variable node to the verification node:

[0081]

[0082] (4) Decoding decision: After iteration, the posterior probability of the variable node is:

[0083]

[0084] Therefore, the posterior probability is greater than 0, so v i The judgment is 0, otherwise the judgment is 1;

[0085] In the formula, l max The maximum number of iterations is given by q in the l-th iteration. ij The verification node information is r jiThe posterior probability information is q i ;

[0086] Does the information sequence y obtained after the judgment satisfy H*C? T =0, if H*C T If H*C = 0, then decoding is complete; otherwise, H*C is not satisfied. T If the value is 0, then we need to check if the current iteration count has reached l. max If it is not reached, continue iterating; if it has already reached l... max Then the decoding is complete.

[0087] In summary, this invention refines the decoding parallelism from the original M×M submatrix granularity to the M / 4×M / 4 cyclic shift block granularity, increasing column parallelism by 4 times and row parallelism by 4 times. Under the same clock frequency, the decoding throughput is increased by approximately 4 times, meeting the requirements of high-speed data transmission. Furthermore, by utilizing the characteristic of "alternating updates of check nodes and variable nodes", only one storage space is used to alternately store the two types of node information, reducing the number of intermediate message memories by approximately 50%, and significantly reducing chip area and power consumption.

[0088] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0089] For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances. When an element is referred to as being "assembled on," "mounted on," "fixed to," or "set on" another element, it may be directly on the other element or there may be an intermediate element present. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible embodiments.

[0090] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

[0091] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

Claims

1. An improved partial parallel architecture decoder, characterized by, The application relates to a parallel decoding device for CCSDS standard near-earth communication LDPC code, which comprises the following parts: a confidence message storage unit for alternately storing updating information of variable nodes and check nodes by using a single-port storage space, so as to reduce the storage resource requirement; a parallel degree optimization unit, which comprises a variable node processing module and a check node processing module, and the variable node processing module and the check node processing module adopt a parallel division strategy based on a cyclic shift sub-block granularity to further divide an original M*M sub-matrix into M / 4*M / 4 cyclic shift blocks, so as to improve the column parallel degree and the row parallel degree of the decoder; wherein a pipeline type cascade comparator network is integrated in the check node processing module, which is used for realizing extreme value comparison of multi-input data and accelerating the check node information processing; a control unit for dynamically starting and stopping the alternative iteration of the variable node processing unit and the check node processing unit and monitoring the maximum iteration number.

2. An improved partially parallel architecture decoder according to claim 1, wherein: The confidence message storage unit comprises a plurality of double-port RAMs, each of which corresponds to the position of "1" in a check matrix and supports row / column parallel reading and writing by using a cyclic shift address mapping mode, and only one copy of node information can meet the alternative updating requirement of variable nodes and check nodes.

3. An improved partially parallel architecture decoder according to claim 2, wherein: The specific implementation method of the parallel degree optimization unit is as follows: the M*M sub-matrix in the check matrix is divided into a plurality of M / 4*M / 4 cyclic shift blocks; the cyclic shift blocks are used as parallel processing units to construct a decoding structure with row parallel degree and column parallel degree.

4. An improved partially parallel architecture decoder according to claim 3, wherein: The variable node processing module comprises a plurality of parallel variable node updating sub-units, the check node processing module comprises a plurality of parallel check node updating sub-units, and both of them take the M / 4*M / 4 cyclic shift block as the minimum processing granularity to realize partial parallel decoding of the CCSDS standard near-earth communication LDPC code.

5. An improved partially parallel architecture decoder according to claim 4, wherein: The cascade comparator network in the check node processing module comprises the following parts: a plurality of pipeline type comparators are used to compare the absolute values of input data, and each comparator outputs a minimum value and a second minimum value; a symbol bit exclusive OR circuit is used to calculate a global symbol product; the minimum value or the second minimum value is multiplied by a normalization factor and then output.

6. An improved partially parallel architecture decoder according to claim 5, wherein: The control module comprises a state machine, the state machine comprises at least four states of idle, initialization, decoding and output, and whether the iteration is terminated in advance and the decoding result is output is determined by monitoring whether the check equation is satisfied and whether the current iteration number reaches a preset upper limit; where the monitoring check equation is H*C T = 0, if H*C T = 0, then declare the decoding to be finished.

7. An improved decoding method of a partially parallel structured decoder, using an improved partially parallel structured decoder according to any one of claims 1 to 6, characterized in that, a normalization minimum sum decoding algorithm is adopted, and the specific process is as follows: (1) channel initial message: r ji ＝0 q i = L(P i ) (2) external information of check nodes transmitted to variable nodes: (3) external information of variable nodes transmitted to check nodes: (4) decoding decision: the posterior probability of the variable node after iteration is: So the posterior probability is greater than 0, and v i decide 0, otherwise decide 1; In the formula, l max is the maximum iteration number, in the lth iteration, the variable node information is q ij , the check node information is r ji , and the posterior probability information is q i ; Does the information sequence y obtained after the judgment satisfy H*C? T =0, if H*C T = 0, then the decoding is complete; otherwise, H*C is not satisfied. T If the value is 0, then check if the current iteration count has reached l. max If the target is not reached, continue iterating; if the target has been reached... max Then the decoding is complete.

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