A semiconductor device and a method of fabricating the same

Abstract

The application discloses a preparation method of a semiconductor device, comprising the following steps: providing a substrate, wherein a thin film resistance structure is formed on the substrate; sequentially forming a contact intermediate layer, a metal layer and a dielectric reflection layer on the substrate, wherein the contact intermediate layer covers the thin film resistance structure; performing a photoetching process to form a pattern defining a metal wire on the dielectric reflection layer; performing a first etching process to remove the dielectric reflection layer and the metal layer outside the pattern defining the metal wire; and performing a second etching process to remove the contact intermediate layer outside the pattern defining the metal wire, thereby forming a metal wire overlapping the thin film resistance structure, wherein the metal wire is electrically connected to the thin film resistance structure through the bottom contact intermediate layer. The preparation method provided by the application does not need a redundant photoetching step and additional planarization and via etching, and is simple, easy to control and less likely to cause process defects.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and a preparation method of the semiconductor device. BACKGROUND

[0002] Integrated resistor is an important component in analog circuit, and its electrical performance directly affects the precision and stability of the circuit. The traditional diffusion resistor or polysilicon resistor has problems such as large resistance temperature coefficient, poor matching, and high noise. In order to improve the performance, thin film resistors are widely used in high-performance analog circuits due to their near-zero resistance temperature coefficient, low noise, good matching and tunability.

[0003] However, the thin film resistor in the prior art usually includes a thin film resistor layer arranged between two metal layers, and the layers need to be connected through a via hole, which has a complex integrated structure and process.

[0004] Therefore, there is an urgent need for a semiconductor device with a simple process and simplified process to overcome the defects of integrated thin film resistors in the prior art. SUMMARY

[0005] The present application provides a preparation method of a semiconductor device, which can simplify the structure of the semiconductor device and is beneficial to the semiconductor device with a simplified preparation process. The specific scheme is as follows:

[0006] In a first aspect, the present application provides a preparation method of a semiconductor device, comprising:

[0007] providing a substrate, wherein a thin film resistor structure is formed on the substrate;

[0008] forming a contact intermediate layer, a metal layer and a dielectric reflection layer in sequence on the substrate, wherein the contact intermediate layer covers the thin film resistor structure;

[0009] performing a photolithography process to form a pattern defining a metal wire on the dielectric reflection layer;

[0010] performing a first etching process to remove the dielectric reflection layer and the metal layer outside the pattern defining the metal wire;

[0011] performing a second etching process to remove the contact intermediate layer outside the pattern defining the metal wire, thereby forming a metal wire overlapping the thin film resistor structure, wherein the metal wire is electrically connected to the thin film resistor through the bottom contact intermediate layer.

[0012] Optionally, the first etching process is dry etching.

[0013] By adjusting the proportion of nitrogen in the etching gas, the etching selectivity of the metal layer to the contact intermediate layer is improved, so that the etching rate of the metal layer is larger.

[0014] Optionally, the contact intermediate layer has a thickness greater than the thickness of the thin film resistance structure, and the thickness of the contact intermediate layer is greater than or equal to 100 nm and less than or equal to 200 nm.

[0015] Optionally, the metal layer has a thickness greater than the thickness of the thin film resistance structure, and the thickness of the metal layer is greater than or equal to 50 nm and less than or equal to 1000 nm.

[0016] Optionally, the substrate includes a lower via hole, and a metal filled in the lower via hole forms electrical contact with a corresponding portion of the thin film resistance structure.

[0017] Optionally, a bottom dielectric layer is formed on the substrate, and the thin film resistance structure is formed on the bottom dielectric layer.

[0018] In a second aspect, the present application also provides a semiconductor device, comprising:

[0019] a substrate, and a thin film resistance structure, a contact intermediate layer, and a metal layer formed on the substrate in the same layer;

[0020] the thin film resistance structure is on the substrate;

[0021] the contact intermediate layer is on the thin film resistance structure;

[0022] the metal layer is on the contact intermediate layer and forms a metal wire overlapping the thin film resistance structure; the metal wire is ohmically connected to the thin film resistance structure through the contact intermediate layer.

[0023] Optionally, the thickness of the metal wire is ten to one hundred times the thickness of the thin film resistance structure.

[0024] the thickness of the metal layer is greater than the thickness of the thin film resistance structure, and the thickness of the metal layer is greater than or equal to 50 nm and less than or equal to 1000 nm.

[0025] Optionally, the contact intermediate layer has a thickness greater than the thickness of the thin film resistance structure, and the thickness of the contact intermediate layer is greater than or equal to 100 nm and less than or equal to 200 nm.

[0026] Optionally, the substrate includes a lower via hole, and a metal filled in the lower via hole forms electrical contact with a corresponding portion of the thin film resistance structure.

[0027] Optionally, a bottom dielectric layer is formed on the substrate, and the thin film resistance structure is formed on the bottom dielectric layer.

[0028] Optionally, the semiconductor device further comprises an isolation layer, which is wrapped around the semiconductor device.

[0029] In a third aspect, the present application provides a method for manufacturing a semiconductor device, comprising:

[0030] providing a substrate, wherein a thin-film resistor structure is formed on the substrate, and a contact intermediate layer is formed on the thin-film resistor structure;

[0031] forming a metal layer and a dielectric reflective layer on the substrate in sequence, wherein the metal layer and the dielectric reflective layer cover the thin-film resistor structure and the contact intermediate layer;

[0032] performing a photolithography process to form a pattern defining a metal wire on the dielectric reflective layer;

[0033] performing a first etching process to remove the dielectric reflective layer and the metal layer outside the pattern defining the metal wire, so as to expose the contact intermediate layer on the thin-film resistor structure;

[0034] performing a second etching process to remove the remaining metal layer and the exposed contact intermediate layer outside the pattern defining the metal wire, so as to form a metal wire overlapping the thin-film resistor structure, wherein the metal wire is electrically connected to the thin-film resistor structure through the contact intermediate layer at the bottom.

[0035] In a fourth aspect, the present application provides a method for manufacturing a semiconductor device, comprising:

[0036] providing a substrate, wherein a resistor structure is formed on the substrate;

[0037] forming a first conductive layer and a second conductive layer on the substrate in sequence, wherein the second conductive layer covers the resistor structure, and the thickness of the second conductive layer is more than ten times of the resistor structure;

[0038] performing a photolithography process to form a pattern defining a conductive wire on the second conductive layer;

[0039] performing a first etching process to remove the second conductive layer outside the pattern defining the conductive wire;

[0040] performing a second etching process to remove the first conductive layer outside the pattern defining the conductive wire, so as to form a conductive wire overlapping the resistor structure, wherein the conductive wire is electrically connected to the resistor structure through the first conductive layer at the bottom.

[0041] Compared with the prior art, the present application has the following advantages:

[0042] The method for fabricating a semiconductor device provided in this application includes: providing a substrate, forming a thin-film resistor structure on the substrate, and sequentially forming a contact interlayer, a metal layer, and a dielectric reflective layer covering the thin-film resistor structure on the substrate; then performing a photolithography process to define a pattern of metal interconnects; then performing a first etching process to remove the dielectric reflective layer and the metal layer outside the patterned area of ​​the metal interconnects to form metal interconnects; and then performing a second etching process to remove the contact interlayer exposed outside the area of ​​the metal interconnects.

[0043] In the semiconductor device fabrication method provided in this application, the photolithography process can accurately define the pattern of the metal interconnects. The first etching process can simultaneously remove the excess dielectric reflective layer and metal layer, retaining only the metal interconnects that need to be connected to the thin-film resistor structure. The second etching process removes the contact interlayer exposed outside the metal interconnect area, allowing the thin-film resistor structure and the metal interconnects to make electrical contact through the contact interlayer. Notably, the first etching process does not completely remove the contact interlayer, preventing the thin-film resistor structure under the contact interlayer from being over-etched and damaged. The fabrication method provided in this application eliminates redundant photolithography steps and additional planarization and via etching, resulting in a simple, easily controllable process that is less prone to defects. Using the fabrication method provided in this application, the obtained semiconductor device has the thin-film resistor structure and metal layer located on the same layer, eliminating the need for traditional multilayer metal jumper structures. This results in a compact structure, high yield, and a large contact area between the thin-film resistor structure and the metal contact interlayer, leading to better heat dissipation. Attached Figure Description

[0044] Figure 1 This is a flowchart of the method for fabricating the semiconductor device provided in this application.

[0045] Figure 2A This is a first structural diagram of the method for fabricating the semiconductor device provided in this application.

[0046] Figure 2B This is a second structural diagram of the method for fabricating the semiconductor device provided in this application.

[0047] Figure 2C This is the third structural diagram of the semiconductor device fabrication method provided in this application.

[0048] Figure 2D This is the fourth structural diagram of the semiconductor device fabrication method provided in this application.

[0049] Figure 3 This is the fifth structural diagram of the semiconductor device fabrication method provided in this application.

[0050] Figure 4 This is a flowchart of the manufacturing method of the semiconductor device provided in this application.

[0051] Figure 5 This is a flowchart of another manufacturing method for the semiconductor device provided in this application. Detailed Implementation

[0052] To enable those skilled in the art to better understand the technical solutions of this application, the application will be clearly and completely described below with reference to the accompanying drawings of the embodiments. However, this application can be implemented in many other ways different from those described below. Therefore, based on the embodiments provided in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0053] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described in this application. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0054] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0055] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0056] In the design of semiconductor integrated circuits, especially analog and mixed-signal circuits, integrated resistors, as one of the key passive components, are widely used in circuit modules such as amplifiers, reference sources, filters, and data converters. Their electrical performance directly affects the accuracy, stability, and reliability of the circuit. However, traditional integrated resistors based on diffusion regions or polysilicon processes have many performance limitations, such as a large temperature coefficient of resistance (TCR), significant resistance mismatch, high noise levels, and difficulty in achieving precise resistance control, thus limiting the development of high-performance analog circuits. To improve resistor matching characteristics, existing technologies often employ matching layout techniques such as common-centroid layout and dummy structure. Although these techniques can suppress mismatch caused by process gradients to some extent, their optimization effect is limited by process uniformity and increases layout complexity and area overhead.

[0057] To overcome the aforementioned bottlenecks, thin-film resistors have attracted widespread attention due to their superior electrical characteristics. Thin-film resistors are typically fabricated using highly stable alloy materials (such as CrSi, NiCr, and TaSi), exhibiting near-zero total resistance coefficient (TCR), low current noise, good long-term stability, and excellent inter-component matching performance. Furthermore, thin-film resistors support laser trimming or electrical trimming processes, facilitating high-precision resistance adjustment. Therefore, thin-film resistors have become an important technological path for achieving high-precision resistor integration in high-performance analog integrated circuits. Despite the significant performance advantages of thin-film resistors, their conventional integration processes typically involve multiple steps of photolithography, deposition, and etching, resulting in complex processes and high costs. Therefore, how to simplify the structure and manufacturing process of thin-film resistors while ensuring their excellent electrical performance, reducing integration complexity, and improving production yield has become a pressing technical problem to be solved in this field.

[0058] Existing technology provides a method for integrating high-performance thin-film resistors in the back-end interconnect layer (BEOL) of a chip. The core idea involves setting up a layer containing the thin-film resistors, with metal interconnects placed on another layer, which can be called the metal layer. The thin-film resistors are connected to the metal layer via vias between the contact interlayer and the through-layer. The specific process flow includes depositing a CrSi thin film, depositing a contact interlayer, obtaining a patterned thin film using dry etching, and removing the middle portion of the contact interlayer using a combination of dry and wet etching, leaving only the two ends intact. It is evident that this process requires one mask for the first etching (dry etching) and another mask for the second etching (dry etching combined with wet etching). This means that the process requires two masks, and each additional mask adds another step of photolithography, resist coating, development, and etching. This obviously makes the process more complex, increases equipment occupancy, and raises the risk of low yield. Wet etching of the contact intermediate layer not only produces downward etching but also lateral etching. Lateral etching reduces the contact area between the contact intermediate layer and the thin film layer, leading to increased parasitic resistance and low heat dissipation efficiency.

[0059] To address the above issues, this application provides a method for fabricating a semiconductor device, aiming to reduce the complexity of its integrated structure and process while ensuring the excellent electrical performance of the thin-film resistor.

[0060] Please refer to Figure 1 , Figure 1 A flowchart illustrating the fabrication method of the semiconductor device provided in this application embodiment; please also refer to... Figures 2A-2D These four figures illustrate the structural changes of the semiconductor device at key nodes in the fabrication method of the semiconductor device provided in this application embodiment. The raised portions in the figures are intended to more clearly represent the stacked structure inside the semiconductor; the actual morphology is nearly flat. The fabrication method of the semiconductor device includes the following four steps:

[0061] S101: Provide a substrate 201 on which a thin film resistor structure 202 is formed;

[0062] S102: A contact intermediate layer 203, a metal layer 204, and a dielectric reflective layer 205 covering the thin film resistor structure are sequentially formed on the substrate 201.

[0063] The substrate provides physical support for the semiconductor structure and also enables electrical isolation and connection between the semiconductor structure and other electronic components. Optionally, the substrate material can be single-crystal silicon, on which a single-crystal semiconductor thin film is grown using epitaxial growth technology as an epitaxial layer to construct the active region of the high-performance device. Alternatively, a bottom dielectric layer (referred to as the bottom dielectric layer to distinguish it from other dielectric layers that will appear later) can be formed on the single-crystal silicon, such as a SiO2 dielectric layer. The thin-film resistor structure 202 can actually be formed on the bottom dielectric layer. Of course, other materials can also be used for the substrate, such as SiC; the bottom dielectric layer can also be Si3N4, etc. Since the substrate, epitaxial layer, and bottom dielectric layer are not the focus of this application, they are collectively referred to as the substrate. Furthermore, various devices and structures can be formed on the substrate, such as various memory device cells or logic device cells formed through isolation structures. These devices can be formed through front-end manufacturing processes, which will not be elaborated here.

[0064] A thin-film resistor structure 202 is formed on the substrate 201. The thin-film resistor structure 202 can be formed as follows: a thin-film resistor layer is formed on the substrate 201; a photolithography process is performed on the thin-film resistor layer to form a thin-film resistor pattern; according to the thin-film resistor pattern, an etching process is performed to etch the portion of the thin-film resistor layer not covered by the mask, leaving the remaining portion of the thin-film resistor layer as the thin-film resistor structure 202. The thin-film resistor layer can be formed on the substrate by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other deposition methods, preferably PVD. The thin-film resistor layer material can be CrSiN, CrSi, TaSi2, etc., where the proportions of each element are adjustable; the specific element proportions are not specifically limited in this application. The thickness of the thin-film resistor is generally between several hundred angstroms and 1 micrometer. In the embodiments of this application, the typical thickness of the thin-film resistor structure is 5nm-10nm (inclusive). Of course, the thin-film resistor structure can also be fabricated using other methods or processes.

[0065] A contact interlayer and a metal layer are sequentially formed on the substrate. The contact interlayer provides better contact resistance between the metal layer and the thin-film resistor structure. The contact interlayer is typically made of TiN, which has good contact characteristics with both the thin-film resistor layer and the metal, reducing contact resistance and improving interface adhesion and thermal stability, thus effectively enhancing device stability. The formation of the contact interlayer can be achieved through the following process: First, a TiN thin film is uniformly grown on the substrate with the patterned thin-film resistor structure and exposed contact areas via physical vapor deposition or chemical vapor deposition. This TiN layer, as a contact interlayer to improve conductivity, not only has good conductivity and thermal stability but also effectively improves the interface characteristics between the resistor material and the upper metal layer. Finally, the TiN layer forms a high-quality electrical contact between the resistor layer and the metal layer. Besides providing reliable electrical contact between the resistor layer and the metal layer, the contact interlayer also serves as a stop layer in subsequent processes. Therefore, its thickness cannot be too thin to prevent damage to the underlying resistor layer. In one embodiment, the thickness of the deposited contact interlayer is approximately 100 nm-200 nm.

[0066] The metal layer 204 can be formed through the following process: First, plasma cleaning is performed on the surface of the prepared TiN contact intermediate layer 203 to remove surface oxides and organic contaminants, ensuring good interfacial adhesion. Then, a metal material is deposited on the TiN layer via physical vapor deposition or chemical vapor deposition to serve as the conductive metal layer 204. The metal layer is typically made of a material with good conductivity, such as aluminum, copper, tungsten, gold, or silver. The metal layer 204 is deposited on the contact intermediate layer 203. Due to the protrusions caused by the thin-film resistor structure 202, the upper structure also has protrusions. To ensure continuity at these protrusions, the metal layer should be thicker. In one embodiment, the thickness of the deposited metal layer 204 is approximately several tens of times the thickness of the thin-film resistor structure 202. Since the thicknesses of the contact intermediate layer 203 and the metal layer 204 are much greater than the thickness of the thin-film resistor structure 202, the thin-film resistor structure 202, the contact intermediate layer 203, and the metal layer 204, formed sequentially on the substrate, constitute a complete integrated resistor connection structure. The metal layer can be made of materials such as aluminum, copper, or cobalt, with aluminum being the preferred material.

[0067] A dielectric anti-reflective coating (DARC) 205 is formed on the metal layer to suppress light reflection from the metal layer surface during photolithography, reduce standing wave effects and critical dimension (CD) fluctuations, thereby improving photolithography resolution and pattern fidelity. This dielectric anti-reflective coating 205 also improves the interfacial adhesion between the photoresist and the metal layer 204 and isolates the metal layer to prevent contamination during coating and development. In this embodiment, the dielectric anti-reflective coating 205 is made of SiON material.

[0068] S103: Perform a photolithography process to form a pattern defining metal interconnects on the dielectric reflective layer 205.

[0069] This step involves performing a photolithography process on the metal layer to define the pattern of the metal interconnects to be formed, preparing for the next step of etching to form the metal interconnects. The pattern of the metal interconnects can be adjusted according to the number, position, and shape of the thin-film resistor structure, with the aim of etching metal interconnects according to the pattern to cover the thin-film resistor structure and connect the thin-film resistor to the integrated circuit.

[0070] In this step, to protect the metal layer 204, the photoresist directly contacts the dielectric reflective layer 205. Specifically, photoresist is first applied to the surface of the dielectric reflective layer, and the designed pattern is projected onto the photoresist using a mask. Then, a developer is used to dissolve the soluble areas, forming a photoresist pattern consistent with the pattern of the metal interconnects. In the embodiments of this application, the specific circuit pattern is the pattern of the metal interconnects.

[0071] S104: Perform the first etching process to remove the dielectric reflective layer 205 and the metal layer 204 outside the patterned area defining the metal interconnect.

[0072] This step mainly involves performing an etching process to remove the dielectric reflective layer and metal layer that are not protected by photoresist, and cleaning away any residual photoresist.

[0073] The first step is to use the previously formed photoresist pattern as a mask to dry etch the upper dielectric reflective layer 205 to remove the areas not protected by the photoresist; the remaining part is shown in Figure 205-1.

[0074] The second step is to transfer the photoresist pattern from the dielectric reflective layer to the underlying metal layer 204, and then use dry etching to remove the portion of the metal layer that is not protected by the dielectric reflective layer; the remaining portion is shown in Figure 204-1.

[0075] In one embodiment, the first etching process is dry etching. By adjusting the proportion of nitrogen in the etching gas, the etching selectivity of the metal layer for the contact intermediate layer is increased, resulting in a higher etching rate for the metal layer. For example, increasing the nitrogen proportion can help reduce the etching rate of TiN, thereby increasing the selectivity of aluminum for TiN.

[0076] The gases commonly used in dry etching (RIE) vary depending on the metal layer to be etched: AlCu: BCl3 + Cl2 + N2; TiN: Cl2 + HBr or CHF3; CrSi: Cl2 + O2. During the metal etching stage, the plasma etches downwards into the metal layer. When the etching front reaches the surface of the contact intermediate layer, the etching rate drops sharply. The contact intermediate layer acts as an etching stop layer, preventing further downward etching and avoiding penetration into the lower layer or causing a short circuit.

[0077] All steps employ dry etching. However, due to the high etching rate of Cl2 / BCl3 on CrSi and low etching rate on TiN in metal dry etching, this method makes it easier to control the dry etching to stop at the underlying contact interlayer, preventing excessive corrosion of the CrSi thin-film resistor structure through the contact interlayer 203. In practical scenarios, this can be combined with setting a reasonable over-etching time and in-situ endpoint detection to ensure complete removal of the metal layer, even if etching is terminated, without excessive damage to the underlying layer. The final result is a metal interconnected thin-film resistor structure.

[0078] S105: Perform the second etching process to remove the contact interlayer 203-1 outside the patterned area defining the metal interconnects, forming metal interconnects that overlap the thin-film resistor structure. These metal interconnects are electrically connected to the thin-film resistor through the bottom contact interlayer. Since the contact interlayer still covers the thin-film resistor structure and substrate after the previous etching step, a second etching is required to remove the area of ​​the contact interlayer outside the metal interconnects. Because the pattern of the metal interconnects has been defined, the upper metal interconnect pattern can be directly used as a mask for wet etching to remove the exposed area of ​​the contact interlayer, retaining only the area 203-2 covered by the metal interconnects. The remaining contact interlayer 203-2 contacts the thin-film resistor structure 202 from the top and sides, resulting in a large contact area. Consequently, the contact area between the thin-film resistor structure and the metal layer 204-1 through the contact interlayer is also large. The metal layer is etched to form metal interconnects connecting the thin-film resistor structure. There are two ways to implement the metal interconnect overlay thin-film resistor structure. One is, as in this embodiment, the metal layer 204 spans across the thin-film resistor structure 202, thereby leading out one lead of the thin-film resistor structure 202. The other is that the metal interconnect is placed at a certain point on the thin-film resistor structure 202. In practice, the overlay of the metal interconnect only needs to ensure that the metal interconnect is in contact with each part of the thin-film resistor structure. The etching in this step needs to ensure that the contact intermediate layer 203-2 exposed on the surface of the thin-film resistor region is completely etched without any residue, so as not to affect the resistance performance or cause a metal short circuit. In this embodiment, the contact intermediate layer 203 is above the thin-film resistor layer 202, so the use of wet etching will not affect the contact surface between the contact intermediate layer and the thin-film resistor layer. In practice, a contact intermediate layer etching solution that is selectively non-corrosive to CrSi can be used, and the time and temperature can be controlled.

[0079] The thickness of the thin-film resistor is 5-10 nm (inclusive). To ensure the etching window, the thickness of the contact interlayer 203 should not be too small, nor too large to avoid causing additional parasitic resistance. In one embodiment, the thickness of the contact interlayer 203 is much greater than the thickness of the thin-film resistor structure, and the thickness of the contact interlayer 203 is greater than or equal to 100 nm and less than or equal to 200 nm. The thickness of the metal layer is greater than the thickness of the thin-film resistor structure 202, approximately tens of times that of the thin-film resistor, and its range is approximately 50 nm-1000 nm (inclusive). The relationship between the thicknesses of these three elements results in the thickness of the contact interlayer and the metal layer formed on the thin-film resistor being much greater than the thickness of the thin-film resistor itself. Because the resistive layer is very thin, it hardly affects the flatness of the metal surface, so the actual morphology of the formed semiconductor device is almost flat. The raised portion in the figure is intended to more clearly illustrate the internal structural stacking relationship. In other words, the technical solution provided in this application embodiment utilizes the contact intermediate layer 203 to make the thin film resistor structure 202 and the metal layer 204 almost the same layer and form a reliable contact, with little impact on the metal morphology, significantly optimizing the fabrication process and structure of the integrated thin film resistor.

[0080] In one embodiment, the substrate includes a lower via, in which a metal already filled with the lower via forms a reliable contact with a corresponding portion of the thin-film resistor structure 202. For example, prior to the formation of the thin-film resistor structure, a TiN layer is formed between the substrate and the bottom of the thin-film resistor structure 202, through which the metal in the lower via forms a reliable contact with the thin-film resistor structure. The metal filling the lower via can be tungsten. Similarly, an upper via can be formed above the metal layer through a dielectric reflective layer. Devices in other layers of an integrated circuit can be connected through the upper and lower vias.

[0081] As previously described, in one embodiment, a bottom dielectric layer is formed on the substrate, and the thin-film resistor structure is formed on the bottom dielectric layer.

[0082] In one embodiment, an isolation layer is also formed to protect the internal structure of the entire semiconductor device. This isolation layer is typically made of SiO2, which needs to completely cover the CrSi sidewalls to fill the area around the resistors and the regions hollowed out by wet etching, insulate the sidewalls of the resistive structure, prevent short circuits, and provide a planarization basis for subsequent chemical mechanical polishing.

[0083] The semiconductor device fabrication method provided in this application provides a substrate and a thin-film resistor structure formed thereon. A contact interlayer, a metal layer, and a dielectric reflective layer covering the thin-film resistor structure are formed on the substrate. The layers are formed by direct deposition without the need for via connections. A photolithography process is then performed on the metal layer to define the pattern of metal interconnects. This single-defined pattern can be used to etch both layers, i.e., the dielectric reflective layer and the metal layer are etched according to the pattern of the metal interconnects. Further etching is performed on the contact interlayer exposed outside the metal interconnect pattern to form the final semiconductor device. Since this process uses only one mask to complete the etching of the metal layer, dielectric reflective layer, and contact interlayer, compared to the prior art which requires additional patterning of the contact interlayer and uses two masks, the fabrication process of this application is simpler, with more accurate single-step positioning, smaller errors, and higher yield. The semiconductor device fabricated using the technical solution provided in this application has the advantages of compact structure and good heat dissipation.

[0084] This application also provides a semiconductor device corresponding to the semiconductor device fabrication method embodiment provided in the foregoing embodiments. Since the structural features in the semiconductor device embodiment are basically the result of the various process features in the method embodiment, the description is relatively simple. For details of the relevant technical features and their effects, please refer to the corresponding descriptions of the semiconductor device fabrication method embodiments provided above.

[0085] Please also refer to Figure 2D and Figure 3 , Figure 2D This is a schematic diagram of the fourth structure of the semiconductor device provided in the embodiments of this application. Figure 3 This is a fifth structural schematic diagram of a semiconductor device provided in an embodiment of this application.

[0086] The semiconductor device provided in this application includes:

[0087] Substrate 201, and thin film resistor structure 202, contact intermediate layer 203-2, metal layer 204-1 and dielectric reflective layer 205-1 formed on the same layer of said substrate;

[0088] The thin-film resistor structure 202 is on the substrate;

[0089] The contact intermediate layer 203-2 is on top of the thin film resistor structure;

[0090] The metal layer 204-1 is on the contact intermediate layer 203-2 and forms a metal interconnect 204-1 that overlaps the thin film resistor structure 202;

[0091] The metal wire 204-1 is ohmically connected to the thin film resistor structure 202 through the contact intermediate layer 203-2;

[0092] The dielectric reflective layer 205-1 is on the metal interconnect 204-1.

[0093] The substrate serves to provide physical support for the semiconductor structure and to achieve electrical isolation and connection between the semiconductor structure and other electronic components. Optionally, the substrate material can be a Si, SiC, or CoSi compound. A bottom dielectric layer is formed on the upper surface of the substrate. In this embodiment, the bottom dielectric layer can be made of SiO2. The thin-film resistor structure can be two separate parts. In this embodiment, the thickness of the thin-film resistor structure is 5nm-10nm (inclusive), and its length and width are preferably such that they do not extend beyond the edge of the substrate.

[0094] The contact interlayer enables good electrical contact between the metal layer and the thin-film resistor structure. The contact interlayer is typically made of TiN, which has good contact characteristics with both the thin-film resistor layer and the metal, thus reducing contact resistance and improving device stability. Since the thickness of the contact interlayer and the metal layer is much greater than the thickness of the thin-film resistor structure, the thin-film resistor structure, the contact interlayer, and the metal layer sequentially formed on the substrate constitute a complete integrated resistor connection structure. The metal layer can be made of aluminum, copper, cobalt, etc., but aluminum is preferred.

[0095] The dielectric reflective layer is used to reduce reflection from the metal layer during photolithography, prevent the photoresist from adhering to the metal layer, prevent contamination of the metal during coating / development, avoid standing wave effects and CD fluctuations, and improve photolithography resolution and pattern fidelity. The dielectric anti-reflective layer can be made of SiON.

[0096] To ensure the etching window, the thickness of the contact interlayer should not be too small, nor too large to avoid causing additional parasitic resistance. In one embodiment, the thickness of the contact interlayer is greater than the thickness of the thin-film resistor structure, and the thickness of the contact interlayer is greater than or equal to 100 nm and less than or equal to 200 nm. In one embodiment, the thickness of the metal interconnect is ten to one hundred times the thickness of the thin-film resistor structure. In one embodiment, the thickness of the metal layer is greater than the thickness of the thin-film resistor structure, and the thickness of the metal layer is greater than or equal to 50 nm and less than or equal to 1000 nm. The relationship between these three thicknesses means that the thickness of both the contact interlayer and the metal layer formed on the thin-film resistor is much greater than the thickness of the thin-film resistor itself. Because the resistor layer is very thin, it hardly affects the flatness of the metal surface, so the actual morphology of the formed semiconductor device is almost flat. The protrusions in the figures are intended to more clearly illustrate the internal structural stacking relationship. In other words, the technical solution provided by the embodiments of this application utilizes the contact interlayer to allow the thin-film resistor structure and the metal layer to be regarded as being fabricated in the same layer and forming a reliable contact, significantly simplifying the structure of the integrated thin-film resistor.

[0097] In one embodiment, the substrate includes a lower via 206 filled with metal and reliably contacting a corresponding portion of the thin-film resistor structure 202. In fact, prior to the formation of the thin-film resistor structure, a TiN layer is formed between the substrate and the bottom of the thin-film resistor structure 202, through which the metal in the lower via forms reliable contact with the thin-film resistor structure. The metal filled in the lower via can be tungsten.

[0098] As previously described, in one embodiment, a bottom dielectric layer is formed on the substrate, and the thin-film resistor structure is formed on the bottom dielectric layer.

[0099] In one embodiment, the semiconductor device further includes an isolation layer surrounding the semiconductor device.

[0100] The semiconductor device provided in this application has a compact structure, simple manufacturing process, and good heat dissipation performance. This semiconductor device forms the thin-film resistor structure and the metal layer in the same layer through a contact interlayer, eliminating the need for via connections and simplifying the device structure. Simultaneously, the increased contact area between the contact interlayer and the thin-film resistor structure improves the heat dissipation capacity of the resistor structure. The patterns of the dielectric reflective layer, the metal layer, and the contact interlayer are identical to the pattern of the metal interconnects. Therefore, the manufacturing process of this semiconductor device requires only one photomask and one positioning step, resulting in a simple and accurate process, thus leading to better quality and higher yield.

[0101] This application also provides a method for manufacturing a semiconductor device. Since the foregoing embodiments are substantially similar to the foregoing preparation method embodiments, they are described in a relatively simple manner. For details regarding the relevant technical features and their effects, please refer to the corresponding descriptions of the semiconductor device preparation method embodiments provided above.

[0102] Please refer to Figure 4 , Figure 4 A method for manufacturing a semiconductor device provided in the embodiments of this application.

[0103] This application also provides a method for manufacturing a semiconductor device, including:

[0104] S401: Provide a substrate on which a thin-film resistor structure is formed, and a contact interlayer is formed on the thin-film resistor structure;

[0105] S402: A metal layer and a dielectric reflective layer covering the thin-film resistor structure and the contact intermediate layer are sequentially formed on the substrate;

[0106] S403: Perform a photolithography process to form a pattern defining metal interconnects on the dielectric reflective layer;

[0107] S404: Perform the first etching process to remove the dielectric reflective layer and metal layer outside the patterned area defining the metal interconnect, until the contact intermediate layer on the thin film resistor structure is exposed;

[0108] S405: Perform a second etching process to remove the remaining metal layer and exposed contact intermediate layer outside the patterned area of ​​the defined metal interconnect, forming a metal interconnect that overlaps the thin film resistor structure. The metal interconnect is electrically connected to the thin film resistor structure through the bottom contact intermediate layer.

[0109] In this embodiment, a thin-film resistor structure has been formed on the provided substrate, and a contact intermediate layer has been formed on the thin-film resistor structure; the subsequent process can directly deposit a metal layer on the already processed substrate, and then form a pattern defining the metal interconnects.

[0110] The embodiments of this application also provide a method for manufacturing semiconductor devices that can incorporate the process of forming a contact intermediate layer on a substrate into the substrate manufacturing process, thereby simplifying the subsequent semiconductor device fabrication process.

[0111] This application also provides another method for manufacturing a semiconductor device. Since the foregoing embodiments are essentially similar to the foregoing preparation method embodiments, they are described simply. For details of the relevant technical features and their effects, please refer to the corresponding descriptions of the semiconductor device preparation method embodiments provided above.

[0112] Please refer to Figure 5 , Figure 5 This application provides a method for manufacturing a semiconductor device. This application also provides a method for manufacturing a semiconductor device, comprising:

[0113] S501: Provide a substrate on which a resistive structure is formed;

[0114] S502: A first conductive layer and a second conductive layer covering the resistive structure are formed on the substrate at one time, wherein the thickness of the second conductive layer is more than ten times that of the resistive structure;

[0115] S503: Perform a photolithography process to form a pattern defining conductive interconnects on the second conductive layer;

[0116] S504: Perform the first etching process to remove the second conductive layer outside the patterned area defining the conductive interconnects;

[0117] S505: Perform a second etching process to remove the first conductive layer outside the patterned area defining the conductive connection, forming a conductive connection that overlaps the resistor structure. The conductive connection is electrically connected to the resistor structure through the bottom first conductive layer.

[0118] The embodiments of this application aim to provide a process flow for semiconductor devices. The provided substrate can be any resistive structure other than a thin-film resistor; as long as these resistive structures are fabricated according to this method, the improved process effect can be achieved. Considering that different resistive structures may have different thicknesses, the thickness needs to be considered when forming the conductive layer. The first conductive layer can be the metal layer in the above embodiments, and the second conductive layer can be a contact intermediate layer. In order to form a continuous and flat conductive layer on the resistive structure of the substrate, the thickness of the second conductive layer should be more than ten times that of the resistive structure. The first conductive layer, as the main conductive channel of the resistor, is usually made of a material with good conductivity, such as aluminum or copper. The second conductive layer needs to achieve reliable contact between the first conductive layer and the resistive layer; materials that can be used include TaN (tantalum nitride), Ti / TiN (composite layer), and WN (tungsten nitride).

[0119] The semiconductor device manufacturing method of this application provides a better solution for the application of resistors in semiconductor devices. This method has a simple process flow and is controllable. Furthermore, the semiconductor device produced using this method forms a multi-layer structure within a single layer, eliminating the need for vias or other connection structures. Therefore, the semiconductor device has a simple structure and a high yield.

[0120] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0121] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0122] 1. Computer-readable media includes both permanent and non-permanent, removable and non-removable media, which can store information by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined in this application, computer-readable media does not include non-transitory computer-readable media, such as modulated data signals and carrier waves.

[0123] 2. Those skilled in the art will understand that embodiments of this application can provide methods, systems, or computer program products. Therefore, embodiments of this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, embodiments of this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0124] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided on which a thin-film resistor structure is formed; A contact interlayer, a metal layer, and a dielectric reflective layer covering the thin-film resistor structure are sequentially formed on the substrate. A photolithography process is performed to form a pattern defining metal interconnects on the dielectric reflective layer; Perform a first etching process to remove the dielectric reflective layer and metal layer outside the patterned area defining the metal interconnects; A second etching process is performed to remove the contact interlayer outside the patterned area defining the metal interconnect, forming a metal interconnect that overlaps the thin film resistor structure. The metal interconnect is electrically connected to the thin film resistor through the bottom contact interlayer. The first etching process is dry etching; by adjusting the proportion of nitrogen in the etching gas, the etching selectivity of the metal layer to the contact intermediate layer is increased, resulting in a higher etching rate for the metal layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The thickness of the contact interlayer is greater than the thickness of the thin film resistor structure, and the thickness of the contact interlayer is greater than or equal to 100 nm and less than or equal to 200 nm.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The thickness of the metal layer is greater than the thickness of the thin-film resistor structure, and the thickness of the metal layer is greater than or equal to 50 nm and less than or equal to 1000 nm.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The substrate includes a lower via, in which a metal already filled with metal forms an electrical contact with a corresponding portion of the thin-film resistor structure.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, A bottom dielectric layer is formed on the substrate, and the thin-film resistor structure is formed on the bottom dielectric layer.

6. A semiconductor device, prepared by any one of the methods of claims 1-5, characterized in that, include: Substrate, and thin-film resistor structure, contact interlayer and metal layer formed on the same layer of said substrate; The thin-film resistor structure is on the substrate; The contact interlayer is on a thin-film resistor structure; The metal layer is on the contact intermediate layer and forms a metal interconnect that overlaps the thin film resistor structure; the metal interconnect is ohmically connected to the thin film resistor structure through the contact intermediate layer.

7. The semiconductor device according to claim 6, characterized in that, The thickness of the metal interconnect is ten to one hundred times the thickness of the thin-film resistor structure.

8. The semiconductor device according to claim 6, characterized in that, The thickness of the metal layer is greater than the thickness of the thin-film resistor structure, and the thickness of the metal layer is greater than or equal to 50 nm and less than or equal to 1000 nm.

9. The semiconductor device according to claim 6, characterized in that, The thickness of the contact interlayer is greater than the thickness of the thin film resistor structure, and the thickness of the contact interlayer is greater than or equal to 100 nm and less than or equal to 200 nm.

10. The semiconductor device according to claim 6, characterized in that, The substrate includes a lower via filled with metal and in electrical contact with a corresponding portion of the thin-film resistor structure.

11. The semiconductor device according to claim 6, characterized in that, A bottom dielectric layer is formed on the substrate, and the thin-film resistor structure is formed on the bottom dielectric layer.

12. The semiconductor device according to claim 6, characterized in that, The semiconductor device also includes an isolation layer that surrounds the semiconductor device.

13. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided on which a thin-film resistor structure is formed, and a contact interlayer is formed on the thin-film resistor structure; A metal layer and a dielectric reflective layer covering the thin-film resistor structure and the contact intermediate layer are sequentially formed on the substrate; A photolithography process is performed to form a pattern defining metal interconnects on the dielectric reflective layer; Perform a first etching process to remove the dielectric reflective layer and metal layer outside the patterned area defining the metal interconnects, until the contact interlayer on the thin film resistor structure is exposed; A second etching process is performed to remove the remaining metal layer and exposed contact intermediate layer outside the patterned area of ​​the defined metal interconnect, forming a metal interconnect that overlaps the thin film resistor structure. The metal interconnect is electrically connected to the thin film resistor structure through the bottom contact intermediate layer. The first etching process is dry etching; by adjusting the proportion of nitrogen in the etching gas, the etching selectivity of the metal layer to the contact intermediate layer is increased, resulting in a higher etching rate for the metal layer.

14. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, on which a resistive structure is formed; A first conductive layer and a second conductive layer covering the resistive structure are formed on the substrate in one step, wherein the thickness of the second conductive layer is more than ten times that of the resistive structure; A photolithography process is performed to form a pattern defining conductive interconnects on the second conductive layer; Perform a first etching process to remove the second conductive layer outside the patterned area defining the conductive interconnects; A second etching process is performed to remove the first conductive layer outside the patterned area defining the conductive interconnect, forming a conductive interconnect that overlaps the resistor structure. The conductive interconnect is electrically connected to the resistor structure through the bottom first conductive layer. The first etching process is dry etching; by adjusting the proportion of nitrogen in the etching gas, the etching selectivity of the metal layer to the contact intermediate layer is increased, resulting in a higher etching rate for the metal layer.

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