SiC trench gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with heterojunction diode and preparation method thereof

Abstract

The invention relates to the technical field of power semiconductors, in particular to a SiC trench gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with a heterojunction diode and a preparation method thereof. According to the invention, heavily-doped P-type polycrystalline silicon or NiO penetrating into the heavily-doped N-type current enhancement layer in the SiC body is respectively arranged at the four corners in the cell, and each surface of the heavily-doped P-type polycrystalline silicon or NiO and the N-type current enhancement layer form a heterojunction diode with low turn-on voltage drop; and the N-type current enhancement layer and the surface metal between the two heterojunction columns on each side of the groove form a Schottky diode. According to the invention, by adopting the scheme that the cylindrical heterojunction goes deep into the SiC body to form the heterojunction diode, the current path during forward and reverse conduction can be obviously increased, so that the forward specific on-resistance and reverse conduction voltage drop are reduced.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of power semiconductors, in particular to a SiC trench gate MOSFET integrated with a heterojunction diode and a preparation method thereof. BACKGROUND

[0002] SiC trench gate power MOSFET has the advantages of high channel density, high withstand voltage and low specific on-resistance, and is very suitable for high-frequency, high-voltage and high-power power electronic system applications. However, the gate oxide layer of the trench gate MOSFET cannot have a reliable breakdown voltage exceeding 4 MV / cm, so special protection needs to be provided for the trench gate oxide layer. The most common technique is to make a P-type electric field shielding region at the bottom of the trench or on both sides of the trench, as described in references 1 (Rupp, Roland. "CoolSiC TM and major trend in SiC powerdevice development." 2017 47th European Solid-State Device Research Conference (ESSDERC). IEEE, 2017.) and 2 (Nakano Y, Nakamura R, Sakairi H, Mitani S and Nakamura T 2012 690V, 1.00mΩ·cm2 4H-SiC double-trench MOSFETs Mater. Sci. Forμm 717-720 1069-72).

[0003] The conventional technology uses Al ion implantation to form a deep P region, but the PN junction diode formed by the P region and the N-type withstand voltage layer has an opening voltage drop of about 3V during reverse current continuation, and the conduction voltage drop is generally 4-5V. This results in very large conduction loss during reverse current continuation, and since the PN junction diode is used for current continuation, there is a large reverse recovery loss, and the reverse recovery loss increases significantly with temperature.

[0004] To solve this problem, a scheme of integrating a reverse parallel heterojunction diode in a SiC MOSFET (i.e. a SiC trench gate MOSFET integrated with a heterojunction current continuation diode, patent No. ZL201810920890.6) is proposed. This structure can significantly reduce the conduction loss, and the reverse recovery loss is not affected by temperature. However, the heterojunction diode in the prior art occupies a large cell area, reducing the channel density and thus damaging the specific on-resistance.

[0005] Therefore, we propose a SiC trench gate MOSFET integrated with a heterojunction diode and a preparation method thereof. SUMMARY

[0006] The present application aims to provide a SiC trench gate MOSFET integrated with a heterojunction diode and a preparation method thereof to solve the problems in the background art.

[0007] To solve the above technical problems, the present application provides the following technical solutions:

[0008] A preparation method of a SiC trench gate MOSFET integrated with a heterojunction diode, comprising the following steps:

[0009] Step S1: selecting an N+ heavily doped SiC substrate; forming an N-type buffer layer on the N+ heavily doped SiC substrate by epitaxial growth; forming an N-type lightly doped voltage-resisting layer on the N-type buffer layer by epitaxial growth; depositing a SiO2 hard mask layer on the upper surface of the N-type lightly doped voltage-resisting layer, coating glue, exposing and developing, dry etching the SiO2 hard mask layer to the SiC surface, and removing the glue; depositing a SiO2 protective layer on the upper surface of the N-type lightly doped voltage-resisting layer, forming a P-type electric field shielding region by aluminum ion implantation, and removing the protective layer;

[0010] Step S2: epitaxially growing N-type current enhancement layer SiC on the P-type electric field shielding region; the upper surface of the N-type current enhancement layer SiC is referred to as the upper surface of the device; depositing a SiO2 hard mask layer on the upper surface of the device, coating glue, exposing and developing, dry etching the SiO2 hard mask layer to the SiC surface, and removing the glue; depositing a SiO2 protective layer, forming a P-type channel body region by aluminum ion implantation, and removing the protective layer;

[0011] Step S3: depositing a SiO2 hard mask layer on the upper surface of the device, coating glue, exposing and developing, dry etching the SiO2 hard mask layer to the SiC surface, and removing the glue; depositing a SiO2 protective layer, forming a P+ heavily doped source ohmic contact region on the upper surface of the device by aluminum ion implantation, and removing the protective layer;

[0012] Step S4: depositing a SiO2 hard mask layer on the upper surface of the device, coating glue, exposing and developing, and removing the glue; depositing a SiO2 protective layer; forming an N+ heavily doped source ohmic contact region on the upper surface of the device by nitrogen ion implantation, and removing the protective layer;

[0013] Step S5: depositing a SiO2 hard mask layer on the upper surface of the device, coating glue, exposing and developing, dry etching the hard mask layer, and then etching the SiC, with the etching depth of the SiC being 1.5-2.5 μm, to form a trench, and removing the glue; depositing a 100-200 nm SiO2 side wall protective layer, forming an electric field shielding layer below the trench by aluminum ion implantation, and removing the SiO2 side wall protective layer and the hard mask layer;

[0014] Step S6: Carbon film preparation, after activation at 1600-1700℃ for 5-10 minutes, remove the carbon film, then form a gate dielectric layer on the electric field shielding layer by thermal oxidation or deposition process; fill polysilicon, etch back to the upper surface of SiC, form polysilicon gate;

[0015] Step S7: deposit SiO2 hard mask layer on the upper surface of the device, coat glue, expose and develop, dry etch the hard mask layer and SiC to expose the P-type electric field shielding area, form a deep trench, and remove the glue;

[0016] Step S8: fill the deep trench by chemical vapor deposition or sputtering process to form heavily doped P-type polysilicon or NiO, and then chemical mechanical polishing to the upper surface of the device;

[0017] Step S9: deposit SiO2 layer on the surface of SiC to form a dielectric isolation layer, coat glue, expose and develop, etch the dielectric isolation layer, remove the glue, then make ohmic metal on both sides of the dielectric isolation layer to form source ohmic contact metal and gate ohmic contact metal, and form ohmic contact at a temperature of 1000℃ in a nitrogen atmosphere;

[0018] Step S10: evaporate or sputter metal, coat glue, expose and develop, dry or wet etch to form source electrode on the source ohmic contact metal and gate electrode on the gate ohmic contact metal; remove the glue; make polyimide passivation layer, coat glue, expose and develop, etch the polyimide passivation layer, expose the source electrode and gate electrode pad area, and remove the glue;

[0019] Step S11: back thinning, make drain metal electrode on the back of the N+ heavily doped SiC substrate by evaporation or sputtering process, and laser anneal the alloy.

[0020] In the above technical solution one, a heavily doped P-type polysilicon or NiO which deeply penetrates into the N-type current enhancement layer of the SiC body is arranged at each of the four corners of a cell, and each face of the heavily doped P-type polysilicon or NiO forms a heterojunction diode with the N-type current enhancement layer, which significantly reduces the reverse on-voltage of the PN junction diode. The heterojunction diode is a unipolar device, has low reverse recovery loss, and the leakage current does not increase with temperature when the voltage is applied, which solves the problem of soft breakdown caused by the increase of leakage current with temperature when integrating Schottky diodes. Each face of the heavily doped P-type polysilicon or NiO forms a heterojunction diode, which increases the area of the heterojunction and further reduces the reverse on-voltage. At the same time, an additional current path is introduced between the two polysilicon columns or NiO columns on each side of the slot gate, which can further reduce the forward specific on-resistance.

[0021] Further, after the step S9, a source electrode with Schottky contact is made on the source ohmic contact metal, the P+ heavily doped source ohmic contact region, the heavily doped P-type polysilicon or NiO, and the current enhancement layer. The specific steps are as follows: gluing, exposure and development, etching the contact area on the surface of the source ohmic contact metal, the P+ heavily doped source ohmic contact region, the heavily doped P-type polysilicon or NiO, the gate ohmic contact metal and part of the current enhancement layer, and removing the glue; making metal by evaporation or sputtering process; gluing, exposure and development, etching the metal by dry or wet etching, and removing the glue; forming the source electrode and the gate electrode at 400-500℃, and the Schottky diode is formed between the current enhancement layer and the source electrode; making a polyimide passivation layer, gluing, exposure and development, etching the polyimide passivation layer, and exposing the source electrode and the gate electrode pad area, and removing the glue.

[0022] Further, in the step S1, the doping concentration of the N-type lightly doped voltage-resisting layer is 5e15-2e16 cm -3 , and the doping concentration of the N-type current enhancement layer is 5e16-5e17 cm -3 .

[0023] Further, in the step S2, the thickness of the SiO2 layer is 30-50nm.

[0024] Further, in the step S3, the thickness of the SiO2 layer is 30-50nm.

[0025] Further, the thickness of the hard mask is 2-5μm.

[0026] Further, in the step S6, the thermal oxidation growth temperature is 1000-1100℃, and the thickness of the gate dielectric layer is 30-50nm.

[0027] Further, in the step S8, the heavily doped P-type polysilicon or NiO is specifically the heavily doped P-type polysilicon or the heavily doped NiO, wherein the heavily doped P-type polysilicon is the CVD-grown in-situ doped heavily doped P-type polysilicon, and the heavily doped NiO is the sputtered heavily doped P-type NiO, and the doping concentration is 1e18-1e20 cm -3 .

[0028] Further, in the step S9, the dielectric isolation layer is the SiO2 layer with a thickness of 0.5-1.0μm, and the ohmic metal is Ni with a thickness of 100-200nm.

[0029] The application discloses a SiC trench gate MOSFET integrated with a heterojunction diode, which comprises a SiC substrate, a drain metal electrode arranged on a lower surface of the SiC substrate, an N-type buffer layer, an N-type lightly-doped voltage-resisting layer and a P-type electric field shielding region arranged in sequence on an upper surface of the SiC substrate, wherein the P-type electric field shielding region is embedded on the N-type lightly-doped voltage-resisting layer, and the P-type electric field shielding region is connected with a heavily-doped P-type polysilicon or NiO, an electric field shielding layer and a bottom part of an N-type current enhancement layer; an N-type current enhancement layer and a trench gate structure are arranged on an upper surface of the P-type electric field shielding region, the trench gate structure extends in a one-dimensional direction and is embedded in the N-type current enhancement layer at a lower end, and the trench gate structure is composed of a gate dielectric layer and a polysilicon gate filled in a groove, and an upper end of the polysilicon gate is connected with a gate ohmic contact metal.

[0030] An upper surface of the N-type current enhancement layer is provided with a P-type channel body region, the P-type channel body region is located on both sides of the trench gate structure and is in contact with the gate dielectric layer; and an upper surface of the P-type channel body region is provided with an adjacent N+ heavily-doped source ohmic contact region and a P+ heavily-doped source ohmic contact region, the source ohmic contact region is located on both sides of the trench gate structure and is in contact with the gate dielectric layer.

[0031] Heavily-doped P-type polysilicon or NiO is arranged on both sides of the N-type current enhancement layer, the heavily-doped P-type polysilicon or NiO is located at four corners in a cell, an upper end of the heavily-doped P-type polysilicon or NiO is covered with a source ohmic contact metal, a lower end of the heavily-doped P-type polysilicon or NiO extends downwards in sequence through the P+ heavily-doped source ohmic contact region, the P-type channel body region and the N-type current enhancement layer, and a bottom part of the heavily-doped P-type polysilicon or NiO is in contact with an upper surface of the P-type electric field shielding region; a source ohmic contact metal is arranged on the N+ heavily-doped source ohmic contact region and the P+ heavily-doped source ohmic contact region, a source electrode is arranged on the source ohmic contact metal, a gate electrode is arranged on the gate ohmic contact metal, and the source ohmic contact metal and the gate ohmic contact metal are isolated by a dielectric isolation layer.

[0032] Further, a grounded electric field shielding layer is arranged directly below the trench gate structure, the electric field shielding layer is connected with the N-type current enhancement layer on both sides and is connected with the electric field shielding region at a bottom part.

[0033] Further, the application further comprises a source electrode with a Schottky contact, the source electrode is arranged on surfaces of the source ohmic contact metal, the P+ heavily-doped source ohmic contact region, the heavily-doped P-type polysilicon or NiO and part of the current enhancement layer, and forms a Schottky diode with the current enhancement layer.

[0034] In the above technical solution two, four corners in a cell are respectively provided with heavily doped P-type polysilicon or NiO of N-type current enhancement layer deeply doped in SiC body, each surface forms a heterojunction diode with the N-type current enhancement layer, and the solution two forms a Schottky diode through the N-type current enhancement layer and the surface metal between the two heterojunction columns on each side of the groove, and the combination of the Schottky diode and the heterojunction diode is realized. Generally, the heterojunction diode formed by SiC and P-type polysilicon or NiO has a higher opening voltage than the opening voltage of the Schottky diode; compared with the original solution, the solution two can significantly reduce the reverse conduction voltage drop of the PN junction diode by integrating the Schottky diode on the surface of SiC and the composite structure of the heterojunction diode in the body, and the reverse conduction voltage drop is lower than that of the pure heterojunction diode, and the heterojunction diode and the Schottky diode are unipolar devices, and the reverse recovery loss is low, and since the heterojunction diode is integrated in the body with a large area, the spacing between the two heterojunction columns, i.e. the additional current path area in the figure, can be reduced to a certain extent, and a lower conduction voltage drop can be obtained. Reducing the above spacing can help the Schottky diode on the surface to form a stronger electric field protection, thereby reducing the leakage current of the Schottky diode and improving the technical problem that the leakage current of the Schottky diode increases sharply with temperature when the voltage resistance is high. In addition, the introduction of the additional current path between the two polysilicon columns or NiO columns on each side of the groove can further reduce the forward specific on-resistance.

[0035] Compared with the prior art, the beneficial effects of the present application are as follows:

[0036] 1. The SiC trench gate MOSFET integrated with a heterojunction diode and a preparation method thereof, by adopting the scheme of embedding the columnar heterojunction diode into the SiC body, the current path during forward and reverse conduction can be significantly increased, thereby reducing the forward specific on-resistance and the reverse conduction voltage drop.

[0037] 2. The SiC trench gate MOSFET integrated with a heterojunction diode and a preparation method thereof, by introducing the heterojunction diode, the body diode reverse current can be avoided, the conduction voltage drop is reduced, and the PN junction injection is avoided, thereby reducing the reverse recovery loss. More importantly, the heterojunction diode is locally embedded in the SiC body in the form of a column, and the conduction channel is increased between each two columns, thereby reducing the forward and reverse on-resistance.

[0038] 3. The SiC trench gate MOSFET integrated with a heterojunction diode and a preparation method thereof, by introducing an additional low-opening-voltage Schottky diode on the surface of SiC between the heterojunction diodes, the reverse conduction voltage drop is further reduced. BRIEF DESCRIPTION OF DRAWINGS

[0039] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and are meant to explain the present application but are not intended to limit the application. In the drawings:

[0040] Figure 1 is a schematic diagram of the complete cell structure of Example 1 in the present application;

[0041] Figure 2 is a schematic diagram of the cut along the dotted line of Example 1 in the present application;

[0042] Figure 3 is a schematic diagram of the complete cell structure of Example 1 in the present application after removing the dielectric isolation layer and the source ohmic contact metal;

[0043] Figure 4 is a schematic diagram of the complete cell structure of Example 1 in the present application after removing the heavily doped P-type polysilicon or NiO;

[0044] Figures 5-7 is a schematic diagram of the process flow of Example 1 in the present application.

[0045] Figure 8 is a schematic diagram of the complete cell structure of Example 2 in the present application;

[0046] Figure 9 is a schematic diagram of the cut along the dotted line of Example 2 in the present application;

[0047] Figure 10 is a schematic diagram of the complete cell structure of Example 2 in the present application after removing the dielectric isolation layer, the source ohmic contact metal and the source electrode;

[0048] Figure 11 is a schematic diagram of the complete cell structure of Example 2 in the present application after removing the heavily doped P-type polysilicon or NiO;

[0049] Figures 12-14 is a schematic diagram of the process flow of Example 2 in the present application.

[0050] In the figure: 4 is the drain metal electrode, 3 is the SiC substrate, 2 is the N-type buffer layer, 1 is the N-type lightly doped voltage-resisting layer, 5 is the N-type current-enhancing layer, 6 is the electric field shielding layer, 7 is the P-type channel body region, 8 is the N+ heavily doped source ohmic contact region, 9 is the P+ heavily doped source ohmic contact region, 10 is the gate dielectric layer, 11 is the polysilicon gate, 12 is the heavily doped P-type polysilicon or NiO, 13 is the source ohmic contact metal, 14 is the gate ohmic contact metal, 15 is the P-type electric field shielding region, 16 is the dielectric isolation layer, and 17 is the source electrode with Schottky contact. DETAILED DESCRIPTION

[0051] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be clearly and completely described below, obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work belong to the scope of protection of the present application.

[0052] Embodiment 1: A preparation method of a SiC trench gate MOSFET integrated with a heterojunction diode, comprising the following processes:

[0053] Step S1: Selecting an N+ heavily doped SiC substrate 3; forming an N-type buffer layer 2 on the N+ heavily doped SiC substrate 3 by epitaxial growth; forming an N-type lightly doped voltage-resistant layer 1 on the N-type buffer layer 2 by epitaxial growth; depositing a 2-micron SiO2 hard mask layer on the upper surface of the N-type lightly doped voltage-resistant layer 1, coating, exposing, developing, dry etching the SiO2 hard mask layer to the SiC surface, and removing the glue; depositing a 30-nanometer SiO2 protective layer, forming a P-type electric field shielding region 15 by aluminum ion implantation, and removing the protective layer;

[0054] Step S2: Epitaxially growing an N-type current enhancement layer 5 on the P-type electric field shielding region 15; at this time, the upper surface of the N-type current enhancement layer 5 is located on the upper surface of the device; depositing a 2-micron SiO2 hard mask layer on the upper surface of the device, coating, exposing, developing, dry etching the SiO2 hard mask layer to the upper surface of the device, and removing the glue; depositing a 30-nanometer SiO2 protective layer, forming a P-type channel body region 7 by aluminum ion implantation on the upper surface of the device, and removing the protective layer;

[0055] Step S3: Depositing a 3-micron SiO2 hard mask layer on the upper surface of the device, coating, exposing, developing, dry etching the SiO2 hard mask layer to the SiC surface, and removing the glue; depositing a 30-nanometer SiO2 protective layer, forming a P+ heavily doped source ohmic contact region 9 by aluminum ion implantation on the upper surface of the device, and removing the protective layer;

[0056] Step S4: Depositing a 3-micron SiO2 hard mask layer on the upper surface of the device, coating, exposing, developing, and removing the glue; depositing a 30-nanometer SiO2 protective layer; forming an N+ heavily doped source ohmic contact region 8 by nitrogen ion implantation on the upper surface of the device, and removing the protective layer;

[0057] Step S5: Depositing a 3-micron SiO2 hard mask layer on the upper surface of the device, coating, exposing, developing, dry etching the hard mask layer, and then etching the SiC, the etching depth of the SiC being 2 microns, to form a trench, and removing the glue; depositing a 100-nanometer SiO2 side wall protective layer, forming an electric field shielding layer 6 below the trench by aluminum ion implantation, and removing the SiO2 side wall protective layer and the hard mask layer;

[0058] Step S6: Carbon film preparation, after activation at 1600°C for 10 min, the carbon film is removed, and a gate dielectric layer 10 with a thickness of 30 nm is formed on the electric field shielding layer 6 by using a thermal oxidation process, the thermal oxidation growth temperature is 1000°C; filling polysilicon, and etching back to the upper surface of the SiC to form a polysilicon gate 11;

[0059] Step S7: A SiO2 hard mask layer with a thickness of 2 μm is deposited on the upper surface of the device, and is coated, exposed, developed, dry etched to expose the P-type electric field shielding region 15 to form a deep trench, and is removed, as shown in Figure 5

[0060] Step S8: The deep trench is filled by using a chemical vapor deposition method to form a heavily doped P-type polysilicon or NiO 12, and is then chemically mechanically polished to the upper surface of the device, as shown in Figure 6

[0061] Step S9: A SiO2 layer with a thickness of 0.5 μm is deposited on the SiC surface to form a dielectric isolation layer 16, is coated, exposed, developed, and etched to the dielectric isolation layer 16, and is removed, and then the ohmic metal is respectively made on both sides of the dielectric isolation layer 16 to form a source ohmic contact metal 13 and a gate ohmic contact metal 14, and the ohmic contact is formed in a nitrogen atmosphere at a temperature of 1000°C;

[0062] Step S10: The metal is evaporated or sputtered, is coated, exposed, developed, and dry or wet etched to form a source electrode (not shown in the figure) on the source ohmic contact metal and a gate electrode (not shown in the figure) on the gate ohmic contact metal; is removed, and a polyimide passivation layer (not shown in the figure) is made, is coated, exposed, developed, and etched to the polyimide passivation layer to expose the source electrode and the gate electrode pad area, and is removed;

[0063] Step S12: The back is thinned, and then the drain metal electrode 4 is made on the back of the N+ heavily doped SiC substrate 3 by using an evaporation or sputtering process, and is laser annealed and alloyed, as shown in Figure 7

[0064] The product structure is prepared according to the preparation method disclosed in Example 1 as follows:

[0065] ​​​The application discloses a SiC trench gate MOSFET integrated with a heterojunction diode, which comprises a SiC substrate 3, a drain metal electrode 4 arranged on a lower surface of the SiC substrate 3, an N-type buffer layer 2, an N-type lightly-doped voltage-resisting layer 1 and a P-type electric field shielding area 15 arranged in sequence on an upper surface of the SiC substrate 3, the P-type electric field shielding area 15 being embedded in the N-type lightly-doped voltage-resisting layer 1, and the P-type electric field shielding area 15 being connected with a heavily-doped P-type polysilicon or NiO 12, an electric field shielding layer 6 and a part of a bottom of an N-type current enhancement layer 5; an N-type current enhancement layer 5 and a trench gate structure are arranged on an upper surface of the P-type electric field shielding area 15, the trench gate structure extends in a one-dimensional direction and is embedded in the N-type current enhancement layer 5 at a lower end, and the trench gate structure is composed of a gate dielectric layer 10 and a polysilicon gate 11 filled in a groove, and an upper end of the polysilicon gate 11 is connected with a gate ohmic contact metal 14.

[0066] An N-type current enhancement layer 5 and a trench gate structure are arranged on an upper surface of the P-type electric field shielding area 15, the trench gate structure extends in a one-dimensional direction and is embedded in the N-type current enhancement layer 5 at a lower end, and the trench gate structure is composed of a gate dielectric layer 10 and a polysilicon gate 11 filled in a groove, and an upper end of the polysilicon gate 11 is connected with a gate ohmic contact metal 14.

[0067] An N-type current enhancement layer 5 and a trench gate structure are arranged on an upper surface of the P-type electric field shielding area 15, the trench gate structure extends in a one-dimensional direction and is embedded in the N-type current enhancement layer 5 at a lower end, and the trench gate structure is composed of a gate dielectric layer 10 and a polysilicon gate 11 filled in a groove, and an upper end of the polysilicon gate 11 is connected with a gate ohmic contact metal 14.

[0068] An N-type current enhancement layer 5 and a trench gate structure are arranged on an upper surface of the P-type electric field shielding area 15, the trench gate structure extends in a one-dimensional direction and is embedded in the N-type current enhancement layer 5 at a lower end, and the trench gate structure is composed of a gate dielectric layer 10 and a polysilicon gate 11 filled in a groove, and an upper end of the polysilicon gate 11 is connected with a gate ohmic contact metal 14.

[0069] Embodiment 2: a preparation method of the SiC trench gate MOSFET integrated with the heterojunction diode, comprising the following steps:

[0070] Step S1: select N+ heavily doped SiC substrate 3; form N type buffer layer 2 on N+ heavily doped SiC substrate 3 by epitaxial growth; form N type lightly doped voltage resistance layer 1 on N type buffer layer 2 by epitaxial growth; deposit 2.5 μm SiO2 hard mask on the upper surface of N type lightly doped voltage resistance layer 1, coat glue, expose and develop, dry etch SiO2 hard mask layer to SiC surface, and remove glue; deposit 50 nm SiO2 protective layer, form P type electric field shielding area 15 by aluminum ion implantation, remove the protective layer, and remove SiO2 layer;

[0071] Step S2: epitaxially grow N type current enhancement layer 5 on P type electric field shielding area 15; at this time, the upper surface of N type current enhancement layer 5 is located on the upper surface of the device; deposit 2.5 μm SiO2 hard mask layer on the upper surface of the device, coat glue, expose and develop, dry etch SiO2 hard mask layer to the upper surface of the device, remove glue; deposit 50 nm SiO2 protective layer, form P type channel body area 7 by aluminum ion implantation, and remove the protective layer;

[0072] Step S3: deposit 2.5 μm SiO2 hard mask layer on the upper surface of the device, coat glue, expose and develop, dry etch SiO2 hard mask layer to SiC surface, remove glue; deposit 50 nm SiO2 protective layer, form P+ heavily doped source ohmic contact area 9 by aluminum ion implantation on the upper surface of the device, remove the protective layer;

[0073] Step S4: deposit 2.5 μm SiO2 hard mask layer on the upper surface of the device, coat glue, expose and develop, and remove glue; deposit 50 nm SiO2 protective layer; form N+ heavily doped source ohmic contact area 8 by nitrogen ion implantation on the upper surface of the device, remove the protective layer;

[0074] Step S5: deposit SiO2 hard mask layer on the upper surface of the device, coat glue, expose and develop, dry etch SiO2 hard mask layer, then etch SiC, etch SiC to a depth of 1.5 μm to form a groove, remove glue; deposit 200 nm SiO2 side wall protective layer, form electric field shielding layer 6 under the groove by aluminum ion implantation, remove SiO2 side wall protective layer and hard mask layer;

[0075] Step S6: carbon film preparation, after activation at 1600 ℃ for 10 min, remove the carbon film, then form 30 nm thick gate dielectric layer 10 on electric field shielding layer 6 by thermal oxidation process, and the thermal oxidation growth temperature is 1100 ℃; fill polycrystalline silicon and etch back to the upper surface of SiC to form polycrystalline silicon gate 11;

[0076] Step S7: deposit 2.5 μm thick SiO2 hard mask layer on the upper surface of the device, coat glue, expose and develop, dry etch to expose P type electric field shielding area 15 to form a deep groove, remove glue, and Figure 12as shown;

[0077] Step S8: filling the deep trench by chemical vapor deposition method to form heavily doped P-type polysilicon or NiO 12, and then chemical mechanical polishing to the device upper surface, as shown in Figure 13

[0078] Step S9: depositing a 0.5 μm thick SiO2 layer on the SiC surface to form a dielectric isolation layer 16, coating, exposing, developing, etching the dielectric isolation layer 16, and then removing the photoresist, and then making an ohmic metal on both sides of the dielectric isolation layer 16 to form a source ohmic contact metal 13 and a gate ohmic contact metal 14, and forming an ohmic contact in a nitrogen atmosphere at a temperature of 1000°C;

[0079] Step S10: coating, exposing, developing, etching the surface of the source ohmic contact metal 13, the P+ heavily doped source ohmic contact region 9, the heavily doped P-type polysilicon or NiO 12, the gate ohmic contact 14, and the current enhancement layer 5 to form a contact region, and then removing the photoresist; making a metal by evaporation or sputtering process, coating, exposing, developing, and etching the metal by dry or wet etching, and then removing the photoresist; alloying at 450°C to form a source electrode 17 and a gate electrode (not shown in the figure), and the current enhancement layer 5 and the source electrode 17 form a Schottky diode; making a polyimide passivation layer (not shown in the figure), coating, exposing, developing, etching the polyimide passivation layer to expose the source electrode and the gate electrode pad area, and then removing the photoresist;

[0080] Step S11: back thinning, making a drain metal electrode 4 on the back of the N+ heavily doped SiC substrate 3 by evaporation or sputtering process, and laser annealing alloying, as shown in Figure 14

[0081] The product structure is as follows according to the preparation method disclosed in Example 2:

[0082] A SiC trench gate MOSFET integrated with a heterojunction diode comprises a SiC substrate 3, a drain metal electrode 4 arranged on the lower surface of the SiC substrate 3, an N-type buffer layer 2, an N-type lightly doped voltage resistance layer 1, and a P-type electric field shielding region 15 arranged in sequence on the upper surface of the SiC substrate 3, the P-type electric field shielding region 15 embedded in the N-type lightly doped voltage resistance layer 1, and the P-type electric field shielding region 15 connected with a heavily doped P-type polysilicon or NiO 12, an electric field shielding layer 6, and a part of the bottom of an N-type current enhancement layer 5; an N-type current enhancement layer 5 and a trench gate structure arranged on the upper surface of the P-type electric field shielding region 15, the trench gate structure extending in one dimension and embedded in the N-type current enhancement layer 5 at the lower end, the trench gate structure composed of a gate dielectric layer 10 and a polysilicon gate 11 filled in the trench, and the upper end of the polysilicon gate 11 connected with a gate ohmic contact metal 14;

[0083] ​​The upper surface of the N-type current enhancement layer 5 is provided with a P-type channel body region 7, which is located on both sides of the trench gate structure and in contact with the gate dielectric layer 10; the upper surface of the P-type channel body region 7 is provided with an adjacent N+ heavily doped source ohmic contact region 8 and a P+ heavily doped source ohmic contact region 9, and the source ohmic contact region 8 is located on both sides of the trench gate structure and in contact with the gate dielectric layer 10;

[0084] The N-type current enhancement layer 5 is provided with a heavily doped P-type polysilicon or NiO 12 on both sides, which is located at the four corners in the cell, the upper end of the heavily doped P-type polysilicon or NiO 12 is covered with a source ohmic contact metal 13, and the lower end extends downward through the P+ heavily doped source ohmic contact region 9, the P-type channel body region 7 and the N-type current enhancement layer 5 in sequence, and the bottom is in contact with the upper surface of the P-type electric field shielding region 15; the N+ heavily doped source ohmic contact region 8 and the P+ heavily doped source ohmic contact region 9 are provided with the source ohmic contact metal 13, the source ohmic contact metal 13 is provided with a source electrode, the gate ohmic contact metal is provided with a gate electrode, and the source ohmic contact metal 13 and the gate ohmic contact metal 14 are isolated by a dielectric isolation layer 16;

[0085] The trench gate structure is provided below with an electric field shielding layer 6 grounded through the electric field shielding region 15, and the electric field shielding layer 6 is connected with the N-type current enhancement layer 5 on both sides;

[0086] The source electrode 17 with a Schottky contact is arranged on the surface of the source ohmic contact metal 13, the P+ heavily doped source ohmic contact region 9, the heavily doped P-type polysilicon or NiO 12 and part of the current enhancement layer 5, and forms a Schottky diode with the current enhancement layer 5.

[0087] It should be noted that, in this document, the terms such as first and second are used only to distinguish one entity or operation from another, and do not necessarily require or imply any actual such relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process method article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process method article or device.

[0088] Finally, it should be noted that: the above only describes the preferred embodiments of the present application, and is not used to limit the present application, although the present application has been described in detail with reference to the foregoing embodiments, and the skilled in the art can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for fabricating a SiC trench-gate MOSFET with integrated heterojunction diode, characterized in that: The method comprises the following steps: Step S1: selecting an N+ heavily doped SiC substrate (3); forming an N-type buffer layer (2) on the N+ heavily doped SiC substrate (3) by epitaxial growth; forming an N-type lightly doped voltage-resisting layer (1) on the N-type buffer layer (2) by epitaxial growth; depositing a SiO2 hard mask layer on the upper surface of the N-type lightly doped voltage-resisting layer (1), coating glue, exposing and developing, dry etching the SiO2 hard mask layer to the SiC surface, and removing the glue; Depositing a SiO2 protective layer on the upper surface of the N-type lightly doped voltage-resisting layer (1), forming a P-type electric field shielding region (15) by aluminum ion implantation, and removing the protective layer; Step S2: epitaxially growing an N-type current enhancement layer (5) on the P-type electric field shielding region (15) and the N-type lightly doped voltage-resisting layer (1); the upper surface of the N-type current enhancement layer (5) is referred to as a device upper surface; depositing a SiO2 hard mask layer on the device upper surface, coating glue, exposing and developing, dry etching the SiO2 hard mask layer to the SiC surface, removing the glue, depositing a SiO2 protective layer, forming a P-type channel body region (7) by aluminum ion implantation, and removing the protective layer; Step S3: depositing a SiO2 hard mask layer on the device upper surface, coating glue, exposing and developing, dry etching the SiO2 hard mask layer to the SiC surface, removing the glue, depositing a SiO2 protective layer, forming a P+ heavily doped source ohmic contact region (9) by aluminum ion implantation on the device upper surface, and removing the protective layer; Step S4: depositing a SiO2 hard mask layer on the device upper surface, coating glue, exposing and developing, and removing the glue; depositing a SiO2 protective layer; forming an N+ heavily doped source ohmic contact region (8) by nitrogen ion implantation on the device upper surface, and removing the protective layer; Step S5: depositing a SiO2 hard mask layer on the device upper surface, coating glue, exposing and developing, dry etching the hard mask layer, and then etching the SiC, with the etching depth of the SiC being 1.5-2.5 μm, to form a groove, removing the glue, depositing a 100-200 nm SiO2 side wall protective layer, forming an electric field shielding layer (6) under the groove by aluminum ion implantation, and removing the SiO2 side wall protective layer and the hard mask layer; Step S6: carbon film preparation, removing the carbon film after activation at 1600-1700 ℃ for 5-10 min, and then forming a gate dielectric layer (10) on the electric field shielding layer (6) by a thermal oxidation or deposition process; filling polycrystalline silicon and etching back to the upper surface of the SiC to form a polycrystalline silicon gate (11); Step S7: depositing a SiO2 hard mask layer on the device upper surface, coating glue, exposing and developing, dry etching the hard mask layer and the SiC to expose the P-type electric field shielding region (15), forming a deep groove, and removing the glue; Step S8: filling the deep groove by a chemical vapor deposition method or a sputtering process to form a heavily doped P-type polycrystalline silicon or NiO (12), and then chemical mechanical polishing to the device upper surface; Step S9: depositing a SiO2 layer on the SiC surface to form a dielectric isolation layer (16), coating, exposing, developing, etching the dielectric isolation layer (16), and removing the photoresist; then forming an ohmic metal on both sides of the dielectric isolation layer (16) to form a source ohmic contact metal (13) and a gate ohmic contact metal (14), and forming an ohmic contact in a nitrogen atmosphere at a temperature of 1000℃; Step S10: evaporating or sputtering a metal, coating, exposing, developing, and etching to form a source electrode on the source ohmic contact metal (13) and a gate electrode on the gate ohmic contact metal (14) by dry or wet etching; removing the photoresist; forming a polyimide passivation layer, coating, exposing, developing, etching the polyimide passivation layer, and removing the photoresist to expose the source electrode and gate electrode pad area; Step S11: thinning the back side, forming a drain metal electrode (4) on the back side of the N+ heavily doped SiC substrate (3) by evaporation or sputtering process, and laser annealing the alloy.

2. The method of claim 1, wherein: After the step S9, a source electrode (17) with Schottky contact is formed on the source ohmic contact metal (13), P+ heavily doped source ohmic contact region (9), heavily doped P-type polysilicon or NiO (12), and current enhancement layer (5), and the specific steps are as follows: coating, exposing, developing, etching the surface of the source ohmic contact metal (13), P+ heavily doped source ohmic contact region (9), heavily doped P-type polysilicon or NiO (12), gate ohmic contact metal (14), and current enhancement layer (5) to form a contact area, and removing the photoresist; then forming a metal by evaporation or sputtering process, coating, exposing, developing, and etching the metal by dry or wet etching, and removing the photoresist; forming the source electrode (17) and the gate electrode at 400-500℃, and the current enhancement layer (5) and the source electrode (17) form a Schottky diode; forming a polyimide passivation layer, coating, exposing, developing, etching the polyimide passivation layer, and removing the photoresist to expose the source electrode and gate electrode pad area; 3. The method of claim 1, wherein: In the step S1, the doping concentration of the N-type lightly doped voltage-resistant layer (1) is 5e15-2e16 cm-3, and the doping concentration of the N-type current enhancement layer (5) is 5e16-5e17 cm-3.

4. The method of claim 1, wherein: In the step S2, the thickness of the SiO2 protective layer is 30-50 nm.

5. The method of claim 1, wherein: The thickness of the SiO2 hard mask layer is 2-5 μm.

6. The method of claim 1, wherein: In the step S6, the thermal oxidation growth temperature is 1000-1100℃, and the thickness of the gate dielectric layer is 30-50 nm.

7. The method of claim 1, wherein: In the step S8, the heavily doped P-type polysilicon or NiO (12) is specifically a heavily doped P-type polysilicon or a heavily doped NiO, wherein the heavily doped P-type polysilicon is a CVD-grown in-situ doped heavily doped P-type polysilicon, and the heavily doped NiO is a sputtered heavily doped P-type NiO, and the doping concentration is 1e18-1e20 cm-3.

8. A SiC trench-gate MOSFET integrated with a heterojunction diode, characterized by: The application relates to a SiC substrate (3) provided with a drain metal electrode (4) on the lower surface, an N-type buffer layer (2), an N-type lightly-doped voltage-resisting layer (1) and a P-type electric field shielding area (15) on the upper surface of the SiC substrate (3) in sequence, wherein the P-type electric field shielding area (15) is embedded on the N-type lightly-doped voltage-resisting layer (1), the P-type electric field shielding area (15) is connected with heavily-doped P-type polysilicon or NiO (12), an electric field shielding layer (6) and a bottom part of an N-type current enhancement layer (5), the upper surface of the P-type electric field shielding area (15) is provided with the N-type current enhancement layer (5) and a trench gate structure, the trench gate structure extends in one-dimensional direction, the lower end is embedded in the N-type current enhancement layer (5), the trench gate structure is composed of a gate dielectric layer (10) and a polysilicon gate (11) filled in the trench, and the upper end of the polysilicon gate (11) is connected with a gate ohmic contact metal (14). The upper surface of the N-type current enhancement layer (5) is provided with a P-type channel body area (7) located on both sides of the trench gate structure and in contact with the gate dielectric layer (10), the upper surface of the P-type channel body area (7) is provided with an adjacent N+ heavily-doped source ohmic contact area (8) and a P+ heavily-doped source ohmic contact area (9), and the source ohmic contact area (8) is located on both sides of the trench gate structure and in contact with the gate dielectric layer (10). Both sides of the N-type current enhancement layer (5) are provided with heavily-doped P-type polysilicon or NiO (12) located at four corners in the cell, the heavily-doped P-type polysilicon or NiO (12) is covered with a source ohmic contact metal (13) on the upper end, extends downwards in sequence through the P+ heavily-doped source ohmic contact area (9), the P-type channel body area (7) and the N-type current enhancement layer (5) and is in contact with the upper surface of the P-type electric field shielding area (15) at the bottom, the N+ heavily-doped source ohmic contact area (8) and the P+ heavily-doped source ohmic contact area (9) are provided with the source ohmic contact metal (13), the source ohmic contact metal (13) is provided with a source electrode, the gate ohmic contact metal (14) is provided with a gate electrode, and the source ohmic contact metal (13) and the gate ohmic contact metal (14) are isolated by a dielectric isolation layer (16).

9. The SiC trench-gate MOSFET integrated with a heterojunction diode according to claim 8, characterized in that: The trench gate structure is provided with a grounded electric field shielding layer (6) below, the electric field shielding layer (6) is connected with the N-type current enhancement layer (5) on both sides and connected with the P-type electric field shielding area (15) at the bottom.

10. The SiC trench-gate MOSFET integrated with a heterojunction diode of claim 8, wherein: The application further comprises a source electrode (17) with a Schottky contact, which is arranged on the surfaces of the source ohmic contact metal (13), the P+ heavily-doped source ohmic contact area (9), the heavily-doped P-type polysilicon or NiO (12) and part of the current enhancement layer (5) and forms a Schottky diode with the current enhancement layer (5).

Images