High-conductivity insulated gate bipolar transistor with multiple deep trench insulating columns and manufacturing process thereof

Abstract

The invention discloses a high-conductivity insulated gate bipolar transistor with multiple deep trench insulating columns and a manufacturing process thereof, and relates to the technical field of power semiconductor manufacturing, the high-conductivity insulated gate bipolar transistor comprises an emitter end and a collector end, the emitter end comprises an emitter region, a base region and an insulating layer, and trench gates are arranged on two sides of the base region; the emitter end further comprises a potential floatable P-type region and a plurality of deep trench insulating columns therein; the P-type region is formed by doping P-ions on the side wall and the bottom of the insulating column groove, and the deep groove insulating column is filled with an insulating material; the emitter region comprises two N + emitter regions and a P + region between the N + emitter regions. The processing difficulty of the potential floatable P-type region is reduced by increasing the number of the insulating columns, performing side wall ion implantation and backfilling an insulating material process, and the process reliability is improved; according to the structure, low saturation voltage between the collector electrode and the emitter electrode is realized by changing the flow direction of holes, excessive carriers at the emitter electrode are reduced, the switching time is shortened, the switching loss is reduced, the electric field intensity at the bottom of the grid electrode can be reduced, and the breakdown voltage is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor manufacturing, in particular to a multi-deep trench insulation column high-conductivity insulated gate bipolar transistor and a process thereof. BACKGROUND

[0002] In recent years, insulated gate bipolar transistors (IGBT) have been widely used, with application ranges extending from industrial motor drives, buses, high-speed rail passenger vehicles to household appliances, and have been mass-produced by many international manufacturers.

[0003] The structure of a conventional trench insulated gate bipolar transistor (Trench IGBT) is shown in Figure 2a , which mainly depends on the competitive relationship between the on-state loss P on and the off-state loss P off of the collector-emitter saturation voltage VCE sat under the rated current. When the transistor is in the on state, more carrier injection can increase the conductivity and thus reduce the on-state loss, but when the transistor is in the off state, it takes energy to empty the injected carriers, so more carrier injection will also produce higher off-state loss P off . Recently, researchers have proposed a structure that can reduce the collector-emitter saturation voltage VCE sat , as shown in Figure 2b . In this structure, isolated P-doped regions are provided on both sides of the main structure region, which are not connected to the electrodes and can freely float. Holes need to bypass these isolated P-doped regions to pass through the P-base region of the main structure region to reach the N+ emitter electrode, so the holes will accumulate in these isolated P-doped regions, thereby increasing the N-drift region conductivity modulation effect and reducing the on-state voltage drop. The P-doped region with floating potential extends the zero-potential region outside the gate region downward, reducing the electric field strength at the edge of the gate, which reduces the probability of tunneling effect at the lower corner of the gate, thereby improving the voltage resistance of the component.

[0004] The current method for making isolated P-type regions is to use high-energy injection and long-time diffusion doping technology, which requires special equipment or processes. Forming a large-volume P-type region takes a long time, and the annealing temperature is not easy to control, which has problems such as high process difficulty, expensive equipment requirements, and difficulty in accurately controlling the doping concentration. SUMMARY

[0005] In view of the above problems existing in actual production, one of the purposes of the present application is to provide a multiple deep trench insulating column high-conductivity insulated gate bipolar transistor, which, while achieving low on-state voltage drop and off-state loss by setting an isolated P-doped region, sets multiple deep trench insulating columns in the isolated P-doped region to optimize the production process to overcome the difficulty of large volume doping. In order to produce the multiple deep trench insulating column high-conductivity insulated gate bipolar transistor, the second purpose of the present application also proposes a multiple deep trench insulating column high-conductivity insulated gate bipolar transistor process, which processes multiple deep trenches in the isolated P-doped region, performs P-type ion implantation through the sidewall of the deep trench, and backfills insulating material to form a P-type region with floating potential, i.e., a P-doped region, containing multiple insulating columns, to replace the traditional high-energy implantation process, thereby reducing the process difficulty and increasing the process feasibility. The specific scheme is as follows: A multiple deep trench insulating column high-conductivity insulated gate bipolar transistor, comprising an emitter end and a collector end, the emitter end comprising a main unit and auxiliary units on both sides of the main unit; wherein, The main unit comprises an emission region, a base region, and an insulating layer, and the base region is flanked by trench gates; The auxiliary unit comprises a P-type region with floating potential and multiple deep trench insulating columns therein; The P-type region with floating potential is formed by doping P-ions on the sidewall and bottom of the insulating column trench, and the deep trench insulating column is filled with insulating material; The emission region comprises N+ emitter regions on both sides of the top of the base region, and a P+ region between the two N+ emitter regions.

[0006] Further, the depth of the P-type region with floating potential is greater than the depth of the gate trench.

[0007] Further, the insulating columns are configured as independent insulating columns formed by mutually separated trenches.

[0008] Further, the number of insulating columns is 1-20; the spacing between two adjacent deep trench insulating columns on the same side can be set to be the same or different according to the specific structure design.

[0009] Further, the insulating material comprises oxides and nitrides.

[0010] Further, the oxides comprise silicon dioxide, aluminum oxide, hafnium oxide, or silicon oxynitride; The nitrides comprise silicon nitride, aluminum nitride, or boron nitride.

[0011] A multiple deep trench insulating column high-conductivity insulated gate bipolar transistor process for producing the multiple deep trench insulating column high-conductivity insulated gate bipolar transistor as described above, comprising the following steps: Grind the substrate to the set thickness according to the required thickness of the rated voltage; Define the trench on the substrate by photolithography and etch it to the required depth; Sequentially generate oxide and deposit N-type doped polysilicon and etch back to form trench gate; Fabricate the base region by photolithography and ion implantation; Form the N+ emitter region of the emitter electrode ohmic contact by photolithography and ion implantation; Use photolithography and etching process to fabricate multiple trenches of specific depth at specific locations of the auxiliary unit; Form the potential floating P-type region by P-type ion implantation through the trench sidewall; Fill the trench with insulating material to form deep trench insulating pillars, and polish the emitter terminal surface to the set smoothness through polishing process; Deposit an insulating layer and define the emitter terminal contact hole by photolithography; Form the P+ region by photolithography and ion implantation; Form the buffer region (N+) by ion implantation at the bottom of the substrate; Form the P+ collector terminal by ion implantation at the bottom of the substrate; Deposit metal as the emitter electrode on the emitter terminal; Deposit metal as the collector electrode on the collector terminal.

[0012] The present application has at least one of the following benefits: (1) The zero potential region outside the gate extends downward, which reduces the power line density of the component at the edge of the gate, reduces the electric field peak at the gate corner, slows down the tunneling effect, and improves the voltage withstand performance of the component. The zero potential region outside the gate extends downward, which reduces the potential line density of the component at the edge of the gate, reduces the electric field peak at the gate corner, slows down the tunneling effect, and improves the voltage withstand performance of the component.

[0013] (2) The on-state voltage drop (VCEsat) is reduced: (3) The design of the potential floating P-type region structure containing multiple deep trench insulating pillars makes the component different from the traditional trench insulated gate bipolar transistor in terms of carrier flow. Holes need to bypass the potential floating P-type region, so that holes accumulate under the trench gate, which can effectively change the conductivity of the region; (4) The multiple deep trench insulating pillars are arranged to form independent insulating pillars by separating the trenches, which can maintain the original high conductivity IGBT advantage of changing the direction of hole flow, while reducing excessive carriers at the emitter terminal, thereby reducing the switching time and greatly reducing the switching loss of the component. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 MFTHC-IGBT structure schematic diagram of the present application; Figure 2a Trench IGBT structure schematic diagram of the traditional; Figure 2b HC-IGBT structure schematic diagram of the high conductivity trench gate bipolar transistor; Figure 2c Advanced Trench HiGT structure schematic diagram of the high conductivity trench gate bipolar transistor; Figure 3 MFTHC-IGBT method steps schematic diagram of the present application; Figure 4 (a), (b), (c), (d) are potential distribution diagram of Trench IGBT, HC-IGBT, Advanced Trench HiGT, and MFTHC-IGBT respectively; Figure 5 (a), (b), (c), (d) are electric field distribution diagram of Trench IGBT, HC-IGBT, Advanced Trench HiGT, and MFTHC-IGBT respectively; Figure 6 (a) HC-IGBT, (b) Advanced Trench HiGT, (c) MFTHC-IGBT gate trench bottom horizontal maximum electric field tangent diagram; Figure 7 (a) Trench IGBT, (b) HC-IGBT, (c) Advanced Trench HiGT, and (d) MFTHC-IGBT saturation current curve diagram; Figure 8 (a) Trench IGBT, (b) HC-IGBT, (c) Advanced Trench HiGT, and (d) MFTHC-IGBT VCE-IC output characteristic diagram; Figure 9 HC-IGBT switch characteristic curve diagram; Figure 10 Advanced Trench HiGT switch characteristic curve diagram; Figure 11 MFTHC-IGBT switch characteristic curve diagram; 101, emitter terminal; 102, N+ emitter region; 103, P+ region; 104, base region; 105, gate trench; 106, floating potential P-type region; 107, deep trench insulation pillar; 108, trench gate; 109, insulation pillar trench; 200, collector terminal; 300, buffer region; 400, drift region; 500, mask. DETAILED DESCRIPTION

[0015] Embodiments of the present application are described in detail below with reference to the attached drawing figures, wherein examples of embodiments are shown in the figures. Figures 1-11

[0016] In the description of the present specification, the description of the terms "certain embodiments", "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the described embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Also, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0017] A multiple deep trench insulation pillar high conductivity insulated gate bipolar transistor, as shown in the figure, includes an emitter terminal 101 and a collector terminal 200, and a buffer region 300 (N+ Buffer) and a drift region 400 (N- Drift Region) are arranged between the emitter terminal 101 and the collector terminal 200. The emitter terminal 101 includes a main unit and auxiliary units on both sides of the main unit. Figure 1

[0018] As shown in the figure, the main unit includes an emitter region, a base region 104, and an insulation layer, and the base region 104 has a trench gate 108 on both sides. The emitter region includes N+ emitter regions 102 on both sides of the top of the base region 104, and a P+ region 103 between the two N+ emitter regions 102. Figure 1

[0019] The auxiliary unit includes a floating potential P-type region 106 and a plurality of deep trench insulation pillars 107 therein. The deep trench insulation pillars 107 are filled with insulation material, and the floating potential P-type region 106 is formed by doping P- ions on the sidewall and bottom of the insulation pillar trench 109. The depth of the floating potential P-type region 106 is greater than the depth of the gate trench 105.

[0020] The deep trench insulation pillars 107 are configured as independent insulation pillars formed by trenches separated from each other. In the embodiments of the present application, the number of deep trench insulation pillars 107 is 1-20 (preferably 2-10). Figure 1 ​​​The interval between the two adjacent deep trench insulation columns 107 on the same side (for example, two on the left and two on the right) can be set to be the same or different according to the specific structural design, and is preferably set to be equal interval.

[0021] The insulation material filling the deep trench insulation column 107 includes oxide and nitride, wherein the oxide includes but is not limited to silicon dioxide, aluminum oxide, hafnium oxide or silicon oxynitride, and the nitride includes silicon nitride, aluminum nitride or boron nitride.

[0022] In order to prepare the multiple deep trench insulation column high-conductivity insulated gate bipolar transistor based on the deep trench insulation column 107 structure as described above, an insulated gate bipolar transistor manufacturing method based on the deep trench insulation column 107 structure is disclosed in the embodiment of the present application, and the specific process can be combined with the manufacturing method shown in the above-mentioned Figure 3

[0023] First, the N-type doped substrate, i.e. wafer, is ground to a set thickness according to the required thickness of the rated withstand voltage. Then, a groove of a specific depth is manufactured through a photoetching and etching process, Figure 3 The top shaded area in the figure is a mask 500, and oxide and N-type doped polysilicon are sequentially deposited to form a trench gate 108. Subsequently, a base region 104 and an N+emitter region 102 for ohmic contact with the emitter electrode are manufactured through photoetching and ion implantation. Then, a multiple groove of a specific depth is manufactured at a specific position of the auxiliary unit through a photoetching and etching process, and a P-type region 106 with a floating potential is formed through P-type ion implantation after etching the groove through a sidewall. Then, the deep trench insulation column 107 is filled with insulation material. The surface of the emitter electrode 101 is polished to a set smoothness through a polishing process, and an insulation layer is deposited. Then, a connection hole is manufactured on the emitter electrode 101 through a photoetching and etching process, and a P+region 103 is formed through photoetching and ion implantation. Finally, the emitter electrode is manufactured by evaporating metal. Then, N-type doped polysilicon is deposited on the back of the substrate to form a buffer region 300, and P-type polysilicon is finally deposited to form a P+collector terminal 200, and metal is deposited on the collector terminal 200 as a collector electrode.

[0024] The above manufacturing method steps are summarized as follows: S1, defining a groove on the substrate through photoetching and etching it to a required depth; S2, sequentially depositing oxide and N-type doped polysilicon and etching back to form a trench gate 108; S3, manufacturing a base region 104 through photoetching and ion implantation; S4, forming an N+emitter region 102 for ohmic contact with the emitter electrode through photoetching and ion implantation; S5, manufacturing a multiple insulation column groove 109 of a specific depth at a specific position of the auxiliary unit through a photoetching and etching process; ​S6, P-type ions are implanted through the trench sidewall to form a potential floatable P-type region 106; S7, the trench is filled with insulating material to form a deep trench insulating column 107, and the surface of the emitter terminal 101 is polished to a set smoothness; S8, an insulating layer is deposited and a contact hole for the emitter terminal 101 is defined by photolithography; S9, a P+ region 103 is formed by photolithography and ion implantation; S10, a buffer region 300 is formed by ion implantation at the bottom of the substrate; S11, a P+ collector terminal 200 is formed by ion implantation at the bottom of the substrate; S13, metal is deposited on the emitter terminal 101 as an emitter electrode; S14, metal is deposited on the collector terminal 200 as a collector electrode.

[0025] It should be noted that the above step sequence is only a preferred implementation sequence, which can be adjusted as needed in actual application.

[0026] In combination Figure 1 and Figure 2a , Figure 2b , Figure 2c as shown in Figure 2a the traditional trench insulated gate bipolar transistor (Trench IGBT), Figure 2b high conductivity insulated gate bipolar transistor (HC-IGBT), Figure 2c advanced trench process high conductivity insulated gate bipolar transistor (Advanced Trench HiGT), Figure 1 the structure diagram of the multiple deep trench insulating column high conductivity insulated gate bipolar transistor (MFTHC-IGBT) proposed in the present application.

[0027] First, the electrical characteristics of the multiple deep trench insulating column high conductivity insulated gate bipolar transistor (MFTHC-IGBT) are compared with those of the high conductivity trench insulated gate bipolar transistor (HC-IGBT) and the advanced trench process high conductivity insulated gate bipolar transistor (Advanced Trench HiGT). The carrier concentration and thickness corresponding to a 650V IGBT are simulated and calculated. In the simulation calculation, the voltage loaded is the breakdown voltage value of the transistor, and the potential distribution in the transistor is calculated, and the results are as follows Figure 4As shown in (a), (b), (c), (d), it can be seen that the use of multiple deep trench insulation pillars 107 can extend the zero potential region outside the gate downward. Correspondingly, the potential distribution of the multiple deep trench insulation pillar high conductivity insulated gate bipolar transistor proposed in the present application extends in a parallel manner. The potential change amount is reflected in the electric field, and the greater the potential line density, the greater the electric field strength. As shown in Figure 5 As shown in (a), (b), (c), (d), the potential floating P-type region structure containing multiple deep trench insulation pillars 107 can reduce the electric field strength at the edge of the gate, reduce the probability of avalanche breakdown, and improve the voltage withstand characteristics of the transistor.

[0028] The maximum lateral and vertical electric field tangents of the high conductivity trench insulated gate bipolar transistor, the advanced trench process high conductivity insulated gate bipolar transistor, and the multiple deep trench insulation pillar high conductivity insulated gate bipolar transistor are shown in Figure 6 .

[0029] The saturation current of the conventional insulated gate bipolar transistor, the high conductivity insulated gate bipolar transistor, the advanced trench process high conductivity insulated gate bipolar transistor, and the multiple deep trench insulation pillar high conductivity insulated gate bipolar transistor as a function of voltage is shown in Figure 7 . It can be seen that the saturation current of the latter three decreases relative to the conventional transistor, indicating a decrease in on-state power consumption. In addition, the introduction of the potential floating P-type region 106 extends the zero potential region outside the trench gate 108 downward, reducing the electric field strength at the edge of the gate and increasing the breakdown voltage to 730V. The breakdown voltages of the Advanced Trench HiGT, HC-IGBT, and Trench IGBT insulated gate bipolar transistors under the same conditions are 700V, 680V, and 670V, respectively. It can be seen that the introduction of the potential floating P-type region 106 improves the anti-breakdown capability of the device.

[0030] The VCE-IC output characteristics of the Trench IGBT, HC-IGBT, Advanced Trench HiGT, and MFTHC-IGBT are shown in Figure 8 . The introduction of the potential floating P-type region 106 changes the direction of the holes, which must bypass this region, so that the holes accumulate under the gate trench, effectively increasing the conductivity of the device and reducing the VCEsat of the component.

[0031] The structure and processing technology of the potential floating P-type region 106 containing multiple deep trench insulation pillars 107 of the present application effectively reduces the processing difficulty and increases the feasibility of the process while retaining this advantage. The turn-off characteristics of the HC-IGBT, Advanced Trench HiGT, and MFTHC-IGBT are shown inFigure 9 and Figure 10 As shown in FIG. 6 and FIG. 7, it can be seen that the design of separating the potential floatable P-type region 106 from the main structure region can keep the high conductivity of the IGBT while changing the flow direction of the holes to reduce the excessive carriers at the emitter end 101, which can make the slope of the current decrease more steeply during the turn-off, thereby reducing the switching time and greatly reducing the switching loss of the component.

[0032] The simulation results above show that adjusting the potential floatable P-type region 106 can improve the turn-off time and the power loss generated during the turn-off. Finally, we compared the time required for the Advanced Trench HiGT and MFTHC-IGBT to turn off, i.e., the time required for the device gate voltage (VG) to decrease from 15V to -15V to make the transistor change from the on state to the off state, and observed the time required for the current of the device to decrease to zero, and the results are shown in FIG. 8 and FIG. 9. Figure 10 and Figure 11 As shown in FIG. 8 and FIG. 9, the multiple deep trench insulation column high conductivity insulated gate bipolar transistor has a lower switching loss.

[0033] The following table is the experimental data of different structure designs:

[0034] Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present application, and those of ordinary skill in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A multiple deep trench insulated pillar high conductivity insulated gate bipolar transistor comprising an emitter terminal (101) and a collector terminal (200), characterized in that, The emitter (101) comprises a main unit and auxiliary units on both sides of the main unit, wherein, The main unit comprises an emitting region, a base region (104), and an insulating layer, and the base region (104) is flanked by a groove gate (108); The auxiliary unit comprises a P-type region (106) with a floating potential and a plurality of deep-groove insulating columns (107) therein; The P-type region (106) with a floating potential is formed by P-ion doping on the sidewalls and bottom of an insulating column groove (109), and the deep-groove insulating columns (107) are filled with insulating material; The emitting region comprises N+ emitter regions (102) on both sides of the top of the base region (104), and a P+ region (103) between the two N+ emitter regions (102).

2. The multiple deep trench isolated pillar high conductivity IGBT of claim 1, wherein, The depth of the P-type region (106) with a floating potential is greater than the depth of the gate groove (105).

3. The multiple deep trench isolated pillar high conductivity IGBT of claim 1, wherein, The plurality of deep-groove insulating columns are configured as independent deep-groove insulating columns (107) separated by grooves.

4. The multiple deep trench isolated pillar high conductivity IGBT of claim 1, wherein, The number of the deep-groove insulating columns (107) is 1-20; The spacing between two adjacent deep-groove insulating columns (107) on the same side is set to be the same or different according to specific structural design.

5. The multiple deep trench isolated pillar high conductivity IGBT of claim 1, wherein, The insulating material comprises an oxide and a nitride.

6. The multiple deep trench isolated pillar high conductivity IGBT of claim 5, wherein, The oxide comprises silicon dioxide, aluminum oxide, hafnium oxide, or silicon oxynitride; The nitride comprises silicon nitride, aluminum nitride, or boron nitride.

7. A multiple deep trench pillar high conductivity IGBT process for manufacturing a multiple deep trench pillar high conductivity IGBT based on a deep trench pillar (107) structure according to any one of claims 1 to 6, characterized in that, The method comprises: Grinding the substrate to a set thickness according to the required thickness of the rated withstand voltage; Defining a groove on the substrate by photolithography and etching it to the required depth; Sequentially forming an oxide and depositing N-type doped polysilicon and etching back to form a groove gate (108); Fabricating a base region (104) by photolithography and ion implantation; Forming an N+ emitter region (102) for an emitter electrode ohmic contact by photolithography and ion implantation; Fabricating a plurality of insulating column grooves (109) of specific depth at specific positions of the auxiliary unit by photolithography and etching processes; Forming a P-type region (106) with a floating potential by P-type ion implantation through the sidewalls of the insulating column grooves (109); Forming deep-groove insulating columns (107) by backfilling insulating material in the grooves, and polishing the surface of the emitter (101) to a set smoothness by a polishing process; Depositing an insulating layer and defining an emitter terminal contact hole by photolithography; Forming a P+ region (103) by photolithography and ion implantation; Ion implantation at the bottom of the substrate to form a buffer region (300); Ion implantation at the bottom of the substrate to form a P+ collector terminal (200); Depositing metal on the emitter terminal (101) as an emitter electrode; Depositing metal on the collector terminal (200) as a collector electrode.

8. The multiple deep trench isolation pillar high conductivity IGBT process of claim 7, wherein, After backfilling insulating material to form deep-groove insulating columns (107), the method further comprises polishing the surface of the emitter terminal (101) to a set smoothness by a polishing process, and then depositing the insulating material.

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