Impedance test file making method

Abstract

The invention provides an impedance test file manufacturing method, and belongs to the technical field of impedance testing, and the method comprises the steps: generating a two-dimensional code coordinate file according to the structure distribution information of a circuit board; combining the two-dimensional code coordinate file, the first impedance test files of the plurality of unit plates and the first impedance test file of the at least one test strip, and outputting a third impedance test file of the splice plate; combining the second impedance test files of the plurality of unit plates and the second impedance test file of the at least one test strip, and outputting a fourth impedance test file of the splice plate; and directly applying the third impedance test file of the splice plate and the fourth impedance test file of the splice plate to an impedance test machine for testing. According to the method, the test strip test file is automatically generated and is combined with the two-dimensional code and the unit board test file to form the complete splice board test file, so that the purpose of performing impedance test on the unit board and the splice board in the same equipment is achieved, the flow breakpoint is eliminated, and the test efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of impedance test, in particular to an impedance test file making method. BACKGROUND

[0002] In the production and manufacturing process of printed circuit boards, impedance test is a link to guarantee circuit signal integrity and product reliability. At present, the impedance test methods in the industry are mainly divided into manual test and automatic test. Among them, manual test needs to rely on manual operation to complete test point positioning, data recording and result judgment, and the test efficiency is extremely low, which has been unable to meet the current production demand of large-scale and high-capacity industry. Automatic impedance test gradually becomes the mainstream choice in the industry due to its high efficiency and strong stability.

[0003] When making an automatic impedance test file, it is necessary to make test files of unit boards and splicing boards at the same time. The test file of the splicing board needs to make test bars for assisting verification of impedance performance and two-dimensional codes for tracing. However, at present, only test points can be selected from the smallest functional unit of the circuit board and output to the test file of the unit board, and the merging output of the test points, test bars and two-dimensional code coordinates in the splicing board cannot be realized. Therefore, a complete test file of the splicing board cannot be made, which leads to that only the unit board can be tested by the automatic impedance test machine, and the splicing board needs to be switched to the manual test machine for separate test of the test bar, finally resulting in poor continuity of the test process and greatly reduced test efficiency. SUMMARY

[0004] In order to overcome the problems in the related art, the purpose of the present application is to provide an impedance test file making method. The method automatically generates a test bar test file, and merges the two-dimensional code, the unit board test file into a complete splicing board test file, realizes the purpose of impedance test of the unit board and the splicing board with the same equipment, eliminates the process breakpoint, and improves the test efficiency.

[0005] An impedance test file making method, comprising the following steps: obtaining impedance information of a circuit board and structure distribution information of the circuit board, wherein the circuit board comprises a plurality of unit boards and a splicing board;

[0006] Outputting a first impedance test file of the unit board, a second impedance test file of the unit board and a test bar point position information file according to the impedance information of the circuit board and the structure distribution information of the circuit board;

[0007] According to the impedance information of the circuit board and the test bar point position information file, screening impedance lines for test, and outputting a first impedance test file of the test bar and a second impedance test file of the test bar;

[0008] Generating a two-dimensional code coordinate file according to the structure distribution information of the circuit board;

[0009] merging the second impedance test file of the plurality of unit boards and the second impedance test file of the at least one test strip to output a fourth impedance test file of the spliced board;

[0010] merging the second impedance test file of the plurality of unit boards and the second impedance test file of the at least one test strip to output a fourth impedance test file of the spliced board;

[0011] directly using the third impedance test file of the spliced board and the fourth impedance test file of the spliced board for impedance testing by the impedance tester;

[0012] The first impedance test file, the second impedance test file, the third impedance test file and the fourth impedance test file are four different formats of files.

[0013] The existing test file making cannot realize the merging and output of the test points, test strips and two-dimensional code coordinates in the spliced board, and thus a complete test file of the spliced board cannot be made. The present application first generates a test strip point information file based on impedance information and structure distribution information of the circuit board, then accurately selects the impedance lines in the test strip according to the impedance information and outputs corresponding first and second impedance test files, realizes the automation of the test strip test file making, and then merges the test strip test file with the two-dimensional code and the test file of the unit board to obtain a complete test file of the spliced board, so that the unit board and the spliced board do not need to switch the equipment during impedance testing, the process breakpoint is eliminated, and the overall testing efficiency is improved.

[0014] In the preferred technical scheme of the present application, the impedance information of the circuit board includes impedance line spacing, and the structure distribution information of the circuit board includes impedance lines, impedance line endpoints and impedance line endpoint coordinates. The impedance lines include single-ended impedance lines and differential impedance lines, and the single-ended impedance lines are provided with grounding points.

[0015] The present application provides data support for subsequent impedance line type identification and point selection by specifying the specific content of the impedance information and the structure distribution information.

[0016] In the preferred technical scheme of the present application, the output of the test strip point information file according to the impedance information of the circuit board and the structure distribution information of the circuit board includes:

[0017] According to the impedance information of the circuit board and the structure distribution information of the circuit board, the impedance line types are distinguished, the impedance line lengths are calculated, the endpoints and grounding points of the impedance lines are identified, and the test strip point information file is output.

[0018] The present application realizes the automatic extraction of the test strip point information by distinguishing the impedance line types, calculating the lengths and selecting the endpoints and grounding points to generate the test strip point file.

[0019] In a preferred embodiment of the present invention, distinguishing impedance line types based on the impedance information and structural distribution information of the circuit board includes:

[0020] Based on the impedance information and structural distribution information of the circuit board, the corresponding impedance line spacing is obtained; if the impedance line spacing is equal to 0, the impedance line type is determined to be a single-ended impedance line; if the impedance line spacing is greater than 0, the impedance line type is determined to be a differential impedance line.

[0021] This invention clarifies the distinction between single-ended and differential impedance lines by defining the impedance line spacing, avoiding misclassification and laying the foundation for subsequent endpoint selection.

[0022] In a preferred embodiment of the present invention, the step of identifying the endpoints and grounding points of the impedance line and filtering and outputting the results as a test strip location information file includes:

[0023] Based on the impedance line type and the calculated impedance line length, when the endpoint of a single-ended impedance line is identified, the grounding point of that endpoint within the first length threshold range is simultaneously obtained.

[0024] When the endpoints of the differential impedance lines are identified, the lengths of all differential impedance lines are compared with the second length threshold, and the two endpoints of all differential impedance lines whose lengths are greater than the second length threshold are output; the lengths of the remaining differential impedance lines are compared with the third length threshold, and the two endpoints of all differential impedance lines whose lengths are greater than the third length threshold are output.

[0025] The selected endpoints and grounding points are output as a test strip point information file.

[0026] This invention establishes differentiated endpoint and grounding point screening rules for different types of impedance lines, ensuring accurate acquisition of grounding points for single-ended impedance lines and reasonable endpoint screening for differential impedance lines, thereby improving the effectiveness of test strip location information.

[0027] In a preferred embodiment of the present invention, the unit board is the smallest unit of a circuit board, containing information about a single circuit board. Several unit boards are combined to form a combined board or a splicing board. The number of unit boards in the combined board is greater than the number of unit boards in the splicing board. The splicing board is the board type used in the largest process of production.

[0028] When the circuit board only includes unit boards and splicing boards, the step of merging the QR code coordinate file, the first impedance test files of several unit boards, and the first impedance test files of at least one test strip to output the third impedance test file of the splicing board includes:

[0029] The QR code coordinate file, the first impedance test files of several unit boards, and the first impedance test files of at least one test strip are merged and output as the third impedance test file of the splicing board.

[0030] The first impedance test file of the unit board is decoded into the third impedance test file of the unit board.

[0031] The application formulates file merging and decoding rules for the scene containing only unit boards and spliced boards, realizes flexible generation of test files of unit boards and spliced boards, and improves the use scene adaptability.

[0032] In the preferred technical solution of the application, when the circuit board contains unit boards, combined boards and spliced boards, the merging of the two-dimensional code coordinate file, the first impedance test files of the unit boards and the first impedance test files of the test strips is output as the third impedance test file of the spliced board, including:

[0033] The two-dimensional code coordinate file, the first impedance test files of the unit boards and the first impedance test files of the test strips are merged and output as the third impedance test file of the spliced board.

[0034] The first impedance test files of the unit boards and the first impedance test files of the test strips are merged and output as the third impedance test file of the combined board.

[0035] The first impedance test file of the unit board is decoded into the third impedance test file of the unit board.

[0036] The application formulates hierarchical file merging rules for the complex scene containing unit boards, combined boards and spliced boards, synchronously generates the third impedance test files of the three types of boards, meets the test requirements of diversified use scenes, and further expands the application range of the scheme.

[0037] In the preferred technical solution of the application, when the circuit board contains unit boards, combined boards and spliced boards, the merging of the two-dimensional code coordinate file, the first impedance test files of the unit boards and the first impedance test files of the test strips is output as the third impedance test file of the spliced board, including:

[0038] The two-dimensional code coordinate file, the first impedance test files of the unit boards and the first impedance test files of the test strips are merged and output as the third impedance test file of the spliced board.

[0039] The first impedance test file of the unit board is decoded into the third impedance test file of the unit board.

[0040] The application formulates file merging and decoding rules for the scene containing only unit boards and spliced boards, realizes flexible generation of test files of unit boards and spliced boards, and improves the use scene adaptability.

[0041] In the preferable technical scheme of the present application, when the circuit board comprises unit boards, combination boards and spliced boards, the step of merging the second impedance test files of the unit boards and the second impedance test files of the test strips and outputting the fourth impedance test files of the spliced boards comprises:

[0042] merging the second impedance test files of the unit boards and the second impedance test files of the test strips and outputting the fourth impedance test files of the spliced boards;

[0043] merging the second impedance test files of the unit boards and the second impedance test files of the test strips and outputting the fourth impedance test files of the combination boards;

[0044] decoding the second impedance test files of the unit boards into the fourth impedance test files of the unit boards.

[0045] The present application formulates hierarchical file merging rules for complex scenarios comprising unit boards, combination boards and spliced boards, synchronously generates the fourth impedance test files of the three types of boards, meets the test requirements of diversified use scenarios and improves the practicability of the scheme.

[0046] In the preferable technical scheme of the present application, the first impedance test files of the unit boards comprise all impedance test information of the unit boards, and the second impedance test files of the unit boards comprise effective impedance test information of the unit boards.

[0047] The first impedance test files of the test strips comprise all impedance test information of the test strips, and the second impedance test files of the test strips comprise effective impedance test information of the test strips.

[0048] The third impedance test files of the spliced boards are format files suitable for reading by impedance testers and comprise all impedance test information of the spliced boards.

[0049] The fourth impedance test files of the spliced boards are format files suitable for reading by impedance testers and comprise effective impedance test information of the spliced boards.

[0050] The third impedance test files of the spliced boards further comprise alignment points for alignment by the impedance testers.

[0051] The present application distinguishes all impedance test information from effective impedance test information by specifying the information content and adaptive attributes of each file, and adds alignment points in the third impedance test files to ensure accurate alignment by the impedance testers and improve the convenience and accuracy of the testers.

[0052] The present application has the following beneficial effects:

[0053] The application first generates a test strip point position information file based on impedance information and structure distribution information of the circuit board, and then accurately screens the impedance lines in the test strip according to the impedance information and outputs corresponding first and second impedance test files, thereby realizing the automation of test strip test file making, and then merging the test strip test file with the test file of the unit board and the two-dimensional code into one, obtaining a complete test file of the spliced board, so that the unit board and the spliced board do not need to switch equipment when performing impedance testing, eliminating process breakpoints and improving overall test efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1 is a schematic diagram of the steps of an impedance test file making method in the embodiment of the application. DETAILED DESCRIPTION

[0055] The preferred embodiments of the application will be described in more detail with reference to the drawings. Although the preferred embodiments of the application are shown in the drawings, it should be understood that the application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to make the application more thorough and complete, and to fully convey the scope of the application to those skilled in the art.

[0056] When making an automatic impedance test file, test files of unit boards and spliced boards need to be made synchronously, and test strips for assisting verification of impedance performance and two-dimensional codes for tracing need to be made in the spliced boards. However, at present, test points can only be selected from the smallest functional units of the circuit board and output to the test file of the unit board, and the combined output of the test points, test strips and two-dimensional code coordinates in the spliced board cannot be realized, so that a complete test file of the spliced board cannot be made, resulting in that only the unit board can be tested by the automatic impedance test machine, while the spliced board needs to be switched to the manual test machine for separate testing of the test strips, finally leading to poor continuity of the test process and a significant reduction in test efficiency.

[0057] Based on this, the application provides an impedance test file making method.

[0058] Embodiment 1

[0059] Referring to Figure 1 The impedance test file making method provided in this embodiment can include the following steps:

[0060] S1: obtaining impedance information of a circuit board and structure distribution information of the circuit board, wherein the circuit board includes a plurality of unit boards, combination boards and spliced boards;

[0061] The impedance information of the circuit board includes impedance line spacing, and the structure distribution information of the circuit board includes impedance lines, impedance line endpoints, impedance line endpoint coordinates, etc. The impedance lines include single-ended impedance lines and differential impedance lines, and the single-ended impedance lines are provided with grounding points.

[0062] The structural distribution information of the circuit board is acquired according to a circuit board design image, and contains overall distribution information such as line distribution and component distribution;

[0063] The unit board is the smallest unit of the circuit board and contains information of a single circuit board, and a plurality of unit boards are combined to form a combination board or a splicing board, wherein the number of unit boards contained in the combination board is greater than the number of unit boards contained in the splicing board, and the splicing board is a board type adopted in the largest process of production; in general, whether the combination board is contained depends on whether the customer sets the combination board, because the unit board is small in size and is not convenient for production process, sometimes the customer sets the combination board which is larger than the unit board in size, and the splicing board is a board type customized by the production manufacturer to adapt to the largest process capacity of itself, and is generally the largest board type among the unit board, the combination board and the splicing board.

[0064] S2: output the first impedance test file of the unit board, the second impedance test file of the unit board and the test strip point information file according to the impedance information of the circuit board and the structural distribution information of the circuit board; wherein the first impedance test file of the unit board contains all impedance test information of the unit board, and the second impedance test file of the unit board contains effective impedance test information of the unit board;

[0065] When the test strip point information file is output, it can include: distinguishing impedance line types and calculating impedance line lengths according to the impedance information of the circuit board and the structural distribution information of the circuit board, and identifying endpoints and grounding points of the impedance lines and filtering and outputting as the test strip point information file;

[0066] When the impedance line types are distinguished, it can include: obtaining corresponding impedance line distances according to the impedance information of the circuit board and the structural distribution information of the circuit board; if the impedance line distance is equal to 0, it is determined that the impedance line type is a single-ended impedance line, and if the impedance line distance is greater than 0, it is determined that the impedance line type is a differential impedance line;

[0067] When the endpoints and grounding points of the impedance lines are identified and filtered and output as the test strip point information file, it can include: according to the impedance line type and the calculated impedance line length, when the endpoint of the single-ended impedance line is identified, the grounding point of the endpoint within the first length threshold range is obtained synchronously; when the endpoint of the differential impedance line is identified, the lengths of all differential impedance lines are compared with the second length threshold, and the two endpoints of the impedance line whose length is greater than the second length threshold are output; the lengths of the remaining differential impedance lines are compared with the third length threshold, and the two endpoints of the impedance line whose length is greater than the third length threshold are output; and the filtered endpoints and grounding points are output as the test strip point information file.

[0068] S3: screening impedance lines for testing according to impedance information of the circuit board and test strip point information file, outputting a first impedance test file of the test strip and a second impedance test file of the test strip, the core purpose of screening the impedance lines is to identify target impedance lines meeting the testing requirements from all the impedance lines, and to eliminate invalid or redundant impedance lines, so as to ensure that the subsequent test focuses on the key objects that can effectively reflect the impedance performance of the circuit board, and avoid invalid test data interference, after identification and screening, the first impedance test file of the test strip contains all the impedance test information of the test strip, and the second impedance test file of the test strip contains valid impedance test information of the test strip.

[0069] S4: generating a two-dimensional code coordinate file according to the structure distribution information of the circuit board.

[0070] S5: merging the two-dimensional code coordinate file, the first impedance test files of the unit boards and the first impedance test file of the at least one test strip, and outputting as a third impedance test file of the spliced board; wherein the third impedance test file of the spliced board is a format file suitable for reading by the impedance tester, and contains all the impedance test information of the spliced board; wherein the third impedance test file of the spliced board further includes a positioning point for positioning by the impedance tester.

[0071] When the circuit board only includes unit boards and a spliced board, merging the two-dimensional code coordinate file, the first impedance test files of the unit boards and the first impedance test file of the at least one test strip, and outputting as a third impedance test file of the spliced board can include: merging the two-dimensional code coordinate file, the first impedance test files of the unit boards and the first impedance test file of the at least one test strip, and outputting as a third impedance test file of the spliced board; and decoding the first impedance test file of the unit board into a third impedance test file of the unit board.

[0072] When the circuit board includes unit boards, a combination board and a spliced board, merging the two-dimensional code coordinate file, the first impedance test files of the unit boards and the first impedance test file of the at least one test strip, and outputting as a third impedance test file of the spliced board can include: merging the two-dimensional code coordinate file, the first impedance test files of the unit boards and the first impedance test file of the at least one test strip, and outputting as a third impedance test file of the spliced board; merging the first impedance test files of the unit boards and the first impedance test file of the at least one test strip, and outputting as a third impedance test file of the combination board; and decoding the first impedance test file of the unit board into a third impedance test file of the unit board.

[0073] S6: merging the second impedance test files of the several unit boards and the second impedance test files of the at least one test strip and outputting as fourth impedance test files of the spliced board; wherein the fourth impedance test files of the spliced board are format files suitable for reading by the impedance tester and contain effective impedance test information of the spliced board.

[0074] When the circuit board only includes the unit board and the spliced board, the step of merging the second impedance test files of the several unit boards and the second impedance test files of the at least one test strip and outputting as fourth impedance test files of the spliced board can include: merging the second impedance test files of the several unit boards and the second impedance test files of the at least one test strip and outputting as fourth impedance test files of the spliced board; and decoding the second impedance test files of the unit boards into fourth impedance test files of the unit boards.

[0075] When the circuit board includes the unit board, the combined board and the spliced board, the step of merging the second impedance test files of the several unit boards and the second impedance test files of the at least one test strip and outputting as fourth impedance test files of the spliced board can include: merging the second impedance test files of the several unit boards and the second impedance test files of the at least one test strip and outputting as fourth impedance test files of the spliced board; merging the second impedance test files of the several unit boards and the second impedance test files of the at least one test strip and outputting as fourth impedance test files of the combined board; and decoding the second impedance test files of the unit boards into fourth impedance test files of the unit boards.

[0076] S7: directly using the third impedance test files of the spliced board and the fourth impedance test files of the spliced board for testing by the impedance tester.

[0077] The first impedance test files, the second impedance test files, the third impedance test files and the fourth impedance test files are respectively four different format files.

[0078] The present application first generates test strip point information files based on impedance information and structure distribution information of the circuit board, then accurately selects impedance lines in the test strip according to the impedance information and outputs corresponding first and second impedance test files, realizes automation of test strip test file production, and combines the test strip test file with the two-dimensional code and the test file of the unit board into one, obtains a complete test file of the spliced board, so that the unit board and the spliced board do not need to switch equipment when performing impedance testing, eliminates process breakpoints, and improves overall test efficiency.

[0079] Embodiment 2

[0080] Referring to Figure 1 The impedance test file production method provided in the embodiment can include the following steps:

[0081] S1: Obtain impedance information of a circuit board and structure distribution information of the circuit board, wherein the circuit board comprises a plurality of unit boards, combination boards and splicing boards;

[0082] In actual production application, impedance information of the circuit board is exported from an ERP (Enterprise Resource Planning) system, and the impedance information of the circuit board comprises impedance line distance, working layer to which the impedance line belongs, test strip design line width, test strip design line distance, reference layer, impedance value, impedance tolerance and the like; the structure distribution information of the circuit board comprises impedance line, impedance line endpoint, impedance line endpoint coordinate and the like, and the impedance line comprises a single-ended impedance line and a differential impedance line, and the single-ended impedance line is provided with a grounding point, wherein the structure distribution information of the circuit board can be a TGZ format file;

[0083] The structure distribution information of the circuit board is obtained according to a circuit board design image, and contains overall distribution information such as line distribution and component distribution;

[0084] The unit board is the smallest unit of the circuit board, and contains information of a single circuit board, and a plurality of unit boards are combined to form a combination board or a splicing board, wherein the number of unit boards contained in the combination board is greater than the number of unit boards contained in the splicing board, and the splicing board is a board type adopted in the largest process of production; generally, whether the combination board is contained depends on whether the customer sets the combination board, because the unit board is small in size and is not convenient for production process, sometimes the customer sets the combination board which is larger than the unit board in size, and the splicing board is a board type customized by the production manufacturer to adapt to the largest process capacity of itself, and is generally the largest board type among the unit board, the combination board and the splicing board, in the industry, the unit board can be recorded as Pcs, the combination board can be recorded as Array, and the splicing board can be recorded as Panel.

[0085] S2: Output a first impedance test file of the unit board, a second impedance test file of the unit board and a test strip point information file according to the impedance information of the circuit board and the structure distribution information of the circuit board; wherein the first impedance test file of the unit board contains all impedance test information of the unit board, and the second impedance test file of the unit board contains effective impedance test information of the unit board; the first impedance test file is generally an EMM format file, and the second impedance test file is generally a CSV format file, and the first impedance test file of the unit board can be recorded as Pcs-EMM, and the second impedance test file of the unit board can be recorded as Pcs-CSV;

[0086] When the test strip point information file is output, the impedance line type can be distinguished and the impedance line length can be calculated according to the impedance information of the circuit board and the structure distribution information of the circuit board, and the endpoints of the impedance line, the grounding points and the like can be recognized and screened and output as the test strip point information file;

[0087] In the step of distinguishing the impedance line type, the following steps can be included: obtaining the corresponding impedance line pitch according to the impedance information of the circuit board and the structure distribution information of the circuit board; if the impedance line pitch is equal to 0, determining that the impedance line type is a single-ended impedance line; if the impedance line pitch is greater than 0, determining that the impedance line type is a differential impedance line, and the impedance line pitch is a non-negative number.

[0088] In the step of identifying the end point and the grounding point of the impedance line and screening and outputting the test strip point position information file, the following steps can be included: according to the impedance line type and the calculated impedance line length, when the end point of the single-ended impedance line is identified, the grounding point of the end point within the first length threshold range is synchronously obtained; when the end point of the differential impedance line is identified, the lengths of all the differential impedance lines are compared with the second length threshold, and the two end points of the impedance line whose length is greater than the second length threshold are outputted; the lengths of the remaining differential impedance lines are compared with the third length threshold, and the two end points of the impedance line whose length is greater than the third length threshold are outputted; the screened end point and the grounding point are outputted as the test strip point position information file; in this embodiment, the first length threshold can be 4mm, the second length threshold can be 6INCH, and the third length threshold can be set as 2INCH; when the number of the two end points of the impedance line greater than the second length threshold is sufficient, the output of the end point of the impedance line greater than the third length threshold can be stopped, and when there is no two end points of the impedance line greater than the second length threshold, the end point of the impedance line greater than the third length threshold is outputted.

[0089] S3: screening the impedance line for testing according to the impedance information of the circuit board and the test strip point position information file, and outputting the first impedance test file of the test strip and the second impedance test file of the test strip; the core purpose of screening the impedance line is to identify the target impedance line meeting the testing requirements from all the impedance lines, and to eliminate invalid or redundant impedance lines, so as to ensure that the subsequent test focuses on the key object that can effectively reflect the impedance performance of the circuit board, and to avoid invalid test data interference; after the identification and screening, the first impedance test file of the test strip contains all the impedance test information of the test strip, and the second impedance test file of the test strip contains the effective impedance test information of the test strip; the first impedance test file of the test strip can be recorded as Coupon-EMM, and the second impedance test file of the test strip can be recorded as Coupon-CSV.

[0090] S4: generating a two-dimensional code coordinate file according to the structure distribution information of the circuit board.

[0091] S5: merging the two-dimensional code coordinate file, the first impedance test file of the plurality of unit boards and the first impedance test file of the at least one test strip to output a third impedance test file of the spliced board; wherein the first impedance test files of multiple test strips are generally used for merging, the third impedance test file of the spliced board is a format file suitable for reading by the impedance tester, the third impedance test file is generally a PCB format file, and the third impedance test file of the spliced board contains all impedance test information of the spliced board and can be recorded as Panel-PCB; wherein the third impedance test file of the spliced board further includes a positioning point for positioning by the impedance tester, and the positioning point can be arranged at the upper right corner and the lower left corner of the top unit board, the upper left corner and the lower right corner of the bottom unit board in the third impedance test file of the spliced board;

[0092] When the circuit board only includes unit boards and a spliced board, merging the two-dimensional code coordinate file, the first impedance test file of the plurality of unit boards and the first impedance test file of the at least one test strip to output a third impedance test file of the spliced board can include: merging the two-dimensional code coordinate file, the first impedance test file of the plurality of unit boards and the first impedance test file of the at least one test strip to output a third impedance test file of the spliced board; and decoding the first impedance test file of the unit board into a third impedance test file of the unit board, which can be recorded as Pcs-PCB.

[0093] When the circuit board includes unit boards, a combined board and a spliced board, merging the two-dimensional code coordinate file, the first impedance test file of the plurality of unit boards and the first impedance test file of the at least one test strip to output a third impedance test file of the spliced board can include: merging the two-dimensional code coordinate file, the first impedance test file of the plurality of unit boards and the first impedance test file of the at least one test strip to output a third impedance test file of the spliced board; merging the first impedance test file of the plurality of unit boards and the first impedance test file of the at least one test strip to output a third impedance test file of the combined board, which can be recorded as Array-PCB; and decoding the first impedance test file of the unit board into a third impedance test file of the unit board.

[0094] S6: merging the second impedance test file of the plurality of unit boards and the second impedance test file of the at least one test strip to output a fourth impedance test file of the spliced board; wherein the second impedance test files of multiple test strips are generally used for merging, the fourth impedance test file of the spliced board is a format file suitable for reading by the impedance tester, the fourth impedance test file is generally a DIF format file, and the fourth impedance test file of the spliced board contains valid impedance test information of the spliced board and can be recorded as Panel-DIF.

[0095] When the circuit board only includes unit boards and splicing boards, the combining of the second impedance test files of the unit boards and the second impedance test files of the at least one test strip into the fourth impedance test files of the splicing boards can include: combining the second impedance test files of the unit boards and the second impedance test files of the at least one test strip into the fourth impedance test files of the splicing boards; and decoding the second impedance test files of the unit boards into the fourth impedance test files of the unit boards, which can be recorded as Pcs-DIF.

[0096] When the circuit board includes unit boards, combination boards and splicing boards, the combining of the second impedance test files of the unit boards and the second impedance test files of the at least one test strip into the fourth impedance test files of the splicing boards can include: combining the second impedance test files of the unit boards and the second impedance test files of the at least one test strip into the fourth impedance test files of the splicing boards; combining the second impedance test files of the unit boards and the second impedance test files of the at least one test strip into the fourth impedance test files of the combination boards, which can be recorded as Array-DIF; and decoding the second impedance test files of the unit boards into the fourth impedance test files of the unit boards.

[0097] S7: directly using the third impedance test files of the splicing boards and the fourth impedance test files of the splicing boards for impedance testing by the impedance tester.

[0098] In actual production applications, the above method steps can be implemented by using the InCamPro software.

[0099] The present application first generates test strip point information files based on impedance information and structure distribution information of the circuit board, then accurately screens the impedance lines in the test strip according to the impedance information and outputs corresponding first and second impedance test files, thereby realizing the automation of test strip test file production, and further combining the test strip test file with the two-dimensional code and the test file of the unit board into one, obtaining a complete test file of the splicing board, so that the unit board and the splicing board do not need to switch equipment when performing impedance testing, eliminating process breakpoints and improving overall testing efficiency.

[0100] For purposes of the description hereinafter, the terms "upper", "lower", "right", "left", "rear", "front", "vertical" and "horizontal" as can be perceived herein relative to the accompanying drawings refer to the orientation of the components being described. However, it is to be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device described herein relative to the other device or structure is inverted, then a spatially relative term such as "above" can be interpreted as meaning "below" or "below" can be interpreted as meaning "above". The device can also be oriented in other ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0101] In addition, it should be pointed out that the use of "first", "second" and the like words to define parts, only for the convenience of the corresponding parts to be distinguished, such as no other declaration, the above words have no special meaning, therefore can not be understood as limiting the scope of the present application.

[0102] The above only the preferred embodiments of the present application, and is not intended to limit the present application, for those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application, should be included in the scope of protection of the present application.

Claims

1. A method for creating an impedance test file, characterized in that: Includes the following steps: Obtain impedance information and structural distribution information of the circuit board, wherein the circuit board includes several unit boards and splicing boards; Based on the impedance information and structural distribution information of the circuit board, the system outputs the first impedance test file, the second impedance test file, and the test strip location information file for the unit board. Based on the impedance information of the circuit board and the test strip location information file, the impedance lines used for testing are selected, and the first impedance test file and the second impedance test file of the test strip are output. Generate a QR code coordinate file based on the structural distribution information of the circuit board; The QR code coordinate file, the first impedance test files of several unit boards, and the first impedance test files of at least one test strip are merged and output as the third impedance test file of the splicing board. The second impedance test files of several unit boards and the second impedance test files of at least one test strip are merged and output as the fourth impedance test file of the splicing board. The third and fourth impedance test files of the splicing board are directly used in the impedance testing machine for testing. Among them, the first impedance test file, the second impedance test file, the third impedance test file, and the fourth impedance test file are four different file formats.

2. The method for preparing an impedance test file according to claim 1, characterized in that: The impedance information of the circuit board includes the impedance line spacing, and the structural distribution information of the circuit board includes the impedance lines, the endpoints of the impedance lines, and the coordinates of the endpoints of the impedance lines. The impedance lines include single-ended impedance lines and differential impedance lines, and the single-ended impedance lines are provided with a grounding point.

3. The method for preparing an impedance test file according to claim 2, characterized in that: The step of outputting a test strip location information file based on the impedance information and structural distribution information of the circuit board includes: Based on the impedance information and structural distribution information of the circuit board, the impedance line type is distinguished and the impedance line length is calculated. The endpoints and grounding points of the impedance lines are identified and the output is filtered as a test strip point information file.

4. The method for preparing an impedance test file according to claim 3, characterized in that: The method of distinguishing impedance line types based on the impedance information and structural distribution information of the circuit board includes: Based on the impedance information and structural distribution information of the circuit board, the corresponding impedance line spacing is obtained. If the impedance line spacing is 0, the impedance line type is determined to be a single-ended impedance line; if the impedance line spacing is greater than 0, the impedance line type is determined to be a differential impedance line.

5. The method for preparing an impedance test file according to claim 3, characterized in that: The process of identifying the endpoints and grounding points of the impedance line and filtering the output as a test strip location information file includes: Based on the impedance line type and the calculated impedance line length, when the endpoint of a single-ended impedance line is identified, the grounding point of that endpoint within the first length threshold range is simultaneously obtained. When the endpoints of the differential impedance lines are identified, the lengths of all differential impedance lines are compared with the second length threshold, and the two endpoints of all differential impedance lines whose lengths are greater than the second length threshold are output; the lengths of the remaining differential impedance lines are compared with the third length threshold, and the two endpoints of all differential impedance lines whose lengths are greater than the third length threshold are output. The selected endpoints and grounding points are output as a test strip point information file.

6. The method for preparing an impedance test file according to claim 1, characterized in that: The unit board is the smallest unit of a circuit board, containing information about a single circuit board. Several unit boards are combined to form a combined board or a splicing board. The number of unit boards in a combined board is greater than the number of unit boards in a splicing board. The splicing board is the board type used in the largest process of production. When the circuit board only includes unit boards and splicing boards, the step of merging the QR code coordinate file, the first impedance test files of several unit boards, and the first impedance test files of at least one test strip to output the third impedance test file of the splicing board includes: The QR code coordinate file, the first impedance test files of several unit boards, and the first impedance test files of at least one test strip are merged and output as the third impedance test file of the splicing board. The first impedance test file of the unit board is decoded into the third impedance test file of the unit board.

7. The method for preparing an impedance test file according to claim 6, characterized in that: When the circuit board includes unit boards, combined boards, and splicing boards, the step of merging the QR code coordinate file, the first impedance test files of several unit boards, and the first impedance test files of at least one test strip to output the third impedance test file of the splicing board includes: The QR code coordinate file, the first impedance test files of several unit boards, and the first impedance test files of at least one test strip are merged and output as the third impedance test file of the splicing board. The first impedance test files of several unit boards and the first impedance test files of at least one test strip are merged and output as the third impedance test file of the combined board. The first impedance test file of the unit board is decoded into the third impedance test file of the unit board.

8. The method for preparing an impedance test file according to claim 6, characterized in that: When the circuit board only includes unit boards and splicing boards, the step of merging the second impedance test files of several unit boards and the second impedance test files of at least one test strip to output the fourth impedance test file of the splicing board includes: The second impedance test files of several unit boards and the second impedance test files of at least one test strip are merged and output as the fourth impedance test file of the splicing board. The second impedance test file of the unit board is decoded into the fourth impedance test file of the unit board.

9. The method for preparing an impedance test file according to claim 8, characterized in that: When the circuit board includes unit boards, combined boards, and splicing boards, the step of merging the second impedance test files of several unit boards and the second impedance test files of at least one test strip to output the fourth impedance test file of the splicing board includes: The second impedance test files of several unit boards and the second impedance test files of at least one test strip are merged and output as the fourth impedance test file of the splicing board. The second impedance test files of several unit boards and the second impedance test files of at least one test strip are merged and output as the fourth impedance test file of the combined board. The second impedance test file of the unit board is decoded into the fourth impedance test file of the unit board.

10. The method for preparing an impedance test file according to claim 1, characterized in that: The first impedance test file of the unit board contains all the impedance test information of the unit board, and the second impedance test file of the unit board contains the effective impedance test information of the unit board. The first impedance test file of the test strip contains all the impedance test information of the test strip, and the second impedance test file of the test strip contains the effective impedance test information of the test strip. The third impedance test file of the splicing board is a format file adapted to be read by an impedance tester, containing all impedance test information of the splicing board; The fourth impedance test file of the splicing board is a format file adapted to be read by an impedance tester, which contains the effective impedance test information of the splicing board. The third impedance test file for the splicing board also includes alignment points for the impedance testing machine.

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