Microwave anechoic chamber antenna plane near-field time schedule controller, system and method

Abstract

The invention discloses a microwave anechoic chamber antenna plane near-field time schedule controller, system and method, and belongs to the field of antenna testing, and the time schedule controller, a wave control circuit board, FPGA control software, a cooling fan, a DC power supply and a plurality of communication connectors are integrated in an integrated cabinet. A scanning frame trigger signal is received through a hardware platform with an FPGA as a core, high-precision signal interaction with an antenna control system and a vector network analyzer is carried out, and automatic time sequence control over the multi-frequency-point and multi-wave-position testing process is achieved. Through configurable delay parameters, sequential logic of key signals such as BMR (beam ready), SOB (beam switching), TTL (trigger acquisition) and the like is accurately managed. And an independent working mode and an AC working mode are supported so as to adapt to different test scenes. According to the invention, high integration and integration of the test system are realized, the test efficiency and synchronization precision of multi-channel antennas such as phased-array antennas and the like are significantly improved, and the system has good expandability and maintainability.

Description

Technical Field

[0001] This invention relates to the field of antenna testing, and more particularly to a planar near-field timing controller, system, and method for microwave anechoic chamber antennas. Background Technology

[0002] A simple antenna test system uses a vector network analyzer as both the transmitter and receiver. A turntable controller manages the turntable's operation, and test software controls the entire system. The timing controller is a key technology for controlling the coordinated operation of various devices during antenna testing. As test systems become more complex, direct computer control of the test software becomes more difficult, necessitating the configuration of separate signal sources for multi-frequency or frequency sweep testing, which increases system complexity. Furthermore, with the increasing prevalence of phased array and array antennas, antenna test systems face the need for multi-channel testing, requiring testing under different beam conditions. This places higher demands on the design of the timing control system.

[0003] With the continuous development and iteration of antennas, the application of phased array antennas is becoming increasingly widespread, and the performance requirements for phased arrays are becoming increasingly stringent. Correspondingly, the testing requirements are also becoming more demanding, especially in terms of testing efficiency. However, testing efficiency in phased array antenna testing is constrained by various factors, including receiver measurement speed, frequency switching speed, beam switching speed, channel switching speed, and synchronization methods of various components. Reasonable control of the timing of these components is necessary to maximize testing efficiency. Existing testing systems often primarily use microwave anechoic chambers, combined with various equipment such as scanning racks, turntables, and instruments. During testing, the data and signal interactions between different parts of the system are frequent and complex. Some equipment is also geographically dispersed and cannot be moved, making timing control of the entire system difficult. Therefore, an efficient and accurate timing control scheme is urgently needed. Summary of the Invention

[0004] The purpose of this invention is to overcome the problems existing in the prior art and provide a planar near-field timing controller, system and method for microwave anechoic chamber antennas. It can meet the timing control requirements of each part during antenna testing. The devices in the system are convenient and portable, and the delay of each part in the system can be configured by the host computer test software. It also reserves multiple interfaces for external communication such as network port and serial port, which can adapt to timing logic control under various conditions and improve the efficiency of antenna testing to a certain extent.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] In a first aspect, a planar near-field timing controller for a microwave anechoic chamber antenna is provided, including a chassis and components disposed within the chassis:

[0007] The wave control circuit board is used to interact with the antenna control system, vector network analyzer, host computer and scanning frame respectively;

[0008] The FPGA control software, integrated in the wave controller circuit board, is used for timing logic control.

[0009] Cooling fan, used to control the internal temperature of the controller;

[0010] DC power supply, used to convert 220V AC power to 12V DC power to power the wave control circuit board and cooling fan;

[0011] Multiple communication connectors are used to connect to the antenna control system, vector network analyzer, host computer and scanning rack, including at least two network port connectors, multiple BNC connectors and at least two DB25 connectors.

[0012] In some embodiments, the FPGA control software includes:

[0013] Clock / reset module, used to provide global clock and reset signal;

[0014] The network port transceiver module is used to send and receive data via the network port.

[0015] The network port data analysis module is used to analyze the received network port data;

[0016] The command parsing module is used to parse the network interface data after it has been analyzed by the network interface data analysis module. After parsing, it outputs the corresponding control signals based on the results.

[0017] The data return module is used to return network port data.

[0018] The beam control module is used to control the data acquisition of the vector network analyzer based on external signals and to control the antenna control system to perform beam switching.

[0019] In some embodiments, the sending and receiving of network interface data includes:

[0020] While receiving data, it checks whether the frame header, checksum, and frame trailer are correct. If correct, the data is sent to the command parsing module for command parsing. When sending data, the frame header, frame trailer, and checksum data are automatically added.

[0021] The command parsing module is also used to envelop the PULSE_OUT signal sent by the vector network analyzer into an EXT signal, and send the EXT signal to the antenna control system.

[0022] In some embodiments, the wave control circuit board integrates a DC-DC power supply circuit, an FPGA configuration circuit, a FLASH storage circuit, a 422 communication interface, a buffer circuit, a gigabit network communication interface, and a 100 Mbps network communication interface.

[0023] In some embodiments, one of the two DB25 connectors is an AC communication interface, and the other is a TTL connector.

[0024] Secondly, a planar near-field timing control system for a microwave anechoic chamber antenna is provided, comprising:

[0025] Such as any of the timing controllers in the first aspect, used for sequential logic control;

[0026] Vector network analyzer, used to control data acquisition;

[0027] The scanning frame is used to move the probe or antenna.

[0028] Antenna control system, used to control the antenna beam state;

[0029] The host computer is used to send test commands and receive test data.

[0030] In some embodiments, the timing controller communicates with the antenna control system via three pairs of differential signals, each pair of signals having a backup channel; the timing controller interacts with the vector network analyzer via three 5V signals.

[0031] Thirdly, a planar near-field timing control method for a microwave anechoic chamber antenna is provided, used in the timing controller of the first aspect, comprising the following steps:

[0032] Receives trigger pulse signals from the scanning frame;

[0033] Determine whether the vector network analyzer and antenna control system are idle;

[0034] If both the vector network analyzer and the antenna control system are idle, an SOB signal is sent to the antenna control system to trigger beam switching.

[0035] After beam switching is completed, a TTL signal is sent to the vector network analyzer to trigger data acquisition;

[0036] After the vector calculus data collection is completed, proceed to the next cycle until all frequency points and waveforms are tested.

[0037] Fourthly, a planar near-field timing control method for a microwave anechoic chamber antenna is provided, used in the timing controller of the first aspect, comprising the following steps:

[0038] Receives trigger pulse signals from the scanning frame;

[0039] Determine if the antenna control system is idle;

[0040] If the line control system is idle, it sends an SOB signal to the antenna control system to trigger beam switching.

[0041] After beam switching is completed, a TTL signal is sent to the vector network analyzer to trigger data acquisition;

[0042] After the vector calculus data collection is completed, proceed to the next cycle until all frequency points and waveforms are tested.

[0043] In some embodiments, a pulse envelope processing step is also included:

[0044] Receive the PULSE_OUT pulse signal from the vector network analyzer;

[0045] The pulse's leading and trailing edges are delayed and extended to generate an ETX signal;

[0046] The ETX signal is sent to the antenna control system for pulse antenna testing.

[0047] It should be further noted that the technical features corresponding to the above embodiments can be combined or substituted with each other to form new technical solutions without conflict.

[0048] Compared with existing technologies, this invention utilizes an FPGA-based hardware platform to receive scanning rack trigger signals and engages in high-precision signal interaction with the antenna control system and vector network analyzer, achieving automated timing control of multi-frequency, multi-wavelength testing processes. It precisely manages the timing logic of key signals such as BMR (Beam Ready), SOB (Beam Switching), and TTL (Trigger Acquisition) through configurable delay parameters. It supports both standalone and AC operating modes to adapt to different testing scenarios. This achieves a high degree of integration and unification of the testing system, significantly improving the efficiency and synchronization accuracy of multi-channel antenna testing, such as phased array antennas, and possesses good scalability and maintainability. Specific beneficial effects are as follows:

[0049] 1. The highly integrated, one-piece design of the complete set of equipment eliminates the need for additional external functional modules. Upon power-up, it can perform timing logic control based on the various signals involved in the antenna testing system, thereby completing wave control and data acquisition.

[0050] 2. An FPGA is used as the data processing center for the entire timing control system. One backup of each of the three signal sets (BMR±, SOB±, and ETX±) is provided in the system, along with two BNC ports and two network ports, facilitating future maintenance and significantly improving system fault tolerance.

[0051] 3. The operation is simple and easy to use. Users only need to know the test interface of each signal, which can greatly improve the efficiency of system antenna testing.

[0052] 4. The FPGA control software can be further developed according to user needs.

[0053] 5. The structure is designed as a chassis and can be installed in a standard server rack. Attached Figure Description

[0054] Figure 1 This is a chassis structure diagram of a planar near-field timing controller for a microwave anechoic chamber antenna according to the present invention;

[0055] Figure 2 This is a schematic diagram of the FPGA control software of the present invention;

[0056] Figure 3 This is a circuit diagram of the wave-controlled circuit board of the present invention;

[0057] Figure 4 This is a schematic diagram of the planar near-field timing control system for a microwave anechoic chamber antenna according to the present invention;

[0058] Figure 5 This is a flowchart of the antenna testing process for the timing control system of the present invention;

[0059] Figure 6 The flowcharts are for different operating modes of the timing controller of the present invention;

[0060] Figure 7 This is a timing logic diagram of each signal in the timing controller of the present invention;

[0061] Figure 8 This is a schematic diagram of the envelope processing performed by the timing controller of the present invention. Detailed Implementation

[0062] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0063] It should be noted that the defects in the solutions in the prior art are all the results of the inventors' practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the embodiments of this application in the following text should be the inventors' contributions to this application in the process of invention and creation, and should not be understood as technical content known to those skilled in the art.

[0064] In one exemplary embodiment, such as Figure 1 As shown, a planar near-field timing controller for a microwave anechoic chamber antenna includes a chassis and components disposed within the chassis:

[0065] The wave control circuit board 1 is the core platform of the entire timing control system. It is used to interact with the antenna control system (AC system), vector network analyzer (vector network analyzer), host computer and scanning frame, and to perform data processing.

[0066] The FPGA control software is integrated into the wave control circuit board 1 and is used for timing logic control.

[0067] Cooling fan 5 is used to control the internal temperature of the controller, providing heat dissipation for the entire timing control system and ensuring that the internal operating temperature does not become too high.

[0068] DC power supply 2 is used to convert 220V AC power to 12V DC power to power the wave control circuit board 1, cooling fan 5, etc.

[0069] Multiple communication connectors are used to connect to the antenna control system, vector network analyzer, host computer, and scanning frame, including at least two Ethernet connectors 6, multiple BNC connectors 3, and at least two DB25 connectors 4. Specifically, the signals in the BNC connector 3 are PULSE_OUT (pulse output), TRIG_RDY (trigger ready), TRIG_IN (trigger input), and RX_BNC3 (BNC connector signal if it is a scanning frame pulse), which are used for interaction with the vector network analyzer and the scanning frame. The remaining two are spares. One of the two DB25 connectors 4 is an AC communication interface with three pairs of differential signals, two channels per pair, and the other is a TTL connector, which is a spare. The two Ethernet connectors 6 are responsible for Ethernet communication, with one as a spare.

[0070] For example, according to the size requirements, construct the timing controller chassis structure and rationally plan the location of each functional module area. Use screws to assemble the timing controller chassis, reserving threaded positions for fixing the wave controller circuit board, DC power supply, and heat dissipation devices, and pre-drilling holes for each connector. Based on the functional module area design of the timing controller chassis, connect each functional area with cables, distinguishing between power cables, communication cables, and data control cables.

[0071] For example, the structure of FPGA control software is as follows: Figure 2 As shown, it is divided into 6 modules, and the functions of the modules are as follows.

[0072] Clock / Reset Module: This module is mainly responsible for providing the global clock and global reset for the FPGA.

[0073] Network port transceiver module: This module is mainly responsible for sending and receiving data through the host's network port. When receiving data, it checks whether the frame header, checksum, and trailer are correct. If correct, it sends the data to the command parsing module for command parsing. When sending data, it automatically adds frame header, trailer, and checksum data.

[0074] Network interface data analysis module: This module is mainly responsible for analyzing the received network interface data. After receiving the frame header 0xAAAA, it indicates that the subsequent received data is valid data. After receiving the checksum rxsumcheck, it indicates that a frame of data has been received.

[0075] Command Parsing Module: This module primarily performs command parsing on the network interface data analyzed by the network interface data analysis module. After parsing, it outputs corresponding control signals based on the results, such as data backhaul and beam control. Additionally, it performs envelope processing on the PULSE_OUT signal sent by the vector network analyzer to convert it into an EXT signal, which is then sent to the antenna control system.

[0076] Data backhaul module: This module mainly completes the network port data backhaul function, including version information, beam scan cycle end information, SOB signal period information, etc.

[0077] Beam control module: This module controls the vector network analyzer to acquire data based on the BMR signal (beam ready) sent by the AC system, the TRIG_RDY signal sent by the vector network analyzer, and the RX_BNC_3 signal sent by the scanning frame. It also outputs an SOB trigger signal (beam switching) to the AC system according to the timing logic of the control, informing the AC system that beam switching operation can be performed.

[0078] For example, the circuit principle of the wave control circuit board 1 is as follows: Figure 3 As shown, the wave control circuit board 1 receives power from the power module. The +12V power supply is converted into six power channels by DC-DC power chips (LTM4644IY) and (LTM4622IY#PBF) to power the devices on the wave control assembly. The wave control board circuit includes DC-DC power supply circuitry, FPGA configuration circuitry, FLASH memory circuitry, 422 communication interface, buffer circuitry, gigabit network communication interface, and 100Mbps network communication interface.

[0079] In another exemplary embodiment, a planar near-field timing control system for a microwave anechoic chamber antenna is provided, comprising:

[0080] A timing controller is used for sequential logic control.

[0081] Vector network analyzer, used to control data acquisition;

[0082] The scanning frame is used to move the probe or antenna.

[0083] Antenna control system, used to control the antenna beam state;

[0084] The host computer is used to send test commands and receive test data.

[0085] like Figure 4 As shown, communication between the FPGA and the PC (host computer) of the timing controller is achieved through the PHY chip RTL8211. Communication between the FPGA and the AC system is accomplished through three 422 differential signals, with the differential signals at 5V level. The level conversion chip is AM26C31 / 32. Data interaction between the FPGA and the network analyzer and scanning rack is accomplished through BNC connectors, with the 5V level conversion chip being SN74LVC8T245.

[0086] For example, the testing process of this system is as follows: Figure 5 As shown, it specifically includes:

[0087] The system first calculates the scanning frequency and wave position information and initializes the instrument (such as a vector network analyzer);

[0088] The system then calculates information such as the scanning range and sampling step, and sends all frequency points and waveform information to the timing controller; then it controls the test turntable (scanning frame) to move to the test starting point and controls the test turntable to start moving according to the scanning range;

[0089] The timing controller waits for the scanning frame trigger signal and cyclically sends frequency and waveform information to the antenna control system. The antenna control system switches the test frequency and waveform to perform pulse testing; the generated pulse test signal is sent to the vector network analyzer.

[0090] The timing controller generates a TTL trigger signal to trigger the vector network analyzer to start a data acquisition cycle; after switching through all frequency points and waveforms, the data acquisition is completed.

[0091] In the multi-frequency point and multi-wavelength mode, the timing control system and the AC system interact with each other to complete the wave control and data acquisition. The host computer and the AC system exchange the wave control protocol in advance and send multi-frequency point and multi-wavelength information to the AC system. The AC system then starts the process of cycling through the frequency points and then cycling through the waveforms to perform the corresponding state control.

[0092] In another exemplary embodiment, a planar near-field timing control method for a microwave anechoic chamber antenna is provided to complete the control acquisition in AC mode, such as... Figure 6 As shown, it includes the following steps:

[0093] Receives trigger pulse signals from the scanning frame;

[0094] Determine whether the vector network analyzer and antenna control system are idle;

[0095] If both the vector network analyzer and the antenna control system are idle, an SOB signal is sent to the antenna control system to trigger beam switching.

[0096] After beam switching is completed, a TTL signal is sent to the vector network analyzer to trigger data acquisition;

[0097] After the vector calculus data collection is completed, proceed to the next cycle until all frequency points and waveforms are tested.

[0098] Specifically, first, check if the scanning frame pulse signal arrives. Then, determine if the AC's BMR signal and the vector network's TRIG_RDY signal are both in an idle state. If they are idle, immediately pull the SOB signal high to inform the AC system to perform a waveform switching. After the waveform switching is completed, the timing controller triggers a TTL signal to the vector network, which then performs data acquisition. This process continues until all frequency points and all waveforms are tested.

[0099] In another exemplary embodiment, a planar near-field timing control method for a microwave anechoic chamber antenna is provided to complete the control acquisition of independent modes, such as... Figure 6 As shown, it includes the following steps:

[0100] Receives trigger pulse signals from the scanning frame;

[0101] Determine if the antenna control system is idle;

[0102] If the line control system is idle, it sends an SOB signal to the antenna control system to trigger beam switching.

[0103] After beam switching is completed, a TTL signal is sent to the vector network analyzer to trigger data acquisition;

[0104] After the vector calculus data collection is completed, proceed to the next cycle until all frequency points and waveforms are tested.

[0105] In this mode, it is first determined whether the scanning carriage has moved to the data acquisition position. The timing control system determines whether the scanning carriage pulse has arrived. When the scanning carriage pulse arrives, the data acquisition cycle begins. Then, it checks whether the vector network acquisition signal is in an idle state. If it is idle, the SOB signal is immediately pulled high to inform the AC system to perform a waveform switching. After the waveform switching is completed, the timing controller triggers a TTL signal to the vector network, and the vector network performs data acquisition. The above process continues until all frequency points and all waveforms are tested.

[0106] During testing, the timing control system and the AC system primarily interact via three sets of 5V differential signals: BMR±, SOB±, and ETX± at RS422 level. If the antenna under test is a pulse antenna, the timing control system or the AC system provides the pulse signal. The pulse frequency and duty cycle are configurable, and the generated pulse signal is mainly used for inputting the antenna pulse state and for synchronizing the network distribution pulse.

[0107] Furthermore, the working principle of the timing controller is described. The timing controller receives instructions from the host computer and trigger pulse signals from the scanning frame. Then, it performs timing logic control on the control signals interacting with the AC system and the vector network analyzer, ultimately completing beam control and data acquisition. The timing control system and the antenna control system mainly interact through three sets of 5V differential signals: BMR±, SOB±, and ETX±. The timing controller and the vector network analyzer mainly interact through three 5V signals: TRIG_RDY, TTL, and PULSE_OUT. The timing logic diagram of each signal in the timing controller is shown below. Figure 7 As shown. Figure 7 The delay annotations for each segment are as follows:

[0108] Delay "1": Delay for the second confirmation of TRIG_RDY;

[0109] Delay "2": SOB reduces latency;

[0110] Delay "3": TTL delay;

[0111] Delay "4": TTL pulse width;

[0112] Delay "5": Loop delay;

[0113] Delay "6": Vector scattering time;

[0114] T SOB SOB signal period.

[0115] The logic changes of each signal in the entire beam control and data acquisition cycle are as follows:

[0116] After the timing controller receives the scan rack trigger pulse, the BMR signal will be pulled low for a period of time, and then pulled high again. It then waits for the vector network analyzer (VNA) trigger signal TRIG_RDY. When the TRIG_RDY signal is detected as high, it undergoes a second confirmation with a delay of "1". After the second confirmation, the SOB signal is pulled high, then pulled low after a delay of "2", and then pulled high after a delay of "3". The TTL signal remains high for a delay of "4" before being pulled low. The TTL signal going low indicates the end of one cycle. After a delay of "5", the VNA begins data acquisition with a delay of "6". After data acquisition, the VNA enters the next cycle, continuing until all frequency points and waveforms are scanned.

[0117] The timing logic diagrams of each signal of the timing controller in the receiving and transmitting states are as follows: Figure 7 As shown, the difference between the two states is that in the transmit state, the timing controller receives a pulse signal PULSE_OUT sent by the vector network analyzer. The timing controller performs envelope processing on this signal and sends the enveloped signal ETX to the AC system (see details of the envelope). This operation is not performed in the receive state. The timing diagram of the PULSE_OUT and ETX signals is shown below. Figure 8 As shown.

[0118] The following are the annotations for each delay segment:

[0119] Delay "7": Pulse envelope delay;

[0120] Delay "8": PULSE_OUT pulse width.

[0121] After receiving the pulse signal PULSE_OUT from the vector network analyzer, the timing controller performs an envelope operation: extending the pulse width of PULSE_OUT by a delay of "7" before and after, thus obtaining the enveloped signal ETX, which is then sent to the AC system. The pulse width of ETX is a delay of "2*7+8".

[0122] The above detailed embodiments are a description of the present invention. It should not be considered that the specific embodiments of the present invention are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the protection scope of the present invention.

Claims

1. A planar near-field timing controller for a microwave anechoic chamber antenna, characterized in that, Including the chassis and the components inside the chassis: The wave control circuit board is used to interact with the antenna control system, vector network analyzer, host computer and scanning frame respectively; The FPGA control software, integrated in the wave controller circuit board, is used for timing logic control. Cooling fan, used to control the internal temperature of the controller; DC power supply, used to convert 220V AC power to 12V DC power to power the wave control circuit board and cooling fan; Multiple communication connectors are used to connect to the antenna control system, vector network analyzer, host computer and scanning rack, including at least two network port connectors, multiple BNC connectors and at least two DB25 connectors.

2. The planar near-field timing controller for a microwave anechoic chamber antenna according to claim 1, characterized in that, The FPGA control software includes: Clock / reset module, used to provide global clock and reset signal; The network port transceiver module is used to send and receive data via the network port. The network port data analysis module is used to analyze the received network port data; The command parsing module is used to parse the network interface data after it has been analyzed by the network interface data analysis module. After parsing, it outputs the corresponding control signals based on the results. The data return module is used to return network port data. The beam control module is used to control the data acquisition of the vector network analyzer based on external signals and to control the antenna control system to perform beam switching.

3. A planar near-field timing controller for a microwave anechoic chamber antenna according to claim 2, characterized in that, The sending and receiving of network port data includes: While receiving data, it checks whether the frame header, checksum, and frame trailer are correct. If correct, the data is sent to the command parsing module for command parsing. When sending data, the frame header, frame trailer, and checksum data are automatically added. The command parsing module is also used to envelop the PULSE_OUT signal sent by the vector network analyzer into an EXT signal, and send the EXT signal to the antenna control system.

4. A planar near-field timing controller for a microwave anechoic chamber antenna according to claim 1, characterized in that, The wave control circuit board integrates a DC-DC power supply circuit, an FPGA configuration circuit, a FLASH storage circuit, a 422 communication interface, a buffer circuit, a gigabit network communication interface, and a 100 Mbps network communication interface.

5. A planar near-field timing controller for a microwave anechoic chamber antenna according to claim 1, characterized in that, One of the two DB25 connectors is an AC communication interface, and the other is a TTL connector.

6. A planar near-field timing control system for a microwave anechoic chamber antenna, characterized in that, include: The timing controller as described in any one of claims 1 to 5 is used for performing sequential logic control; Vector network analyzer, used to control data acquisition; The scanning frame is used to move the probe or antenna. Antenna control system, used to control the antenna beam state; The host computer is used to send test commands and receive test data.

7. A planar near-field timing control system for a microwave anechoic chamber antenna according to claim 6, characterized in that, The timing controller communicates with the antenna control system via three pairs of differential signals, each pair of signals having a backup channel; the timing controller interacts with the vector network analyzer via three 5V signals.

8. A planar near-field timing control method for a microwave anechoic chamber antenna, used in any of the timing controllers in claims 1 to 5, characterized in that, Includes the following steps: Receives trigger pulse signals from the scanning frame; Determine whether the vector network analyzer and antenna control system are idle; If both the vector network analyzer and the antenna control system are idle, an SOB signal is sent to the antenna control system to trigger beam switching. After beam switching is completed, a TTL signal is sent to the vector network analyzer to trigger data acquisition; After the vector calculus data collection is completed, proceed to the next cycle until all frequency points and waveforms are tested.

9. A planar near-field timing control method for a microwave anechoic chamber antenna, used in any of the timing controllers in claims 1 to 5, characterized in that, Includes the following steps: Receives trigger pulse signals from the scanning frame; Determine if the antenna control system is idle; If the line control system is idle, it sends an SOB signal to the antenna control system to trigger beam switching. After beam switching is completed, a TTL signal is sent to the vector network analyzer to trigger data acquisition; After the vector calculus data collection is completed, proceed to the next cycle until all frequency points and waveforms are tested.

10. A planar near-field timing control method for a microwave anechoic chamber antenna according to claim 8 or 9, characterized in that, It also includes a pulse envelope processing step: Receive the PULSE_OUT pulse signal from the vector network analyzer; The pulse's leading and trailing edges are delayed and extended to generate an ETX signal; The ETX signal is sent to the antenna control system for pulse antenna testing.

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