Reading circuit of memory and operation method

Abstract

The present disclosure provides a readout circuit of a memory and an operating method thereof, the readout circuit of the memory comprising: a memory array comprising a plurality of memory cells; the control module is connected with the storage array, and the control module is used for respectively applying a first voltage and a second voltage to a selected storage unit so as to obtain a first read current and a second read current; and the read-out module is connected with the storage array and is used for determining a read-out result of the selected storage unit according to a comparison result of an absolute value of a difference value between the first read-out current and the second read-out current and a preset reference current difference value.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and in particular to a memory readout circuit and operating method. Background Technology

[0002] Existing RRAM (Resistive Random Access Memory) arrays rely on judging the current value of the device to read stored information. When data is written to the device (set to a high resistance state HR or a low resistance state LR), the fluctuation of its own resistance will directly cause changes or deviations in the read current value, thereby causing the risk of data errors.

[0003] In existing technologies, by using already written data (I write A voltage (V) is applied to the memory cell. read ) Measure its current (I) read ) and the reference value (I ref The comparison is used to determine the stored information. If the RRAM device is working normally, the current I is in the high-resistance state of the memory cell. read Less than reference value I ref When the memory cell is in a low-resistance state, the current I read Greater than reference value I ref However, as Figure 1 As shown, RRAM devices experience resistance fluctuations after writing, such as noise, relaxation, and degradation, leading to some memory cells experiencing resistance issues. read Deviating from the original I write Even exceeding I ref Errors can occur due to limitations in the judgment threshold. For example, the read current I of a certain memory cell. read It should be greater than I ref The stored information is "1", but due to resistance fluctuations, I... read Less than I ref The actual information read is "0", which leads to a bit error. Summary of the Invention

[0004] This disclosure provides a memory readout circuit and operation method to at least solve the above-mentioned technical problems existing in the prior art.

[0005] According to a first aspect of this disclosure, a readout circuit for a memory is provided, wherein the readout circuit for the memory includes:

[0006] A storage array, the storage array comprising multiple storage units;

[0007] a control module connected to the memory array, the control module configured to apply a first voltage and a second voltage to the selected memory cell respectively to obtain a first read current and a second read current;

[0008] a read module connected to the memory array, the read module configured to determine a read result of the selected memory cell according to a comparison result of an absolute value of a difference between the first read current and the second read current and a preset reference current difference.

[0009] In an implementation, the control module is specifically configured to apply the first voltage and the second voltage to a word line connected to the selected memory cell respectively, or the control module is specifically configured to apply the first voltage and the second voltage to a bit line connected to the selected memory cell respectively.

[0010] In an implementation, the control module is further configured to apply a third voltage to a bit line connected to the selected memory cell when applying the first voltage and the second voltage to a word line connected to the selected memory cell respectively; or,

[0011] apply a fourth voltage to a word line connected to the selected memory cell when applying the first voltage and the second voltage to a bit line connected to the selected memory cell respectively.

[0012] In an implementation, the read module is specifically configured to determine the read result of the selected memory cell as "1" if it is judged that the absolute value of the difference between the first read current and the second read current is greater than the preset reference current difference.

[0013] In an implementation, the read module is specifically configured to determine the read result of the selected memory cell as "0" if it is judged that the absolute value of the difference between the first read current and the second read current is less than the preset reference current difference.

[0014] In an implementation, the memory array further comprises:

[0015] a reference current determination module connected to the memory array;

[0016] The reference current determination module comprises:

[0017] a first sub-read module configured to, if the memory cell is in a high resistance state, read a read current corresponding to each memory cell at the first voltage to determine as a first current, and read a read current corresponding to each memory cell at the second voltage to determine as a second current;

[0018] a first sub-determination module configured to determine an absolute value of a difference between the first current and the second current corresponding to each memory cell;

[0019] a second sub-determining module configured to determine a maximum value of all absolute values of the differences as a first difference value according to absolute values of the differences between the first current and the second current;

[0020] a second sub-reading module configured to read out a reading current corresponding to each of the memory cells at a first voltage to determine a third current and at a second voltage to determine a fourth current if the memory cells are in a low resistance state;

[0021] a third sub-determining module configured to determine absolute values of the differences between the third current and the fourth current corresponding to each of the memory cells;

[0022] a fourth sub-determining module configured to determine a minimum value of all absolute values of the differences as a second difference value according to absolute values of the differences between the third current and the fourth current;

[0023] a fifth sub-determining module configured to determine that the preset reference current difference value is greater than the first difference value and smaller than the second difference value.

[0024] According to a first aspect of the present disclosure, an operating method of a reading circuit of a memory is provided, wherein the method comprises:

[0025] providing a memory array comprising a plurality of memory cells;

[0026] applying a first voltage and a second voltage to selected memory cells respectively to obtain a first reading current and a second reading current;

[0027] determining a reading result of the selected memory cells according to a comparison result of absolute values of the differences between the first reading current and the second reading current and a preset reference current difference value.

[0028] In an implementation manner, the applying the first voltage and the second voltage to the selected memory cells respectively comprises:

[0029] applying the first voltage and the second voltage to word lines connected with the selected memory cells respectively, or applying the first voltage and the second voltage to bit lines connected with the selected memory cells respectively.

[0030] In an implementation manner, the method further comprises:

[0031] applying a third voltage to bit lines connected with the selected memory cells when the first voltage and the second voltage are applied to word lines connected with the selected memory cells respectively; or

[0032] applying a fourth voltage to word lines connected with the selected memory cells when the first voltage and the second voltage are applied to bit lines connected with the selected memory cells respectively.

[0033] In an embodiment, the comparison result of the absolute value of the difference between the first readout current and the second readout current and the preset reference current difference is used to determine the readout result of the selected memory cell, including:

[0034] If the absolute value of the difference between the first readout current and the second readout current is greater than the preset reference current difference, the readout result of the selected memory cell is “1”;

[0035] If the absolute value of the difference between the first readout current and the second readout current is less than the preset reference current difference, the readout result of the selected memory cell is “0”.

[0036] In an embodiment, the method further includes:

[0037] Before the first voltage and the second voltage are respectively applied to the selected memory cell, a preset reference current difference is determined;

[0038] The determination of the preset reference current difference includes:

[0039] If the memory cell is in a high resistance state, the readout current corresponding to each memory cell is read out under the first voltage and determined as a first current, and the readout current corresponding to each memory cell is read out under the second voltage and determined as a second current;

[0040] The absolute value of the difference between the first current and the second current corresponding to each memory cell is determined;

[0041] The maximum value among all the absolute values of the differences is determined as a first difference according to the absolute value of the difference between the first current and the second current;

[0042] If the memory cell is in a low resistance state, the readout current corresponding to each memory cell is read out under the first voltage and determined as a third current, and the readout current corresponding to each memory cell is read out under the second voltage and determined as a fourth current;

[0043] The absolute value of the difference between the third current and the fourth current corresponding to each memory cell is determined;

[0044] The minimum value among all the absolute values of the differences is determined as a second difference according to the absolute value of the difference between the third current and the fourth current;

[0045] The preset reference current difference is determined to be greater than the first difference and less than the second difference.

[0046] The readout circuit and operation method of the memory of the present disclosure obtain a first readout current and a second readout current by respectively applying a first voltage and a second voltage to a selected memory cell, compare the absolute value of the difference between the first readout current and the second readout current with a preset reference current difference, and then determine the readout result. In the present disclosure, the characteristic that the memory cell can maintain the original resistance state conduction mechanism even if resistance fluctuation occurs is utilized, that is, when different memory cells are in the same resistance state, the change rate of the readout current approaches as the applied voltage increases, for example, although different memory cells in the same resistance state have different currents as the applied voltage increases, the current changes slowly in the high resistance state and the current changes rapidly in the low resistance state, so the change amount of the readout current under different voltages can be used as the basis for determining the readout result of the device, and the comparison between a single current value and a reference current is avoided, thereby avoiding the direct influence of resistance fluctuation, improving the accuracy of data reading, and expanding the judgment interval.

[0047] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0048] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will be more apparent from the following detailed description read in conjunction with the accompanying drawings, in which:

[0049] In the drawings, identical or corresponding reference numerals indicate identical or corresponding parts.

[0050] Figure 1 Cumulative distribution graph of readout current of memory cell in prior art;

[0051] Figure 2 Structure schematic diagram of readout circuit of memory provided by embodiments of the present disclosure;

[0052] Figure 3a Working schematic diagram of memory cell in low resistance state when working normally;

[0053] Figure 3b Working schematic diagram of memory cell in high resistance state when working normally;

[0054] Figure 4a Working schematic diagram of memory cell in low resistance state after degradation;

[0055] Figure 4b Working schematic diagram of memory cell in high resistance state after degradation;

[0056] Figure 5a graph of read current of different storage units versus voltage change;

[0057] Figure 6 a cumulative distribution graph of read current of different storage units versus voltage change;

[0058] Figure 7 a test result graph of a readout circuit of a memory provided by an embodiment of the present disclosure;

[0059] Figure 8 a flowchart of an operating method of a readout circuit of a memory provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] In order to make the objectives, characteristics and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0061] An embodiment of the present disclosure provides a readout circuit of a memory, Figure 2 a structural schematic diagram of a readout circuit of a memory provided by an embodiment of the present disclosure, as Figure 2 shown, the readout circuit of the memory comprises:

[0062] a storage array 10, the storage array comprising a plurality of storage units 101;

[0063] a control module 20 connected with the storage array 10, the control module 20 being configured to apply a first voltage and a second voltage to a selected storage unit 101 respectively to obtain a first readout current and a second readout current;

[0064] a readout module 30 connected with the storage array 10, the readout module 30 being configured to determine a readout result of the selected storage unit 101 according to a comparison result of an absolute value of a difference between the first readout current and the second readout current and a preset reference current difference.

[0065] In an embodiment, the storage array 10 comprises a plurality of storage units 101, and each storage unit 101 comprises a memristor and a transistor.

[0066] Figure 3a a working schematic diagram of a storage unit in a low resistance state when the storage unit is normally working, Figure 3b a working schematic diagram of a storage unit in a high resistance state when the storage unit is normally working.

[0067] If a storage unit is normally working, then as Figure 3aAs shown, the storage unit is in a low resistance state because the conductive filament connects the upper and lower electrodes, i.e. Figure 3a The resistance change layer in the resistance change layer is in communication with the upper and lower electrodes, the electric field and the current density are linearly related, forming a typical ohmic conductance, and the storage unit is in a conductive state. As shown in Figure 3b As shown, the storage unit is in a high resistance state because the interface oxygen vacancy and oxygen ion complex form a non-conductive dielectric region, and the conductive filament is broken, so the conductive mechanism is close to Schottky emission or trap-assisted tunneling, and the storage unit is in a disconnected state between the upper and lower electrodes.

[0068] Figure 4a The working schematic diagram of the storage unit in a low resistance state after degradation is shown in Figure 4b The working schematic diagram of the storage unit in a high resistance state after degradation is shown in

[0069] As shown in Figure 4a and Figure 4b A storage unit degrades and causes resistance fluctuations, but the large-scale conductive filament still maintains the original form (i.e. the storage unit is in a low resistance state and the storage unit is not in a high resistance state), and the conductive mechanism does not change.

[0070] The storage unit in the storage array is written with data and placed for a period of time (usually high temperature acceleration), and the resistance state fluctuates due to the redistribution (diffusion / complexation mechanism) of a small amount of oxygen vacancies, and the current value originally used to represent the data is offset and even exceeds the reference current distinguishable range, causing errors.

[0071] However, since the conductive filament is constructed by a large number of oxygen vacancies, the low resistance state connecting the upper and lower electrodes and the high resistance state disconnecting the interface have strong robustness, and a small amount of oxygen vacancy redistribution will not change the on-off form of the conductive filament, so the conductive mechanism does not change. The present disclosure is to distinguish between high and low resistance states by identifying the conductive mechanism, and to resist resistance fluctuations by using its robustness.

[0072] Figure 5 The read current of different storage units as a function of voltage is shown in

[0073] Figure 5In the figure, the upper two curves correspond to the storage units in low resistance state, and the lower two curves correspond to the storage units in high resistance state. The current of the storage units at Vread1 is the same, and when Vread1 gradually increases to Vread6, it can be seen from the figure that the read current of different storage units in the same resistance state has a difference, but the change rate of the current is not much different. The current changes slowly in high resistance state, and the current changes quickly in low resistance state. Therefore, the storage units with the same current value at Vread1 will produce current separation phenomenon divided into groups by high and low resistance states at higher read voltage, which also shows that there are different conduction mechanisms between the high and low resistance states of the storage units, and the high and low resistance states can be distinguished according to the conduction mechanisms.

[0074] Figure 6 Cumulative distribution of the read current of different storage units with respect to the change of voltage.

[0075] Figure 6 In the figure, the blue curve corresponds to the storage unit in low resistance state, and the red curve corresponds to the storage unit in high resistance state. Figure 6 In the figure, 0.1% to 100% refers to the proportion of the storage units. For example, among the storage units in high resistance state, when the applied voltage is 0.667 (it needs to be explained that the coordinates in the figure are normalized and have no actual unit), 100% of the storage units have read current greater than 0, 25% of the storage units have read current greater than 0.1, and only 0.1% of the storage units have read current greater than 0.3.

[0076] And in each resistance state, from 100% to 0.1%, it indicates that the degradation of the storage units is more and more serious. For example, the storage units corresponding to the 100% curve are normal storage units, the storage units corresponding to the 50% curve are storage units with degradation but not serious, and the storage units corresponding to the 0.1% curve are storage units with serious degradation. However, the read current of the storage units in low resistance state changes quickly with the increase of read voltage, regardless of degradation or not, and the read current of the storage units in high resistance state changes slowly with the increase of read voltage, regardless of degradation or not. Therefore, by identifying the change of the read current, the conduction mechanism of the storage unit can be directly distinguished, and the conduction mechanism represented by the conduction filament morphology has stronger robustness and significant anti-fluctuation ability than the resistance itself.

[0077] Therefore, the storage unit in the present disclosure can maintain the original resistance state conduction mechanism even if the resistance fluctuates, that is, when different storage units are in the same resistance state, the change rate of the read current is almost the same as the applied voltage increases. For example, although the current of different storage units in the same resistance state will be different as the applied voltage increases, the current changes slowly in the high resistance state and changes quickly in the low resistance state. Therefore, the change amount of the read current under different voltages can be used as the basis for judging the read result of the device. Instead of only comparing the size of a single current value with the reference current, the direct impact of resistance fluctuation is avoided, the accuracy of data reading is improved, and the judgment window is also expanded.

[0078] In an embodiment, the control module 20 is specifically configured to apply the first voltage and the second voltage to the word line WL connected with the selected storage unit 101 respectively, or the control module 20 is specifically configured to apply the first voltage and the second voltage to the bit line BL connected with the selected storage unit 101 respectively.

[0079] The control module 20 is also configured to apply the third voltage to the bit line BL connected with the selected storage unit 101 when the first voltage and the second voltage are applied to the word line WL connected with the selected storage unit 101 respectively; or,

[0080] The control module 20 is also configured to apply the fourth voltage to the word line WL connected with the selected storage unit 101 when the first voltage and the second voltage are applied to the bit line BL connected with the selected storage unit 101 respectively.

[0081] Specifically, for example, the first voltage is applied to the word line WL connected with the selected storage unit first, at this time, the voltage applied to the bit line BL connected with the selected storage unit is the third voltage, and a first read current Iread1 is obtained. Then, the voltage applied to the word line WL connected with the selected storage unit is changed to the second voltage, and the voltage applied to the bit line BL remains unchanged, and a second read current Iread2 is obtained.

[0082] If the first voltage is applied to the bit line BL connected with the selected storage unit first, the voltage applied to the word line WL connected with the selected storage unit is the fourth voltage, and a first read current Iread1 is obtained. Then, the voltage applied to the bit line BL connected with the selected storage unit is changed to the second voltage, and the voltage applied to the word line WL remains unchanged, and a second read current Iread2 is obtained.

[0083] After obtaining the first read current Iread1 and the second read current Iread2, it is necessary to determine the read result of the selected memory cell 101 according to the comparison result of the absolute value of the difference between the first read current Iread1 and the second read current Iread2 and the preset reference current difference ΔIref.

[0084] In an embodiment, the read circuit of the memory further comprises: a reference current determination module 40 connected with the memory array 10.

[0085] The reference current determination module 40 comprises:

[0086] The first sub read module is configured to, if the memory cell is in a high resistance state, read the read current corresponding to each memory cell at the first voltage to determine as the first current, and read the read current corresponding to each memory cell at the second voltage to determine as the second current.

[0087] The first sub determination module is configured to determine the absolute value of the difference between the first current and the second current corresponding to each memory cell.

[0088] The second sub determination module is configured to determine the maximum value among all the absolute values of the differences as the first difference according to the absolute values of the differences between the first current and the second current.

[0089] The second sub read module is configured to, if the memory cell is in a low resistance state, read the read current corresponding to each memory cell at the first voltage to determine as the third current, and read the read current corresponding to each memory cell at the second voltage to determine as the fourth current.

[0090] The third sub determination module is configured to determine the absolute value of the difference between the third current and the fourth current corresponding to each memory cell.

[0091] The fourth sub determination module is configured to determine the minimum value among all the absolute values of the differences as the second difference according to the absolute values of the differences between the third current and the fourth current.

[0092] The fifth sub determination module is configured to determine that the preset reference current difference ΔIref is greater than the first difference and less than the second difference.

[0093] Specifically, before comparing the absolute value of the difference between the first read current Iread1 and the second read current Iread2 with the preset reference current difference ΔIref, it is necessary to determine the value of the preset reference current difference ΔIref.

[0094] When determining the preset reference current difference ΔIref, all memory cells are pre-read. A first voltage is applied to the memory cell to obtain a read current, and a second voltage is applied to obtain another read current. If the memory cell corresponds to a high-resistance state, the read current corresponding to the first voltage is the first current, and the read current corresponding to the second voltage is the second current. If the memory cell corresponds to a low-resistance state, the read current corresponding to the first voltage is the third current, and the read current corresponding to the second voltage is the fourth current. Then, the maximum absolute value of the difference between the first and second currents is determined as the first difference, and the minimum absolute value of the difference between the third and fourth currents is determined as the second difference. The preset reference current difference is greater than the first difference and less than the second difference.

[0095] Because the read current corresponding to the high-resistance state is less than the read current corresponding to the low-resistance state, and as... Figure 5 As shown, the current change in the high-resistivity state is relatively gradual; as the voltage increases, the current increase is not significant. Conversely, the current change in the low-resistivity state is faster; as the voltage increases, the current increase is more substantial. Therefore, for example... Figure 5 As shown, if the first voltage is Vread1 and the second voltage is Vread6, then when the storage cell corresponds to the high-resistance state, the first current of one storage cell is 0.25 and the second current is 0.35, and the first current of the other storage cell is 0.25 and the second current is 0.45, with a maximum difference of 0.2. When the storage cell corresponds to the low-resistance state, the third current of one storage cell is 0.25 and the fourth current is 0.9, and the third current of the other storage cell is 0.25 and the fourth current is 0.95, with a minimum difference of 0.65. Therefore, a value between 0.2 and 0.65 can be selected as the preset reference current difference. This ensures that when the absolute value of the difference between the first read current and the second read current is greater than the preset reference current difference, the storage cell is confirmed to be in a low-resistance state; when the absolute value of the difference between the first read current and the second read current is less than the preset reference current difference, the storage cell is confirmed to be in a high-resistance state, thereby improving the accuracy of data reading.

[0096] In one embodiment, the readout module 30 is specifically used to determine that the readout result of the selected storage cell 101 is "1" if it is determined that the absolute value of the difference between the first readout current and the second readout current is greater than the preset reference current difference.

[0097] If it is determined that the absolute value of the difference between the first read current and the second read current is less than the preset reference current difference, then the read result of the selected memory cell 101 is determined to be "0".

[0098] The readout result is "1", corresponding to the storage unit in a low resistance state, and the readout result is "0", corresponding to the storage unit in a high resistance state.

[0099] Figure 7 A test result diagram of the readout circuit of the memory provided by the embodiment of the present disclosure is shown. Figure 7 In the diagram, the curve on the left of the preset reference current difference ΔIref corresponds to the test result of the high resistance state, and the curve on the right of the preset reference current difference ΔIref corresponds to the test result of the low resistance state. It can be seen that when the storage unit is in the high resistance state, the absolute value of the difference between the two readout currents obtained after applying two different voltages is less than the preset reference current difference ΔIref, and when the storage unit is in the low resistance state, the absolute value of the difference between the two readout currents obtained after applying two different voltages is greater than the preset reference current difference ΔIref. Figure 7 It can be seen that when the storage unit is in the high resistance state, the absolute value of the difference between the two readout currents obtained after applying two different voltages is less than the preset reference current difference ΔIref, and when the storage unit is in the low resistance state, the absolute value of the difference between the two readout currents obtained after applying two different voltages is greater than the preset reference current difference ΔIref. Therefore, in the present disclosure, the change amount of the readout current under different voltages is used as the basis for judging the readout result of the device, which can avoid the direct influence of resistance fluctuation and improve the accuracy of data reading.

[0100] In addition, in the present disclosure, the change amount of the readout current under two voltages can be used for judgment, so two low voltages can be selected for current reading when selecting the voltage, which can reduce the read power consumption compared with the prior art in which a high voltage must be applied sometimes to distinguish the readout current from the reference current.

[0101] The embodiment of the present disclosure also provides an operation method of a readout circuit of a memory, Figure 8 The flowchart of the operation method of the readout circuit of the memory provided by the embodiment of the present disclosure is shown. Figure 8 As shown in the figure, the method comprises:

[0102] Step 801, providing a storage array, the storage array comprising a plurality of storage units;

[0103] Step 802, respectively applying a first voltage and a second voltage to the selected storage unit to obtain a first readout current and a second readout current;

[0104] Step 803, determining the readout result of the selected storage unit according to the comparison result of the absolute value of the difference between the first readout current and the second readout current and the preset reference current difference.

[0105] In an embodiment, respectively applying the first voltage and the second voltage to the selected storage unit comprises:

[0106] Respectively applying the first voltage and the second voltage to the word line connected with the selected storage unit, or respectively applying the first voltage and the second voltage to the bit line connected with the selected storage unit.

[0107] In an embodiment, the method further comprises:

[0108] applying a third voltage to the bit line connected to the selected memory cell when the first voltage and the second voltage are applied to the word line connected to the selected memory cell, respectively; or

[0109] applying a fourth voltage to the word line connected to the selected memory cell when the first voltage and the second voltage are applied to the bit line connected to the selected memory cell, respectively.

[0110] In an embodiment, determining the read result of the selected memory cell according to the comparison result of the absolute value of the difference between the first read current and the second read current and the preset reference current difference comprises:

[0111] if the absolute value of the difference between the first read current and the second read current is greater than the preset reference current difference, the read result of the selected memory cell is "1";

[0112] if the absolute value of the difference between the first read current and the second read current is less than the preset reference current difference, the read result of the selected memory cell is "0".

[0113] In an embodiment, the method further comprises:

[0114] determining the preset reference current difference before the first voltage and the second voltage are applied to the selected memory cell, respectively;

[0115] determining the preset reference current difference comprises:

[0116] if the memory cell is in a high resistance state, reading the read current corresponding to each memory cell at the first voltage to determine as the first current, and reading the read current corresponding to each memory cell at the second voltage to determine as the second current;

[0117] determining the absolute value of the difference between the first current and the second current corresponding to each memory cell;

[0118] determining the maximum value of all the absolute values of the differences as the first difference according to the absolute value of the difference between the first current and the second current;

[0119] if the memory cell is in a low resistance state, reading the read current corresponding to each memory cell at the first voltage to determine as the third current, and reading the read current corresponding to each memory cell at the second voltage to determine as the fourth current;

[0120] determining the absolute value of the difference between the third current and the fourth current corresponding to each memory cell;

[0121] According to the absolute values of the differences between the third current and the fourth current, a minimum value of all the absolute values of the differences is determined as a second difference value;

[0122] It is determined that the preset reference current difference value is greater than the first difference value and less than the second difference value.

[0123] It should be noted that the above description of the operation method embodiments of the readout circuit for the memory is similar to the description of the product embodiments shown in the foregoing Figures 1 to 7 , has similar beneficial effects as the product embodiments shown in the foregoing Figures 1 to 7 , and thus will not be described again. For technical details not disclosed in the operation method embodiments of the readout circuit for the memory of the present disclosure, please refer to the description of the product embodiments shown in the foregoing Figures 1 to 7 , and thus will not be described again.

[0124] It should be understood that the steps can be reordered, added or deleted using the various forms of flowcharts shown above. For example, each step described in the present disclosure can be executed in parallel, sequentially or in a different order, as long as the desired results of the technical solutions of the present disclosure can be achieved, which is not limited herein.

[0125] In addition, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0126] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A readout circuit for a memory, characterized in that, The readout circuit of the memory includes: A storage array, the storage array comprising multiple storage units; A control module, connected to the storage array, is used to apply a first voltage and a second voltage to the selected storage cell to obtain a first read current and a second read current. A readout module, connected to the storage array, is used to determine the readout result of the selected storage cell based on a comparison between the absolute value of the difference between the first readout current and the second readout current and a preset reference current difference.

2. The readout circuit of the memory according to claim 1, characterized in that, The control module is specifically used to apply a first voltage and a second voltage to the word line connected to the selected memory cell, or the control module is specifically used to apply a first voltage and a second voltage to the bit line connected to the selected memory cell.

3. The readout circuit of the memory according to claim 2, characterized in that, The control module is further configured to apply a third voltage to the bit line connected to the selected memory cell when a first voltage and a second voltage are respectively applied to the word line connected to the selected memory cell. or, When a first voltage and a second voltage are applied to the bit line connected to the selected memory cell, a fourth voltage is applied to the word line connected to the selected memory cell.

4. The readout circuit of the memory according to claim 1, characterized in that, The readout module is specifically used to determine that the readout result of the selected memory cell is "1" if the absolute value of the difference between the first readout current and the second readout current is greater than the preset reference current difference. If the absolute value of the difference between the first read current and the second read current is determined to be less than the preset reference current difference, then the read result of the selected memory cell is determined to be "0".

5. The readout circuit of the memory according to claim 1, characterized in that, Also includes: A reference current determination module is connected to the storage array; The reference current determination module includes: The first sub-read module is used to read the read current corresponding to each memory cell under a first voltage and determine it as the first current if the memory cell is in a high-impedance state; and to read the read current corresponding to each memory cell under a second voltage and determine it as the second current. The first sub-determination module is used to determine the absolute value of the difference between the first current and the second current corresponding to each storage cell; The second sub-determination module is used to determine the maximum value among all absolute values ​​of differences as the first difference based on the absolute value of the difference between the first current and the second current; The second sub-read module is used to read the read current corresponding to each memory cell under the first voltage and determine it as the third current if the memory cell is in a low-resistance state; and to read the read current corresponding to each memory cell under the second voltage and determine it as the fourth current. The third sub-determination module is used to determine the absolute value of the difference between the third current and the fourth current corresponding to each storage cell; The fourth sub-determination module is used to determine the minimum value among all the absolute values ​​of the differences between the third current and the fourth current as the second difference; The fifth sub-determination module is used to determine that the preset reference current difference is greater than the first difference and less than the second difference.

6. A method for operating a readout circuit of a memory, characterized in that, The method includes: A storage array is provided, the storage array comprising a plurality of storage cells; A first voltage and a second voltage are applied to the selected memory cell respectively to obtain a first read current and a second read current; The readout result of the selected memory cell is determined by comparing the absolute value of the difference between the first readout current and the second readout current with the difference of the preset reference current.

7. The method according to claim 6, characterized in that, Applying the first voltage and the second voltage to the selected memory cell respectively includes: A first voltage and a second voltage are applied to the word line connected to the selected memory cell, or the first voltage and the second voltage are applied to the bit line connected to the selected memory cell.

8. The method according to claim 7, characterized in that, The method further includes: When a first voltage and a second voltage are applied to the word line connected to the selected memory cell, a third voltage is applied to the bit line connected to the selected memory cell; or, When a first voltage and a second voltage are applied to the bit line connected to the selected memory cell, a fourth voltage is applied to the word line connected to the selected memory cell.

9. The method according to claim 6, characterized in that, The step of determining the read result of the selected memory cell based on a comparison between the absolute value of the difference between the first read current and the second read current and a preset reference current difference includes: If the absolute value of the difference between the first read current and the second read current is greater than the preset reference current difference, then the read result of the selected memory cell is "1". If the absolute value of the difference between the first read current and the second read current is less than the preset reference current difference, then the read result of the selected memory cell is "0".

10. The method according to claim 6, characterized in that, The method also includes: Before applying the first voltage and the second voltage to the selected memory cell, a preset reference current difference is determined; The determination of the preset reference current difference includes: If the memory cell is in a high-impedance state, then under the first voltage, the read current corresponding to each memory cell is read out and determined as the first current; under the second voltage, the read current corresponding to each memory cell is read out and determined as the second current. Determine the absolute value of the difference between the first current and the second current corresponding to each memory cell; Based on the absolute value of the difference between the first current and the second current, the maximum value among all the absolute values ​​of the differences is determined as the first difference; If the memory cell is in a low-resistance state, then under the first voltage, the read current corresponding to each memory cell is read out and determined as the third current; under the second voltage, the read current corresponding to each memory cell is read out and determined as the fourth current. Determine the absolute value of the difference between the third current and the fourth current corresponding to each memory cell; Based on the absolute value of the difference between the third current and the fourth current, the minimum value among all the absolute values ​​of the differences is determined as the second difference. The preset reference current difference is determined to be greater than the first difference and less than the second difference.

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