A data synchronous acquisition method and system in a ring main unit

Abstract

The application relates to a data synchronous acquisition method and system in a ring main unit, wherein the method comprises the following steps: in response to a downlink frame sent by a voltage acquisition unit, performing three-phase voltage sampling, and acquiring a reference phase sampling moment according to three-phase voltage data; acquiring a configurable delay time from a downlink frame sending moment to a three-phase voltage sampling moment; acquiring a fixed delay time from the three-phase voltage sampling moment to the reference phase sampling moment; determining a voltage delay time based on the configurable delay time and the fixed delay time; in response to the current acquisition unit receiving the downlink frame, performing current sampling, and acquiring a current delay time from the downlink frame sending moment to a current sampling moment; and based on the voltage delay time and the current delay time, performing data synchronous acquisition in the ring main unit. The high-precision synchronization of data acquisition in the ring main unit is realized, and the problem of how to improve the voltage and current data synchronous acquisition precision in the ring main unit in the related art is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of ring main unit, and particularly relates to a data synchronous acquisition method and system in a ring main unit. BACKGROUND

[0002] In an intelligent power distribution system, a ring main unit is composed of one power grid bus and multiple parallel user sub-circuits. Voltage data of the power grid bus and current data of the sub-circuits need to be synchronously acquired. Synchronous acquisition of voltage and current data of the ring main unit is a key link to realize accurate relay protection and line loss calculation. The synchronous precision directly relates to the safety and economy of power grid operation, and requires that the time error between voltage sampling time and current sampling time be controlled within 3 microseconds.

[0003] The existing synchronous acquisition of voltage and current data of the ring main unit has the following shortcomings. First, the physical connection length of current acquisition and voltage acquisition is not fixed, resulting in low synchronization accuracy of transmission delay. Second, the power grid bus needs to be synchronized with multiple sub-circuits, and the clocks are not synchronized, resulting in difficulty in synchronous acquisition of voltage data and current data.

[0004] At present, for the synchronous acquisition of voltage and current data in the ring main unit, there is no effective solution to improve the accuracy of synchronous acquisition of voltage and current data. SUMMARY

[0005] Embodiments of the present application provide a data synchronous acquisition method and system in a ring main unit to at least solve the problem of how to improve the accuracy of synchronous acquisition of voltage and current data in the ring main unit in the related art.

[0006] In a first aspect, the embodiments of the present application provide a data synchronous acquisition method in a ring main unit. The ring main unit includes a voltage acquisition unit for acquiring voltage data and a current acquisition unit for acquiring current data. The voltage acquisition unit is in communication connection with the current acquisition unit. The method includes the following steps.

[0007] In response to a downlink frame sent by the voltage acquisition unit, three-phase voltage sampling is performed, and a reference phase sampling time is obtained according to three-phase voltage data. The reference phase sampling time is used to align the sampling time of the three-phase voltage data.

[0008] A configurable delay time from the time when the downlink frame is sent to the time when the three-phase voltage is sampled is obtained. A fixed delay time from the time when the three-phase voltage is sampled to the reference phase sampling time is obtained. Based on the configurable delay time and the fixed delay time, a voltage delay time is determined.

[0009] In response to the current acquisition unit receiving the downlink frame, current sampling is performed, and a current delay time from the time when the downlink frame is sent to the time when the current is sampled is obtained.

[0010] Based on the voltage delay time and the current delay time, data synchronization collection in the ring main unit is performed.

[0011] In an embodiment, the configurable delay time from the downlink frame sending time to the three-phase voltage sampling time is obtained, including:

[0012] The voltage collection unit generates a synchronization master clock through a master FPGA chip to control AD sampling control enable and downlink frame control enable respectively;

[0013] The time when the AD sampling control enable is triggered is taken as the three-phase voltage sampling time;

[0014] The time when the downlink frame control enable is triggered is taken as the downlink frame sending time;

[0015] A configurable delay time between the downlink frame sending time and the three-phase voltage sampling time is obtained, wherein the configurable delay time is used to adjust the delay of the voltage sampling path relative to the current sampling path to realize the synchronization of voltage sampling and current sampling.

[0016] In an embodiment, in response to the downlink frame sent by the voltage collection unit, three-phase voltage sampling is triggered, and a reference phase sampling time is obtained according to three-phase voltage data, including:

[0017] In response to the downlink frame sent by the voltage collection unit, three-phase voltage sampling is performed through a preset sampling sequence, wherein the preset sampling sequence is A-phase first sampling A1, B-phase first sampling B1, C-phase sampling C, B-phase second sampling B2, and A-phase second sampling A2.

[0018] The sampling values of A1 and A2 are averaged to obtain A-phase data equivalent to the C-phase sampling time;

[0019] The sampling values of B1 and B2 are averaged to obtain B-phase data equivalent to the C-phase sampling time;

[0020] Based on the C-phase sampling data and the equivalent A-phase data and B-phase data, three-phase voltage data aligned at the C-phase sampling time are obtained, and the C-phase sampling time is taken as the reference phase sampling time.

[0021] In an embodiment, a fixed delay time is determined through a fixed sampling order and a sampling interval of the preset sampling sequence.

[0022] In an embodiment, based on the configurable delay time and the fixed delay time, a voltage delay time is determined, including:

[0023] The voltage delay time is added to the configurable delay time to obtain a voltage delay time.

[0024] In an embodiment, the current delay time from the downlink frame sending time to the current sampling time is obtained by:

[0025] The current delay time is determined according to the sum of the downlink frame sending time, the line transmission delay time, the processing delay time and the current sampling delay time, wherein:

[0026] The downlink frame sending time is the time required from the downlink frame sending time to the time when the downlink frame is completely sent out;

[0027] The line transmission delay time is the physical transmission time required for the downlink frame to be transmitted from the voltage collection unit to the current collection unit;

[0028] The processing delay time is the processing time required for the current collection unit to complete decoding after receiving the downlink frame;

[0029] The current sampling delay time is the time required for the current collection unit to perform current sampling.

[0030] In an embodiment, the data synchronization collection in the ring network cabinet is performed based on the voltage delay time and the current delay time, comprising:

[0031] The configurable delay time is dynamically adjusted according to the difference between the voltage delay time and the current delay time until the voltage delay time is equal to the current delay time;

[0032] When the voltage delay time is equal to the current delay time, the data synchronization collection in the ring network cabinet is performed according to the adjusted configurable delay time, so that the voltage sampling time of the voltage collection unit in the ring network cabinet is synchronized with the current sampling time of the current collection unit.

[0033] In an embodiment, the voltage collection unit and the current collection unit are connected through an RS485 communication chip;

[0034] The voltage collection unit comprises a master control FPGA chip, an AD sampling chip, a frequency sampling chip, a crystal oscillator and an RS485 communication chip;

[0035] The current collection unit comprises a master control CPU, an AD sampling chip, a frequency sampling chip, a crystal oscillator and an RS485 communication chip;

[0036] The data broadcasted from the voltage collection unit to the current collection unit is a downlink frame, wherein the downlink frame comprises synchronization control information and power grid frequency information;

[0037] The data sent by the current acquisition unit to the voltage acquisition unit is an uplink frame, wherein the uplink frame comprises a current parameter acquired by a sensor.

[0038] In an embodiment, when data is continuously and synchronously acquired in the ring main unit, the method further comprises the following protection mechanism:

[0039] The voltage acquisition unit sends a downlink frame according to a preset period, wherein the preset period is to send a downlink frame control enable after N AD sampling control enables are generated, and N is an integer greater than 1;

[0040] The current acquisition unit starts current sampling at a preset time after receiving the downlink frame control enable, and performs timing sampling based on frequency information carried by the downlink frame control enable, and sets a protection window, and if no new downlink frame control enable is received within a plurality of consecutive sampling frame periods, the current frequency is maintained for acquisition;

[0041] The voltage acquisition unit waits to receive the uplink frame of the current acquisition unit after power-on, and delays the sending time of the downlink frame according to the time of receiving the uplink frame;

[0042] When the voltage acquisition unit detects that the bus voltage is lower than a preset proportion of the nominal voltage, the voltage acquisition unit sets the downlink frame sending frequency and the AD voltage sampling interval to a rated frequency value.

[0043] In a second aspect, the embodiments of the present application provide a data synchronous acquisition system in a ring main unit, comprising a reference phase sampling time acquisition module, a voltage delay time module, a current delay time module and a synchronous acquisition module; wherein:

[0044] The reference phase sampling time acquisition module is configured to perform three-phase voltage sampling in response to a downlink frame sent by the voltage acquisition unit, and acquire a reference phase sampling time according to three-phase voltage data, wherein the reference phase sampling time is used to align the sampling time of the three-phase voltage data.

[0045] The voltage delay time module is configured to acquire a configurable delay time from the downlink frame sending time to the three-phase voltage sampling time, acquire a fixed delay time from the three-phase voltage sampling time to the reference phase sampling time, and determine a voltage delay time based on the configurable delay time and the fixed delay time.

[0046] The current delay time module is configured to perform current sampling in response to the current acquisition unit receiving the downlink frame, and acquire a current delay time from the downlink frame sending time to the current sampling time.

[0047] The synchronization acquisition module is configured for acquiring data in the ring network cabinet synchronously based on the relationship between the voltage delay time and the current delay time.

[0048] In a third aspect, an embodiment of the present application provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the method for acquiring data in a ring network cabinet synchronously according to the first aspect.

[0049] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program, and the program is executable on a processor to implement the method for acquiring data in a ring network cabinet synchronously according to the first aspect.

[0050] The method for acquiring data in a ring network cabinet synchronously provided by the embodiments of the present application has at least the following technical effects.

[0051] The three-phase voltage sampling is performed in response to the downlink frame sent by the voltage acquisition unit, and the reference phase sampling time is obtained according to the three-phase voltage data, which is used to align the sampling time of the three-phase voltage data, effectively eliminating the inherent phase deviation of the serial AD sampling, and ensuring the synchronization and accuracy of the voltage data. The configurable delay time from the downlink frame sending time to the three-phase voltage sampling time is obtained, the fixed delay time from the three-phase voltage sampling time to the reference phase sampling time is obtained, the voltage delay time is determined based on the configurable delay time and the fixed delay time, and the accurate determination of the voltage sampling path delay is realized. The current sampling is performed in response to the downlink frame received by the current acquisition unit, the current delay time from the downlink frame sending time to the current sampling time is obtained, and a consistent synchronization trigger starting point is established, which ensures the controllability and measurability of the current sampling time. Finally, the data in the ring network cabinet is acquired synchronously based on the voltage delay time and the current delay time, the delay difference of different transmission paths can be dynamically compensated, the high-precision synchronization of data acquisition in the ring network cabinet is realized, and the problem of how to improve the synchronization acquisition accuracy of voltage and current data in the ring network cabinet in the related art is solved.

[0052] The details of one or more embodiments of the present application are presented in the following drawings and description to make other features, objects and advantages of the present application more clear and easy to understand. BRIEF DESCRIPTION OF DRAWINGS

[0053] The drawings described herein are used to provide further understanding of the present application, and form a part of the present application. The schematic embodiments of the present application and the description thereof are used to explain the present application, and do not constitute improper limitations on the present application. In the drawings:

[0054] Figure 1is a flow chart of a data synchronous acquisition method in a ring net cabinet;

[0055] Figure 2 is a flow chart of step S101 according to an exemplary embodiment;

[0056] Figure 3 is a flow chart of step S103 according to an exemplary embodiment;

[0057] Figure 4 is a flow chart of step S104 according to an exemplary embodiment;

[0058] Figure 5 is a system structure block diagram of a data synchronous acquisition in a ring net cabinet according to an exemplary embodiment;

[0059] Figure 6 is a structure block diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0060] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application is described and explained below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application. Based on the embodiments provided in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of the present application.

[0061] Obviously, the drawings in the following description are only some examples or embodiments of the present application, and for those of ordinary skill in the art, the present application can be applied to other similar scenarios without creative labor on the basis of these drawings. In addition, it can be understood that although the efforts made in this development process can be complex and lengthy, for those of ordinary skill in the art related to the content disclosed in the present application, some design, manufacture or production changes based on the technical content disclosed in the present application are only routine technical means and should not be understood as insufficient disclosure of the present application.

[0062] In the present application, "embodiment" means that the specific features, structures or characteristics described in combination with the embodiment can be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily mean the same embodiment, nor is it an independent or alternative embodiment to other embodiments. Those of ordinary skill in the art explicitly and implicitly understand that the embodiments described in the present application can be combined with other embodiments without conflict.

[0063] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," and "third" used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.

[0064] In smart grid distribution systems, ring main units (RNBs) consist of a main grid bus and multiple parallel user sub-circuits. They require the synchronous acquisition of voltage data from the main grid bus and current data from the sub-circuits. Synchronous acquisition of voltage and current data from the RNB is a crucial step in achieving accurate relay protection and line loss calculation. Its synchronization accuracy directly affects the safety and economy of grid operation, requiring the time error between voltage and current sampling to be controlled within 3 microseconds.

[0065] The existing synchronous acquisition of voltage and current data in ring main units has the following drawbacks: 1. The merging unit requires one-to-many sensing units for synchronization, and the clocks of the merging unit and the sensing units are not synchronized, making it difficult to acquire voltage and current data synchronously; 2. The bus input voltage is an unstable 50Hz voltage, requiring real-time frequency tracking for synchronization; 3. The physical connection length between each sensing unit and the merging unit is not fixed, resulting in different transmission delays; 4. The merging unit's AD converter is a serial sampling AD converter, and the acquired voltage data is not synchronized; 5. Communication between the merging unit and the sensing unit may experience communication abnormalities under strong external interference in the actual power grid, requiring system protection.

[0066] Currently, no effective solution has been proposed for improving the accuracy of synchronous voltage and current data acquisition within ring main units.

[0067] Based on the above situation, the embodiment of the present application provides a data synchronous acquisition method and system in a ring main unit.

[0068] In this document, it needs to be understood that the terms involved can be technical means or other summary technical terms for implementing part of the present application, for example, the terms can include:

[0069] Downlink frame sending time: refers to the time when the main control FPGA chip of the merging unit generates the downlink frame control enable. This time is the starting point of the downlink frame starting to broadcast outward through the RS485 chip, and is the trigger reference of the whole synchronization process.

[0070] Three-phase voltage sampling time: refers to the starting time when the AD sampling chip of the merging unit starts to collect three-phase voltage (A, B, C) under the control of the FPGA. Since serial sampling is adopted, this is the starting time of a sequence.

[0071] Current sampling time: refers to the time when the main control CPU or AD sampling chip of the sensing unit actually starts to perform analog-to-digital conversion on the line current after receiving the downlink frame and after a fixed processing delay (such as 10us).

[0072] Reference phase sampling time: refers to the time when the selected three-phase voltage data time alignment reference is obtained after V-shaped sampling. In the present application, this reference is the sampling time of the C phase. The data of the A and B phases is equivalent to this time through calculation.

[0073] Configurable delay time: refers to a adjustable time parameter set in the FPGA of the merging unit. It is the delay between the downlink frame sending enable time (Tb1) and the AD sampling enable time (Ta1). By accurately adjusting the configurable delay time, the line transmission delay can be compensated.

[0074] Fixed delay time: refers to the fixed and unchangeable time necessary from starting AD sampling of the merging unit to completing sampling of the reference phase (C phase). This delay is determined by the inherent characteristics of the serial sampling sequence of the AC chip, and is a known hardware constant.

[0075] Synchronization master clock: refers to the high-precision clock signal generated by the main control FPGA chip for coordinating all internal operations (such as issuing AD sampling enable and downlink frame enable) based on the reference frequency provided by the crystal oscillator of the merging unit.

[0076] AD sampling control enable: refers to the control signal issued by the FPGA of the merging unit for starting the on-board AD sampling chip to perform a voltage sampling sequence.

[0077] Downlink frame control enable: refers to the control signal sent by the merging unit FPGA to trigger the RS485 communication chip to start broadcasting the downlink frame. The time when the signal is valid is the "downlink frame sending time" (Tb1).

[0078] Master FPGA chip: the core logic controller located in the merging unit. It generates synchronization timing according to the crystal oscillator clock, accurately generates AD sampling control enable and downlink frame control enable signals, and calculates and configures the configurable delay time.

[0079] Master CPU: the core processor located in the sensing unit. It is responsible for receiving and decoding the downlink frame, controlling the current sampling timing according to the frequency information in the frame, and triggering the AD sampling chip to collect current after a fixed delay.

[0080] AD sampling chip: refers to the analog-to-digital converter respectively existing in the merging unit and the sensing unit. The merging unit is used to collect three-phase voltage, and the sensing unit is used to collect line current. They are sampled under the control of the enable signal of the respective control unit (FPGA or CPU).

[0081] Frequency sampling chip: refers to a special chip or circuit module for measuring the real-time frequency of the power grid bus voltage. The measurement result is provided to the FPGA of the merging unit to dynamically adjust the AD sampling interval and the downlink frame sending frequency, realizing frequency tracking.

[0082] In a first aspect, the embodiments of the present application provide a data synchronous acquisition method in a ring network cabinet, the ring network cabinet comprising a voltage acquisition unit for acquiring voltage data and a current acquisition unit for acquiring current data, the voltage acquisition unit being in communication connection with the current acquisition unit. Figure 1 A flowchart of a data synchronous acquisition method in a ring network cabinet is shown in Figure 1 The method comprises the following steps:

[0083] Step S101, in response to a downlink frame sent by the voltage acquisition unit, performing three-phase voltage sampling, and acquiring a reference phase sampling time according to the three-phase voltage data, the reference phase sampling time being used to align the sampling time of the three-phase voltage data.

[0084] Step S102, acquiring a configurable delay time from the downlink frame sending time to the three-phase voltage sampling time; acquiring a fixed delay time from the three-phase voltage sampling time to the reference phase sampling time, and determining a voltage delay time based on the configurable delay time and the fixed delay time.

[0085] Step S103, in response to the current acquisition unit receiving the downlink frame, performing current sampling, and acquiring a current delay time from the downlink frame sending time to the current sampling time.

[0086] In step S104, data synchronization collection in the ring main unit is performed based on the voltage delay time and the current delay time.

[0087] In summary, the embodiment of the present application provides a data synchronization collection method in a ring main unit. The method performs three-phase voltage sampling in response to a downlink frame sent by a voltage collection unit, and acquires a reference phase sampling time based on three-phase voltage data. The reference phase sampling time is used to align the sampling time of the three-phase voltage data, effectively eliminating the inherent phase deviation of serial AD sampling and ensuring the synchronization and accuracy of the voltage data. The method acquires a configurable delay time from the time when the downlink frame is sent to the time when the three-phase voltage is sampled, acquires a fixed delay time from the time when the three-phase voltage is sampled to the time when the reference phase is sampled, determines the voltage delay time based on the configurable delay time and the fixed delay time, and accurately determines the delay of the voltage sampling path. In response to the current collection unit receiving the downlink frame, the method performs current sampling and acquires a current delay time from the time when the downlink frame is sent to the time when the current is sampled, establishes a consistent synchronization trigger starting point, and ensures the controllability and measurability of the current sampling time. Finally, the method performs data synchronization collection in the ring main unit based on the voltage delay time and the current delay time, can dynamically compensate for the delay difference of different transmission paths, thereby achieving high-precision synchronization of data collection in the ring main unit, and solving the problem of how to improve the accuracy of voltage and current data synchronization collection in the ring main unit in related technologies.

[0088] In an implementation, the ring main unit is composed of one power grid bus and multiple parallel user sub-circuits. The ring main unit includes a voltage collection unit for collecting bus voltage data and a current collection unit for collecting current data on each sub-circuit. The voltage collection unit and the current collection unit are in communication connection. Wherein:

[0089] The voltage collection unit and the current collection unit are connected through an RS485 communication chip and can perform bidirectional data transmission, for example, the voltage collection unit transmits to the current collection unit, and the current collection unit transmits to the voltage collection unit.

[0090] The voltage collection unit includes a main control FPGA chip, an AD sampling chip, a frequency sampling chip, a crystal oscillator, and an RS485 communication chip.

[0091] The current collection unit includes a main control CPU, an AD sampling chip, a frequency sampling chip, a crystal oscillator, and an RS485 communication chip.

[0092] The data broadcasted by the voltage collection unit to the current collection unit is a downlink frame, wherein the downlink frame includes synchronization control information and power grid frequency information.

[0093] The data sent by the current collection unit to the voltage collection unit is an uplink frame, wherein the uplink frame includes current parameters collected by a sensor.

[0094] Through the cooperative architecture design of the voltage acquisition unit and the current acquisition unit, high-precision synchronization of data acquisition in the ring main unit is realized.

[0095] Figure 2 is a flowchart of step S101 according to an exemplary embodiment, as shown, step S101, in response to the downlink frame sent by the voltage acquisition unit, performs three-phase voltage sampling, and acquires the reference phase sampling time according to the three-phase voltage data, which is used to align the sampling time of the three-phase voltage data. Specifically, it includes the following steps: Figure 2

[0096] Step S1011, in response to the downlink frame sent by the voltage acquisition unit, three-phase voltage sampling is performed through a preset sampling sequence, wherein the preset sampling sequence is A-phase first sampling A1, B-phase first sampling B1, C-phase sampling C, B-phase second sampling B2, and A-phase second sampling A2.

[0097] Optionally, the sampling of the three-phase voltage A, B, and C should be performed synchronously, that is, the voltage values of the three phases A, B, and C are acquired at the same time. However, due to the limitation of hardware cost or physical connection delay, serial sampling (that is, sampling the three phases A, B, and C in turn) is adopted in actual application, resulting in a deviation of the sampling time of each phase (for example, after A-phase sampling, B-phase and C-phase are sampled in turn). This deviation will intensify with the increase of the sampling interval, affecting the synchronization accuracy of the data. Therefore, the preset sampling sequence (v-shaped sampling) is adopted, taking C-phase as the sampling midpoint, and the sampling interval as the isochronous difference, and the sampling sequence is A-phase first sampling A1, B-phase first sampling B1, C-phase sampling C, B-phase second sampling B2, and A-phase second sampling A2.

[0098] Step S1012, the sampling values of A1 and A2 are averaged to obtain A-phase data equivalent to the sampling time of C-phase.

[0099] Optionally, A1 plus A2 divided by 2 is equivalent to data close to the sampling time of C, and the formula is: A = ((A1 + A2) / 2).

[0100] Step S1013, the sampling values of B1 and B2 are averaged to obtain B-phase data equivalent to the sampling time of C-phase.

[0101] Optionally, B1 plus B2 divided by 2 is equivalent to data close to the sampling time of C, and the formula is: B ((B1 + B2) / 2).

[0102] Step S1014, based on the C-phase sampling data and the equivalent A-phase data and B-phase data, three-phase voltage data aligned at the sampling time of C-phase is obtained, and the sampling time of C-phase is taken as the reference phase sampling time.

[0103] ​Optionally, the equivalent acquisition times of phases A and B are aligned to the time of phase C to eliminate serial sampling deviation and ensure the equivalent synchronization of the three-phase voltage data at the time of phase C.

[0104] Steps S1011-S1014 employ a specific V-shaped sampling sequence (A1→B1→C→B2→A2) for serial sampling of three-phase voltage, effectively overcoming the sampling timing deviation problem caused by hardware limitations. By averaging the first and last A-phase sampling values, the equivalent A-phase data at the C-phase sampling time is calculated. Simultaneously, the first and last B-phase sampling values ​​are averaged to obtain the equivalent B-phase data at the C-phase sampling time, thus eliminating the phase error introduced by serial sampling. Finally, using the actual sampling time of C-phase as a reference, the equivalent A and B-phase data are aligned with it, obtaining high-precision synchronized data of the three-phase voltage at a unified time. This provides an accurate voltage phase reference for subsequent precise comparison with current data and system protection.

[0105] In one implementation, step S102 involves obtaining the configurable delay time from the downlink frame transmission time to the three-phase voltage sampling time. Specifically, this includes:

[0106] The voltage acquisition unit generates a synchronous master control clock through the main control FPGA chip, which controls the AD sampling control enable and the downlink frame control enable respectively.

[0107] The moment when the AD sampling control is enabled is taken as the sampling moment for the three-phase voltage;

[0108] The moment when downlink frame control is enabled is taken as the downlink frame transmission moment;

[0109] The configurable delay time between the downlink frame transmission time and the three-phase voltage sampling time is obtained. The configurable delay time is used to adjust the delay of the voltage sampling path relative to the current sampling path to achieve synchronization of voltage and current sampling.

[0110] Optionally, the master FPGA chip of the voltage acquisition unit generates a synchronous master clock sequence based on a clock reference generated by an internal crystal oscillator thereof. The FPGA outputs two enable signals, one of which is an AD sampling control enable signal for starting the AD sampling chip to perform three-phase voltage sampling in a V-shaped sequence, and the time point at which the signal is valid is recorded as a three-phase voltage sampling time point T a1; the other is a downstream frame control enable signal for triggering the RS485 communication chip to broadcast a downstream frame, and the time point at which the signal is valid is recorded as a downstream frame sending time point T b1; the FPGA can programmably adjust the delay amount between the output time points of the two enable signals through software or hardware logic, and the delay amount is intended to compensate for all delays so as to make the current sampling time point exactly align with the required precise advance amount of the voltage sampling time point. The delay amount is a configurable delay time T1, and by changing the value of T1, the total delay of the voltage sampling path can be accurately controlled, thereby matching the delay of the current sampling path, and finally realizing the synchronization of the voltage and current sampling time points.

[0111] In an implementation, the fixed delay time from the three-phase voltage sampling time point to the reference phase sampling time point in step S102 specifically includes:

[0112] The fixed delay time is determined by the fixed sampling sequence and sampling interval of the preset sampling sequence.

[0113] Optionally, the master FPGA of the voltage acquisition unit calculates the total time from starting three-phase voltage sampling (i.e., the time point T a1 at which A1 phase starts sampling) to completing reference phase (C phase) sampling according to the fixed execution sequence of the preset V-shaped sampling sequence (A1→B1→C→B2→A2) and the inherent and stable sampling interval time of the AD chip; the total time is a fixed delay time T a2, and the value thereof is determined by the number of sampling intervals contained between A1 and C in the sampling sequence and the time length of each interval, and is a predetermined fixed constant.

[0114] By using the fixity and timing predictability of the sampling sequence, the inevitable phase deviation in the serial AD sampling process is converted into a constant delay amount which can be accurately calculated, and the seemingly stray sampling points can be converted into effective data with a unified time reference (C phase time point).

[0115] In an implementation, the voltage delay time is determined based on the configurable delay time and the fixed delay time in step S102. Specifically, the voltage delay time is determined by:

[0116] The voltage delay time is obtained by adding the configurable delay time and the fixed delay time.

[0117] Optionally, the master FPGA chip of the voltage acquisition unit calls preset addition calculation logic to perform summation operation on the configurable delay time T1 and the fixed delay time Ta2, and the output value of the summation result is the voltage delay time, which is mathematically expressed as: voltage delay time = T1 + T2. The value represents the total time from the start of the downlink frame transmission to the completion of the voltage reference phase sampling.

[0118] Figure 3 is a flowchart of step S103 according to an exemplary embodiment, as shown in Figure 3 As shown in step S103, in response to the current acquisition unit receiving the downlink frame, the current sampling is performed to obtain the current delay time from the downlink frame transmission time to the current sampling time. Specifically, the following steps are included:

[0119] S1031, the communication interface of the current acquisition unit receives the downlink frame and decodes the same by the master CPU to obtain the synchronization control information and the grid frequency information therein;

[0120] S1032, after the decoding is completed, the master CPU starts the AD sampling chip to sample the current of the sub-circuit to obtain the current delay time from the downlink frame transmission time to the current sampling time. The current delay time is determined according to the sum of the downlink frame transmission time Tb2, the line transmission delay time Tb3, the processing delay time Tb4 and the current sampling delay time Tb5; wherein:

[0121] The downlink frame transmission time is the time required from the downlink frame transmission time to the time when the downlink frame is completely sent out; the line transmission delay time is the physical transmission time required for the downlink frame to be transmitted from the voltage acquisition unit to the current acquisition unit; the processing delay time is the processing time required for the current acquisition unit to receive the downlink frame to complete the decoding; and the current sampling delay time is the time required for the current acquisition unit to perform current sampling.

[0122] Optionally, the current acquisition unit receives the downlink frame through the RS485 communication interface, the master CPU of which analyzes the frame structure to extract the synchronization control command and the real-time grid frequency parameter; then, the CPU controls the AD sampling chip to start the conversion operation of the sub-circuit current according to the parsed instruction, and accurately calculates the total delay time from the start of the downlink frame transmission to the completion of the current sampling by adding the downlink frame transmission time Tb2, the line transmission delay time Tb3, the processing delay time Tb4 and the current sampling delay time Tb5, i.e. current delay time = Tb2 + Tb3 + Tb4 + Tb5.

[0123] Figure 4 is a flowchart of step S104 according to an exemplary embodiment, as shown in Figure 4As shown, step S104, based on the voltage delay time and the current delay time, the data synchronization collection in the ring net cabinet is carried out. Specifically, it includes the following steps:

[0124] Step S1041, according to the difference between the voltage delay time and the current delay time, the configurable delay time is dynamically adjusted until the voltage delay time and the current delay time are equal.

[0125] Step S1042, when the voltage delay time and the current delay time are equal, according to the adjusted configurable delay time, the data synchronization collection in the ring net cabinet is carried out, realizing the synchronization of the voltage sampling time of the voltage sampling unit and the current sampling time of the current sampling unit in the ring net cabinet.

[0126] Optionally, the current sampling time and the voltage C point sampling time need to be aligned, and the total delay of the voltage sampling path and the total delay of the current sampling path are balanced to derive the synchronization equation:

[0127] T1+ T2= Tb2 + Tb3 + Tb4 + Tb5

[0128] The configurable delay time T1 formula is the total delay of the current sampling loop minus the voltage loop sampling delay, and the formula is as follows:

[0129]

[0130] In the formula, T1 is the configurable delay time, Ta2 is the fixed delay time, Tb2 is the line frame sending time, Tb3 is the line transmission delay time, Tb4 is the processing delay time, and Tb5 is the current sampling delay time.

[0131] The Tb3 line transmission delay of the plurality of sensing units of the ring net cabinet is an unfixed delay, and the other delays are the same delay. The synchronization error between the sensing units of the ring net cabinet is the Tb3 difference value of each sub-loop, and the maximum value is 0.05us. The sensing units of the plurality of ring net cabinet sub-loops of the merging unit simultaneously issue the downlink frame to synchronize the plurality of sub-sensing units. The merging unit adjusts the on-board AD voltage sampling enable time interval (78.125us under 50hz) and the downlink frame output enable according to the frequency change. The current frequency information is attached in the downlink frame. The sensing unit starts the AD current sampling 10us after receiving the downlink frame, and then collects the data of the next point according to the attached frequency information.

[0132] Steps S1041-S1042 compensate for the delay time by dynamically adjusting the configurable delay time T1, so that the voltage delay time and the current delay time always remain equal, thereby ensuring that even in the case of different physical positions of the sensing units in the ring net cabinet, the bus voltage sampling time and the current sampling time of each sub-loop can also achieve high-precision synchronization of microseconds.

[0133] In an embodiment, when the data is continuously and synchronously collected in the ring main unit, the method further comprises the following protection mechanism:

[0134] The voltage collection unit sends a downlink frame according to a preset period, and the preset period is to send a downlink frame control enable after N AD sample control enables are generated, where N is an integer greater than 1;

[0135] The current collection unit starts current sampling at a preset time after receiving the downlink frame control enable, and performs timing sampling based on the frequency information carried by the downlink frame control enable, and sets a protection window, and if no new downlink frame control enable is received within a plurality of consecutive sampling frame periods, the current frequency is maintained for collection;

[0136] The voltage collection unit waits to receive the uplink frame of the current collection unit after power-on, and delays the sending time of the downlink frame according to the time of receiving the uplink frame;

[0137] When the voltage collection unit detects that the bus voltage is lower than the preset proportion of the nominal voltage, the voltage collection unit sets the downlink frame sending frequency and the AD voltage sampling interval to the rated frequency value.

[0138] Optionally, to prevent continuous synchronization from damaging the CPU logic of the sensing unit, the merging unit sends a downlink frame control enable for every 6-8 AD sample control enables. The sensing unit performs AD sampling after receiving the downlink frame for 10-15 us each time, and then performs timing collection according to the frequency information, and sets a 6-10 frame protection window to receive a new downlink frame. To prevent abnormal interference of communication, if there is no downlink frame, the current frequency is maintained. To protect the sensing unit from unstable operation when starting, the merging unit FPGA sets a delay according to the time of receiving the uplink frame, and starts sending the downlink frame after waiting for a certain time. When the bus voltage collected by the merging unit is lower than 2%-5% of the rated voltage, the sending frequency of the downlink frame and the AD voltage sampling time interval of the merging unit are both set to 45HZ-55HZ default value to protect the operation of the sensing unit.

[0139] In summary, the embodiment of the present application provides a data synchronous acquisition method in a ring main unit. The method performs three-phase voltage sampling in response to a downlink frame sent by a voltage acquisition unit, and acquires a reference phase sampling time based on three-phase voltage data. The reference phase sampling time is used to align the sampling time of the three-phase voltage data, effectively eliminating the inherent phase deviation of serial AD sampling and ensuring the synchronization and accuracy of the voltage data. The method acquires a configurable delay time from the time when the downlink frame is sent to the time when the three-phase voltage is sampled, acquires a fixed delay time from the time when the three-phase voltage is sampled to the time when the reference phase is sampled, determines the voltage delay time based on the configurable delay time and the fixed delay time, and accurately determines the delay of the voltage sampling path. In response to the current acquisition unit receiving the downlink frame, the current sampling is performed, and the current delay time from the time when the downlink frame is sent to the time when the current is sampled is acquired, thereby establishing a consistent synchronous trigger starting point and ensuring the controllability and measurability of the current sampling time. Finally, based on the voltage delay time and the current delay time, the data synchronous acquisition in the ring main unit is performed, which can dynamically compensate for the delay difference of different transmission paths, thereby realizing high-precision synchronization of data acquisition in the ring main unit and solving the problem of how to improve the accuracy of voltage and current data synchronous acquisition in the ring main unit in related technologies.

[0140] In a second aspect, the embodiment of the present application provides a data synchronous acquisition system in a ring main unit. Figure 5 is a system structure block diagram of data synchronous acquisition in a ring main unit according to an exemplary embodiment. As shown in Figure 5 , the system includes a reference phase sampling time acquisition module 510, a voltage delay time module 520, a current delay time module 530, and a synchronous acquisition module 540; wherein:

[0141] The reference phase sampling time acquisition module 510 is configured to perform three-phase voltage sampling in response to a downlink frame sent by a voltage acquisition unit, and acquire a reference phase sampling time based on three-phase voltage data. The reference phase sampling time is used to align the sampling time of the three-phase voltage data.

[0142] The voltage delay time module 520 is configured to acquire a configurable delay time from the time when the downlink frame is sent to the time when the three-phase voltage is sampled, and acquire a fixed delay time from the time when the three-phase voltage is sampled to the time when the reference phase is sampled. The voltage delay time is determined based on the configurable delay time and the fixed delay time.

[0143] The current delay time module 530 is configured to perform current sampling in response to the current acquisition unit receiving the downlink frame, and acquire a current delay time from the time when the downlink frame is sent to the time when the current is sampled.

[0144] The synchronous acquisition module 540 is configured to realize data synchronous acquisition in the ring main unit based on the relationship between the voltage delay time and the current delay time.

[0145] To sum up, the data synchronous acquisition system in the ring main unit provided in the application can dynamically compensate for the delay difference of different transmission paths through the reference phase sampling time obtaining module 510, the voltage delay time module 520, the current delay time module 530 and the synchronous acquisition module 540, thereby achieving high-precision synchronization of data acquisition in the ring main unit and solving the problem of how to improve the voltage and current data synchronous acquisition precision in the ring main unit in the related art.

[0146] It should be noted that the data synchronous acquisition system in the ring main unit provided in the embodiment is used to implement the above-described embodiments, and has been described above. As used above, the terms "module", "unit", "sub-unit" and the like can be a combination of software and / or hardware that can implement a predetermined function. Although the device described in the above embodiment is preferably implemented in software, hardware or a combination of software and hardware can also be implemented and conceived.

[0147] In a third aspect, the embodiments of the application provide an electronic device, Figure 6 is a block diagram of an electronic device according to an exemplary embodiment. As shown in the figure, Figure 6 The electronic device can include a processor 61 and a memory 62 storing computer program instructions.

[0148] Specifically, the processor 61 described above can include a central processing unit (CPU), or a specific integrated circuit (Application Specific Integrated Circuit, referred to as ASIC), or can be configured as one or more integrated circuits that implement one or more embodiments of the application.

[0149] The memory 62 can include a mass storage for data or instructions. By way of example, and without limitation, the memory 62 can include a Hard Disk Drive (HDD), a floppy disk drive, a Solid State Drive (SSD), a flash drive, a Compact Disc Read Only Memory (CD-ROM), a Digital Versatile Disk (DVD), a Blu-Ray, a magneto-optical disk, a magnetic tape, or a Universal Serial Bus (USB) drive, or a combination of two or more of these. The memory 62 can be removable and / or non-removable (or fixed) as appropriate. The memory 62 can be internal or external as appropriate. In certain embodiments, the memory 62 is a Non-Volatile Memory. In certain embodiments, the memory 62 includes a Read-Only Memory (ROM) and a Random-Access Memory (RAM). The ROM can be a mask-programmed ROM, a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically EPROM (EEPROM), an Electrically Alterable ROM (EAROM), or a FLASH memory, or a combination of two or more of these, as appropriate. The RAM can be a Static Random-Access Memory (SRAM) or a Dynamic Random-Access Memory (DRAM), which can be a Fast Page Mode Dynamic Random-Access Memory (FPMDRAM), an Extended Data Output Dynamic Random-Access Memory (EDODRAM), a Synchronous Dynamic Random-Access Memory (SDRAM), or the like, as appropriate.

[0150] The memory 62 can be used to store or buffer various data files required for processing and / or communication, and possible computer program instructions executed by the processor 61.

[0151] The processor 61 realizes the data synchronous acquisition method in the ring main unit in any one of the above embodiments by reading and executing the computer program instructions stored in the memory 62.

[0152] In an embodiment, the data synchronous acquisition device in the ring main unit can further include a communication interface 63 and a bus 60. As shown in the figure, Figure 6 The processor 61, the memory 62, and the communication interface 63 are connected through the bus 60 and complete communication with each other.

[0153] The communication interface 63 is used to realize communication between various modules, devices, units, and / or equipment in the embodiments of the present application. The communication interface 63 can also realize data communication with other components, such as external devices, image / data acquisition devices, databases, external storage, and image / data processing workstations, etc.

[0154] Bus 60 includes hardware, software, or both, to couple components of the data-synchronized acquisition device within a ring main unit to each other. Bus 60 includes, but is not limited to, at least one of a data bus, an address bus, a control bus, an expansion bus, a local bus, etc. For example, and without limitation, the bus 60 can include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VLB) bus, or another suitable bus or combination of two or more of these. Where suitable, bus 60 can include one or more buses. Although specific buses are described and illustrated in the embodiments of the application, the application contemplates any suitable bus or interconnect.

[0155] In a fourth aspect, the embodiments of the present application provide a computer readable storage medium, having a program stored thereon, which, when executed by a processor, implements the method for data-synchronized acquisition in a ring main unit according to the first aspect.

[0156] More specifically, the computer readable storage medium can include, but is not limited to, a portable disc, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0157] In possible implementation manners, the application can also be implemented in the form of a program product, which comprises program code for causing an end device to execute steps of a method for synchronously collecting data in a ring main unit according to the first aspect when the program product is run on the end device.

[0158] The program code for executing the application can be written in any combination of one or more programming languages, and can be executed entirely on the user device, partly on the user device, as a stand-alone software package, partly on the user device and partly on a remote device, or entirely on a remote device.

[0159] The technical features of the above-described embodiments can be combined in any manner, and for brevity, not all possible combinations of the technical features in the above-described embodiments are described, but it should be considered that any combination of the technical features is within the scope of the present disclosure as long as the combination does not result in contradictions.

[0160] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are within the scope of protection of the present application. Therefore, the scope of protection of the patent of the present application should be subject to the appended claims.

Claims

1. A method for synchronously collecting data in a ring main unit, characterized in that, The ring main unit comprises a voltage acquisition unit for acquiring voltage data and a current acquisition unit for acquiring current data, and the voltage acquisition unit is in communication connection with the current acquisition unit; the method comprises: in response to a downlink frame sent by the voltage acquisition unit, performing three-phase voltage sampling, and obtaining a reference phase sampling time according to three-phase voltage data, the reference phase sampling time being used for aligning the sampling time of the three-phase voltage data; obtaining a configurable delay time from the time of sending the downlink frame to the three-phase voltage sampling time; obtaining a fixed delay time from the three-phase voltage sampling time to the reference phase sampling time, and determining a voltage delay time based on the configurable delay time and the fixed delay time; in response to the current acquisition unit receiving the downlink frame, performing current sampling, and obtaining a current delay time from the time of sending the downlink frame to the current sampling time; based on the voltage delay time and the current delay time, performing synchronous data acquisition in the ring main unit; wherein, in response to the downlink frame sent by the voltage acquisition unit, triggering three-phase voltage sampling, and obtaining a reference phase sampling time according to three-phase voltage data, comprising: in response to the downlink frame sent by the voltage acquisition unit, performing three-phase voltage sampling through a preset sampling sequence, wherein the preset sampling sequence is A-phase first sampling A1, B-phase first sampling B1, C-phase sampling C, B-phase second sampling B2, and A-phase second sampling A2; averaging the sampling values of A1 and A2 to obtain A-phase data equivalent to the C-phase sampling time; averaging the sampling values of B1 and B2 to obtain B-phase data equivalent to the C-phase sampling time; based on the C-phase sampling data and the equivalent A-phase data and B-phase data, obtaining three-phase voltage data aligned at the C-phase sampling time, and taking the C-phase sampling time as the reference phase sampling time.

2. The method for data synchronization acquisition in a ring main unit according to claim 1, characterized in that, The fixed delay time is determined by the fixed sampling order and sampling interval of the preset sampling sequence.

3. The method for data synchronization acquisition in a ring main unit according to claim 2, characterized in that, based on the configurable delay time and the fixed delay time, determining a voltage delay time, comprising: adding the configurable delay time and the fixed delay time to obtain the voltage delay time.

4. The method for data synchronization acquisition in a ring main unit according to claim 1, characterized in that, The current delay time from the time of sending the downlink frame to the current sampling time is obtained, comprising: determining the current delay time according to the sum of the downlink frame sending time, the line transmission delay time, the processing delay time, and the current sampling delay time; wherein: the downlink frame sending time is the time required from the time of sending the downlink frame to the time of completely sending the downlink frame; the line transmission delay time is the physical transmission time required for the downlink frame to be transmitted from the voltage acquisition unit to the current acquisition unit; the processing delay time is the processing time required for the current acquisition unit to complete decoding after receiving the downlink frame; the current sampling delay time is the time required for the current acquisition unit to perform current sampling.

5. The data synchronization acquisition method in the ring main unit according to claim 3 or 4, characterized in that, based on the voltage delay time and the current delay time, performing synchronous data acquisition in the ring main unit, comprising: According to the difference between the voltage delay time and the current delay time, the configurable delay time is adjusted until the voltage delay time is equal to the current delay time; When the voltage delay time is equal to the current delay time, the data in the ring main unit is collected synchronously according to the adjusted configurable delay time, so that the voltage sampling time of the voltage collection unit in the ring main unit is synchronized with the current sampling time of the current collection unit.

6. The method for data synchronization acquisition in a ring main unit according to claim 1, wherein, The configurable delay time from the downlink frame sending time to the three-phase voltage sampling time is obtained, including: The voltage collection unit generates a synchronous master clock through a master FPGA chip to control AD sampling control enablement and downlink frame control enablement, respectively, wherein the trigger time of the downlink frame control enablement is defined as the downlink frame sending time, and the trigger time of the AD sampling control enablement is defined as the three-phase voltage sampling time; The time interval between the downlink frame control enablement and the AD sampling control enablement is controlled through the synchronous master clock, and the time interval is determined as the configurable delay time between the downlink frame sending time and the three-phase voltage sampling time, wherein the configurable delay time is used to adjust the delay of the voltage sampling path relative to the current sampling path to realize the synchronization of voltage sampling and current sampling.

7. The method of claim 1, wherein The voltage collection unit and the current collection unit are connected through an RS485 communication chip; The voltage collection unit includes a master FPGA chip, an AD sampling chip, a frequency sampling chip, a crystal oscillator, and an RS485 communication chip; The current collection unit includes a master CPU, an AD sampling chip, a frequency sampling chip, a crystal oscillator, and an RS485 communication chip; The data broadcasted by the voltage collection unit to the current collection unit is a downlink frame, wherein the downlink frame includes synchronization control information and power grid frequency information; The data sent by the current collection unit to the voltage collection unit is an uplink frame, wherein the uplink frame includes current parameters collected by a sensor.

8. The method for data synchronization acquisition in a ring main unit according to claim 1, characterized in that, In the continuous synchronous data collection in the ring main unit, the method further includes the following protection mechanism: The voltage collection unit sends a downlink frame according to a preset period, wherein the preset period is to send one downlink frame control enablement after generating N AD sampling control enablements, and N is an integer greater than 1; The current collection unit starts current sampling at a preset time after receiving the downlink frame control enablement, and performs timing sampling based on the frequency information carried by the downlink frame control enablement, while setting a protection window, if no new downlink frame control enablement is received within a plurality of consecutive sampling frame periods, the current frequency is maintained for collection; After the voltage collection unit is powered on, it waits to receive the uplink frame of the current collection unit, and delays the sending time of the downlink frame according to the time when the uplink frame is received; When the voltage collection unit detects that the bus voltage is lower than the preset proportion of the nominal voltage, the voltage collection unit sets the downlink frame sending frequency and the AD voltage sampling interval to the rated frequency value.

9. A data synchronous acquisition system in a ring main unit, characterized in that, The ring main unit comprises a voltage acquisition unit for acquiring voltage data and a current acquisition unit for acquiring current data, and the voltage acquisition unit is in communication connection with the current acquisition unit; the system comprises a reference phase sampling time acquisition module, a voltage delay time module, a current delay time module and a synchronous acquisition module; wherein: The reference phase sampling time acquisition module is configured to perform three-phase voltage sampling in response to a downlink frame sent by the voltage acquisition unit, and acquire a reference phase sampling time according to three-phase voltage data, the reference phase sampling time being used to align the sampling time of the three-phase voltage data; specifically, the three-phase voltage sampling is performed through a preset sampling sequence in response to the downlink frame sent by the voltage acquisition unit, wherein the preset sampling sequence is A-phase first sampling A1, B-phase first sampling B1, C-phase sampling C, B-phase second sampling B2 and A-phase second sampling A2; the sampling values of A1 and A2 are averaged to obtain A-phase data equivalent to the C-phase sampling time; the sampling values of B1 and B2 are averaged to obtain B-phase data equivalent to the C-phase sampling time; three-phase voltage data aligned at the C-phase sampling time is obtained based on the C-phase sampling data and the equivalent A-phase data and B-phase data, and the C-phase sampling time is taken as the reference phase sampling time; The voltage delay time module is configured to acquire a configurable delay time from the downlink frame sending time to the three-phase voltage sampling time, acquire a fixed delay time from the three-phase voltage sampling time to the reference phase sampling time, and determine a voltage delay time based on the configurable delay time and the fixed delay time; The current delay time module is configured to perform current sampling in response to the current acquisition unit receiving the downlink frame, and acquire a current delay time from the downlink frame sending time to the current sampling time; The synchronous acquisition module is configured to achieve synchronous data acquisition in the ring main unit based on the relationship between the voltage delay time and the current delay time.

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