Field effect transistor including trench gate structure
By introducing trench gate and trench field structure into the field-effect transistor, inversion channel is suppressed, and the on-state resistance and reliability problems caused by avalanche breakdown and parasitic device behavior are solved, thereby improving device performance.
Patent Information
- Application Number
- CN202510581067.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-06-04
- Filing Date
- 2025-05-07
- Publication Date
- 2025-12-09
AI Technical Summary
In the process of shrinking the geometry of field-effect transistors, how can we improve device functionality and reduce costs while solving the on-state resistance and reliability problems caused by avalanche breakdown behavior and parasitic device behavior?
By employing trench gate and trench field structures, and through the specific vertical arrangement of the trench gate electrode and trench field electrode, the formation of inversion channels is suppressed, leakage current is reduced, and the reliability and electrical breakdown strength of the device are improved.
It effectively reduces the on-state resistance, improves the reliability and electrical breakdown strength of the device, and enhances the current carrying capacity of the device.
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Figure CN121099656A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to a semiconductor device, and more particularly to a field-effect transistor (FET) including a trench gate structure. Background Technology
[0002] The technological development of next-generation semiconductor devices (such as field-effect transistors (FETs)) aims to improve electronic device characteristics and reduce costs by shrinking device geometry. While reducing device geometry can lower costs, various trade-offs and challenges must be met when increasing device functionality per unit area. For example, region-specific on-state resistance R is affected by behaviors such as avalanche breakdown or parasitic device behavior. on The design optimization requires a trade-off between xA and reliability requirements.
[0003] Therefore, an improved field-effect transistor is needed. Summary of the Invention
[0004] Examples of this disclosure relate to a field-effect transistor (FET). The FET includes a transistor cell in a semiconductor substrate having a first surface. The transistor cell includes a source region at the first surface of the semiconductor substrate. The transistor cell further includes a drain region spaced apart from the source region along a first lateral direction. The transistor cell further includes a trench gate structure disposed along the first lateral direction between the source and drain regions. The trench gate structure includes a trench gate dielectric and a trench gate electrode. The transistor cell further includes a trench field structure disposed along the first lateral direction between the trench gate structure and the drain region. A top side of a first portion of the trench gate electrode is disposed below the first surface at a vertical distance from the first surface.
[0005] Another example of this disclosure relates to a field-effect transistor (FET). The FET includes a transistor cell in a semiconductor substrate having a first surface. The transistor cell includes a source region at the first surface of the semiconductor substrate. The transistor cell further includes a drain region spaced apart from the source region along a first lateral direction. The transistor cell further includes a trench gate structure disposed along the first lateral direction between the source and drain regions. The transistor cell includes a trench field structure disposed along the first lateral direction between the trench gate structure and the drain region. The trench field structure includes a trench field dielectric and a trench gate electrode. A top side of a first portion of the trench field electrode is disposed below the first surface at a vertical distance from the first surface.
[0006] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and viewing the accompanying drawings. Attached Figure Description
[0007] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate examples of semiconductor devices and, together with the description, serve to explain the principles of the examples. Further examples are described in the following detailed description and claims.
[0008] Figure 1 This is a schematic top view illustrating an example configuration of a FET, including a trench gate structure and a trench field structure.
[0009] Figure 2A It is along Figure 1 An exemplary cross-sectional view of line a-a' of the FET illustrated in the figure.
[0010] Figure 2B It is along Figure 1 An exemplary cross-sectional view of line A-A' of the FET shown in the figure.
[0011] Figure 2C It is along Figure 1 An exemplary cross-sectional view of line B-B' of the FET shown in the figure.
[0012] Figure 3A It is along Figure 1 A further exemplary cross-sectional view of line a-a' of the FET illustrated in the figure.
[0013] Figure 3B It is along Figure 1 An exemplary cross-sectional view of line D-D' of the FET illustrated in the figure.
[0014] Figure 3C It is along Figure 1 An exemplary cross-sectional view of the line C-C' of the FET illustrated in the figure.
[0015] Figure 4 It is along Figure 1 A further exemplary cross-sectional view of line a-a' of the FET illustrated in the figure. Detailed Implementation
[0016] In the following detailed description, reference is made to the accompanying drawings, which form part of the detailed description and illustrate specific examples of the FET by way of illustration. It is to be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of this disclosure. For example, a feature illustrated or described for one example may be combined with other examples to produce yet another further example. This disclosure is intended to include such modifications and variations. The examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. Unless otherwise stated, corresponding elements in different drawings are designated by the same reference numerals.
[0017] The terms “having,” “containing,” “including,” “possessing,” and the like are open-ended and indicate the presence of the stated structure, element, or feature, but do not exclude the presence of additional elements or features. The quantifiers “a,” “one,” and the pronoun “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.
[0018] The term "electrical connection" can describe a permanent low-resistance connection between electrically connected components, such as a direct contact between related components or a low-resistance connection via a metal and / or heavily doped semiconductor material. The term "electrical coupling" can include one or more intermediate elements adapted for signal and / or power transmission that can be connected between electrically coupled components, for example, elements controllable to temporarily provide a low-resistance connection in a first state and temporarily provide high-resistance electrical decoupling in a second state. Ohmic contacts are non-rectified electrical junctions.
[0019] A range given for a physical dimension can include boundary values. For example, the range from a to b for the parameter y is read as a≤y≤b. The same applies to ranges with a boundary value such as "at most" and "at least".
[0020] The terms “on” and “above” should not be interpreted as simply meaning “directly on” and “directly above”. Rather, if an element is positioned “on” or “above” another element (e.g., a layer “on” or “above” another layer or “on” or “above” a substrate), then a further component (e.g., a further layer) may be positioned between the two elements (e.g., if a layer is “on” or “above” a substrate, then a further layer may be positioned between that layer and the substrate).
[0021] Examples of this disclosure relate to a field-effect transistor (FET). The FET includes a transistor cell in a semiconductor substrate having a first surface. The transistor cell includes a source region at the first surface of the semiconductor substrate. The transistor cell further includes a drain region spaced apart from the source region along a first lateral direction. The transistor cell further includes a trench gate structure disposed along the first lateral direction between the source and drain regions. The trench gate structure includes a trench gate dielectric and a trench gate electrode. The transistor cell further includes a trench field structure disposed along the first lateral direction between the trench gate structure and the drain region. A top side of a first portion of the trench gate electrode may be disposed below the first surface at a certain vertical distance from the first surface.
[0022] The source and drain regions, or portions thereof, can be n-type. In this case, for example, the FET can be an n-channel FET. In some further examples, the source and drain regions can be p-type. In this case, for example, the FET can be a p-channel FET.
[0023] For example, a FET can be a lateral FET. In a lateral FET, the load current flows in a lateral direction, such as a first lateral direction, and the source and drain regions are spaced apart from each other along the first lateral direction. For example, a lateral FET can be a lateral trench FET, such as a lateral trench metal-oxide-semiconductor field-effect transistor or a lateral trench MOSFET. In a trench gate structure, the trench gate dielectric can line the sidewalls and bottom of the trench and electrically isolate the trench gate electrode from the surrounding portion of the semiconductor substrate. For example, in a lateral trench FET, the channel current can flow along the first lateral direction at opposite sidewalls of the trench gate structure and along the bottom of the trench gate structure.
[0024] For example, a FET can be monolithically implemented using hybrid techniques. Such hybrid techniques can be used, for example, to form analog circuit blocks on a chip using bipolar devices included in the technique to provide an interface to a digital system, and to form digital circuit blocks using complementary metal-oxide-semiconductor (CMOS) devices included in the technique to provide signal processing, and to form low-voltage, medium-voltage, or high-voltage or power blocks using field-effect transistors included in the technique. Such hybrid techniques are known, for example, as bipolar CMOS-DMOS (BCD) technology or smart power technology (SPT), and are used in a wide variety of applications, such as lighting, motor control, automotive electronics, power management for mobile devices, audio amplifiers, power supplies, hard drives, and printers. For example, an FET can be part of a BCD or smart power chip in one of the above application areas.
[0025] Semiconductor substrates can be based on various semiconductor materials, such as silicon (Si), silicon-on-insulator (SOI), silicon-sapphire (SOS), silicon-germanium, germanium, gallium arsenide, silicon carbide, gallium nitride, or other compound semiconductor materials. Semiconductor substrates can be based on semiconductor base substrates, such as semiconductor wafers, and can include one or more epitaxial layers deposited thereon and / or can be back-side thinned.
[0026] To achieve the desired current carrying capacity, a FET can be designed using multiple transistor cells connected in parallel. These parallel-connected transistor cells can be, for example, transistor cells formed in a strip or segmented strip shape. Of course, transistor cells can also have any other shape, such as circular, elliptical, or polygonal shapes like hexagons or octagons. The transistor cells can be arranged in a transistor cell region of a semiconductor substrate. The transistor cell region can be an active region, in which the source and drain regions of the FET are arranged opposite each other along a first lateral direction. In the active region, load current can enter or exit the semiconductor substrate of the FET, for example, via contact plugs on a first and / or second surface of the semiconductor substrate.
[0027] For example, the first surface can be the front or top surface of the semiconductor substrate, and the second surface can be the back or rear surface of the semiconductor substrate. For example, the semiconductor substrate can be attached to the lead frame via the second surface. For example, bonding pads can be arranged above the first and / or second surfaces of the semiconductor substrate, and bonding wiring can be bonded to the bonding pads.
[0028] The source region and body contact region can be electrically connected to the source electrode. For example, the source electrode can be a portion of a wiring region above a first surface of the semiconductor substrate. The wiring region can include one or more wiring levels, such as two, three, four, or even more. Each wiring level can be formed by a single conductive layer or a stack of conductive layers (e.g., one or more metal layers). For example, the wiring levels can be lithographically patterned. An interlayer dielectric structure can be arranged between the stacked wiring levels. One or more contact plugs or contact lines can be formed in openings in the interlayer dielectric structure to electrically connect portions of different wiring levels (e.g., metal lines or contact regions) to each other. The source electrode can be formed by one or more elements of the wiring region. Similarly, the FET can further include a drain electrode. The drain electrode can also be formed by one or more elements of the wiring region above the first surface. For example, the source electrode and drain electrode can include separate portions of a patterned first wiring level (e.g., a first metal layer). In some examples, the drain electrode can also be formed above a second surface of the semiconductor substrate. In this case, the drain region of the FET can be electrically connected to the drain electrode via a through contact or trench contact that extends at least partially through the semiconductor substrate.
[0029] For example, the trench gate dielectric of the trench gate structure electrically isolates the trench gate electrode from the surrounding portion of the semiconductor substrate. For example, the trench gate dielectric can be an insulating material, such as an oxide (e.g., SiO2), a nitride (e.g., Si3N4), a high-k dielectric, or a low-k dielectric, or any combination thereof. For example, the trench gate dielectric can be formed as a thermal oxide. The trench gate electrode can be formed of one or more conductive materials, such as a metal, a metal silicide, a metal compound, or a highly doped semiconductor material such as highly doped polycrystalline silicon. For example, the trench gate electrode can be a single layer, such as a highly doped polycrystalline layer, or a stack of layers. For example, the source region can be adjacent to a first sidewall of the trench gate structure. A drift region of a first conductivity type can be arranged between the trench gate structure and the drain region along a first lateral direction. The drift region can be adjacent to a second sidewall of the trench gate structure. The second sidewall can be opposite to the first sidewall along the first lateral direction.
[0030] A trench field structure is arranged between the trench gate structure and the drain region along a first lateral direction. The trench gate structure may be spaced apart from the trench field structure along the first lateral direction. For example, the width of the trench field structure (e.g., along a range that may be perpendicular to the first lateral direction) may be larger than the width of the trench gate structure, for example, more than 20% and less than 200%. For example, in the transistor cell region, the pitch of the trench field structure along the second lateral direction may be equal to the spacing of the trench gate structure along the second lateral direction. The trench field structure and the trench gate structure may or may not be offset from each other along the second lateral direction, for example, offset by half a pitch.
[0031] Similar to the trench gate dielectric, for example, the trench field dielectric electrically isolates the trench field electrode from the surrounding portion of the semiconductor substrate. For example, the trench field dielectric can have a greater thickness compared to the trench gate dielectric. For example, the trench field dielectric can be an insulating material, such as an oxide (e.g., SiO2), a nitride (e.g., Si3N4), a high-k dielectric, or a low-k dielectric, or any combination thereof. For example, the trench field dielectric can be formed as or comprise thermal oxides and / or deposited and annealed oxides. The trench field electrode can be formed from one or more conductive materials, such as metals, metal silicides, metal compounds, or highly doped semiconductor materials such as highly doped polycrystalline silicon. For example, the trench field electrode can be a single layer, such as a highly doped polycrystalline layer, or a stack of layers. For example, the trench gate electrode and the trench field electrode can be made of the same material or a combination of materials. The provision of the trench field structure allows R... on A further decrease in xA.
[0032] For example, the top side of a first portion of the trench gate electrode may form a step with a second portion of the trench gate electrode, the first portion being disposed below the first surface at a certain vertical distance from the first surface. For example, the vertical distance to the first surface may refer to the vertical horizontal direction at the first surface, where the interface between the contact (e.g., a contact plug or contact line) and the source region is located.
[0033] By arranging a first portion of the trench gate electrode below the first surface, device reliability can be improved by suppressing or avoiding the undesirable formation of inversion channels at the corners of the trench gate structure. Furthermore, leakage current caused by inversion channels can be avoided or at least reduced. Compared to device channels at the sidewalls, inversion channels at the corners can have a smaller threshold voltage, and when the first portion of the trench gate electrode is arranged below the first surface, the deterioration of the turn-on current-voltage characteristics of the channel at the corners can therefore be suppressed or avoided.
[0034] For example, the vertical distance of the first portion of the trench gate electrode from the first surface can have a value in the range of 50 nm to 500 nm. For example, this range of values can allow for beneficial suppression of channel turn-on in the corners of the trench gate structure.
[0035] For example, the trench gate dielectric may abut a first portion of the trench gate electrode along a first lateral direction. This first lateral direction can extend from the source region to the drain region. Therefore, for example, the first portion of the trench gate electrode may be arranged outwards towards the source region. This exemplary arrangement of the first portion may, for example, allow advantageous suppression of channel connection in the corners of the trench gate structure on one side of the source region.
[0036] For example, a second portion of the trench gate electrode may extend at least vertically to a first surface of the semiconductor substrate and may be electrically connected to a gate interconnect extending along a second lateral direction. The second lateral direction may be perpendicular to the first lateral direction. The second lateral direction may be a lateral direction along the width of its measuring device. For example, the second portion may include, for instance, a middle portion of the trench gate electrode along the first lateral direction.
[0037] For example, the second portion of the trench gate electrode may have a lateral distance from the source region along the first lateral direction. This lateral distance may have a value ranging from 100 nm to 500 nm. For example, this range may allow for advantageous suppression of channel turn-on at the corners of the trench gate structure.
[0038] For example, the material for the trench gate electrode and the gate interconnect can include doped polysilicon. For instance, the doped polysilicon can have a high doping concentration, such as greater than 10⁻⁶. 19 cm -3 Or even greater than 10 21 cm -3 This is used to reduce the resistance between the gate pad and the trench gate electrode.
[0039] For example, the top side of the third portion of the trench gate electrode can be disposed below the first surface at a certain vertical distance from the first surface. The second portion of the trench gate electrode can be disposed between the first portion and the third portion of the trench gate electrode along a first lateral direction. For example, when a recess is simultaneously formed in the trench gate electrode by an etching process, the vertical distance from the top side of the first portion to the first surface can be equal to the vertical distance from the top side of the third portion to the first surface.
[0040] For example, a trench field structure may include a trench field dielectric and a trench field electrode. The thickness of the trench field dielectric may be greater than the thickness of the trench gate dielectric. The top side of a first portion of the trench field electrode may be disposed below the first surface at a certain vertical distance from the first surface. This exemplary arrangement of the first portion may allow for a beneficial reduction in the electric field strength at the edge of the mesa region adjacent to the trench field structure. This may allow for improved device reliability by improving the electrical breakdown strength of the device.
[0041] For example, a first portion of the trench field electrode may be adjacent to the trench field dielectric along a first lateral direction. This first lateral direction can extend from the source region to the drain region. Therefore, for example, the first portion of the trench field electrode may be arranged outwards on the side facing the drain region. This exemplary arrangement of the first portion can advantageously allow for a reduction in the electric field strength at the edge of the mesa region adjacent to the trench field structure. This can allow for improved device reliability by increasing the device's electrical breakdown strength.
[0042] The details described above regarding the exemplary FET, such as materials, dimensions, and configuration, also apply to the exemplary FETs described further below.
[0043] Another example of this disclosure relates to a different field-effect transistor (FET). The FET includes a transistor cell in a semiconductor substrate having a first surface. The transistor cell includes a source region at the first surface of the semiconductor substrate. The transistor cell further includes a drain region spaced apart from the source region along a first lateral direction. The transistor cell further includes a trench gate structure disposed along the first lateral direction between the source and drain regions. The transistor cell further includes a trench field structure disposed along the first lateral direction between the trench gate structure and the drain region. The trench field structure includes a trench field dielectric and a trench field electrode. The top side of a first portion of the trench field electrode may be disposed below the first surface at a certain vertical distance from the first surface.
[0044] This exemplary vertical arrangement of the top side of the first portion of the trench field electrode can advantageously reduce the electric field strength at the edge of the mesa region adjacent to the trench field structure. This can allow for improved device reliability by enhancing the device's electrical breakdown strength.
[0045] For example, the vertical distance between the first portion of the trench field electrode and the first surface can have a value in the range of 50 nm to 500 nm.
[0046] For example, a first portion of the trench field electrode may be adjacent to the trench field dielectric along a first lateral direction. This first lateral direction can extend from the source region to the drain region. Therefore, for example, the first portion of the trench field electrode may be arranged outwards on the side facing the drain region. This exemplary arrangement of the first portion can advantageously allow for a reduction in the electric field strength at the edge of the mesa region adjacent to the trench field structure. This can allow for improved device reliability by increasing the device's electrical breakdown strength.
[0047] For example, the second portion of the trench field electrode may extend at least vertically to the first surface. The second portion of the trench field electrode may be electrically connected to a field electrode interconnect extending along a second lateral direction. The second lateral direction may be perpendicular to the first lateral direction. For example, the second lateral direction may be the lateral direction along the width of its measuring device.
[0048] For example, the second portion of the trench field electrode may have a lateral distance from the drain region along the first lateral direction, which has a value greater than 25% of the extension of the trench field electrode along the first lateral direction. This value range can allow for a beneficial reduction in the electric field strength at the edge of the mesa region adjacent to the trench field structure.
[0049] For example, the top side of the third portion of the trench field electrode can be disposed below the first surface of the semiconductor substrate at a certain vertical distance from the first surface. The second portion of the trench field electrode can be disposed between the third portion and the first portion of the trench field electrode along a first lateral direction. For example, when a recess is simultaneously formed in the trench field electrode by etching, the vertical distance from the top side of the first portion to the first surface can be equal to the vertical distance from the top side of the third portion to the first surface.
[0050] For example, a FET may further include an intermediate dielectric disposed between a first surface of a semiconductor substrate and a field electrode interconnect. The intermediate dielectric may have a greater thickness compared to a trench field dielectric.
[0051] For example, a trench gate structure may include a trench gate dielectric and a trench gate electrode. The top side of a first portion of the trench gate electrode may be disposed below the first surface at a certain vertical distance from the first surface of the semiconductor substrate. By disposing the first portion of the trench gate electrode below the first surface, device reliability can be improved by suppressing or avoiding the undesirable formation of inversion channels at the corners of the trench gate structure. Furthermore, leakage current caused by inversion channels can be avoided or at least reduced. Compared to device channels at the sidewalls, inversion channels at the corners can have a smaller threshold voltage, and when the first portion of the trench gate electrode is disposed below the first surface, the degradation of the current-voltage characteristics due to the turn-on of the channel at the corners can be suppressed or avoided.
[0052] For example, the trench gate dielectric may abut a first portion of the trench gate electrode along a first lateral direction. Thus, for example, the first portion of the trench gate electrode may be arranged outwards toward the source region. This exemplary arrangement of the first portion may, for example, allow advantageous suppression of channel connection in the corners of the trench gate structure on one side of the source region.
[0053] For example, the FET may further include a body region adjacent to each of the bottom side and opposing sidewalls of the trench gate structure. The body region may have a different conductivity type than the source region. Compared to the trench gate structure, the body region may have a larger distance from the drain region along the first lateral direction. For example, the body region may abut at least a portion of, for example, the bottom side of the trench gate structure. For example, the body region may abut at least a portion of, for example, the bottom side of the trench gate structure, and at least a portion of, for example, the opposing sidewalls of the trench gate structure. Thus, channel regions can be formed at the opposing sidewalls and the bottom side of the trench gate structure. Along the first lateral direction, the body region may extend laterally along the first lateral direction adjacent to the trench gate structure by more than 60%, or more than 70%, or more than 80%, or more than 90%.
[0054] For example, the source region may be adjacent to the body contact region along a second lateral direction. The second lateral direction may be perpendicular to the first lateral direction. For example, in a transistor cell array comprising multiple transistor cells, the source region and the body contact region may be arranged alternately along the second lateral direction.
[0055] The details relating to the structure, function, or technical benefits of the features described above regarding semiconductor devices such as FETs also apply to the illustrated FETs further described below with respect to the figures.
[0056] The description and accompanying drawings illustrate only the principles of this disclosure. Furthermore, all examples set forth herein are intended, in principle, explicitly for illustrative purposes only, to aid the reader in understanding the principles of this disclosure and the concepts contributed by one or more inventors to the field. All statements herein setting forth the principles, aspects, and examples of this disclosure, and their specific examples, are intended to cover their equivalents.
[0057] Further examples of field-effect transistors (FETs) are explained below with reference to the accompanying drawings. The functional and structural details described in the examples above will also apply to the exemplary embodiments illustrated in the figures and further described below.
[0058] Figure 1 A top view of a portion of the transistor cell TC of the FET 100 is shown schematically and exemplary. Figure 2A The illustration shows, schematically and exemplary, along Figure 1 A cross-sectional view of line a-a'. Figure 2BThe illustration shows, schematically and exemplary, along Figure 1 A cross-sectional view of line A-A'. Figure 2C The illustration shows, schematically and exemplary, along Figure 1 A cross-sectional view of line B-B'.
[0059] Reference Figure 1 , Figure 2A , Figure 2B and Figure 2C Each transistor unit TC is formed in the semiconductor substrate 102.
[0060] At the first surface 108 of the semiconductor substrate 102, n + A doped source region 104 is formed. A drain region 110 is spaced apart from the source region 104 along a first lateral direction x1. The drain region 110 can be electrically connected to a second surface of the semiconductor substrate 102 opposite to the first surface 108, or electrically connected to the first surface 108 (not shown). Figure 2A As shown in the further figures described below, the drain region 110 extends into a portion of the semiconductor substrate 102. The drain region 110 is electrically connected via a second surface (not shown) of the semiconductor substrate 102.
[0061] The first surface 108 is a contact between a doped region (e.g., source region 104) in the semiconductor substrate 102 and the contact with the doped region (e.g., ...). Figure 2A The interface between the contact plug or line 124 shown in the diagram is located on the surface thereon.
[0062] The trench gate structure 112 is arranged along a first lateral direction x1 between the source region 104 and the drain region 110. The trench gate dielectric 1121 of the trench gate structure 112 electrically isolates the trench gate electrode 1122 of the trench gate structure 112 from the surrounding portion of the semiconductor substrate 102.
[0063] The p-doped body region 118 is adjacent to the opposite sidewall of the trench gate structure 112 (see, for example...). Figure 1 ) and bottom side (see example) Figure 2A Thus, channel regions can be formed at opposite sidewalls and bottom sides of the trench gate structure 112. The body region 118 has a distance l1 from the drain region 110 along the first lateral direction x1, which is greater than the distance l2 from the trench gate structure 112 to the drain region 110.
[0064] Each of the transistor cells TC further includes a trench field structure 114. The trench field structure 114 is arranged along a first lateral direction x1 between the trench gate structure 112 and the drain region 110. The thickness t2 of the trench field dielectric 1141 is greater than the thickness t1 of the trench gate dielectric 1121.
[0065] Reference Figure 2A The trench gate electrode 1122 includes a first portion 11221. The first portion 11221 is positioned toward the source region 104. Therefore, the first portion 11221 is the portion of the trench gate electrode 1122 facing the source region 104.
[0066] The trench gate electrode 1122 further includes a second portion 11222 that extends at least vertically to a first surface 108 of the semiconductor substrate 102.
[0067] Reference Figure 2A and Figure 2C The second portion 11222 of the trench gate structure 1122 is electrically connected to the gate interconnect 116. The gate interconnect 116 extends along a second lateral direction x2 perpendicular to the first lateral direction x1. The second portion 11222 of the trench gate electrode 1122 has a lateral distance l3 from the source region 104 along the first lateral direction x1.
[0068] Reference Figure 2A The trench gate electrode 1122 further includes a third portion 11223. The second portion 11222 of the trench gate electrode 1122 is arranged along a first lateral direction x1 between the first portion 11221 of the trench gate electrode 1122 and the third portion 11223 of the trench gate electrode 1122.
[0069] The top side of the first portion 11221 of the trench gate electrode 1122 is disposed below the first surface 108 at a certain vertical distance d11 from the first surface 108. The top side of the third portion 11223 of the trench gate electrode 1122 is disposed below the first surface 108 at a certain vertical distance d12 from the first surface 108. For example, d11 can be equal to d12, for example, when a recess is formed simultaneously in the trench gate electrode. The third portion 11223 of the trench gate electrode 1122 can also be omitted. In this case, for example, the trench gate electrode 1122 can be formed by the first portion 11221 and the second portion 11222.
[0070] For example, by interrupting the source region 104 along the second lateral direction x2, an electrical contact (not shown) can be formed in the body contact region for the body region 118. The electrical contact from the source electrode 122 to the source region 104 (and the body region 118) is provided via a contact plug or line 124 extending through the intermediate dielectric 126.
[0071] The trench field electrode 1142 of the trench field structure 114 is electrically connected to the field electrode interconnect 120.
[0072] Other examples of cross-sectional views are illustrated in Figures 3A to 3C middle. Figure 3A The illustration shows, schematically and exemplary, along Figure 1 Another cross-sectional view of line a-a'. Figure 3B The illustration shows, schematically and exemplary, along Figure 1 A cross-sectional view of line D-D'. Figure 3C The illustration shows, schematically and exemplary, along Figure 1 A cross-sectional view of line C-C'.
[0073] Reference Figure 3A The trench field electrode 1142 includes a first portion 11421. The first portion 11421 is positioned toward the drain region 110. Therefore, the first portion 11421 is the portion of the trench field electrode 1142 facing the drain region 110.
[0074] The trench field electrode 1142 further includes a second portion 11422, which extends at least vertically to the first surface 108 of the semiconductor substrate 102.
[0075] Reference Figure 3A and Figure 3C The second portion 11422 of the trench field electrode 1142 is electrically connected to the field electrode interconnect 120. The field electrode interconnect 120 extends along a second lateral direction x2 perpendicular to the first lateral direction x1. The second portion 11422 of the trench field electrode 1142 has a lateral distance l4 from the drain region 110 along the first lateral direction x1.
[0076] Reference Figure 3A The trench field electrode 1142 further includes a third portion 11423. The second portion 11422 of the trench field electrode 1142 is arranged along a first lateral direction x1 between the first portion 11421 of the trench field electrode 1142 and the third portion 11423 of the trench field electrode 1142.
[0077] Reference Figure 3A and Figure 3B The top side of the first portion 11421 of the trench field electrode 1142 is arranged below the first surface 108 at a certain vertical distance d21 from the first surface 108. The top side of the third portion 11423 of the trench field electrode 1142 is arranged below the first surface 108 at a certain vertical distance d22 from the first surface 108. For example, the distance d21 can be equal to the distance d22 when a recess is formed simultaneously in the trench field electrode. The third portion 11423 of the trench field electrode 1142 can also be omitted. In this case, for example, the trench field electrode 1142 can be formed by the first portion 11421 and the second portion 11422. See reference. Figure 3CAn intermediate dielectric 121 is disposed between the first surface 108 of the semiconductor substrate 102 and the field electrode interconnect 120. The intermediate dielectric 121 has a greater thickness t3 compared to the trench field dielectric 1141.
[0078] exist Figure 4 The diagram shows along Figure 1 A further example of a cross-sectional view of line a-a'.
[0079] and Figure 3A Similar examples exist. Figure 4 Examples include one or more recessed portions in the trench field electrode 1142, namely the first portion 11421 and the third portion 11423. However, the recessed portions are omitted in the trench gate electrode 1122.
[0080] The aspects and features mentioned and described together with the examples and one or more of the figures described above may also be combined with one or more other examples in order to replace similar features in other examples or to additionally introduce features into other examples.
[0081] While specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various alternative and / or equivalent implementations may be made in place of the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.
Claims
1. A field-effect transistor (FET) (100) comprising a transistor cell (TC) in a semiconductor substrate (102) having a first surface (108), wherein the transistor cell (TC) comprises: The source region (104) is located at the first surface (108) of the semiconductor substrate (102); The drain region (110) is separated from the source region (104) along a first lateral direction (x1); A trench gate structure (112) is arranged along a first lateral direction (x1) between a source region (104) and a drain region (110), wherein the trench gate structure (112) includes a trench gate dielectric (1121) and a trench gate electrode (1122). A trench field structure (114) is arranged along a first lateral direction (x1) between the trench gate structure (112) and the drain region (110); and wherein The top side of the first portion (11221, 11223) of the trench gate electrode (1122) is arranged below the first surface (108) at a certain vertical distance (d11, d12) from the first surface (108).
2. The FET (100) according to the preceding claim, wherein the vertical distance (d11, d12) of the first portion (11221, 11223) of the trench gate electrode (1122) from the first surface (108) has a value in the range of 50 nm to 500 nm.
3. The FET (100) according to any of the preceding claims, wherein the trench gate dielectric (1121) abuts a first portion (11221) of the trench gate electrode (1122) along a first lateral direction (x1).
4. The FET (100) according to any of the preceding claims, wherein a second portion (11222) of the trench gate electrode (1122) extends at least vertically to a first surface (108) of the semiconductor substrate (102) and is electrically connected to a gate interconnect (116) extending along a second lateral direction (x2) perpendicular to the first lateral direction (x1).
5. The FET (100) according to the preceding claim, wherein the second portion (11222) of the trench gate electrode (1122) has a lateral distance (l3) from the source region along a first lateral direction (x1), the lateral distance (l3) having a value in the range of 100 nm to 500 nm.
6. The FET (100) according to any one of the preceding two claims, wherein the materials of the trench gate electrode (1122) and the gate interconnect (116) comprise doped polysilicon.
7. The FET (100) according to any one of the preceding two claims, wherein the top side of the third portion (11223) of the trench gate electrode (1122) is disposed below the first surface (108) at a certain vertical distance (d12) from the first surface (108), wherein the second portion (11222) of the trench gate electrode (1122) is disposed between the first portion (11221) of the trench gate electrode (1122) and the third portion (11223) of the trench gate electrode (1122) along a first lateral direction (x1).
8. The FET (100) according to any one of the preceding claims, wherein the trench field structure (114) includes a trench field dielectric (1141) and a trench field electrode (1142), the thickness (t2) of the trench field dielectric (1141) is greater than the thickness (t1) of the trench gate dielectric (1121), and wherein the top side of a first portion (11421, 11423) of the trench field electrode (1142) is disposed below the first surface (108) at a certain vertical distance (d21, d22) from the first surface (108).
9. The FET (100) according to the preceding claim, wherein a first portion (11421) of the trench field electrode (1142) is adjacent to the trench field dielectric (1141) along a first lateral direction (x1).
10. A field-effect transistor (FET) (100) comprising a transistor cell (TC) in a semiconductor substrate (102) having a first surface (108), wherein the transistor cell (TC) comprises: The source region (104) is located at the first surface (108) of the semiconductor substrate (102); The drain region (110) is separated from the source region (104) along a first lateral direction (x1); A trench gate structure (112) is arranged along a first lateral direction (x1) between the source region (104) and the drain region (110); A trench field structure (114) is arranged along a first lateral direction (x1) between a trench gate structure (112) and a drain region (110), wherein the trench field structure (114) includes a trench field dielectric (1141) and a trench field electrode (1142); and wherein The top side of the first portion (11421, 11423) of the trench field electrode (1142) is arranged below the first surface (108) at a certain vertical distance (d21, d22) from the first surface (108).
11. The FET (100) according to the preceding claim, wherein the vertical distance (d21, d22) of the first portion (11421, 11423) of the trench field electrode (1142) from the first surface (108) has a value in the range of 50 nm to 500 nm.
12. The FET (100) according to any one of the preceding two claims, wherein a first portion (11421) of the trench field electrode (1142) is adjacent to the trench field dielectric (1141) along a first lateral direction (x1).
13. The FET (100) according to any one of the preceding five claims, wherein a second portion (11422) of the trench field electrode (1122) extends at least vertically to a first surface (108) and is electrically connected to a field electrode interconnect (120) extending along a second lateral direction (x2) perpendicular to the first lateral direction (x1).
14. The FET (100) according to the preceding claim, wherein the second portion (11422) of the trench field electrode (1142) has a lateral distance (l4) from the drain region (110) along a first lateral direction (x1), the lateral distance (l4) having a value greater than 25% of the extension of the trench field electrode (1142) along the first lateral direction (x1).
15. The FET (100) according to any one of the preceding two claims, wherein the top side of the third portion (11423) of the trench field electrode (1142) is disposed below the first surface (108) of the semiconductor substrate (102) at a certain vertical distance (d22) from the first surface (108), wherein the second portion (11422) of the trench field electrode (1142) is disposed along a first lateral direction (x1) between the third portion (11423) of the trench field electrode (1142) and the first portion (11421) of the trench field electrode (1142).
16. The FET (100) according to any one of the preceding three claims further includes an intermediate dielectric (121) disposed between a first surface (108) of the semiconductor substrate (102) and a field electrode interconnect (120), wherein the intermediate dielectric (121) has a greater thickness (t3) than the trench field dielectric (1141).
17. The FET (100) according to any one of the preceding seven claims, wherein the trench gate structure (112) includes a trench gate dielectric (1121) and a trench gate electrode (1122); and The top side of the first portion (11221, 11223) of the trench gate electrode (1122) is arranged below the first surface (108) at a certain vertical distance (d11, d12) from the first surface (108) of the semiconductor substrate (102).
18. The FET (100) according to the preceding claim, wherein the trench gate dielectric (1121) abuts a first portion (11221) of the trench gate electrode (1122) along a first lateral direction (x1).
19. The FET (100) according to any of the preceding claims further includes a body region (118) adjacent to each of the bottom side and the opposing sidewalls of the trench gate structure (112), the body region having a different conductivity type than the source region (104), and wherein the body region (118) has a greater distance (l1) from the drain region (110) along a first lateral direction (x1) compared to the trench gate structure (112).