Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: forming a dielectric fin groove which is located on a substrate and extends in a first direction, and forming a partition groove which extends in a second direction and transversely penetrates through the dielectric fin groove; forming a first sacrificial layer in the dielectric fin groove and a second sacrificial layer in the partition groove; performing patterning processing to obtain a plurality of fins, including patterning the first sacrificial layer to obtain sacrificial fins, patterning the substrate to obtain semiconductor fins, and arranging a second sacrificial layer between the semiconductor fins to obtain a sacrificial partition structure; forming an isolation layer between the plurality of fins; removing the sacrificial fins and the sacrificial partition structures, and forming first grooves located between the semiconductor fins along the first direction and second grooves located between the semiconductor fins along the second direction; a clamping layer covering the top of the first groove and the top of the second groove is formed, so that a first cavity and a second cavity are correspondingly formed; forming a gate structure crossing the semiconductor fin; the embodiment of the invention is favorable for improving the performance of the semiconductor transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] Semiconductor technology is constantly increasing in demand for higher storage capacity, faster processing systems, higher performance, and lower cost. To meet these demands, the feature size of semiconductor devices continues to shrink. Accordingly, to accommodate the smaller feature size, semiconductor device structures gradually change from planar MOSFET to three-dimensional structure transistors, such as fin field effect transistor (Fin FET), which generally includes a plurality of fins arranged in a certain direction on the surface of a semiconductor substrate, a gate structure covering the top and sidewall of the fins, and source / drain doping regions in the fins on both sides of the gate structure.

[0003] However, the existing disclosed fin field effect transistor has the problem of low performance of semiconductor transistors. SUMMARY

[0004] The present application solves the technical problem by providing a semiconductor structure and a forming method thereof, for improving the performance of the semiconductor structure.

[0005] To solve the above problems, the present application provides a semiconductor structure forming method, comprising: providing a substrate; forming a dielectric fin groove extending in a first direction on the substrate, the first direction being the extension direction of the fin; forming a partition groove extending in a second direction and crossing the dielectric fin groove, the second direction being perpendicular to the first direction; filling a sacrificial material in the dielectric fin groove and the partition groove to form a first sacrificial layer in the dielectric fin groove and a second sacrificial layer in the partition groove; performing a patterning process to obtain a plurality of fins, including: a sacrificial fin obtained by patterning the first sacrificial layer, a semiconductor fin obtained by patterning the substrate, and a sacrificial partition structure obtained by patterning the second sacrificial layer, which is further arranged between the semiconductor fins; forming an isolation layer between the plurality of fins; removing the sacrificial fin and the sacrificial partition structure to form a first recess between the semiconductor fins in the first direction and a second recess between the semiconductor fins in the second direction; forming a pinch-off layer covering the top of the first recess and the second recess, the pinch-off layer surrounding the first recess to form a first cavity and surrounding the second recess to form a second cavity; and forming a gate structure across the semiconductor fin.

[0006] Optionally, the step of forming the pinch-off layer comprises: forming a pinch-off material layer on the first recess and the second recess, the pinch-off material layer covering the top of the first recess and the second recess; and removing a portion of the thickness of the pinch-off material layer to expose the top surface of the fin portion and the isolation layer.

[0007] Optionally, the pinch-off layer is formed by a chemical vapor deposition process.

[0008] Optionally, the pinch-off layer material includes one or more of silicon nitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, and silicon boron nitride.

[0009] Optionally, the forming method further includes, after forming the pinch-off layer, thinning the isolation layer between the fins before forming the gate structure.

[0010] Optionally, the sacrificial material includes one or more of silicon germanium, germanium, silicon carbide, cobalt silicide, nickel silicide, gallium arsenide, indium phosphide, indium gallium arsenide, and indium arsenide.

[0011] Optionally, the forming method further includes, before forming the pinch-off layer, forming a liner layer covering the sidewalls and bottom of the first and second recesses.

[0012] Optionally, the liner layer is formed by an atomic layer deposition process.

[0013] Optionally, the liner layer has a thickness in a range of 100 angstroms to 300 angstroms.

[0014] Optionally, the liner layer material includes one or more of silicon nitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, and silicon boron nitride.

[0015] Optionally, the dielectric fin trench and the isolation trench are formed in the same step.

[0016] Optionally, the forming the gate structure includes forming a plurality of gate structures spanning the first and second cavities.

[0017] Correspondingly, the application also provides a semiconductor structure, including: a substrate; a plurality of semiconductor fins on the substrate and extending along a first direction; a first recess between the plurality of semiconductor fins along the first direction; a second recess extending along the first direction and between the semiconductor fins and the first recess along a second direction perpendicular to the first direction; a pinch-off layer covering the top of the first and second recesses, the pinch-off layer being configured to enclose a first cavity with the first recess and a second cavity with the second recess; an isolation layer between the plurality of semiconductor fins and the second recess, the surface of the isolation layer being lower than the top surface of the semiconductor fins; and a plurality of gate structures spanning the semiconductor fins.

[0018] Optionally, the semiconductor structure further includes a liner layer formed on the sidewalls and bottom of the first and second recesses.

[0019] Optionally, the liner layer has a thickness in a range of 100 angstroms to 300 angstroms.

[0020] Optionally, the material of the liner layer comprises one or more of silicon nitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, silicon oxycarbonitride and silicon oxynitride.

[0021] Optionally, the material of the pinch layer comprises one or more of silicon nitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, silicon oxycarbonitride and silicon oxynitride.

[0022] Optionally, further comprising: a plurality of gate structures across the first cavity and the second cavity.

[0023] Optionally, the gate structure is a dummy gate.

[0024] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0025] The semiconductor structure provided by the embodiment of the present application comprises a plurality of semiconductor fins on a substrate, a first cavity between the semiconductor fins in a first direction, and a second cavity between the semiconductor fins in a second direction, the first cavity and the second cavity being filled with air, and the dielectric constant of air being low, so that the air cavity can better reduce the coupling capacitance between semiconductor transistor films and improve the performance of the semiconductor transistor. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the provided drawings.

[0027] Figures 1 to 6 FIG. 1 is a schematic diagram of a semiconductor structure;

[0028] Figures 7 to 1 7 is a schematic diagram of the structure corresponding to each step in the method for forming a semiconductor structure according to an embodiment of the present application;

[0029] FIGS. 18 to 20 are schematic diagrams of a semiconductor structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0031] As can be learned from the background art, the prior art fin field effect transistor structure has the problem of reduced performance of the semiconductor transistor. In the following, the reasons for the reduced performance of the semiconductor transistor are analyzed in connection with the fin field effect transistor semiconductor structure shown in Figures 1 to 6 The semiconductor structure is described in detail as follows:

[0032] As shown in Figure 1 , a substrate 100 is provided, and a plurality of semiconductor fins 101 extending along a first direction Y are formed on the substrate 100 by a photolithography process using a patterned mask M1.

[0033] As shown in Figure 2 , an isolation structure 102 covering the surface of the substrate 100, the semiconductor fins 101 and the mask M1 is formed; the isolation structure 102 encloses a plurality of dielectric grooves A1 extending along the first direction Y.

[0034] As shown in Figure 3 , the isolation structure 102, the semiconductor fins 101 and the mask M1 are etched with the mask 103 as a mask until the substrate 100 is exposed, so as to form a groove C1 on the substrate 100, which divides the semiconductor fins 101 into a plurality of parts along a second direction X, each part being used to form a transistor.

[0035] As shown in Figure 4 , a dielectric material layer is deposited above the substrate 100 and the isolation structure 102, and fills the dielectric grooves A1 and the groove C1; the top surface of the substrate 100 is planarized by a chemical mechanical polishing process, exposing the mask M1, the semiconductor fins 101 and the isolation structure 102, and forming a dielectric block 104.

[0036] As shown in Figure 5 , the mask M1 is removed by a dry or wet etching process; then the isolation structure 102 is dry or wet etched so that the top surface of the isolation structure 102 is lower than the semiconductor fins 101.

[0037] With reference to Figure 5 , for example, an oxide layer 105 is formed on each surface of the semiconductor fins 101, the isolation structure 102 and the dielectric block 104 by an atomic layer deposition process.

[0038] As shown in Figure 6 , a gate layer structure material layer (not shown) is deposited on the substrate 100, and a plurality of gate layer structures 106 are formed by a patterned mask M2; part of the gate layer structures 106 straddle the semiconductor fins 101, and part of the gate layer structures 106 straddle the dielectric block 104.

[0039] In the above-mentioned fin field-effect transistor structure, as the feature size shrinks, the thickness of the isolation structure 102 and the dielectric block 104 decreases, and the coupling capacitance between semiconductor devices increases accordingly, resulting in a decrease in the performance of the semiconductor transistor.

[0040] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure. The method includes: providing a substrate; forming a dielectric fin trench extending along a first direction on the substrate, the first direction being the extension direction of the fin; forming a partition trench extending along a second direction and traversing the dielectric fin trench, the second direction being perpendicular to the first direction; filling the dielectric fin trench and the partition trench with sacrificial material to form a first sacrificial layer in the dielectric fin trench and a second sacrificial layer in the partition trench; performing patterning processing to obtain multiple fins, including: patterning the first sacrificial layer to obtain sacrificial fins, patterning the substrate to obtain semiconductor fins, and further providing a patterned second sacrificial layer between the semiconductor fins to obtain a sacrificial partition structure; forming an isolation layer between the multiple fins; removing the sacrificial fins and the sacrificial partition structure to form a first groove between the semiconductor fins along the first direction and a second groove between the semiconductor fins along the second direction; forming a clamping layer covering the top of the first groove and the second groove, the clamping layer forming a first cavity with the first groove and also forming a second cavity with the second groove; and forming a gate structure spanning the semiconductor fins.

[0041] In the method of forming a semiconductor structure, a plurality of semiconductor fins are formed on a substrate, and a first cavity is located between the semiconductor fins along a first direction and a second cavity is located between the semiconductor fins along a second direction; the first cavity and the second cavity are filled with air, and the dielectric constant of air is low. Therefore, the air cavity is set to better reduce the coupling capacitance between the semiconductor transistor film layers and improve the performance of the semiconductor transistor.

[0042] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0043] refer to Figures 7 to 1 7 is a schematic diagram of the structure corresponding to each step in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0044] It should be noted that, Figure 10b It is along Figure 10a A10A11 in the figure is a cross-sectional view of the section in the second direction X. Figure 10c It is along Figure 10a A12 and A13 in the figure are cross-sectional views of the first direction Y. Figure 10d It is along Figure 10a A14 and A15 are sectional views of the section in the second direction X; Figure 11b It is along Figure 11aB10B11 in FIG. 1 is a sectional view of the cross section of B10B11 in the second direction X, Figure 11c is along Figure 11a B12B13 in FIG. 2 is a sectional view of the cross section of B12B13 in the second direction X; Figure 12b is along Figure 12a C10C11 in FIG. 3 is a sectional view of the cross section of C10C11 in the second direction X, Figure 12c is along Figure 12a C12C13 in FIG. 4 is a sectional view of the cross section of C12C13 in the second direction X;

[0045] Figure 13b is along Figure 13a D10D11 in FIG. 5 is a sectional view of the cross section of D10D11 in the second direction X, Figure 13c is along Figure 13a D12D13 in FIG. 6 is a sectional view of the cross section of D12D13 in the second direction X; Figure 14b is along Figure 14a E10E11 in FIG. 7 is a sectional view of the cross section of E10E11 in the second direction X, Figure 14c is along Figure 14a E12E13 in FIG. 8 is a sectional view of the cross section of E12E13 in the second direction X; Figure 15b is along Figure 15a F10F11 in FIG. 9 is a sectional view of the cross section of F10F11 in the second direction X, Figure 15c is along Figure 15a F12F13 in FIG. 10 is a sectional view of the cross section of F12F13 in the second direction X; Figure 16b is along Figure 16a H10H11 in FIG. 11 is a sectional view of the cross section of H10H11 in the second direction X, Figure 16c is along Figure 16a H12H13 in FIG. 12 is a sectional view of the cross section of H12H13 in the second direction X; Figure 17b is along Figure 17a J10J11 in FIG. 13 is a sectional view of the cross section of J10J11 in the second direction X, Figure 17c is along Figure 17a J12J13 in FIG. 14 is a sectional view of the cross section of J12J13 in the second direction X.

[0046] Referring to Figure 7 and Figure 8 , a substrate 200 is provided; a dielectric fin groove 201 extending along a first direction Y is formed on the substrate 200, the first direction Y being the extending direction of the fin; the dielectric fin groove 201 is mainly used to provide process space for subsequent formation of a first cavity; a partition groove 202 extending along a second direction X and crossing the dielectric fin groove 201 is formed on the substrate 200, the second direction X being perpendicular to the first direction Y; the partition groove 202 is mainly used to provide position space for formation of a second cavity. It should be noted that, for the sake of simplicity and clarity of the drawings, all embodiments of the present application are exemplified by one dielectric fin groove and one partition groove, which do not limit the present application.

[0047] In this embodiment, the substrate 200 is used to provide a process platform for the formation of a semiconductor structure. The substrate 200 is a silicon substrate, and the material of the substrate 200 is single crystal silicon. In other embodiments, the material of the substrate 200 can also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide, and the substrate 200 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate or other types of substrates. In some other embodiments, an epitaxial layer (not shown) having the same crystal structure as the substrate 200 is formed on the surface of the substrate 200 to improve the quality of pattern transfer.

[0048] In this embodiment, after the substrate 200 is provided, a dielectric fin groove 201 is first formed, and then a partition groove 202 is formed (as shown in FIG. 2B). Figure 7 In other embodiments, the dielectric fin groove 201 and the partition groove 202 can be formed in the same step. Figure 8

[0049] The specific process of forming the dielectric fin groove 201 and the partition groove 202 on the substrate 200 includes: forming a hard mask (not shown) for patterning the substrate 200 on the surface of the substrate 200, coating a layer of photoresist (not shown) on the hard mask, patterning the photoresist by exposure and development, transferring the photoresist pattern to the hard mask, and then etching part of the substrate 200 by dry etching or wet etching process with the hard mask as a mask, so as to transfer the pattern of the hard mask to the substrate 200 again to form the dielectric fin groove 201 and the partition groove 202; and removing the hard mask layer after the dielectric fin groove 201 and the partition groove 202 are formed.

[0050] It should be noted that the hard mask is less affected by semiconductor processes and is more suitable for processes with smaller feature sizes. For example, after high-temperature processes, the pattern of the formed hard mask is not easy to deform and has high fineness, so that the quality of pattern transfer can be ensured by the setting of the hard mask. In other embodiments, the patterning method of the hard mask can also not be used.

[0051] Referring to FIG. 2C, Figure 9 the dielectric fin groove 201 and the partition groove 202 are filled with a sacrificial material to form a first sacrificial layer 203 located in the dielectric fin groove 201 and a second sacrificial layer 204 located in the partition groove 202; the first sacrificial layer 203 is used to form a sacrificial fin; and the second sacrificial layer 204 is used to form a partition structure.

[0052] In this embodiment, the sacrificial material is selected to be a material close to the properties of the substrate 200, so that the widths and heights of the plurality of fins formed in the process of patterning can be relatively close. The sacrificial material includes one or more of silicon germanium, germanium, silicon carbide, cobalt silicide, nickel silicide, gallium arsenide, indium phosphide, indium gallium arsenide, and indium arsenide. As an example, the sacrificial material is silicon germanium.​

[0053] In this embodiment, the sacrificial material can be filled in the dielectric fin groove 201 and the partition groove 202 by an epitaxial growth process; the epitaxially grown film layer has the advantages of uniform thickness, dense structure, and better adhesion to the substrate 200.

[0054] The step of forming the first sacrificial layer 203 and the second sacrificial layer 204 further comprises: taking the substrate 200 as a stop layer, and performing chemical mechanical polishing on the sacrificial material to form the first sacrificial layer 203 and the second sacrificial layer 204.

[0055] Referring to FIG. 10, FIG. 10 includes Figure 10a 、 10b , 10c and 10d; the substrate 200, the first sacrificial layer 203 and the second sacrificial layer 204 are patterned to obtain a plurality of fins Q, which include: a sacrificial fin 205 obtained by patterning the first sacrificial layer 203, the sacrificial fin 205 being used to preoccupy a position space for subsequent formation of a first recess (or a first cavity); a semiconductor fin 206 obtained by patterning the substrate 200, the semiconductor fin 206 being used to form a channel of a semiconductor transistor; and a sacrificial partition structure 207 obtained by patterning the second sacrificial layer 204, the sacrificial partition structure 207 being used to preoccupy a position space for subsequent formation of a second recess (or a second cavity).

[0056] In this embodiment, the step of patterning the substrate filled with the sacrificial material to form fins is the same as the process of patterning a semiconductor substrate to form a semiconductor fin in the prior art, and thus has good compatibility. Specifically, because the dry etching process can better control the etching direction and etching amount, the substrate 200, the first sacrificial layer 203 and the second sacrificial layer 204 are patterned by a dry etching process to form the sacrificial fin 205, the semiconductor fin 206 and the sacrificial partition structure 207. In other embodiments, the patterning step can also use a wet etching process.

[0057] It should be noted that the height and width of the plurality of fins obtained by patterning are the same or similar, that is, the width and height of the semiconductor fin, the sacrificial fin and the partition structure are the same or similar, that is, the uniformity of the key dimensions of the plurality of fins formed is good. In addition, the semiconductor fin, the sacrificial fin and the sacrificial partition structure formed after patterning are all trapezoidal in cross section in the second direction X, which is narrow at the top and wide at the bottom.

[0058] Referring to FIG. 11, FIG. 11 includes Figure 11a 、 11band 11c; forming an isolation layer 208 between the plurality of fins; the isolation layer 208 is used for electrical isolation between the plurality of fins Q, and also prevents external impurities from entering the semiconductor structure through the bottom of the substrate 200 to cause failure of the semiconductor transistor.

[0059] In this embodiment, the material of the isolation layer 208 is silicon oxide, which has good chemical stability and strong isolation ability. In other embodiments, the material of the isolation layer 208 can also be other insulating materials, such as silicon nitride, silicon oxynitride, etc.

[0060] The specific process steps of forming the isolation layer 208 between the plurality of fins include: forming an isolation material layer (not shown) by chemical vapor deposition, which fills between the plurality of fins and covers the semiconductor fins 206, the first sacrificial layer 203 and the second sacrificial layer 204.

[0061] After depositing the isolation material layer, the isolation material layer is also chemically mechanically polished with the semiconductor fins 206 as a stop layer, to form the isolation layer 208, so that the surface of the formed isolation layer 208 is flush with the surfaces of the semiconductor fins 206, the first sacrificial layer 203 and the second sacrificial layer 204.

[0062] Referring to FIG. 12, FIG. 12 includes Figure 12a 、 12b and 12c; removing the sacrificial fins 205 and the sacrificial partition structures 207, to form first recesses 209 between the semiconductor fins 206 along the first direction Y, and second recesses 210 between the semiconductor fins 206 along the second direction X; the first recesses 209 are used for forming first cavities; the second recesses 210 are used for forming second cavities.

[0063] It should be noted that the semiconductor fins, the sacrificial fins and the partition structures are formed by the same patterning process, so their widths and heights are the same or similar, and correspondingly, the widths and heights of the first recesses formed by removing the sacrificial fins and the second recesses formed by removing the sacrificial partition structures are also the same or similar.

[0064] In the actual process, in order to ensure that the width and height of the first groove and the second groove are the same or similar, a dry etching process is used in the method of removing the sacrificial fins 205 and the sacrificial partition structure 207. The dry etching process includes the following process steps: placing the substrate 200 on a load table in an etching chamber, introducing a mixed gas containing oxygen, fluorine and chlorine into the etching chamber, and using a thermal energy source or a plasma energy source to provide energy, so that the mixed gas in the chamber reacts with the sacrificial fins and the partition structure to remove the sacrificial fins and the partition structure, thereby forming the first groove 209 between the semiconductor fins 206 along the first direction Y and the second groove 210 between the semiconductor fins 206 along the second direction X.

[0065] Referring to FIGS. 13-15, FIG. 13 includes Figure 13a , 13b and 13c, FIG. 14 includes Figure 14a , 14b and 14c, and FIG. 15 includes Figure 15a , 15b and 15c; a pinch-off layer 211 is formed covering the top of the first groove 209 and the second groove 210, the pinch-off layer 211 surrounding the first groove 209 to form a first cavity 212 and surrounding the second groove 210 to form a second cavity 213. The first cavity 212 and the second cavity 213 are used to electrically or physically isolate the semiconductor fins 206. Because the first cavity 212 and the second cavity 213 are filled with air, the dielectric constant of air is low, so that the parasitic capacitance can be reduced and the performance of the semiconductor device can be optimized.

[0066] In this embodiment, the material of the pinch-off layer is one or more of silicon nitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, silicon oxycarbonitride, and silicon oxynitride. As an example, the material of the pinch-off layer is silicon nitride.

[0067] With reference to FIGS. 14 and 15, in this embodiment, the step of forming the pinch-off layer 211 includes: forming a pinch-off material layer G1 on the first groove 209 and the second groove 210, the pinch-off material layer G1 covering the top of the first groove 209 and the second groove 210; removing part of the thickness of the pinch-off material layer G1 to expose the top surface of the fin portion and the isolation layer 208.

[0068] Specifically, the pinch-off material layer G1 is formed on the first groove 209 and the second groove 210 by a chemical vapor deposition process; the pinch-off material layer G1 also covers the surface of the semiconductor fins 206 and the isolation layer 208; the pinch-off material layer G1 covers the top of the first groove 209 and the second groove 210, and is used to seal the first groove 209 and the second groove 210. In other embodiments, the pinch-off material layer can also be formed by physical vapor deposition, semi-atmospheric pressure vapor deposition, spray vapor deposition, or plasma nitriding process.

[0069] Part of the pinch-off material layer G1 is removed by dry etching or chemical mechanical polishing process to expose the top surface of the fin and the isolation layer 208, forming a pinch-off layer 211. The pinch-off layer 211 and the first recess 209 form a first cavity 212, and the pinch-off layer 211 and the second recess 210 form a second cavity 213.

[0070] It should be noted that the first recess 209 and the second recess 210 have the same or similar width and height in the second direction X, and correspondingly, the first cavity 212 and the second cavity 213 have the same or similar width and height in the second direction X as the semiconductor fin 206.

[0071] With reference to FIGS. 13-15, before forming the pinch-off layer 211, a liner layer 214 is further formed to cover the sidewalls and bottom of the first recess 209 and the second recess 210. The liner layer 214 has good interface contact properties with the pinch-off layer 211, the sidewalls and bottom of the first recess 209 and the second recess 210, and provides good sealing effect for the subsequent formation of the first cavity and the second cavity.

[0072] In the embodiment, the material of the liner layer 214 includes one or more of silicon nitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, and silicon boron nitride. As an example, the material of the liner layer 214 is silicon nitride.

[0073] In the embodiment, the liner material layer G2 is formed by an atomic layer deposition process. The film formed by the atomic layer deposition process is thin and uniform, has a dense structure, and has good adhesion to the pinch-off layer.

[0074] It should be noted that after the atomic layer deposition process forms the liner material layer G2, a dry etching process is further used to remove the liner material layer G2 on the surface of the isolation layer 208 and the fin Q, forming the liner layer 214.

[0075] It should be noted that if the thickness of the liner layer 214 is too large, it will compress the internal space of the first cavity 212 and the second cavity 213, affecting the effect of reducing the coupling capacitance; if the thickness of the liner layer 214 is too small, pinholes and other defects are likely to be formed, affecting the sealing effect of the first cavity 212 and the second cavity 213, and also reducing the isolation effect; in the embodiment, the thickness of the liner layer 214 is in the range of 100 angstroms to 300 angstroms.

[0076] Referring to FIG. 16, FIG. 16 includes Figure 16a , 16band 16c; after forming the pinch-off layer 211, before forming the gate structure, the forming method further comprises: thinning the isolation layer 208 between the fins, so that the surface of the thinned isolation layer G3 is lower than the surfaces of the semiconductor fins 206, the first cavity 212 and the second cavity 213. A growth interface is provided for subsequent formation of the gate structure across the fins on the fins, to form a three-dimensional transistor.

[0077] In this embodiment, the isolation layer 208 between the fins is thinned by a dry etching process, so that the surface of the thinned isolation layer G3 is lower than the surfaces of the semiconductor fins 206, the first cavity 212 and the second cavity 213.

[0078] Referring to FIG. 17, FIG. 17 includes Figure 17a 、 17b and 17c; the gate structure G4 is formed across the semiconductor fins 206.

[0079] It should be noted that after the sacrificial material is filled in the dielectric fin groove and the partition groove, the filled material and the substrate are patterned to form a plurality of fins. Compared with the step of forming a groove first and then etching to form a fin, the width and height uniformity of the fins formed by the embodiment of the present application is good; accordingly, when the gate structure across the fins is formed, the uniformity of the distribution of the line width or line spacing of the gate structure on the substrate can be improved, thereby improving the uniformity of the distribution of the threshold voltage of the semiconductor transistor on the substrate, and the performance of the semiconductor transistor is also improved.

[0080] Continuing to refer to FIG. 17, the step of forming the gate structure includes: further forming a plurality of gate structures across the first cavity 212 and the second cavity 213.

[0081] The plurality of gate structures are uniformly distributed at the first cavity and the second cavity, further improving the uniformity of the distribution of the line width or line spacing of the gate structure on the substrate.

[0082] It should be noted that in this embodiment, the gate structure is a dummy gate, which is used to preoccupy the space position for subsequent formation of the gate structure layer, and can also protect the channel of the semiconductor transistor at the gate structure layer.

[0083] In this embodiment, the dummy gate material can be polysilicon or amorphous silicon.

[0084] Chemical vapor deposition has the advantages of fast speed, uniform film thickness and good crystallinity, and in this embodiment, a plurality of dummy gates across the semiconductor fins 206, the first cavity 212 and the second cavity 213 can be formed on the surface of the substrate 200 by chemical vapor deposition.

[0085] Referring again to Figure 17, in this embodiment, after thinning the isolation layer and before forming the dummy gate, a gate dielectric layer 215 is formed covering the semiconductor fin 206, the first cavity 212, and the second cavity 213; the gate dielectric layer 215 is used to achieve electrical isolation between the semiconductor fin 206 and the subsequently formed gate electrode layer.

[0086] In this embodiment, the gate dielectric layer 215 includes a high-k gate dielectric layer, which is made of a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from zirconium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or aluminum oxide. In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer; alternatively, the gate dielectric layer may consist only of a gate oxide layer.

[0087] It should be noted that after forming the dummy gate structure, the process also includes forming a source / drain doped layer (not shown) in the semiconductor fin, and removing the dummy gate to form the gate structure layer.

[0088] To address the aforementioned technical problems, the present invention also provides a semiconductor structure. Figures 18 to 20 are schematic diagrams of the semiconductor structure formation method of the present invention.

[0089] It should be noted that, Figure 18b The gate structure S10 is along Figure 18a K10 and K11 are cross-sectional views in the second direction X section. Figure 18c The gate structure S20 is along Figure 18a K12 and K13 are cross-sectional views of the second direction X section; Figure 19b It is along Figure 19a L10 and L11 are cross-sectional views in the second direction X section. Figure 19c It is along Figure 19a The cross-sectional view of L12 and L13 in the second direction X section; Figure 20b It is along Figure 20a M10 and M11 are cross-sectional views in the second direction X section. Figure 20c It is along Figure 20a M12 and M13 are cross-sectional views of the second direction X section.

[0090] Referring to Figures 18 to 20, Figure 18 includes Figure 18a , 18b And 18c, Figure 19 includes Figure 19a , 19b And 19c, Figure 20 includes Figure 20a , 20b and 20c; the semiconductor structure of this embodiment includes:

[0091] A substrate 300; a plurality of semiconductor fins 301 located on the substrate and extending along a first direction Y; a first groove 302 located between the plurality of semiconductor fins 301 along the first direction Y; a second groove 303 extending along the first direction Y and located between the semiconductor fins 301 and the first groove 302 along a second direction X, the second direction X being perpendicular to the first direction Y; a clamping layer 304 covering the top of the first groove 302 and the second groove 303, the clamping layer 304 being used to form a first cavity 305 with the first groove 302 and also to form a second cavity 306 with the second groove 303; an isolation layer 307 located between the plurality of semiconductor fins 301 and the second groove 303, the surface of the isolation layer 307 being lower than the top surface of the semiconductor fins 301; and a plurality of gate structures S1 spanning the semiconductor fins 301.

[0092] The semiconductor structure provided in this embodiment of the invention includes a plurality of semiconductor fins 301 located on a substrate 300, and a first cavity located between the semiconductor fins 301 along a first direction Y; and a second cavity located between the semiconductor fins along a second direction. The first cavity 305 and the second cavity 306 are filled with air. Air has a low dielectric constant, so the arrangement of the air cavity can better reduce the coupling capacitance between the semiconductor transistor film layers and improve the performance of the semiconductor transistor.

[0093] Substrate 300; the substrate 300 is used to provide a process platform for the formation of semiconductor structures.

[0094] In this embodiment, the substrate 300 is a silicon substrate, and the material of the substrate 300 is single-crystal silicon. In other embodiments, the material of the substrate 300 may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium dihydrogen nitride. The substrate 300 may also be other types of substrates such as silicon-on-insulator or germanium-on-insulator. In other embodiments, an epitaxial layer (not shown) with the same crystal structure as the substrate 300 is formed on the surface of the substrate 300 to improve the pattern transfer quality.

[0095] Multiple semiconductor fins 301 are located on a substrate 300 and extend along a first direction Y; the semiconductor fins 301 are used to form semiconductor transistor channels.

[0096] A first groove 302 is located between a plurality of semiconductor fins 301 along a first direction Y; a second groove 303 extends along the first direction Y and is located between the semiconductor fins 301 and the first groove 302 along a second direction X, wherein the first direction Y is perpendicular to the second direction X; the first groove 302 is used to form a first cavity 305; the second groove 303 is used to form a second cavity 306.

[0097] It should be noted that the first groove 302 and the second groove 303 are both trapezoidal in cross section in the second direction X, which is narrower at the top and wider at the bottom, and their width and height in the second direction X are the same or similar.

[0098] A clamping layer 304 covers the top of the first groove 302 and the second groove 303. The clamping layer 304 is used to form a first cavity 305 with the first groove and to form a second cavity 306 with the second groove.

[0099] It should be noted that the first cavity 305 and the second cavity 306 are both trapezoidal in cross section in the second direction X, which is narrower at the top and wider at the bottom, and their width and height in the second direction X are the same or similar.

[0100] In this embodiment, the material of the clamping layer 304 is one or more of silicon nitride, silicon carbide, silicon carbide, silicon oxycarbide, silicon carbide, and silicon boronitride. As an example, the material of the clamping layer is silicon nitride.

[0101] An isolation layer 307 is located between multiple semiconductor fins 301 and a second groove 303. The surface of the isolation layer 307 is lower than the top surface of the semiconductor fins 301. The isolation layer 307 is used for electrical isolation between multiple fins and can also prevent external impurities from entering the semiconductor structure through the bottom of the substrate 300 and causing semiconductor transistor failure.

[0102] In this embodiment, the material forming the insulating layer 307 is silicon oxide, which has excellent chemical stability and strong insulating ability. In other embodiments, the material of the insulating layer 307 can also be other insulating materials, such as silicon nitride, silicon oxynitride, etc.

[0103] In this embodiment, multiple gate structures S1 span the semiconductor fin 301; the gate structure is a dummy gate; the dummy gate is used to pre-occupy the space for the subsequent formation of the gate structure layer, and at the same time can protect the semiconductor transistor channel region at the gate structure layer.

[0104] In this embodiment, the material of the dummy gate can be polycrystalline silicon or amorphous silicon.

[0105] In this embodiment, the semiconductor structure further includes a plurality of gate structures spanning the first cavity 305 and the second cavity 306. Forming the gate structures at the first cavity 305 and the second cavity 306 can further improve the uniformity of the gate structure linewidth or line spacing distribution on the substrate 300.

[0106] In this embodiment, the semiconductor structure further includes a liner layer 308, which is formed on the sidewalls and bottom of the first groove 302 and the second groove 303. The liner layer 308 has good interfacial contact characteristics with the clamping layer 304, the sidewalls and bottom of the first groove 302 and the second groove 303, providing a good sealing effect for the formed first cavity 305 and second cavity 306.

[0107] In this embodiment, the lining layer 308 material includes one or more of silicon nitride, silicon carbide, silicon carbide, silicon oxycarbide, silicon carbide, and silicon boronitride. As an example, the lining layer 308 material is silicon nitride.

[0108] It should be noted that if the lining layer 308 is too thick, it will compress the internal space of the first cavity 305 and the second cavity 306, affecting the effect of reducing the coupling capacitance; if the lining layer 308 is too thin, it is easy to form defects such as pinholes, which will affect the sealing effect of the first cavity 305 and the second cavity 306, and also reduce the isolation effect; in this embodiment, the thickness of the lining layer 308 is in the range of 100 angstroms to 300 angstroms.

[0109] In this embodiment, the semiconductor structure further includes a gate dielectric layer 309; the gate dielectric layer 309 covers the surfaces of the semiconductor fin 301, the first cavity 305, and the second cavity 306; a source / drain doped layer (not shown), a sidewall layer (not shown) located between the source / drain doped layer and the gate structure, etc.

[0110] In summary, the semiconductor structure provided by the embodiments of the present invention includes a plurality of fins located on a substrate; the plurality of fins include: semiconductor fins, a first cavity located between semiconductor fins along a first direction, and a second cavity located between semiconductor fins along a second direction; the first cavity and the second cavity are filled with air, and air has a low dielectric constant, so the arrangement of the air cavity can better reduce the coupling capacitance between semiconductor transistor film layers and improve the performance of semiconductor transistors.

[0111] It should be noted that the semiconductor structure of this embodiment can be formed using the formation method of the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure of this embodiment, please refer to the corresponding descriptions in the foregoing formation method embodiments, which will not be repeated here.

[0112] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide a base; A medium fin groove extending along a first direction is formed on the substrate, the first direction being the extension direction of the fin; A partition groove is formed that extends along a second direction and traverses the medium fin groove, wherein the second direction is perpendicular to the first direction; Sacrificial material is filled into the medium fin groove and the partition groove to form a first sacrificial layer in the medium fin groove and a second sacrificial layer in the partition groove; The process involves graphical processing to obtain multiple fins, including: a sacrificial fin obtained by graphically patterning a first sacrificial layer, a semiconductor fin obtained by graphically patterning a substrate, and a sacrificial isolation structure obtained by graphically patterning a second sacrificial layer between the semiconductor fins. Forming an isolation layer between multiple fins; Remove the sacrificial fins and sacrificial partition structures to form a first groove located between semiconductor fins along a first direction and a second groove located between semiconductor fins along a second direction; A clamping layer is formed covering the top of the first groove and the second groove, the clamping layer forming a first cavity with the first groove and a second cavity with the second groove; A gate structure is formed that spans the semiconductor fins.

2. The forming method as described in claim 1, characterized in that, The steps involved in forming a fault include: A pinch-off material layer is formed on the first groove and the second groove, and the pinch-off material layer covers the top of the first groove and the second groove; Remove a portion of the thickness of the clamping material layer to expose the top surface of the fins and the insulating layer.

3. The forming method as described in claim 2, characterized in that, The sandwich material layer is formed using a chemical vapor deposition process.

4. The forming method as described in claim 2, characterized in that, The sandwich layer material includes one or more of silicon nitride, silicon carbide, silicon carbide, silicon oxycarbide, silicon carbide, and silicon boroide.

5. The forming method as described in claim 1, characterized in that, The forming method further includes: after forming the sandwich layer and before forming the gate structure, thinning the isolation layer between the fins.

6. The forming method as described in claim 1, characterized in that, The sacrificial material includes one or more of silicon germanium, germanium, silicon carbide, cobalt silicide, nickel silicide, gallium arsenide, indium phosphide, indium gallium arsenide, and indium arsenide.

7. The forming method as described in claim 1, characterized in that, The forming method further includes, before forming the sandwich layer, forming a lining layer covering the sidewalls and bottom of the first and second grooves.

8. The forming method as described in claim 7, characterized in that, The lining layer is formed using an atomic layer deposition process.

9. The forming method as described in claim 7, characterized in that, The thickness of the lining layer is in the range of 100 angstroms to 300 angstroms.

10. The forming method as described in claim 7, characterized in that, The lining material includes one or more of silicon nitride, silicon carbide, silicon carbide, silicon oxycarbide, silicon carbide, and silicon boroide.

11. The forming method as described in claim 1, characterized in that, The medium fin groove and the partition groove are formed in the same step.

12. The forming method as described in claim 1, characterized in that, The step of forming the gate structure includes: further forming a plurality of gate structures spanning the first cavity and the second cavity.

13. A semiconductor structure, characterized in that, include: Base; Multiple semiconductor fins are located on the substrate and extend along a first direction; The first groove is located between multiple semiconductor fins along a first direction; The second groove extends along the first direction and is located between the semiconductor fin and the first groove along the second direction, the second direction being perpendicular to the first direction; A clamping layer covers the top of the first groove and the second groove, the clamping layer being used to form a first cavity with the first groove and also to form a second cavity with the second groove; An isolation layer is located between multiple semiconductor fins and a second groove, the surface of the isolation layer being lower than the top surface of the semiconductor fins; Multiple gate structures span the semiconductor fin.

14. The semiconductor structure as described in claim 13, characterized in that, Also includes: A lining layer is formed on the sidewalls and bottom of the first and second grooves.

15. The semiconductor structure as described in claim 14, characterized in that, The thickness of the lining layer is in the range of 100 angstroms to 300 angstroms.

16. The semiconductor structure as described in claim 14, characterized in that, The lining material includes one or more of silicon nitride, silicon carbide, silicon carbide, silicon oxycarbide, silicon carbide, and silicon boroide.

17. The semiconductor structure as claimed in claim 13, characterized in that, The material of the sandwich layer includes one or more of silicon nitride, silicon carbide, silicon carbide, silicon oxycarbide, silicon carbide, and silicon boroide.

18. The semiconductor structure as described in claim 13, characterized in that, Also includes: Multiple gate structures spanning the first cavity and the second cavity.

19. The semiconductor structure as described in claim 13 or 18, characterized in that, The gate structure is a pseudo-gate.

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