Semiconductor structure and method of fabricating the same

Abstract

The embodiments of the present disclosure disclose a semiconductor structure and a manufacturing method thereof. The manufacturing method comprises: forming a gate structure covering a fin; the fin extends along a first direction and penetrates through the gate structure; the gate structure extends along a second direction, and the second direction intersects with the first direction; forming a first active region in the fin between adjacent gate structures; forming a first contact structure on the first active region, and the first contact structure is coupled with the first active region; forming a second contact structure on the gate structure, and the second contact structure is coupled with the gate structure; and the first contact structure is coplanar with a surface of the second contact structure away from the gate structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and its fabrication method. Background Technology

[0002] In some semiconductor structure or integrated circuit fabrication processes, the fabrication of conductive structures may be included, such as connection structures, contact structures, conductive plugs, or interconnects. For some transistor structures, conductive structures can be placed on the source, drain, and gate of the transistor to supply or lead power to the transistor. Multiple transistors can be connected to form various digital circuits or logic circuits, such as, but not limited to, various logic gate circuits, switching circuits, or voltage generation circuits. As transistor size shrinks and transistor integration density continues to increase, there is still much room for improvement in the fabrication methods and structures of transistors and their connected conductive structures. Summary of the Invention

[0003] According to some aspects of embodiments of this disclosure, a method for fabricating a semiconductor structure is provided, comprising: forming a gate structure covering fins; the fins extending along a first direction and penetrating the gate structure; the gate structure extending along a second direction intersecting the first direction; forming a first active region in the fins between adjacent gate structures; forming a first contact structure on the first active region, the first contact structure being coupled to the first active region; forming a second contact structure on the gate structure, the second contact structure being coupled to the gate structure; the surface of the first contact structure away from the first active region being coplanar with the surface of the second contact structure away from the gate structure.

[0004] In some embodiments, a method of forming the first contact structure and the second contact structure includes: forming a first dielectric layer covering the gate structure and the fin; forming a first opening and a second opening penetrating the first dielectric layer; exposing the first active region at the bottom of the first opening and exposing the gate structure at the bottom of the second opening; forming the first contact structure in the first opening and forming the second contact structure in the second opening.

[0005] In some embodiments, the method for the second opening includes: filling the first opening with a dielectric material to form a sacrificial layer; the sacrificial layer covering the first dielectric layer; forming a third opening through the sacrificial layer and exposing the first dielectric layer; forming a second dielectric layer on the sidewall of the third opening; etching the bottom of the third opening to form a second opening through the first dielectric layer; removing the second dielectric layer; and removing the sacrificial layer.

[0006] In some embodiments, the fabrication method further includes forming a third dielectric layer on the sidewall of the first opening and on the sidewall of the second opening.

[0007] In some embodiments, the manufacturing method further includes: forming a first connection layer in the first opening, the first connection layer being connected to the first active region; and forming the first contact structure on the first connection layer.

[0008] In some embodiments, the first connection layer includes a first sublayer and a second sublayer stacked on the first active region; the method of forming the first connection layer includes: forming the first sublayer at the bottom of the first opening, and forming a second sublayer covering the first sublayer and the sidewall of the first opening in the first opening.

[0009] In some embodiments, the fabrication method further includes: forming a fourth dielectric layer on a contact structure, the contact structure including at least one of the first contact structure and the second contact structure; forming a fourth opening through the fourth dielectric layer; exposing the contact structure at the bottom of the fourth opening; etching the contact structure exposed at the bottom of the fourth opening to form a groove; the sidewalls of the groove being provided by the contact structure and the fourth dielectric layer, the size of the groove in the first direction being larger than the size of the fourth opening in the first direction; and filling the groove and the fourth opening with a conductive material to form a connection structure.

[0010] According to some aspects of embodiments of this disclosure, a semiconductor structure is provided, comprising: a fin extending along a first direction; a gate structure extending along a second direction intersecting the first direction; the gate structure covering a portion of the fin; the fin penetrating the gate structure along the first direction; a portion of the fin located between adjacent gate structures; a first active region at least partially embedded in the fin; the first active region located between and exposed between two adjacent gate structures; a first contact structure located on and coupled to the first active region; a second contact structure located on and coupled to the gate structure; the surface of the first contact structure away from the first active region being coplanar with the surface of the second contact structure away from the gate structure.

[0011] In some embodiments, the semiconductor structure further includes: a first interconnect layer, at least partially located between the first contact structure and the first active region; at least partially surrounding the sidewall of the first contact structure.

[0012] In some embodiments, the semiconductor structure further includes: a connection structure, the connection structure including: a first connection structure coupled to the first contact structure, and a second connection structure coupled to the second contact structure; the connection structure includes a first portion and a second portion disposed in a third direction, the first portion being located between the second portion and the fin; the dimension of the first portion in the first direction is greater than the dimension of the second portion in the first direction.

[0013] This disclosure provides a method for fabricating a semiconductor structure, including: forming a gate structure that covers a semiconductor, wherein the semiconductor structure penetrates the gate structure along a first direction; forming a first active region in a fin exposed between adjacent gate structures; forming a first contact structure coupled to the first active region; and forming a second contact structure coupled to the gate structure; wherein the first contact structure and the second contact structure can be formed in the same process step, such that the surface of the first contact structure away from the first active region and the surface of the second contact structure away from the gate structure are coplanar, which facilitates the fabrication of connection structures on the first contact structure and the second contact structure, and facilitates process integration and expands the fabrication process window. Attached Figure Description

[0014] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0015] Figures 3 to 5 This is a schematic diagram illustrating the fabrication of a semiconductor structure according to an exemplary embodiment;

[0016] Figure 6 This is a schematic diagram of the semiconductor structure fabrication process according to an embodiment of the present disclosure;

[0017] Figures 7 to 19 This is a schematic diagram illustrating the fabrication of a semiconductor structure according to an embodiment of this disclosure. Detailed Implementation

[0018] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0019] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers.

[0020] It should be understood that the phrases "some embodiments" or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "some embodiments" or "an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0021] In the fabrication processes of some semiconductor structures, corresponding conductive structures are set up for coupling the power supply and electrical signal output of devices such as transistors, memory, and capacitors. These structures include contact structures, connection structures, conductive plugs, or interconnects. For example, in some transistor structures, conductive structures can be set up to couple with the gate, source, or drain of the transistor. The conductive structures can include multiple stacked structures, such as contact structures coupled to the source or drain of the transistor, and connection structures coupled to the contact structures. Multiple interconnect layers can also be set up, with connection structures coupled to the interconnect layers, allowing the electrical signals of multiple transistors to be connected to the interconnect layers to form logic circuits or digital circuits with different functions. The transistors mentioned in the embodiments of this disclosure may include, but are not limited to, three-dimensional transistors, multi-channel field-effect transistors, vertical transistors, planar transistors, or other types of transistors; this disclosure does not limit the type of transistor.

[0022] In some embodiments, refer to Figure 1The semiconductor example shown can be categorized as follows: the x-direction can be a first direction, the y-direction can be a second direction, and the z-direction can be a third direction. The semiconductor structure 10 can include a transistor, which can include at least a fin 110 and a gate structure 120 covering the fin 110. The semiconductor structure 10 can include a fin 110 extending along the x-direction. The fin 110 can be a strip, ridge, fin, or protrusion structure protruding from a substrate, a semiconductor layer (such as an insulating layer), or other material layer. The cross-sectional shape of the fin 110 in the yoz plane can include, but is not limited to: rectangles, triangles, or other regular or irregular polygons; and including circles, ellipses, or other regular or irregular arc shapes. Different regions of the fin 110 can be doped to form the source, drain, and channel of the transistor.

[0023] In some embodiments, refer to Figure 1 As shown, a gate structure 120 extends along the y-direction, covering a portion of the fin 110. A gate dielectric layer is disposed between the gate structure 120 and the fin 110. The gate structure 120 can be a single-film structure or a multi-film structure. The portion of the fin 110 covered by the gate structure 120 serves as the channel region of the transistor. The portion of the fin 110 exposed after penetrating the gate structure 120 along the x-direction, or located between two adjacent gate structures 120 in the x-direction, serves as the source and drain of the transistor. The positions of the source and drain can be interchanged. The gate structure 120 serves as the control gate of the transistor. An isolation structure 130 is formed on the sidewall of the gate structure 120 extending along the z-direction. The isolation structure 130 can be a sidewall structure, used to define the position of the gate structure 120, support and isolate the gate structure 120 to reduce leakage current.

[0024] For example, fin 110 may include semiconductor materials, such as, but not limited to, silicon, germanium, or silicon carbide; gate structure 120 may include, but is not limited to, polycrystalline silicon, conductive materials such as tungsten, cobalt, gold, silver, platinum, copper, aluminum, chromium, titanium, nickel, or ruthenium; gate structure 120 may include a single film layer or multiple film layer structures, such as a core, the core may include tungsten to improve conductivity and resist etching damage; and a connecting layer covering the sidewalls of the core, such as titanium nitride, to reduce the diffusion of conductive materials to other areas. Isolation structure 130 may include, but is not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, and isolation structure 130 may include a single film layer or multiple film layer structures.

[0025] In some embodiments, a plurality of spaced-apart gate structures 120 may be formed. Each gate structure 120 covers the protruding and exposed top surface and sidewalls of the fin 110. One end of the fin 110 extends into the gate structure 120 along the z-direction but is not exposed from the top of the gate structure 120. The fin 110 penetrates the bottom portion of the gate structure 120 along the x-direction. A portion of the fin 110 is exposed on both sides of the gate structure 120 or relative to the gate structure 120 between two adjacent gate structures 120. The fin 110 is isolated from the gate structure 120 by a gate dielectric layer. The gate dielectric layer may exist only at the location where the fin 110 is covered by the gate structure 120 and is not shown; or the gate dielectric layer may cover the top surface and sidewalls of the fin 110. For example, the cross-sectional shape of the fin 110 in the yoz plane may include, but is not limited to, a rectangle or approximately a rectangle. The top surface of the fin 110 and the two sidewalls in the y direction are covered by a gate dielectric layer, which is covered by a gate structure 120. The bottom surface of the fin 110 is not exposed and does not contact the gate structure 120. In other embodiments, the top surface, bottom surface, and sidewalls of the fin 110 are all surrounded by the gate structure 120 to form a multi-channel field-effect transistor.

[0026] In some embodiments, the gate structure 120 may be formed by replacing the dummy gate with a conductive material. For example... Figure 1 The isolation structure 130 can define the position of the pseudo gate, which is the position before the gate structure 120 is formed; after removing the pseudo gate, a trench is formed between the isolation structures 130, and the conductive material fills the trench to form the gate structure 120.

[0027] In some embodiments, the fin regions 110 exposed from both sides of the gate structure 120 or between two adjacent gate structures 120 can be doped to form the source and drain of a transistor. The doping process may include, but is not limited to, ion implantation or diffusion. Alternatively, the region of the fin 110 between two adjacent gate structures 120 can be etched to form a groove, the groove not penetrating the entire thickness of the fin 110 in the z-direction; semiconductor material can then be deposited in the groove using epitaxial deposition or other deposition processes to form the source or drain, the source or drain covering the fin 110 and exposed relative to the fin 110 in the z-direction. During epitaxial deposition, a doping gas can be introduced into the process gas, and doping can be completed simultaneously during epitaxial deposition to improve the uniformity of dopant element dispersion; alternatively, ion implantation can be performed on the source and drain after epitaxial deposition to increase the doping concentration.

[0028] In some embodiments, it may be possible Figure 1A connection structure is formed on the gate structure 120 to supply power to the gate structure 120, or a connection structure is formed on the exposed fins 110 between the gate structures 120 to supply power or lead to the source or drain; the connection structure can be set at different positions on different fins 110 according to the circuit design. In some specific embodiments, a cross-sectional view of the xoy plane of some semiconductor pillars is shown. Figure 2 For illustrative purposes only, the area of ​​the fin 110 exposed between adjacent gate structures 120 is designated as the first active region 111, serving as either the source or drain. The first connection structure 151 coupled to the first active region 111 and the second connection structure 152 coupled to the gate structure 120 may be staggered, either misaligned or aligned in the x-direction. The coupling may be a direct contact electrical connection or an electrical connection through other contact structures.

[0029] In some embodiments, a method for fabricating a semiconductor structure 10 is provided. Figure 3 The fin portion 110 and the gate structure 120 shown correspond to Figure 1 The AA' section portion, such as Figure 3 A first dielectric layer 131 is formed on the fin 110 and the gate structure 120. The first dielectric layer 131 can be a single film or multiple sub-dielectric layers stacked in the z-direction. The first dielectric layer 131 may also include nested or embedded sub-dielectric layers. The first dielectric layer 131 may be part of the front-end fabrication structure of the semiconductor structure 10. When film layers of the same or similar constituent materials in the first dielectric layer 131 are in contact, they do not have physical boundaries. A first contact structure 141 is formed that penetrates the first dielectric layer 131 and is coupled to the first active region 111 in the semiconductor structure 10. The first active region 111 may be exposed relative to the fin 110 between adjacent gate structures 120. Two first contact structures 141 are only examples.

[0030] In some embodiments, refer to Figure 4 As shown, a first connection structure 151 penetrating the dielectric material is formed on the first contact structure 141, and the first connection structure 151 is coupled to the first contact structure 141. (Refer to...) Figure 5As shown, a second connection structure 152 is formed on the gate structure 120, penetrating the dielectric material and penetrating the first dielectric layer 131. The second connection structure 152 is coupled to the gate structure 120. The top ends of the first connection structure 151 and the second connection structure 152 can be chemically and mechanically planarized, making the top ends of the first connection structure 151 and the second connection structure 152 coplanar. Interconnect layers are formed on the first connection structure 151 and the second connection structure 152 for coupling. The interconnect layers may include multiple stacked wiring layers, and adjacent wiring layers can be coupled to interconnect electrical signals through conductive plugs, conductive channels, or conductive vias. In some embodiments, the first connection structure 151 may be formed by selective deposition, depositing the first connection structure 151 from bottom to top to reduce voids within the first connection structure 151, such as selectively depositing tungsten on the contact structure. For example, due to the load effect of the etched opening, the size of the opening end of the opening forming the second connection structure 152 is greater than or equal to the size of the bottom of the opening, and the size of the end of the second connection structure 152 away from the gate structure 120 is greater than or equal to the size of the contact end with the gate structure 120. This part of the size is the size along the x-direction, which can be the diameter and width. The first connection structure 151 may have a similar morphology to the second connection structure 152, and will not be described in detail.

[0031] In some embodiments, the contact structure and connection structure may include, but are not limited to, conductive materials such as tungsten, cobalt, gold, silver, platinum, copper, aluminum, chromium, titanium, nickel, ruthenium, metal silicide, or metal nitride. In some embodiments, a connection layer may be formed between the first contact structure 141 and the first active region 111. The connection layer may be titanium silicide or tungsten silicide to reduce the contact resistance between the first contact structure 141 and the first active region 111. Alternatively, a connection layer, such as titanium nitride or tungsten nitride, may be formed between the first contact structure 141 and the first dielectric layer 131 to improve the adhesion between the first contact structure 141 and the first dielectric layer 131, reduce gaps, and reduce the diffusion of conductive material into the first dielectric layer 131, thereby improving the manufacturing yield. Alternatively, a connection layer, including titanium nitride, may be formed between the sidewall of the connection structure and the dielectric material. It is understood that, corresponding to different regions of different semiconductor structures 10, in the xoz planar cross-sectional schematic diagram of different regions of the semiconductor structure 10, the following diagrams may be used: Figure 5 Multiple first connection structures 151 and second connection structures 152 may exist simultaneously; or only first connection structures 151 or only second connection structures 152 may exist. In other embodiments, [the following may be specified]. Figure 3 On the semiconductor structure 10 shown, a dielectric material that penetrates at least through the first dielectric layer 131 and a second connection structure 152 that penetrates the first dielectric layer 131 and is connected to the gate structure 120 are first formed, and then a first connection structure 151 that is coupled to the first contact structure 141 is formed.

[0032] In some specific embodiments, such as Figure 4 and Figure 5 As exemplified, because the first connection structure 151 and the second connection structure 152 have different height dimensions in the z-direction, the etching amounts in the fabrication process are different. To reduce over-etching damage, the first connection structure 151 and the second connection structure 152 can be formed sequentially. However, because the landing layers of the first connection structure 151 and the second connection structure 152 are different, or the contact materials are different, selective deposition processes cannot be used simultaneously. For example, the first connection structure 151 lands on the first contact structure 141, and the second connection structure 152 lands on the gate structure 120. The materials of the first contact structure 141 and the gate structure 120 are different. To adapt to the material of the first contact structure 141, the first connection structure 151 is formed on the first contact structure 141 using a selective deposition process. It is not possible to use the same selective deposition process to form the second connection structure 152 on the gate structure 120, which is made of different materials. Alternatively, the formed second connection structure 152 may have more voids and defects, leading to increased resistance or even contact failure with the gate structure 120. In view of the above, some aspects of the present disclosure provide a method for fabricating a semiconductor structure 10, in which a second contact structure 142 is formed between the second connection structure 152 and the gate structure 120, and the first connection structure 151 and the second connection structure 152 are subsequently fabricated simultaneously. This method reduces the contact resistance of the connection structure, reduces process steps and process integration, improves the manufacturing yield and reduces the manufacturing cost.

[0033] According to some aspects of embodiments of this disclosure, Figure 6 A method for fabricating a semiconductor structure 10 is provided, comprising:

[0034] A grid structure is formed to cover the fin; the fin extends along a first direction and penetrates the grid structure; the grid structure extends along a second direction, which intersects with the first direction;

[0035] A first active region is formed in the fin between adjacent gate structures;

[0036] A first contact structure is formed on the first active region and coupled to the first active region; a second contact structure is formed on the gate structure and coupled to the gate structure; the surface of the first contact structure away from the first active region is coplanar with the surface of the second contact structure away from the gate structure.

[0037] The relative positions of the fin 110 and the gate structure 120 in this embodiment of the present disclosure are as described above. Figure 1 Partial description, such as Figures 7 to 19 The fin 110 and the gate structure 120 shown correspond to Figure 1A schematic cross-section at AA' is shown; the fin 110 extends along the x-direction and penetrates the gate structure 120. The gate structure 120 covers a portion of the fin 110. A first active region 111 is formed in the region of the fin 110 exposed relative to the gate structure 120 along the x-direction, or in the region of the fin 110 located between adjacent gate structures 120. The surface of the first active region 111 is exposed relative to the fin 110 in the z-direction. The first active region 111 serves as the source or drain of the transistor, and the portion of the fin 110 covered by the gate structure 120 serves as the channel region. The doping type of the first active region 111 and the channel region can be opposite. A gate dielectric layer isolates the fin 110 from the gate structure 120. The gate dielectric layer may exist only in the position where the fin 110 is covered by the gate structure 120, and the gate dielectric layer is covered by the gate structure 120 and is not shown; or the gate dielectric layer may cover the top surface and sidewalls of the fin 110, and a portion of the gate dielectric layer is covered by the gate structure 120.

[0038] The first contact structure 141 and the second contact structure 142 may be formed in the same manufacturing step or sequentially, as exemplified only. Figure 14 It shows in Figure 13 The example opening is simultaneously filled with conductive material to form both the first contact structure 141 and the second contact structure 142, which can reduce manufacturing costs. The first contact structure 141 and the second contact structure 142 can be planarized by chemical mechanical polishing, such as being coplanar along a plane parallel to the xoy plane, or coplanar along a plane not parallel to the xoy plane. Exemplarily, the manufacturing process of the contact structure may include, but is not limited to, deposition processes and electroplating processes. The deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The first contact structure 141 and the second contact structure 142 can be made of the same material. Subsequently, the same selective deposition process can be performed on the first contact structure 141 and the second contact structure 142 to form a connection structure, reducing void defects in the connection structure and reducing the contact resistance of the connection structure.

[0039] In some embodiments, Figures 7 to 11 This illustrates a specific example of a method for fabricating a first dielectric layer 131 and a first opening 11 and a second opening 12 penetrating the first dielectric layer 131, or it can be directly formed. Figure 13The first opening 11 and the second opening 12 shown penetrate the first dielectric layer 131. The first opening 11 is filled with conductive material to form a first contact structure 141, and the second opening 12 is filled with conductive material to form a second contact structure 142. The first dielectric layer 131 may include a single film layer or multiple stacked film layers, such as... Figure 7 The first film layer 1311 and the second film layer 1312 are stacked sequentially on the fin 110. The first film layer 1311 may include, but is not limited to, silicon nitride and silicon oxynitride, and the second film layer 1312 may include, but is not limited to, silicon oxide. The first film layer 1311 covers the top and sidewalls of the gate structure 120. The first film layer 1311 can provide greater etch resistance, reduce over-etching of the etchant in the x-direction, and protect the sidewalls of the gate structure 120.

[0040] In some embodiments, the method of forming the first contact structure 141 and the second contact structure 142 includes: referring to Figures 11 to 13 As shown, a first dielectric layer 131 is formed to cover the gate structure 120 and the fin 110; a first opening 11 and a second opening 12 are formed to penetrate the first dielectric layer 131; the bottom of the first opening 11 exposes the first active region 111, and the bottom of the second opening 12 exposes the gate structure 120.

[0041] Reference Figure 14 As shown, a first contact structure 141 is formed in the first opening 11, and a second contact structure 142 is formed in the second opening 12.

[0042] The first contact structure 141 and the second contact structure 142 can be formed simultaneously to reduce manufacturing costs. The first opening 11 and the second opening 12 can be manufactured simultaneously or separately. A material layer can be formed simultaneously on the sidewall of the first opening 11 or the sidewall of the second opening 12 to reduce the inner diameter of the opening; or the first opening 11 or the second opening 12 can be formed sequentially, and a material layer can be formed on the sidewall of the opening respectively to reduce the inner diameter of the opening respectively. Figure 12 As shown, a third dielectric layer 133 is formed on the inner wall of the first opening 11 and the inner wall of the second opening 12; as Figure 13 As shown, the third dielectric layer 133 at the bottom of the first opening 11 and the bottom of the second opening 12 is removed, while the third dielectric layer 133 on the sidewalls of the first opening 11 and the second opening 12 is retained; reducing the inner diameter of the first opening 11 and the second opening 12 in the x direction can reduce the use of high-resolution photolithography. Figure 14 In the middle, a first contact structure 141 is formed in the first opening 11 of the sidewall including the third dielectric layer 133, and a second contact structure 142 is formed in the second opening 12 of the sidewall including the third dielectric layer 133.

[0043] In some embodiments, a first opening 11 and a second opening 12 may be formed sequentially; such as Figure 7 As shown, a first dielectric layer 131 is formed on the fin 110 and the gate structure 120, and a first opening 11 is formed through the first dielectric layer 131 and exposes the first active region 111; the first opening 11 is filled with a sacrificial material, and the first dielectric layer 131 is etched to form a second opening 12 that exposes the gate structure 120.

[0044] In some embodiments, the method for the second opening 12 includes: referring to Figure 8 As shown, filled with dielectric material Figure 7 A first opening 11 forms a sacrificial layer 136; the sacrificial layer 136 covers the first dielectric layer 131; a third opening 13 is formed, penetrating the sacrificial layer 136 and exposing the first dielectric layer 131; the bottom of the third opening 13 exposes the area of ​​the aligned gate structure 120; (refer to...) Figure 9 As shown, a second dielectric layer 132 is formed on the sidewall of the third opening 13; refer to Figure 10 As shown, the bottom of the third opening 13 is etched to form a second opening 12 penetrating the first dielectric layer 131; the second opening 12 is formed at the bottom of the third opening 13 and communicates with the third opening 13; see reference. Figure 11 As shown, the second dielectric layer 132 and the sacrificial layer 136 are removed; the removal of the sacrificial layer 136 releases the space for the first opening 11. The second dielectric layer 132 and the sacrificial layer 136 can be removed by dry etching, wet etching, or a combination thereof.

[0045] In some embodiments, refer to Figure 8 As shown, after forming the sacrificial layer 136, a patterned mask layer can be formed on the sacrificial layer 136, and the patterned mask layer is used as an etching mask to etch the sacrificial layer 136 to form the third opening 13. Figure 9 In this process, the second dielectric layer 132 formed can cover the sidewalls and bottom of the third opening 13; Figure 10 When etching the bottom of the third opening 13, the second dielectric layer 132 and the first dielectric layer 131 at the bottom of the third opening 13 are removed to form the second opening 12. Figure 10 When the second opening 12 is formed, the mask layer and the second dielectric layer 132 located on top of the sacrificial layer 136 can be etched away.

[0046] In some embodiments, the manufacturing method further includes: referring to Figure 12 As shown, a third dielectric layer 133 is formed on the sidewalls and bottom of the first opening 11, and on the sidewalls and bottom of the second opening 12; Refer to Figure 13As shown, the third dielectric layer 133 at the bottom of the first opening 11 and the bottom of the second opening 12 is removed by etching; the third dielectric layer 133 is formed on the sidewalls of the first opening 11 and the second opening 12. This reduces the size of the first opening 11 and the second opening 12 in the x-direction; as shown... Figure 14 As shown, the first opening 11 and the second opening 12 are filled with conductive material to form a first contact structure 141 coupled to the first active region 111 and a second contact structure 142 coupled to the gate structure 120.

[0047] For example, the constituent materials of the second dielectric layer 132 and the third dielectric layer 133 may include, but are not limited to, insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride; for example, the second dielectric layer 132 may include silicon oxide, and the third dielectric layer 133 may include silicon nitride to reduce etching damage to the second dielectric layer 132. The third dielectric layer 133 may have the same material as the first film layer 1311 of the first dielectric layer 131, which may both be silicon nitride, and there may be no physical boundary between the third dielectric layer 133 and the first film layer 1311.

[0048] In some embodiments, the manufacturing method further includes: referring to Figure 14 As shown, a first connection layer 161 is formed in the first opening 11, and the first connection layer 161 is connected to the first active region 111; a first contact structure 141 is formed on the first connection layer 161.

[0049] Figure 14 The first connecting layer 161 shown can be a single film layer, located on the bottom and sidewalls of the first opening 11. The first connecting layer 161 increases the adhesion between the first contact structure 141 and the first dielectric layer 131, or to the third dielectric layer 133, reduces film layer voids, reduces contact resistance, and also reduces the diffusion of conductive material into the dielectric material. For example, the first connecting layer 161 may include a metal nitride, such as titanium nitride or tungsten nitride, and may surround the sidewalls and bottom of the first contact structure 141. Alternatively, the first connecting layer 161 may be located between the second contact structure 142 and the gate structure 120, surrounding the sidewalls and bottom of the second contact structure 142. The first connecting layer 161 may also include a metal silicide, such as titanium silicide or other silicides, which can reduce the potential barrier between the first contact structure 141 and the first active region 111, thus reducing contact resistance.

[0050] In some embodiments, refer to Figure 15As shown, the first connection layer 161 includes a first sublayer 1611 and a second sublayer 1612 stacked on the first active region 111; the method of forming the first connection layer 161 includes: forming the first sublayer 1611 at the bottom of the first opening 11, and forming a second sublayer 1612 covering the first sublayer 1611 and the sidewall of the first opening 11 in the first opening 11. Figure 15 As shown, the first sublayer 1611 may include metal silicide and is located between the first connection structure 151 and the first active region 111. The second sublayer 1612 may be formed on the sidewall of the first opening 11 and / or cover the first sublayer 1611. The second sublayer 1612 may contain metal nitride and may also be formed on the sidewall of the second opening 12 and / or at the bottom of the second opening 12.

[0051] In some specific embodiments, it is possible to... Figure 13 A metal film is deposited in the first opening 11, which may be a discontinuous film. After heat treatment, the metal film on the first active region 111 reacts with the silicon in the first active region 111 to form a metal silicide, such as a first sublayer 1611 comprising titanium silicide. A portion of the first sublayer 1611 may extend into the first active region 111. The gate structure 120 in the second opening 12 does not react with the titanium and therefore does not form the first sublayer 1611. The first sublayer 1611 can be removed by etching and cleaning. Residual metal film layers in the first opening 11 and the second opening 12; a second sublayer 1612 is deposited in both the first opening 11 having the first sublayer 1611 and the second opening 12 not having the first sublayer 1611, the second sublayer 1612 may include titanium nitride to increase adhesion to the first sublayer 1611; the second sublayer 1612 at the bottom of the first opening 11 and the bottom of the second opening 12 may be removed, leaving only the second sublayer 1612 on the sidewalls of the openings, or it may not be removed. Figure 15 A first contact structure 141 is formed in the first opening 11, and a second contact structure 142 is formed in the second opening 12. The surfaces of the first contact structure 141 and the second contact structure 142 away from the fin 110 are chemically and mechanically polished to flatten them, so that the surface of the first contact structure 141 away from the first active region 111 is coplanar with the surface of the second contact structure 142 away from the gate structure 120.

[0052] In some embodiments, the manufacturing method further includes: referring to Figure 16 As shown, in Figure 14A fourth dielectric layer 134 is formed on the contact structure 140 shown. The contact structure 140 includes at least one of a first contact structure 141 and a second contact structure 142. A fourth opening 14 is formed through the fourth dielectric layer 134. The bottom of the fourth opening 14 exposes the contact structure 140. The fourth dielectric layer 134 may include a single film layer or multiple stacked film layers, including but not limited to stacked silicon nitride layers and silicon oxide layers. (Refer to...) Figure 17 As shown, the contact structure 140 exposed at the bottom of the fourth opening 14 is etched to form a groove 15; the sidewalls of the groove 15 are provided by the contact structure 140 and the fourth dielectric layer 134, and the dimension of the groove 15 in the x-direction is larger than the dimension of the fourth opening 14 in the x-direction; see reference. Figure 18 As shown, the groove 15 and the fourth opening 14 are filled with conductive material to form a connection structure 150.

[0053] Figure 17 In this process, at least a portion of the bottom of the fourth opening 14 and the second contact structure 142 of the fourth opening 14 can be etched to remove portions of the first contact structure 141 and the second contact structure 142. The first dielectric layer 131 at the bottom of the fourth opening 14 is then side-etched along the x-direction to form a groove 15 communicating with the fourth opening 14, or to form a bottom cavity communicating with the fourth opening 14. The shape of the groove 15 can be, but is not limited to, elliptical, arc-shaped, or bowl-shaped. The groove 15 has a portion protruding along the x-direction from the bottom of the fourth opening 14, extending into the first dielectric layer 131. The sidewalls of this portion are provided by the first dielectric layer 131 and the etched contact structure 140. (Refer to...) Figure 18 As shown, conductive material is selectively deposited in the groove 15 and the fourth opening 14 to form the connection structure 150. The conductive material can be deposited from bottom to top to form the connection structure 150. The conductive material is reduced or not deposited on the surface of the fourth dielectric layer 134 to reduce the voids in the connection structure 150 and reduce the resistance of the connection structure 150.

[0054] The connection structure 150 may include a first connection structure 151 coupled to the first contact structure 141, and a second connection structure 152 coupled to the second contact structure 142. The dimension in the x-direction of the portion of the first connection structure 151 that contacts the first contact structure 141 may be larger than the dimension of the portion of the first connection structure 151 that is away from the first contact structure 141. This can prevent the polishing slurry from flowing through the gap between the first connection structure 151 and the fourth dielectric layer 134 and causing corrosive damage to the first contact structure 141 during chemical mechanical polishing of the top of the first connection structure 151. The dimension in the x-direction of the portion of the second connection structure 152 that contacts the second contact structure 142 may be larger than the portion of the second connection structure 152 that is away from the second contact structure 142.

[0055] In some embodiments, refer to Figure 19 As shown, it can be filled with conductive material. Figure 16 The fourth opening 14 shown forms a connecting structure 150, and the end of the connecting structure 150 that contacts the contact structure 140 may not protrude from the other end of the connecting structure 150. Figure 16 Due to the etching load effect, the opening end of the fourth opening 14 may have a dimension in the x-direction that is greater than or equal to the dimension of the bottom. Figure 19 The dimension of the end of the connecting structure 150 away from the contact structure 140 is greater than or equal to the dimension of the other end of the connecting structure 150.

[0056] According to some aspects of embodiments of this disclosure, Figure 18 and Figure 19 A semiconductor structure 10 is provided, comprising: a fin 110 extending along the x-direction; a gate structure 120 extending along the y-direction intersecting the x-direction; the gate structure 120 covering a portion of the fin 110; the fin 110 penetrating the gate structure 120 along the x-direction; a portion of the fin 110 located between adjacent gate structures 120; a first active region 111, at least partially embedded in the fin 110; the first active region 111 located between two adjacent gate structures 120 and exposed between two adjacent gate structures 120; a first contact structure 141 located on and coupled to the first active region 111; a second contact structure 142 located on and coupled to the gate structure 120; the surface of the first contact structure 141 away from the first active region 111 and the surface of the second contact structure 142 away from the gate structure 120 are coplanar. In some embodiments, the semiconductor structure 10 further includes a gate dielectric layer located between the fin 110 and the gate structure 120, wherein at least a portion of the gate dielectric layer is covered by the gate structure 120.

[0057] Figure 18 and Figure 19 The fin 110 and the gate structure 120 shown can correspond to Figure 1 The positions of the fin 110, the gate structure 120, and the gate dielectric layer in the AA' section can be referenced. Figure 1 Some descriptions are omitted here.

[0058] In some embodiments, refer to Figure 18 and Figure 19 As shown, the semiconductor structure 10 further includes: a first interconnect layer 161, at least partially located between the first contact structure 141 and the first active region 111; at least a portion of the first interconnect layer 161 surrounds the sidewall of the first contact structure 141.

[0059] The first connecting layer 161 may be a single film layer. The first connecting layer 161 is used to increase the adhesion between the first contact structure 141 and the first dielectric layer 131, or to the third dielectric layer 133, reducing film layer voids and contact resistance. The first connecting layer 161 may include a metal nitride, such as titanium nitride or tungsten nitride, and may surround the sidewalls and bottom of the first contact structure 141. The first connecting layer 161 may also be located between the second contact structure 142 and the gate structure 120, surrounding the sidewalls and bottom of the second contact structure 142. The first connecting layer 161 may also include a metal silicide, such as titanium silicide or other silicides, and may reduce the potential barrier between the first contact structure 141 and the first active region 111, thus reducing contact resistance.

[0060] In some embodiments, the first connection layer 161 may include multiple film layers, all of which surround the sidewalls and bottom of the first contact structure 141 and the sidewalls and bottom of the second contact structure 142. Or as... Figure 15 As shown, the first connection layer 161 may include a first sublayer 1611 and a second sublayer 1612. The first sublayer 1611 is located between the first contact structure 141 and the first active region 111, and the second sublayer 1612 is located above the first sublayer 1611 and may surround the sidewall of the first contact structure 141. The first sublayer 1611 may include a metal silicide, such as titanium silicide, to reduce the contact resistance between the first contact structure 141 and the first active region 111. The second sublayer 1612 may include titanium nitride to reduce the diffusion of conductive material in the first contact structure 141 to the dielectric material, while increasing adhesion to the first sublayer 1611. The second contact structure 142 and the gate structure 120 may not have the first sublayer 1611, but only the second sublayer 1612. The second sublayer 1612 may only exist at the bottom of the first contact structure 141 to reduce resistance and increase integration density, or it may also surround the sidewall of the second contact structure 142.

[0061] In some embodiments, refer to Figure 18 As shown, the semiconductor structure 10 further includes a connection structure 150, which includes a first connection structure 151 coupled to the first contact structure 141 and a second connection structure 152 coupled to the second contact structure 142. The connection structure 150 includes a first portion and a second portion disposed in the z direction, the first portion being located between the second portion and the fin 110. The size of the first portion in the x direction is larger than the size of the second portion in the x direction.

[0062] The first part is the lateral protrusion at the bottom of the connecting structure 150, and the second part is the vertical extension of the connecting structure 150. Taking the first connecting structure 151 as an example, the part of the first connecting structure 151 connected to the first contact structure 141 is the first part, and the second part is the other part connected to the first part but relatively far away from the first contact structure 141. The first part extends into the first contact structure 141, and the diameter and width of the first part are larger than those of the second part, which helps to increase the contact area, reduce contact resistance, provide greater anchoring force, and improve stability. The first part protrudes from the second part in the x-direction, which can prevent the polishing liquid from flowing through the gap between the first connecting structure 151 and the fourth dielectric layer 134 to the first contact structure 141 and causing corrosive damage to the first contact structure 141 when the top of the first connecting structure 151 is chemically and mechanically polished.

[0063] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A grid structure is formed to cover the fins; The fin extends along a first direction and penetrates the gate structure; The gate structure extends along a second direction, which intersects with the first direction; A first active region is formed in the fin between adjacent gate structures; A first dielectric layer is formed covering the gate structure and the fins; A first opening and a second opening are formed that penetrate the first dielectric layer; The bottom of the first opening exposes the first active region, and the bottom of the second opening exposes the gate structure; The method of forming the second opening includes: filling the first opening with a dielectric material to form a sacrificial layer; the sacrificial layer covering the first dielectric layer; forming a third opening through the sacrificial layer and exposing the first dielectric layer; forming a second dielectric layer on the sidewall of the third opening; etching the bottom of the third opening to form the second opening through the first dielectric layer; removing the second dielectric layer; and removing the sacrificial layer. A first contact structure is formed in the first opening, and a second contact structure is formed in the second opening; the first contact structure is coupled to the first active region, and the second contact structure is coupled to the gate structure; the surface of the first contact structure away from the first active region is coplanar with the surface of the second contact structure away from the gate structure.

2. The manufacturing method according to claim 1, characterized in that, The manufacturing method further includes: A third dielectric layer is formed on the sidewall of the first opening and on the sidewall of the second opening.

3. The manufacturing method according to claim 1, characterized in that, The manufacturing method further includes: A first connection layer is formed in the first opening, and the first connection layer is connected to the first active region; the first contact structure is formed on the first connection layer.

4. The manufacturing method according to claim 3, characterized in that, The first connection layer includes a first sublayer and a second sublayer stacked on the first active region; The method for forming the first connection layer includes: The first sub-layer is formed at the bottom of the first opening. A second sublayer is formed in the first opening, covering the first sublayer and the sidewall of the first opening.

5. The manufacturing method according to claim 1, characterized in that, The manufacturing method further includes: A fourth dielectric layer is formed on the contact structure, the contact structure including at least one of the first contact structure and the second contact structure; A fourth opening is formed that penetrates the fourth dielectric layer; the bottom of the fourth opening exposes the contact structure. The contact structure exposed at the bottom of the fourth opening is etched to form a groove; the sidewalls of the groove are provided by the contact structure and the fourth dielectric layer, and the size of the groove in the first direction is larger than the size of the fourth opening in the first direction; The groove and the fourth opening are filled with a conductive material to form a connection structure.

6. A semiconductor structure, characterized in that, include: The fin extends along the first direction; A grid structure extending along a second direction intersecting the first direction; The grid structure covers a portion of the fin; The fin extends through the grid structure along the first direction; a portion of the fin is located between adjacent grid structures. A first active region is at least partially embedded in the fin; the first active region is located between two adjacent gate structures and is exposed between two adjacent gate structures; The first contact structure is located on the first active region and coupled to the first active region; The second contact structure is located on the gate structure and coupled to the gate structure; The surface of the first contact structure away from the first active region is coplanar with the surface of the second contact structure away from the gate structure; A connection structure, the connection structure comprising: a first connection structure coupled to the first contact structure, and a second connection structure coupled to the second contact structure; The connection structure includes a first part and a second part disposed in a third-party upward orientation, wherein the first part is located between the second part and the fin; The first part has a larger dimension in the first direction than the second part has a larger dimension in the first direction, the first part of the first connecting structure has a larger dimension in the first direction than the first contact structure has a larger dimension in the first direction, and the first part of the second connecting structure has a larger dimension in the first direction than the second contact structure has a larger dimension in the first direction.

7. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure also includes: A first connecting layer is located at least partially between the first contact structure and the first active region; at least a portion of the first connecting layer surrounds the sidewall of the first contact structure.

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