Display panel, preparation method thereof and display device

Abstract

The application discloses a display panel, a preparation method thereof and a display device. The display panel comprises a substrate, a first planarization layer, a first metal layer, a photosensitive element, an etching blocking layer and a light-emitting element. The photosensitive element comprises a first electrode and a semiconductor layer which are electrically connected to each other. The first electrode is located on the first metal layer, and the semiconductor layer is located on one side of the etching blocking layer which is away from the first metal layer. In the display area, the etching blocking layer comprises at least one first opening. In the direction perpendicular to the plane where the substrate is located, the first opening does not overlap with the first metal layer. The display panel, the preparation method thereof and the display device of the embodiment of the application set the first opening on the etching blocking layer as a gas release channel. In the process involving high temperature in the manufacturing process, the gas generated by the first planarization layer can be released outward through the first opening, so that the etching blocking layer is prevented from being peeled off from the first planarization layer, and the reliability of the display panel is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel, its manufacturing method, and a display device. Background Technology

[0002] As smart terminal devices continue to demand thinness, lightness, and high integration, traditional external optical sensors (such as ambient light sensors, color temperature sensors, and under-display fingerprint modules) can no longer meet the development trend of product design.

[0003] To address the aforementioned issues, optical sensors can be embedded within the display panel, effectively reducing the overall thickness of the module and improving the recognition accuracy and response consistency of the optical sensors.

[0004] However, there are problems such as film damage and reduced reliability in the process of embedding optical sensors into display panels. Summary of the Invention

[0005] This invention provides a display panel, a method for manufacturing the same, and a display device, to improve the reliability of the display panel and the display device.

[0006] According to one aspect of the present invention, a display panel is provided, comprising:

[0007] Substrate;

[0008] A first planarization layer located on one side of the substrate;

[0009] A first metal layer located on the side of the first planarization layer opposite to the substrate;

[0010] A photosensitive element located within the display area of ​​the display panel;

[0011] An etching barrier layer located on the side of the first metal layer facing away from the substrate;

[0012] A light-emitting element located on the side of the photosensitive element opposite to the substrate;

[0013] The photosensitive element includes a first electrode and a semiconductor layer that are electrically connected to each other. The first electrode is located on the first metal layer, and the semiconductor layer is located on the side of the etch barrier layer opposite to the first metal layer.

[0014] Within the display area, the etching barrier layer includes at least one first opening and at least one second opening;

[0015] Along a direction perpendicular to the plane of the substrate, the first opening does not overlap with the first metal layer, and there is an overlapping area between the second opening, the first electrode, and the semiconductor layer. The first electrode and the semiconductor layer are connected through the second opening.

[0016] According to another aspect of the present invention, a display device is provided, comprising the display panel described in the first aspect.

[0017] According to another aspect of the present invention, a method for manufacturing a display panel is provided, comprising:

[0018] A first planarization layer is formed on one side of the substrate.

[0019] A first metal layer is formed on the side of the first planarization layer opposite to the substrate, and the first metal layer includes a first electrode;

[0020] An etching barrier layer is formed on the side of the first metal layer away from the substrate.

[0021] The etching barrier layer is etched to form at least one first opening and at least one second opening in the display area; the first opening does not overlap with the first metal layer in a direction perpendicular to the plane of the substrate.

[0022] A semiconductor layer electrically connected to the first electrode is formed on the side of the etch barrier layer away from the substrate. Along a direction perpendicular to the plane of the substrate, there is an overlapping region between the second opening, the first electrode, and the semiconductor layer. The first electrode and the semiconductor layer are connected through the second opening to form a photosensitive element located in the display area.

[0023] A light-emitting element is formed on the side of the photosensitive element that is away from the substrate.

[0024] The display panel, its fabrication method, and display device of this invention incorporate photosensitive elements within the display panel, reducing the overall module thickness. A first planarization layer is provided below the photosensitive elements for planarization, ensuring consistent performance for each photosensitive element. Furthermore, an etching barrier layer is added between the first metal layer and the semiconductor layer to protect the first metal layer and the first planarization layer during the etching process to form the patterned semiconductor layer, preventing over-etching damage. Simultaneously, a first opening that does not overlap with the first metal layer is provided on the etching barrier layer as a gas release channel. During high-temperature processes (high-temperature stations) in the manufacturing process, gas generated by the first planarization layer can be released through the first opening, preventing the etching barrier layer from peeling off the first planarization layer and improving the reliability of the display panel.

[0025] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0028] Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure along the A-A' direction;

[0029] Figure 3 This is a partial structural diagram of a first metal layer and an etching barrier layer within a display area, provided by an embodiment of the present invention.

[0030] Figure 4 This is a schematic diagram of a cross-sectional structure of a semiconductor layer provided in an embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram of the structure of a fingerprint recognition module provided in an embodiment of the present invention;

[0032] Figure 6 This is a schematic diagram of a partial cross-sectional structure of a display panel in the non-display area, provided by an embodiment of the present invention.

[0033] Figure 7 This is a schematic diagram of a partial structure of an etching barrier layer in a non-display area, provided by an embodiment of the present invention.

[0034] Figure 8 This is a schematic diagram of a partial structure of another etching barrier layer in a non-display area provided in an embodiment of the present invention;

[0035] Figure 9 This is a schematic diagram of a partial cross-sectional structure of a display panel in the display area, provided by an embodiment of the present invention.

[0036] Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention;

[0037] Figure 11A schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present invention;

[0038] Figures 12-21 This is a structural schematic diagram of a method for manufacturing a display panel according to an embodiment of the present invention. Detailed Implementation

[0039] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0040] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0041] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure along the A-A' direction. Figure 3 This is a partial structural diagram of a first metal layer and an etching barrier layer within a display area, provided by an embodiment of the present invention. Figures 1-3 As shown, the display panel provided in this embodiment of the invention includes:

[0042] Substrate 10.

[0043] The first planarization layer 11 is located on one side of the substrate 10.

[0044] The first metal layer 12 is located on the side of the first planarization layer 11 that is away from the substrate 10.

[0045] The photosensitive element 20 is located in the display area AA of the display panel.

[0046] An etching barrier layer 13 is located on the side of the first metal layer 12 away from the substrate 10.

[0047] The light-emitting element 30 is located on the side of the photosensitive element 20 that is away from the substrate 10.

[0048] The photosensitive element 20 includes a first electrode 201 and a semiconductor layer 202 that are electrically connected to each other. The first electrode 201 is located on the first metal layer 12, and the semiconductor layer 202 is located on the side of the etch barrier layer 13 away from the first metal layer 12.

[0049] Within the display area AA, the etching barrier layer 13 includes at least one first opening 131 and at least one second opening 132.

[0050] Along the direction perpendicular to the plane of the substrate 10, the first opening 131 does not overlap with the first metal layer 12, and there is an overlapping area between the second opening 132, the first electrode 201 and the semiconductor layer 202. The first electrode 201 and the semiconductor layer 202 are connected through the second opening 132.

[0051] Specifically, such as Figure 1 and Figure 2 As shown, the substrate 10 is used to support various components in the display panel. The substrate 10 can be made of glass, which has high hardness and scratch resistance, enabling it to withstand significant mechanical stress during manufacturing and use, reducing the risk of damage. It also provides high surface flatness and smoothness, helping to ensure the uniformity of subsequently deposited films (such as array layers), reducing film defects and non-uniformity. In other embodiments, the substrate 10 can also be made of other materials such as flexible substrates like PI; this embodiment of the invention does not specifically limit this.

[0052] Furthermore, the display area AA of the display panel is provided with an array of pixel circuits 14 and an array of light-emitting elements 30. The pixel circuits 14 and the light-emitting elements 30 are electrically connected to each other. The pixel circuits 14 are used to transmit driving current to the light-emitting elements 30 under the action of signals from driving signal lines (such as scan signal lines, data signal lines, power signal lines, etc.) on the display panel, so as to drive the light-emitting elements 30 to emit light. Among them, the light-emitting elements 30 and the pixel circuits 14 connected to them together constitute the sub-pixels of the display panel. The multiple sub-pixels are arranged according to a certain pattern. By precisely controlling the brightness of different sub-pixels, the display of a complete image can be achieved.

[0053] It should be noted that the arrangement of the multiple pixel circuits 14 and the multiple light-emitting elements 30 can be set according to actual needs, and the embodiments of the present invention do not impose specific limitations on this.

[0054] like Figure 2As shown, optionally, the pixel circuit 14 may include at least one first thin-film transistor T1, wherein the first thin-film transistor T1 may include a first active layer T11, a first gate T12 and a first source / drain electrode T13 stacked together.

[0055] Furthermore, such as Figure 2 As shown, a gate insulating layer 41 is provided between the first active layer T11 and the first gate T12, and an interlayer insulating layer 42 is provided between the first gate T12 and the first source / drain electrode T13, so as to provide electrical isolation between the first gate T12 and the first active layer T11, and between the first gate T12 and the first source / drain electrode T13, to ensure the normal operation of the first thin film transistor T1.

[0056] The pixel circuit 14 can be a 1T1C circuit, a 2T1C circuit, a 7T1C circuit, an 8T1C circuit, or other types of pixel circuits known to those skilled in the art. The specific structure of the pixel circuit 14 can be set according to the actual needs of the display panel, and the embodiments of the present invention do not limit it in this regard.

[0057] Furthermore, the light-emitting element 30 may include an organic light-emitting diode (OLED), a micro light-emitting diode (such as Micro-LED, Mini-LED) or other types of light-emitting devices, and the embodiments of the present invention do not specifically limit this.

[0058] like Figure 2 As shown, taking an organic light-emitting diode (OLED) as an example, the light-emitting element 30 may include an anode 301, a light-emitting layer 302, and a cathode 303 stacked together. When the pixel circuit 14 provides a driving current to the light-emitting element 30, electrons are injected into the light-emitting layer 302 through the cathode 303, and holes are injected into the light-emitting layer 302 through the anode 301. Electrons and holes recombine in the light-emitting layer 302 and release energy, thereby causing the light-emitting layer 302 to emit visible light.

[0059] By using different materials for the light-emitting layer 302, different colors of visible light can be emitted. For example, the light-emitting element 30 may include a red light-emitting element that emits red light, a blue light-emitting element that emits blue light, and a green light-emitting element that emits green light to achieve color image display. However, it is not limited to this. In some embodiments, the light-emitting element 30 may also include a white light-emitting element that emits white light. This embodiment of the present invention does not specifically limit this.

[0060] Furthermore, such as Figure 1 and Figure 2 As shown, the display area AA of the display panel is provided with multiple photosensitive elements 20 arranged in an array. The photosensitive elements 20 are used to receive light signals and convert the light signals into electrical signals.

[0061] Optional, such as Figure 2 As shown, the photosensitive element 20 includes a first electrode 201, a semiconductor layer 202, and a second electrode 203 stacked together.

[0062] Figure 4 This is a schematic diagram of a cross-sectional structure of a semiconductor layer provided in an embodiment of the present invention, as shown below. Figure 4 As shown, optionally, the semiconductor layer 202 adopts a PIN structure. The PIN structure has photosensitive properties and unidirectional conductivity. When there is no light, the PIN structure has a very small saturation reverse leakage current, and the photodiode is cut off at this time; when exposed to light, the saturation reverse leakage current of the PIN structure increases greatly, thereby forming a photocurrent.

[0063] For example, the semiconductor layer 202 includes an N-type doped N-type semiconductor layer 2021, an undoped intrinsic semiconductor layer 2022, and a P-type doped P-type semiconductor layer 2023 stacked sequentially.

[0064] Optionally, the N-type semiconductor layer 2021 can be doped with pentavalent elements (such as phosphorus, arsenic, etc.) to increase the concentration of free electrons. The N-type semiconductor layer 2023 can provide a large number of free electrons. When the PIN structure is forward biased, these electrons can be injected into the intrinsic semiconductor layer 2022 and eventually reach the P-type semiconductor layer 2023.

[0065] The intrinsic semiconductor layer 2022 is an undoped pure semiconductor material with a very low carrier concentration. The intrinsic semiconductor layer 2022 can provide a high-resistance region, which can effectively block the flow of carriers when the PIN structure is reverse biased, allowing the intrinsic semiconductor layer 2022 to withstand higher voltages without breakdown. When the PIN structure is forward biased, the intrinsic semiconductor layer 2022 allows carriers (such as electrons and holes) to pass through.

[0066] The P-type semiconductor layer 2023 can increase the hole concentration by doping with trivalent elements (such as boron, aluminum, etc.). When the PIN structure is forward biased, the P-type semiconductor layer 2023 receives electrons injected from the N-type semiconductor layer 2021 and recombines with its own holes to form a current.

[0067] Furthermore, the P-type semiconductor layer 2023 is electrically connected to the second electrode 203, and the N-type semiconductor layer 2021 is electrically connected to the first electrode 201, so that the first electrode 201, the semiconductor layer 202, and the second electrode 203 constitute a photodiode. At this time, the second electrode 203 serves as the positive electrode of the photodiode, and the first electrode 201 serves as the negative electrode of the photodiode.

[0068] Optionally, the material of the second electrode 203 may include transparent materials such as indium tin oxide (ITO) or indium zinc oxide (IZO) to avoid the second electrode 203 blocking light and affecting the response of the photosensitive element 20 to light.

[0069] Optionally, the photosensitive element 20 can be used to implement fingerprint recognition or other biometric functions.

[0070] Figure 5 This is a schematic diagram of the structure of a fingerprint recognition module provided in an embodiment of the present invention, as shown below. Figure 2 and Figure 5 As shown, exemplarily, the photosensitive element 20, together with the storage capacitor C and the second thin-film transistor T2, can constitute a fingerprint recognition module. The storage capacitor C is connected in series between the first electrode 201 and the second electrode 203 of the photodiode. The second electrode 203 is electrically connected to the reference voltage signal line VCOM. The second thin-film transistor T2 is connected in series between the first electrode 201 and the signal line DATA. The gate of the second thin-film transistor T2 is electrically connected to the switch control line GATE. The semiconductor layer 202 of the photodiode is connected between the first electrode 201 and the second electrode 203.

[0071] The working principle of the fingerprint recognition module is as follows: During fingerprint recognition, the light-emitting element in at least the finger-touching area emits light to illuminate the finger. The reflected light from the finger illuminates the semiconductor layer 202. The semiconductor layer 202 generates photocurrent due to the action of the reflected light. Since the distances from the ridges and valleys in the fingerprint to the semiconductor layer 202 are different, the intensity of the reflected light formed at the ridge position and the reflected light formed at the valley position received by the semiconductor layer 202 are different, and the magnitude of the converted photocurrent is also different. Thus, the valley and ridge signals can be distinguished by the photocurrent, thereby realizing the fingerprint recognition function.

[0072] For example, during the fingerprint recognition stage, the reference voltage signal line VCOM inputs a low-voltage signal to the second electrode 203 of the photosensitive element 20, and the signal line DATA inputs a high-voltage signal. The entire fingerprint recognition stage can include a preparation stage, a fingerprint signal acquisition stage, and a fingerprint signal detection stage. During the preparation stage, the driver chip (not shown in the figure) electrically connected to the fingerprint recognition module controls the second thin-film transistor T2 to turn on via the switch control line GATE, charging the storage capacitor C until the storage capacitor C is fully charged, forming a fixed voltage difference across the storage capacitor C. During the fingerprint recognition stage, the second thin-film transistor T2 is turned off using the switch control line GATE; when a finger touches the display panel, the light emitted by the light-emitting element 30 illuminates the finger and is reflected on the surface of the finger to form reflected light that illuminates the semiconductor layer 202. The semiconductor layer 202 receives the reflected light and generates a corresponding photocurrent according to the intensity of the received reflected light. This photocurrent affects the potential of the storage capacitor C, causing a voltage drop in the storage capacitor C. During the fingerprint signal detection stage, the second thin-film transistor T2 can be turned on via the switch control line GATE, thereby reading the potential information of the storage capacitor C through the signal line DATA, and thus obtaining the voltage drop of the storage capacitor C. When multiple fingerprint recognition modules are arranged in an array, the fingerprint on the finger surface makes the surface uneven, resulting in different brightness of reflected light. This causes different photocurrents generated by different semiconductor layers 202, ultimately causing different voltage drops in the corresponding storage capacitor C. Therefore, the valley and ridge signals can be distinguished based on the voltage drop of the storage capacitor C, realizing the fingerprint recognition function of the display panel.

[0073] In some embodiments, during the fingerprint signal detection stage, the second thin-film transistor T2 can be turned on using the switch control line GATE. There is a potential difference between the two electrodes of the storage capacitor C, and the storage capacitor C is in a charging state. By detecting the amount of charge charged into the storage capacitor C, the magnitude of the photocurrent can also be determined, thereby realizing the fingerprint recognition function of the display panel.

[0074] Continue to refer to Figure 2 Optionally, the second thin-film transistor T2 may include a second active layer T21, a second gate T22, and a second source / drain electrode T23 stacked together. The second thin-film transistor T2 and the first thin-film transistor T1 can be located in the same film layer; that is, the second thin-film transistor T2 can be disposed in the array layer 40 including the pixel circuit 14. This reduces the number of film layers, which is beneficial for reducing the thickness of the display panel. Furthermore, the second thin-film transistor T2 can be fabricated in the same process as the first thin-film transistor T1, which helps to shorten the process time and reduce manufacturing costs.

[0075] The array layer 40 typically contains multiple metal traces to transmit signals and drive the pixel circuit 14 to operate, such as... Figure 2As shown, optionally, along a direction perpendicular to the plane of the substrate 10, the array layer 40 is located between the substrate 10 and the light-emitting element 30, which can prevent the light emitted by the light-emitting element 30 from being blocked by the metal traces in the array layer 40, thereby ensuring the light emission efficiency of the display panel; at the same time, the array layer 40 is located between the substrate 10 and the photosensitive element 20, which can prevent the photosensitive element 20 from being blocked by the metal traces in the array layer 40, thereby ensuring the photosensitivity of the photosensitive element 20.

[0076] It should be noted that the specific structure of the fingerprint recognition module is not limited to the structure provided in the above embodiments. In other embodiments, the function and specific structure of the photosensitive element 20, the circuit connection relationship and the film layer setting can be set according to actual needs, and the embodiments of the present invention do not limit this.

[0077] It is understood that in this embodiment, the photosensitive element 20 is placed inside the display panel, eliminating the need for an external optical sensor, which helps reduce the overall module thickness. Simultaneously, since the photosensitive element 20 is located within the display area AA, the light emitted by the light-emitting element 30 of the display panel can be used as a light source to achieve fingerprint recognition and detection, saving space and increasing the screen-to-body ratio of the display panel.

[0078] Optional, such as Figure 1 As shown, along the direction parallel to the plane of the substrate 10, the photosensitive element 20 is located between adjacent light-emitting elements 30. That is, the photosensitive element 20 is placed in the gap between adjacent light-emitting elements 30. In this way, the photosensitive element 20 will not affect the aperture ratio of the display panel, and the light emitted by the adjacent light-emitting elements 30 can be effectively used to realize the fingerprint recognition function.

[0079] Continue to refer to Figure 1 and Figure 2 The array layer 40 typically includes multiple thin-film transistors and multiple metal traces, etc. These structures can cause the upper surface of the array layer 40 to be uneven. In the embodiment, for example... Figure 2 As shown, a first planarization layer 11 can be provided between the array layer 40 and the photosensitive element 20 along a direction perpendicular to the plane of the substrate 10. The first planarization layer 11 plays a planarization role, thereby providing a flat surface for the photosensitive element 20 to be fabricated on the array layer 40, which helps to ensure the consistent performance of each photosensitive element 20.

[0080] Optionally, the material of the first planarization layer 11 includes organic materials. Organic materials can be spin-coated to form a uniform and continuous film layer, which has a good filling ability for uneven surfaces, thereby enabling the first planarization layer 11 to achieve a good planarization effect.

[0081] Furthermore, such as Figure 2As shown, the inventors discovered through research that after embedding the photosensitive element 20 into the display panel, a first metal layer 12 containing the first electrode 201 and a semiconductor layer 202, etc., are added above the first planarization layer 11 to form the photosensitive element 20 structure. However, because the semiconductor layer 202 has a relatively large thickness, the etching time is long when etching to form the patterned semiconductor layer 202. The physical bombardment of the etching plasma can easily damage the first metal layer 12 and the first planarization layer 11 beneath the semiconductor layer 202, causing over-etching damage to the first metal layer 12 and the first planarization layer 11.

[0082] Based on the above-mentioned technical problems, in this embodiment, as follows: Figure 2 As shown, an etching barrier layer 13 is added between the first metal layer 12 and the semiconductor layer 202 along a direction perpendicular to the plane of the substrate 10. The etching barrier layer 13 is used to ensure that the etching is limited to the film layer where the semiconductor layer 202 is located when the patterned semiconductor layer 202 is etched, and to protect the first metal layer 12 and the first planarization layer 11 below it, thereby avoiding over-etching damage to the first metal layer 12 and the first planarization layer 11 during the preparation of the semiconductor layer 202.

[0083] Optionally, the material of the etching barrier layer 13 may include inorganic materials. The film layer formed by inorganic materials has good density and low porosity. During the etching process to form the patterned semiconductor layer 202, it can effectively block the etching process and prevent the first metal layer 12 and the first planarization layer 11 below it from being damaged by over-etching.

[0084] Furthermore, such as Figure 2 and Figure 3 As shown, the etch barrier layer 13 includes a second opening 132 corresponding to the first electrode 201. Along a direction perpendicular to the plane of the substrate 10, there is an overlapping region between the second opening 132, the first electrode 201, and the semiconductor layer 202, so that the first electrode 201 and the semiconductor layer 202 can be connected through the second opening 132 to form a photosensitive element 20 structure.

[0085] Further research by the inventors revealed that during the high-temperature process (high-temperature station) in the manufacturing process, some substances in the first planarization layer 11 may volatilize and release gas. When the dense etch barrier layer 13 covers a large area of ​​the first planarization layer 11, the gas cannot escape smoothly, which may cause the etch barrier layer 13 to peel off from the first planarization layer 11, thereby affecting the reliability of the display panel.

[0086] Based on the above-mentioned technical problems, in this embodiment, as follows: Figure 2 and Figure 3As shown, a first opening 131 is provided on the etch barrier layer 13 of the display area AA. The first opening 131 is a through-hole penetrating the etch barrier layer 13, which exposes the underlying first planarization layer 11, thus serving as a gas release channel. In this way, during high-temperature processes (high-temperature stations) in the manufacturing process, gases generated by the first planarization layer 11 can be released outward through the first opening 131, thereby preventing the etch barrier layer 13 from peeling off the first planarization layer 11 and improving the reliability of the display panel.

[0087] Furthermore, along the direction perpendicular to the plane of the substrate 10, the first opening 131 does not overlap with the first metal layer 12. That is, the first opening 131 is disposed within the display area AA, excluding the area where the first metal layer 12 is located. Specifically, the first opening 131 is disposed in the gaps between the various metal components of the first metal layer 12, and the area directly below the first opening 131 does not contain the first metal layer 12. This effectively protects the first metal layer 12 during the etching process to form the patterned semiconductor layer 202, preventing damage to the first metal layer 12 due to over-etching.

[0088] In summary, the display panel provided by the embodiments of the present invention places the photosensitive element inside the display panel, reducing the overall module thickness; a first planarization layer is provided below the photosensitive element for planarization to ensure consistent performance of each photosensitive element. Furthermore, by adding an etching barrier layer between the first metal layer and the semiconductor layer, the first metal layer and the first planarization layer are protected during the etching process to form the patterned semiconductor layer, preventing over-etching damage to the first metal layer and the first planarization layer. Simultaneously, a first opening that does not overlap with the first metal layer is provided on the etching barrier layer as a gas release channel. During high-temperature processes (high-temperature stations) in the manufacturing process, gas generated by the first planarization layer can be released through the first opening, thereby preventing the etching barrier layer from peeling off the first planarization layer and improving the reliability of the display panel.

[0089] Optional, such as Figure 2 As shown, along the direction parallel to the plane where the substrate 10 is located, the length of the first opening 131 is d1, where d1 ≥ 2.5 μm.

[0090] The first opening 131 may have multiple linear dimensions in the direction parallel to the plane of the substrate 10 due to its different shape. The length d1 of the first opening 131 can be the minimum linear dimension of the first opening 131 in all directions, but is not limited to this.

[0091] In this embodiment, by setting the length d1 of the first opening 131 to be at least 2.5 μm, it is ensured that the etching barrier layer 13 can be completely penetrated during the etching process to form the first opening 131, forming a through hole. This avoids incomplete etching or film residue caused by the small size of the first opening 131, thereby ensuring that the gas released from the first planarization layer 11 can escape smoothly through the first opening 131, preventing the etching barrier layer from peeling off from the first planarization layer.

[0092] It should be noted that the specific shape and size of the first opening 131 can be set according to actual needs, and the embodiments of the present invention do not impose specific limitations on this.

[0093] For example, the first opening 131 can be a rectangle of 8μm×4μm to meet the exhaust requirements without taking up too much layout space, but it is not limited to this.

[0094] Optional, such as Figure 2 and Figure 3 As shown, the area of ​​the first opening 131 is smaller than the area of ​​the second opening 132.

[0095] The second opening 132 is used to realize the electrical connection between the first electrode 201 and the semiconductor layer 202. By setting the second opening 132 to have a large area, the contact area between the first electrode 201 and the semiconductor layer 202 can be increased, which is beneficial to reduce the contact resistance between the first electrode 201 and the semiconductor layer 202, and can also avoid poor contact caused by misalignment.

[0096] The first opening 131 is only used for gas release. The first opening 131 only needs to form a through hole through the etched barrier layer 13 to achieve gas exhaust. In this embodiment, by setting a single first opening 131 with a small area, the gas exhaust requirement can be met while avoiding the first opening 131 occupying too much layout space, thereby avoiding the first opening 131 encroaching on the layout space of the first metal layer 12.

[0097] Meanwhile, the first opening 131 and the second opening 132 are usually formed in the same etching process. If the area of ​​the first opening 131 is much larger than the area of ​​the second opening 132, during the etching process of forming the first opening 131 and the second opening 132, in order to completely etch away the etching barrier layer 13 in the larger area of ​​the first opening 131, it is necessary to extend the etching time. This will cause the smaller area of ​​the second opening 132 to continue to be over-etched after the etching is completed. Ultimately, the area of ​​the second opening 132 may exceed the design area, affecting the structural integrity of the etching barrier layer 13. As a result, during the subsequent fabrication of the semiconductor layer 202, the etching barrier layer 13 cannot achieve the expected protection effect on the first metal layer 12 below it, resulting in unexpected over-etching damage to the first metal layer 12 below it.

[0098] Furthermore, multiple smaller first openings 131 can be distributed in the gap area between the various metal components of the first metal layer 12, thereby improving the uniformity of exhaust and ensuring that the gas released from the first planarization layer 11 can escape smoothly through the first openings 131, preventing the etching barrier layer 13 from peeling off from the first planarization layer 11.

[0099] Optional, such as Figure 2 and Figure 3 As shown, along the direction parallel to the plane where the substrate 10 is located, the distance L2 between the boundary of the second opening 132 and the boundary of the first electrode 201 is 1 μm to 2.5 μm.

[0100] By setting the distance L2 between the boundary of the second opening 132 and the boundary of the first electrode 201 to be at least 1 μm, sufficient photolithography alignment margin can be provided to ensure that the second opening 132 is still completely above the first electrode 201 within the process deviation range, thereby ensuring a stable electrical connection between the semiconductor layer 202 and the first electrode 201.

[0101] Meanwhile, setting the distance L2 between the boundary of the second opening 132 and the boundary of the first electrode 201 to be less than or equal to 2.5μm can avoid the first electrode 201 occupying too much space, which is beneficial to improving the pixel aperture ratio and integration density.

[0102] For example, the distance L2 between the boundary of the second opening 132 and the boundary of the first electrode 201 can be 1.65 μm, but is not limited to this.

[0103] Optional, such as Figure 2 and Figure 3 As shown, along the direction parallel to the plane where the substrate 10 is located, the shortest distance between the first opening 131 and the metal component located in the first metal layer 12 is d2, where d2 ≥ 1.5 μm.

[0104] The metal components in the first metal layer 12 refer to the conductive patterns in the first metal layer 12. The metal components may include the first electrode 201, as well as other traces, connection structures, etc.

[0105] In this embodiment, the shortest distance d2 between the first opening 131 and the metal component located in the first metal layer 12 is the minimum horizontal distance between the edge of the first opening 131 and the edge of any metal component in the first metal layer 12. By setting d2 to at least 1.5μm, it can be ensured that the first opening 131 can still maintain a non-overlapping state with all metal components in the first metal layer 12 within the etching process deviation range. This effectively protects the first metal layer 12 during the etching process to form the patterned semiconductor layer 202, preventing the first metal layer 12 from being damaged due to over-etching at the first opening 131, thereby improving the reliability and yield of the display panel.

[0106] Optional, such as Figure 2 and Figure 3 As shown, the first metal layer 12 further includes a photosensitive element connection line 121, a first power signal line 122, and a data signal line 123 extending along a first direction X and arranged along a second direction Y. The first direction X and the second direction Y intersect. The photosensitive element connection line 121 is connected to the first electrode 201. Along a direction parallel to the plane of the substrate 10, a first opening 131 is located between the data signal line 123 and the first power signal line 122; and / or, the first opening 131 is located between the photosensitive element 20 and the first power signal line 122; and / or, the first opening 131 is located between the photosensitive element connection line 121 and the first power signal line 122.

[0107] Among them, such as Figure 3 As shown, the first direction X can be perpendicular to the second direction Y. For example, the first direction X can be a column direction and the second direction Y can be a row direction, but it is not limited to this.

[0108] In this embodiment, as Figure 3 As shown, in addition to the first electrode 201, the first metal layer 12 may also include a photosensitive element connection line 121, a first power signal line 122, and a data signal line 123 extending along the first direction X and arranged along the second direction Y.

[0109] The photosensitive element connection line 121 is used to connect the first electrode 201 to the driving circuit of the photosensitive element 20 (e.g., storage capacitor C and / or second thin film transistor T2, etc.).

[0110] The first power signal line 122 is used to provide power voltage (e.g., first power voltage PVDD, etc.) to the pixel circuit 14.

[0111] Data signal line 123 is used to provide data signals to pixel circuit 14.

[0112] In this embodiment, as Figure 2 and Figure 3 As shown, along a direction parallel to the plane of the substrate 10, the first opening 131 can be provided in the gap region between the data signal line 123 and the first power signal line 122, or in the gap region between the photosensitive element 20 (e.g., the first electrode 201) and the first power signal line 122, or in the gap region between the photosensitive element connection line 121 and the first power signal line 122. This configuration allows for the release of outgassing without increasing the additional layout area, preventing the etching barrier layer from peeling off from the first planarization layer. Simultaneously, it ensures isolation between the first opening 131 and the first metal layer 12, thereby preventing damage to the first metal layer 12 due to over-etching at the first opening 131 during the etching process to form the patterned semiconductor layer 202, thus improving the reliability and yield of the first metal layer 12.

[0113] It should be noted that the first opening 131 can be provided at two or more locations simultaneously in the gap area between the data signal line 123 and the first power signal line 122, the gap area between the photosensitive element 20 (e.g., the first electrode 201) and the first power signal line 122, and the gap area between the photosensitive element connection line 121 and the first power signal line 122, so as to realize multi-point release of outgas, thereby improving the uniformity of exhaust, ensuring that the gas released by the first planarization layer 11 can escape smoothly through the first opening 131, and preventing the etching barrier layer from peeling off from the first planarization layer.

[0114] Furthermore, a first opening 131 may be provided in any of the following regions: the gap region between the data signal line 123 and the first power signal line 122, the gap region between the photosensitive element 20 (e.g., the first electrode 201 of the photosensitive element 20) and the first power signal line 122, and the gap region between the photosensitive element connection line 121 and the first power signal line 122. Alternatively, two or more first openings 131 may be provided. This embodiment of the invention does not specifically limit this.

[0115] Optional, such as Figure 2 and Figure 3As shown, the first power signal line 122 includes a first trace portion 1221 and a second trace portion 1222 interconnected, and the first trace portion 1221 and the second trace portion 1222 are arranged along a first direction X. Along a second direction Y, the width d8 of the second trace portion 1222 is greater than the width d7 of the first trace portion 1221. Along a direction parallel to the plane of the substrate 10, a first opening 131 is located between the photosensitive element 20 and the first trace portion 1221; and / or, the first opening 131 is located between the first trace portion 1221 and the data signal line 123; and / or, the first opening 131 is located between the photosensitive element connection line 121 and the second trace portion 1222; and / or, the first opening 131 is located between the data signal line 123 and the second trace portion 1222.

[0116] Specifically, such as Figure 3 As shown, the first power signal line 122 is composed of a first routing section 1221 and a second routing section 1222.

[0117] In particular, the width d8 of the second trace portion 1222 along the second direction Y is relatively large, which can play a role in shielding light and preventing ambient light from entering areas that should not be exposed to light (such as the channel area of ​​the thin film transistor in the pixel circuit 14). It also protects the lower components of the first power signal line 122 (such as the thin film transistor in the pixel circuit 14) from the influence of unexpected light, and avoids the generation of unnecessary photocurrent that affects the performance of the pixel circuit 14, thereby affecting the display effect of the display panel.

[0118] Meanwhile, by setting the width d7 of the first wiring section 1221 to be small, sufficient wiring gaps can be formed between the first wiring section 1221 and other metal components in the first metal layer 12 (such as data signal lines 123, photosensitive element connection lines 121 and first electrodes 201, etc.), thereby improving the space utilization of the display area AA.

[0119] Furthermore, along a direction parallel to the plane of the substrate 10, a first opening 131 can be provided in the gap region between the photosensitive element 20 (e.g., the first electrode 201 of the photosensitive element 20) and the first wiring portion 1221, or in the gap region between the first wiring portion 1221 and the data signal line 123, or in the gap region between the photosensitive element connection line 121 and the second wiring portion 1222, or in the gap region between the data signal line 123 and the second wiring portion 1222. By carefully planning the position of the first opening 131, necessary pathways for venting can be provided without increasing the additional layout area, preventing the etching barrier layer 13 from peeling off from the first planarization layer 11. Simultaneously, it ensures isolation between the first opening 131 and the first metal layer 12, thereby preventing damage to the first metal layer 12 due to over-etching at the first opening 131 during the etching process to form the patterned semiconductor layer 202, thus improving the reliability and yield of the first metal layer 12.

[0120] It should be noted that the first opening 131 can be provided at two or more locations simultaneously in the gap region between the photosensitive element 20 (e.g., the first electrode 201 of the photosensitive element 20) and the first wiring portion 1221, the gap region between the first wiring portion 1221 and the data signal line 123, the gap region between the photosensitive element connection line 121 and the second wiring portion 1222, and the gap region between the data signal line 123 and the second wiring portion 1222, so as to realize multi-point release of outgas, thereby improving the uniformity of exhaust, ensuring that the gas released by the first planarization layer 11 can escape smoothly through the first opening 131, and preventing the etching barrier layer 13 from peeling off from the first planarization layer 11.

[0121] Furthermore, a first opening 131 may be provided in any of the following regions: the gap region between the photosensitive element 20 (e.g., the first electrode 201 of the photosensitive element 20) and the first wiring portion 1221; the gap region between the first wiring portion 1221 and the data signal line 123; the gap region between the photosensitive element connection line 121 and the second wiring portion 1222; and the gap region between the data signal line 123 and the second wiring portion 1222. Alternatively, two or more first openings 131 may be provided. This embodiment of the invention does not specifically limit this.

[0122] Optional, such as Figure 2 and Figure 3As shown, along a direction parallel to the plane of the substrate 10, the first opening 131 between the photosensitive element 20 and the first wiring portion 1221 is a first type opening 131A; the first opening 131 between the first wiring portion 1221 and the data signal line 123 is a second type opening 131B; the first opening 131 between the photosensitive element connection line 121 and the second wiring portion 1222 is a third type opening 131C; and the first opening 131 between the data signal line 123 and the second wiring portion 1222 is a fourth type opening 131D. The area of ​​the third type opening 131C is larger than the area of ​​the first type opening 131A and larger than the area of ​​the second type opening 131B. The area of ​​the fourth type opening 131D is larger than the area of ​​the first type opening 131A and larger than the area of ​​the second type opening 131B.

[0123] Specifically, such as Figure 2 and Figure 3 As shown, the first type opening 131A is located in the gap region between the photosensitive element 20 and the first wiring portion 1221. It is close to the photosensitive element 20, and the layout space near the photosensitive element 20 is relatively compact. In this gap region, the etching barrier layer 13 covers a small area of ​​the first planarization layer 11, and the outgas release pressure is small. By setting a single first type opening 131A with a small area, the exhaust requirements can be met while avoiding the first type opening 131A occupying too much layout space. This ensures that the first type opening 131A can still maintain a non-overlapping state with the first electrode 201 and the first wiring portion 1221 of the photosensitive element 20 within the etching process deviation range. Thus, during the etching process to form the patterned semiconductor layer 202, the first electrode 201 and the first wiring portion 1221 are prevented from being damaged by over-etching at the first type opening 131A, thereby improving reliability and yield.

[0124] The second type opening 131B is located in the gap region between the first trace portion 1221 and the data signal line 123. The signal lines are relatively dense in this region. In this gap region, the etching barrier layer 13 covers a small area of ​​the first planarization layer 11, resulting in lower outgas release pressure. By setting a single second type opening 131B with a small area, the exhaust requirements can be met while avoiding the second type opening 131B occupying too much layout space. This ensures that the second type opening 131B can remain non-overlapping with the first trace portion 1221 and the data signal line 123 within the etching process deviation range. Thus, during the etching process to form the patterned semiconductor layer 202, the first trace portion 1221 and the data signal line 123 are prevented from being damaged by over-etching at the second type opening 131B, improving reliability and yield.

[0125] The third type opening 131C is located in the gap region between the photosensitive element connection line 121 and the second trace portion 1222. This region has ample space. Within this gap region, the etching barrier layer 13 covers a large area of ​​the first planarization layer 11, resulting in significant outgas release pressure. By providing a single third type opening 131C with a large area, it facilitates outgas release, thereby preventing the etching barrier layer 13 from peeling off from the first planarization layer 11. Simultaneously, the larger size of the third type opening 131C makes it easier to manufacture precisely during the etching process, thus improving the dimensional stability of the third type opening 131C and the reliability of venting.

[0126] The fourth type opening 131D is located in the gap region between the data signal line 123 and the second trace portion 1222. This region has ample space, and within it, the etching barrier layer 13 covers a large area of ​​the first planarization layer 11, resulting in significant outgas release pressure. By providing a single fourth type opening 131D with a large area, outgas release is facilitated, thereby preventing the etching barrier layer 13 from peeling off from the first planarization layer 11. Furthermore, the larger size of the fourth type opening 131D makes it easier to manufacture precisely during the etching process, thus improving the dimensional stability of the fourth type opening 131D and the reliability of venting.

[0127] In this embodiment, by designing the area of ​​the first opening 131 at different locations differently, the exhaust requirements and space constraints of different regions can be matched, thereby achieving efficient and uniform outgas release while ensuring the quality of the first metal layer 12 film, and preventing the etching barrier layer 13 from peeling off from the first planarization layer 11.

[0128] Optional, such as Figure 2 and Figure 3 As shown, the etch barrier layer 13 includes a plurality of first openings 131. Along a direction parallel to the plane of the substrate 10, the shortest distance between adjacent first openings 131 is d3, where d3 ≥ 1.5 μm.

[0129] The etching barrier layer 13 has multiple first openings 131 to release the outgas of the underlying first planarization layer 11 during the high-temperature process. This can improve the uniformity of outgas release and help prevent the etching barrier layer 13 from peeling off from the first planarization layer 11.

[0130] Furthermore, if the shortest distance d3 between adjacent first openings 131 is too small, it is easy to cause communication between adjacent first openings 131 when etching to form the first opening 131, affecting the structural integrity of the etch barrier layer 13. As a result, during the subsequent fabrication of the semiconductor layer 202, the etch barrier layer 13 cannot achieve the expected protective effect on the first planarization layer 11 below it, resulting in unexpected over-etching damage to the first planarization layer 11 below it.

[0131] Based on the above technical problems, in this embodiment, by setting the shortest distance d3 between adjacent first openings 131 to be greater than or equal to 1.5μm, it is possible to avoid the connection between adjacent first openings 131, which would cause the area of ​​a single first opening 131 to exceed the design area. This ensures the structural integrity of the etching barrier layer 13 and helps to reduce the over-etching damage of the first planarization layer 11 during the preparation of the semiconductor layer 202.

[0132] Figure 6 This is a schematic diagram of a partial cross-sectional structure of a display panel in the non-display area, provided by an embodiment of the present invention. Figure 7 This is a schematic diagram of a partial structure of an etching barrier layer in a non-display area, provided by an embodiment of the present invention. Figure 1 , Figure 6 and Figure 7 As shown, optionally, the display panel also includes a non-display area NA located on at least one side of the display area AA. Within the non-display area NA, the etch barrier layer 13 includes at least one third opening 133, which is located in an area other than the area where the first metal layer 12 is located.

[0133] The display area AA is the main area of ​​the display panel used for displaying images, including core display components such as the light-emitting element 30 and pixel circuit 14. The non-display area NA is the peripheral area surrounding the display area AA, used for laying out scanning drive circuits, signal lines, power lines, bonding areas, etc.

[0134] In this embodiment, the non-display area NA is also provided with a first planarization layer 11, a first metal layer 12, and an etch barrier layer 13. During the manufacturing process involving high temperatures (high-temperature stations), the first planarization layer 11 of the non-display area NA will also release outgas. When the dense etch barrier layer 13 covers a large area of ​​the non-display area NA above the first planarization layer 11, the gas cannot escape smoothly, which may cause the etch barrier layer 13 to peel off from the first planarization layer 11 in the non-display area NA, thereby affecting the reliability of the display panel.

[0135] Based on the above-mentioned technical problems, in this embodiment, as follows: Figure 6 and Figure 7As shown, a third opening 133 is provided on the etch barrier layer 13 of the non-display area NA. The third opening 133 is a through-hole penetrating the etch barrier layer 13, which exposes the underlying first planarization layer 11, thus serving as a gas release channel. In this way, during high-temperature processes (high-temperature stations) in the manufacturing process, gases generated by the first planarization layer 11 of the non-display area NA can be released outward through the third opening 133, thereby preventing the etch barrier layer 13 of the non-display area NA from peeling off from the first planarization layer 11, and improving the reliability of the display panel.

[0136] Furthermore, along a direction perpendicular to the plane of the substrate 10, the third opening 133 does not overlap with the first metal layer 12. That is, the third opening 133 is disposed within the non-display area NA, excluding the area where the first metal layer 12 is located. Specifically, the third opening 133 is positioned within the gaps between the various metal components of the first metal layer 12, and the area directly below the third opening 133 does not contain the first metal layer 12. This effectively protects the first metal layer 12 during the etching process to form the patterned semiconductor layer 202, preventing damage to the first metal layer 12 due to over-etching.

[0137] Optional, such as Figure 2 , Figure 3 , Figure 6 and Figure 7 As shown, the area of ​​the first opening 131 is S1, the area of ​​the third opening 133 is S3, and 0.8≤S3 / S1≤1.2.

[0138] The first opening 131 and the third opening 133 are usually formed in the same etching process. If the area difference between a single first opening 131 and a single third opening 133 is large, in order to completely etch and remove the etching barrier layer 13 in the larger area opening during the etching process of forming the first opening 131 and the third opening 133, it is necessary to extend the etching time. This will cause the smaller opening to continue to be over-etched after the etching is completed, and eventually the area of ​​the smaller opening may exceed its design area, affecting the structural integrity of the etching barrier layer 13. As a result, in the subsequent process of preparing the semiconductor layer 202, the etching barrier layer 13 cannot achieve the expected protection effect on the first planarization layer 11 below it, resulting in unexpected over-etching damage to the first planarization layer 11 below it.

[0139] Based on the above-mentioned technical problems, in this embodiment, the area S1 of the first opening 131 and the area S3 of the third opening 133 are set to satisfy 0.8≤S3 / S1≤1.2, so that the areas of the first opening 131 of the display area AA and the third opening 133 of the non-display area NA tend to be consistent. In this way, when etching to form the first opening 131 and the third opening 133, the etching deviation between the display area AA and the non-display area NA can be reduced, so that the size of the first opening 131 and the third opening 133 can be controlled within the design range, which helps to improve the reliability of the display panel.

[0140] For example, the area S1 of the first opening 131 is set to be equal to the area S3 of the third opening 133. When etching to form the first opening 131 and the third opening 133, the etching time of the first opening 131 and the third opening 133 is more consistent, further reducing the etching deviation between the display area AA and the non-display area NA, thereby making the size of the first opening 131 and the third opening 133 consistent, which helps to further improve the reliability of the display panel.

[0141] Optional, such as Figure 2 , Figure 3 , Figure 6 and Figure 7 As shown, the etch barrier layer 13 includes a plurality of first openings 131 and a plurality of third openings 133. Along a direction parallel to the plane of the substrate 10, the shortest distance between adjacent first openings 131 is d3, and the shortest distance between adjacent third openings 133 is d4, where 0.8 ≤ d4 / d3 ≤ 1.2.

[0142] In this process, multiple first openings 131 are provided on the etch barrier layer 13 in the display area AA to release the outgas of the lower first planarization layer 11 during the high-temperature process. This can improve the uniformity of outgas release in the display area AA and help prevent the etch barrier layer 13 in the display area AA from peeling off from the first planarization layer 11.

[0143] Similarly, by providing multiple third openings 133 on the etch barrier layer 13 in the non-display area NA to release the outgas of the underlying first planarization layer 11 during the high-temperature process, the uniformity of outgas release in the non-display area NA can be improved, which is beneficial to prevent the etch barrier layer 13 in the non-display area NA from peeling off from the first planarization layer 11.

[0144] Furthermore, the first opening 131 and the third opening 133 are usually formed in the same etching process. If the density of the first opening 131 in the display area AA and the density of the third opening 133 in the non-display area NA are significantly different, during the etching process of forming the first opening 131 and the third opening 133, in order to completely etch away the etching barrier layer 13 in the larger density opening, it is necessary to extend the etching time. This will cause the smaller density opening to continue to be over-etched after etching is completed, and eventually the area of ​​the smaller density opening may exceed its designed area, affecting the structural integrity of the etching barrier layer 13. As a result, during the subsequent fabrication of the semiconductor layer 202, the etching barrier layer 13 cannot achieve the expected protection effect on the first planarization layer 11 below it, resulting in unexpected over-etching damage to the first planarization layer 11 below it.

[0145] Based on the aforementioned technical issues, in this embodiment, the shortest distance d3 between adjacent first openings 131 and the shortest distance d4 between adjacent third openings 133 are set to satisfy 0.8≤d4 / d3≤1.2, so that the spacing between the first openings 131 in the display area AA and the spacing between the third openings 133 in the non-display area NA tend to be consistent. This makes the distribution density of the first openings 131 in the display area AA and the distribution density of the third openings 133 in the non-display area NA tend to be consistent. Thus, when etching to form the first openings 131 and the third openings 133, the etching deviation between the display area AA and the non-display area NA can be reduced, so that the sizes of the first openings 131 and the third openings 133 can be controlled within the design range, which helps to improve the reliability of the display panel.

[0146] For example, by setting the shortest distance d3 between adjacent first openings 131 to be equal to the shortest distance d4 between adjacent third openings 133, the etching time of the first openings 131 and the third openings 133 is made more consistent during etching, further reducing the etching deviation between the display area AA and the non-display area NA, thereby making the size of the first openings 131 and the third openings 133 closer to the design value, which helps to further improve the reliability of the display panel.

[0147] Figure 8 This is a schematic diagram of a partial structure of an etching barrier layer in a non-display area, as provided in an embodiment of the present invention. Figure 8 As shown, optionally, the etch barrier layer 13 includes a plurality of third openings 133, which are arranged in an array. Along a direction parallel to the plane of the substrate 10, the distance between adjacent third openings 133 is L1, where 15μm≤L1≤25μm.

[0148] In particular, multiple arrayed third openings 133 are provided on the etch barrier layer 13 in the non-display area NA to release the outgas of the underlying first planarization layer 11 during the high-temperature process. This can improve the uniformity of outgas release in the non-display area NA and help prevent the etch barrier layer 13 in the non-display area NA from peeling off from the first planarization layer 11.

[0149] Furthermore, by setting the distance L1 between adjacent third openings 133 to satisfy 15μm≤L1≤25μm, the third opening 133 in the non-display area NA can be matched with the first opening 131 in the display area AA. This makes the distribution density of the third opening 133 in the non-display area NA and the distribution density of the first opening 131 in the display area AA more consistent. In this way, when etching to form the first opening 131 and the third opening 133, the etching deviation between the display area AA and the non-display area NA can be reduced, and the size of the first opening 131 and the third opening 133 can be controlled within the design range, which helps to improve the reliability of the display panel.

[0150] It should be noted that the specific shape and size of the third opening 133 can be set according to actual needs, and the embodiments of the present invention do not impose specific limitations on this.

[0151] Optionally, the shape of the third opening 133 can be the same as that of the first opening 131, thereby helping to reduce the etching deviation between the display area AA and the non-display area NA when etching to form the first opening 131 and the third opening 133, so that the shape and size of the first opening 131 and the third opening 133 can be controlled within the design range, and the reliability of the display panel can be improved.

[0152] For example, the third opening 133 can be a rectangle of 8μm×4μm, and the distance L1 between adjacent third openings 133 can be 19μm, so that the third opening 133 matches the first opening 131 in the display area AA. At this time, the ratio between the area of ​​all openings on the etching barrier layer 13 (e.g., the sum of the areas of the first opening 131, the second opening 132 and the third opening 133) and the area of ​​the display panel (e.g., the sum of the areas of the display area AA and the non-display area NA) is greater than or equal to 8.5%, which can achieve efficient outgas release and effectively prevent the etching barrier layer 13 from peeling off from the first planarization layer 11, but it is not limited to this.

[0153] Figure 9 This is a schematic diagram of a partial cross-sectional structure of a display panel in the display area, provided by an embodiment of the present invention. Figure 9As shown, optionally, the etch stop layer 13 includes a first etch stop portion 134 and a second etch stop portion 135. The first etch stop portion 134 overlaps with the semiconductor layer 202 along a direction perpendicular to the plane of the substrate 10. The second etch stop portion 135 is located in a region other than the region where the semiconductor layer 202 is located. The thickness H1 of the first etch stop portion 134 is greater than the thickness H2 of the second etch stop portion 135.

[0154] Specifically, such as Figure 9 As shown, the first etch barrier portion 134 is the etch barrier layer 13 portion in the region where the semiconductor layer 202 is located, and the second etch barrier portion 135 is the etch barrier layer 13 portion in the region where the non-semiconductor layer 202 is located.

[0155] In this embodiment, by setting the first etching barrier portion 134 to have a large thickness H1, it is beneficial to protect the first metal layer 12 below the semiconductor layer 202 and avoid damage to the first metal layer 12 at the semiconductor layer 202 due to over-etching. This can improve the resistance of the photosensitive element 20 to process damage and improve the reliability and yield of the photosensitive element 20.

[0156] Meanwhile, the second etch barrier portion 135 has a smaller thickness H2, which can reduce the coverage thickness of the first planarization layer 11 in the area where the non-semiconductor layer 202 is located. This can promote the release of outgas from the first planarization layer 11 and reduce the accumulation of interfacial stress between the first planarization layer 11 and the second etch barrier portion 135, preventing the etch barrier layer 13 from peeling off from the first planarization layer 11.

[0157] Optional, such as Figure 9 As shown, the thickness of the first etch barrier portion 134 is H1, and the thickness of the second etch barrier portion 135 is H2, where 1 / 2 ≤ H2 / H1 ≤ 2 / 3.

[0158] Specifically, by setting the thickness H2 of the second etch-blocking portion 135 to be 1 / 2 to 2 / 3 of the thickness H1 of the first etch-blocking portion 134, the second etch-blocking portion 135 can protect the first planarization layer 11 and the first metal layer 12 it covers, preventing the first planarization layer 11 and the first metal layer 12 below from being damaged due to over-etching. At the same time, the second etch-blocking portion 135 is not too thick, which would affect the outgas release of the first planarization layer 11. It also helps to reduce the accumulation of interface stress between the first planarization layer 11 and the second etch-blocking portion 135, and prevents the etch-blocking layer 13 from peeling off from the first planarization layer 11.

[0159] The specific thicknesses of the first etch barrier portion 134 and the second etch barrier portion 135 can be set according to actual needs. For example, the thickness H1 of the first etch barrier portion 134 is 300 μm, and the thickness H2 of the second etch barrier portion 135 is 100 μm to 200 μm, but it is not limited to these.

[0160] Optional, such as Figure 9 As shown, along the direction parallel to the plane where the substrate 10 is located, the distance d9 between the boundary of the second opening 132 and the boundary of the semiconductor layer 202 is greater than or equal to 1.8 μm.

[0161] By setting the distance d9 between the boundaries of the boundary semiconductor layer 202 of the second opening 132 to be at least 1.8 μm, sufficient photolithography alignment margin can be provided to ensure that the semiconductor layer 202 still completely covers the second opening 132 within the process deviation range, thereby ensuring a stable electrical connection between the semiconductor layer 202 and the first electrode 201.

[0162] For example, the distance d9 between the boundary of the second opening 132 and the boundary of the semiconductor layer 202 can be 1.8 μm, but is not limited to this.

[0163] Optional, such as Figure 2 and Figure 9 As shown, the display panel provided in this embodiment of the invention further includes a second planarization layer 15 and a second metal layer 16. The second planarization layer 15 is located on the side of the semiconductor layer 202 facing away from the substrate 10. The second metal layer 16 is located on the side of the second planarization layer 15 facing away from the substrate 10. The etching barrier layer 13 further includes a fourth opening 136, and the second planarization layer 15 includes a fifth opening 151. The first metal layer 12 further includes a pixel circuit connection portion 124 electrically connected to the pixel circuit 14, and the second metal layer 16 includes a light-emitting element connection portion 161 electrically connected to the light-emitting element 30. Along a direction perpendicular to the plane of the substrate 10, there is an overlapping region between the pixel circuit connection portion 124, the fourth opening 136, the fifth opening 151, and the light-emitting element connection portion 161, and the pixel circuit connection portion 124 and the light-emitting element connection portion 161 are connected through the fourth opening 136 and the fifth opening 151. Along a direction perpendicular to the plane of the substrate 10, the fifth opening 151 covers the fourth opening 136.

[0164] Specifically, because the semiconductor layer 202 has a large thickness, it will form a large step difference on the first planarization layer 11. This step difference will affect the flatness of the film layer above it, for example, affecting the flatness of the anode 301. This will cause the light-emitting layer 302 above the anode 301 to be uneven. As a result, when the display panel is viewed from different directions at the same tilt angle, the brightness of the light-emitting layer 302 will be different. This will cause the color shift to be inconsistent under the same tilt angle view from different directions, that is, there is a problem of inconsistent color shift in four directions, which will affect the display effect of the display panel.

[0165] Based on the above-mentioned technical problems, in this embodiment, as follows: Figure 2 and Figure 9 As shown, a second planarization layer 15 is disposed between the semiconductor layer 202 and the light-emitting element 30 along a direction perpendicular to the plane of the substrate 10. The second planarization layer 15 is used to planarize the light-emitting element 30, providing a relatively flat surface for the fabrication of the light-emitting element 30, ensuring that the film layer on the second planarization layer 15 can be deposited uniformly, and avoiding color shift problems caused by uneven surface.

[0166] Furthermore, in order to fully cover the large step difference, a planarization layer with a large thickness is required. However, if only a second planarization layer 15 with a large thickness is set, the material flow of the second planarization layer 15 may be uneven during the preparation of the second planarization layer 15, resulting in local thickness differences and affecting the planarization effect.

[0167] Based on the above-mentioned technical problems, in this embodiment, as follows: Figure 2 and Figure 9 As shown, a third planarization layer 17 can also be provided on the second planarization layer 15. The planarization effect is achieved by the second planarization layer 15 and the third planarization layer 17 together. At the same time, by preparing the second planarization layer 15 and the third planarization layer 17 layer by layer, the step difference can be gradually reduced, and a flatter surface can be formed in the end, thus achieving a better planarization effect.

[0168] Furthermore, such as Figure 2 and Figure 9As shown, a second metal layer 16 including a light-emitting element connection portion 161 is disposed between the second planarization layer 15 and the third planarization layer 17. The first metal layer 12 also includes a pixel circuit connection portion 124. The light-emitting element connection portion 161 is connected to the pixel circuit connection portion 124 through the fifth opening 151 on the second planarization layer 15 and the fourth opening 136 on the etching barrier layer 13. At this time, the anode 301 of the light-emitting element 30 is connected to the pixel circuit 14 in sequence through the light-emitting element connection portion 161 and the pixel circuit connection portion 124, thereby realizing the electrical connection between the light-emitting element 30 and the pixel circuit 14. This structure can decompose the traditional deep hole connection method into a multiple shallow hole connection method, avoiding problems such as uneven etching and poor contact caused by a single through hole needing to penetrate multiple film layers, which is beneficial to improving manufacturing yield and reliability.

[0169] Furthermore, the vertical projection of the fifth opening 151 on the substrate 10 covers the vertical projection of the fourth opening 136 on the substrate 10, which can compensate for process alignment errors and ensure the reliability of the electrical connection between the pixel circuit connection portion 124 and the light-emitting element connection portion 161.

[0170] Optional, such as Figure 2 and Figure 9 As shown, the reference voltage signal line VCOM is located in the second metal layer 16, that is, the reference voltage signal line VCOM and the light-emitting element connection portion 161 are located in the same film layer. This reduces the number of film layers, which is beneficial for reducing the thickness of the display panel. At the same time, the reference voltage signal line VCOM and the light-emitting element connection portion 161 can be fabricated in the same process, thereby shortening the process time and reducing manufacturing costs. Figure 2 As shown, the reference voltage signal line VCOM is electrically connected to the cathode 303. In this embodiment, the second electrode 203 of the photosensitive element 20 receives the cathode potential. Of course, the reference voltage signal line VCOM may not be electrically connected to the cathode 303. In this case, the reference voltage signal line VCOM can be connected to a separate signal. For example, the reference voltage signal line VCOM can be extended into the non-display area of ​​the display panel in the plan view, and the required signal can be connected from the reference voltage signal bus in the non-display area. The connection method and connection potential of the reference voltage signal line VCOM can be set according to the needs of those skilled in the art, and are not specifically limited here.

[0171] Optional, such as Figure 9 As shown, along the direction parallel to the plane where the substrate 10 is located, the shortest distance between the boundary of the fifth opening 151 and the boundary of the fourth opening 136 is d5, where d5 ≥ 1 μm.

[0172] Specifically, such as Figure 9As shown, the area of ​​the fifth opening 151 is larger than the area of ​​the fourth opening 136, and the fifth opening 151 covers the area where the fourth opening 136 is located. The minimum distance d5 between the boundary of the fifth opening 151 and the boundary of the fourth opening 136 is set to be at least 1μm, so as to ensure that the fifth opening 151 can still completely cover the fourth opening 136 even in the presence of photolithography hole etching errors, thereby ensuring the reliability of the electrical connection between the pixel circuit connection part 124 and the light-emitting element connection part 161.

[0173] Optional, such as Figure 9 As shown, the pixel circuit connection portion 124 covers the fifth opening 151 along a direction perpendicular to the plane of the substrate 10. The shortest distance between the boundary of the fifth opening 151 and the boundary of the pixel circuit connection portion 124 along a direction parallel to the plane of the substrate 10 is d6, where d6 ≥ 1.6 μm.

[0174] Specifically, such as Figure 9 As shown, the fifth opening 151 is set in the area where the pixel circuit connection portion 124 is located, so that the fifth opening 151 only exposes the pixel circuit connection portion 124 and does not expose other structures such as the first planarization layer 11, thereby protecting the first planarization layer 11 during the fabrication of the semiconductor layer 202.

[0175] Meanwhile, setting the minimum distance d6 between the boundary of the fifth opening 151 and the boundary of the pixel circuit connection portion 124 to be at least 1.6μm ensures that even in the event of etching offset error, the pixel circuit connection portion 124 can still be located within the area where the pixel circuit connection portion 124 is located. This protects the first planarization layer 11 while ensuring that the light-emitting element connection portion 161 can form a reliable electrical connection with the pixel circuit connection portion 124 through the fifth opening 151, effectively preventing poor contact caused by the offset of the fifth opening 151.

[0176] Optional, such as Figure 3 As shown, at least two first openings 131 have different areas.

[0177] The etching barrier layer 13 has multiple first openings 131 to release the outgas of the underlying first planarization layer 11 during the high-temperature process. This can improve the uniformity of outgas release and help prevent the etching barrier layer 13 from peeling off from the first planarization layer 11.

[0178] Furthermore, by setting at least two first openings 131 with different areas, the area of ​​the first openings 131 at different locations can be matched with the exhaust requirements and space constraints at different locations, thereby ensuring the quality of the film layer while achieving efficient and uniform outgas release and preventing the etching barrier layer 13 from peeling off from the first planarization layer 11.

[0179] Optional, such as Figure 3 As shown, the first metal layer 12 further includes a first power signal line 122 and a data signal line 123 extending along a first direction X and arranged along a second direction Y. The first direction X and the second direction Y intersect. The areas of at least two first openings 131 arranged along the first direction X are different; and / or, the areas of at least two first openings 131 arranged along the second direction Y are the same.

[0180] The specific structure and function of the first power signal line 122 and the data signal line 123 can be referred to in the above embodiments, and will not be repeated here.

[0181] In this embodiment, as Figure 3 As shown, by setting at least two first openings 131 arranged along the first direction X with different areas, the area of ​​the first openings 131 at different positions in the first direction X can match the exhaust requirements and space constraints at different gap positions between the first power signal line 122 and the data signal line 123, thereby achieving efficient and uniform outgas release while ensuring the quality of the film layer, and preventing the etching barrier layer 13 from peeling off from the first planarization layer 11.

[0182] In some embodiments, at least two first openings 131 arranged along the second direction Y can be configured to have the same area, which can ensure that the area of ​​the first openings 131 near different first power signal lines 122 and data signal lines 123 tends to be consistent, thereby helping to ensure the consistency of signal loss transmitted by different first power signal lines 122 and data signal lines 123.

[0183] Optional, such as Figure 2 , Figure 6 and Figure 9 As shown, the display panel provided in this embodiment of the invention further includes a pixel definition layer 52, which is located on the side of the third planarization layer 17 facing away from the substrate 10. The pixel definition layer 52 includes a sixth opening 61, and along a direction perpendicular to the plane of the substrate 10, the sixth opening 61 and the photosensitive element 20 at least partially overlap.

[0184] Specifically, such as Figure 2 , Figure 6 and Figure 9 As shown, a pixel definition layer 52 is provided on the third planarization layer 17. The pixel definition layer 52 is disposed on the upper layer of the anode 301, and a seventh opening 62 is provided on the pixel definition layer 52. The light-emitting layer 302 can be formed in the seventh opening 62 of the pixel definition layer 52.

[0185] The pixel definition layer 52 is used to define the boundary of each pixel. The pixel definition layer 52 isolates each light-emitting element 30 from each other, which can effectively prevent current leakage and light crosstalk between adjacent pixels, thereby improving display quality.

[0186] Continue to refer to Figure 2 , Figure 6 and Figure 9 Optionally, the pixel definition layer 52 may include a first pixel definition layer 521 and a second pixel definition layer 522 stacked together, with the second pixel definition layer 522 located on the side of the first pixel definition layer 521 away from the substrate 10. The first pixel definition layer 521 may be configured as a black pixel definition layer to absorb light between adjacent pixels and prevent light crosstalk between adjacent pixels.

[0187] In this embodiment, as Figure 2 , Figure 6 and Figure 9 As shown, a sixth opening 61 is provided on the pixel definition layer 52, and along the direction perpendicular to the plane of the substrate 10, the sixth opening 61 overlaps at least partially with the photosensitive element 20, reducing the occlusion of light by the pixel definition layer 52, so that more light can pass through the pixel definition layer 52 to illuminate the photosensitive element 20, and the performance of the photosensitive element 20 can meet the application requirements (e.g., improve fingerprint recognition efficiency).

[0188] Continue to refer to Figure 2 and Figure 9 Optionally, the cathode 303 is located within the sixth opening 61, wherein the cathode 303 can be electrically connected to the reference voltage signal line VCOM, thereby providing a low voltage signal to the second electrode 203 of the photosensitive element 20 through the sixth opening 61 using the cathode 303. This eliminates the need for additional wiring or complex circuit connections, simplifies the structure of the display panel, and helps to streamline the manufacturing process and reduce production costs.

[0189] In other embodiments, a connection line can be directly set on the film layer where the reference voltage signal line VCOM is located to introduce a low voltage signal, thereby simplifying the manufacturing process and reducing production costs. This embodiment of the invention does not specifically limit this.

[0190] Continue to refer to Figure 9 Optionally, the display panel also includes support pillars PS, which are located on the side of the pixel definition layer 52 facing away from the substrate 10. The support pillars PS are located on the pixel definition layer 52 between adjacent pixels and can be used to support structures such as photomasks, encapsulation layers, or cover plates, preventing deformation or damage to the devices in the display panel due to external forces or pressure.

[0191] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 10The schematic diagram of a display device provided in an embodiment of the present invention is shown. The display device 70 includes the display panel 71 described in any embodiment of the present invention. Therefore, the display device 70 provided in the embodiment of the present invention has the technical effects of the technical solutions in any of the above embodiments. The explanations of the same or corresponding structures and terms as described in the above embodiments will not be repeated here.

[0192] The display device 70 provided in this embodiment of the invention can be Figure 10 The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, in-vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on this.

[0193] Based on the same inventive concept, this embodiment of the invention also provides a method for preparing a display panel, which is used to prepare any of the display panels provided in the above embodiments. The explanations of the same or corresponding structures and terms as in the above embodiments will not be repeated here.

[0194] Figure 11 This is a schematic flowchart of a method for manufacturing a display panel according to an embodiment of the present invention. Figures 12-21 This is a schematic diagram of a method for manufacturing a display panel according to an embodiment of the present invention, as shown below. Figures 11-21 As shown, the preparation method provided in this embodiment of the invention includes:

[0195] S11. A first planarization layer is formed on one side of the substrate.

[0196] Specifically, such as Figure 12 As shown, the substrate 10 is used to support various components in the display panel. An array layer 40 may be disposed on the substrate 10, and a pixel circuit (not shown in the figure) is disposed within the array layer 40 to drive the light-emitting elements to emit light.

[0197] A first planarization layer 11 is prepared on the array layer 40 to achieve the effect of planarization.

[0198] Optionally, the material of the first planarization layer 11 includes organic materials so that the first planarization layer 11 can achieve a better planarization effect.

[0199] S12. A first metal layer is formed on the side of the first planarization layer away from the substrate, and the first metal layer includes a first electrode.

[0200] Specifically, such as Figure 13As shown, a first metal material layer (not shown in the figure) is formed on the first planarization layer 11, and a first metal layer 12 containing the first electrode 201 is formed by etching the first metal material layer.

[0201] Optionally, during the etching process of the first metal material layer, the pixel circuit connection portion 124 can be formed simultaneously. In this case, the pixel circuit connection portion 124 and the first electrode 201 are both located in the first metal layer 12, which can reduce the number of film layers, which is beneficial to reduce the thickness of the display panel. At the same time, it can also shorten the process time and reduce the manufacturing cost.

[0202] S13. An etching barrier layer is formed on the side of the first metal layer away from the substrate.

[0203] Specifically, such as Figure 14 As shown, an etch barrier layer 13 is deposited on the first metal layer 12. The etch barrier layer 13 is used to protect the first metal layer 12 and the first planarization layer 11 below it during the subsequent fabrication of the semiconductor layer, thereby avoiding over-etching damage to the first metal layer 12 and the first planarization layer 11 during the fabrication of the semiconductor layer.

[0204] S14. Etch an etch barrier layer to form at least one first opening and at least one second opening in the display area on the etch barrier layer; the first opening does not overlap with the first metal layer in a direction perpendicular to the plane of the substrate.

[0205] Specifically, such as Figure 15 As shown, the etch barrier layer 13 is etched to form at least one first opening 131 and at least one second opening 132 located in the display area. The first opening 131 is a through-hole penetrating the etch barrier layer 13, exposing the underlying first planarization layer 11 and serving as a gas release channel. Thus, during high-temperature processes (high-temperature stations) in the manufacturing process, gases generated by the first planarization layer 11 can be released through the first opening 131, preventing the etch barrier layer 13 from peeling off the first planarization layer 11 and improving the reliability of the display panel.

[0206] Along the direction perpendicular to the plane of the substrate 10, the first opening 131 does not overlap with the first metal layer 12. That is, the first opening 131 is disposed in the display area AA, excluding the area where the first metal layer 12 is located. The first opening 131 is disposed in the gap between the various metal components in the first metal layer 12. There is no first metal layer 12 in the area directly below the first opening 131. This can effectively protect the first metal layer 12 and prevent the first metal layer 12 from being damaged due to over-etching.

[0207] Furthermore, the second opening 132 is also a through hole penetrating the etch barrier layer 13. Along the direction perpendicular to the plane of the substrate 10, the second opening 132 at least partially overlaps with the first electrode 201, so that the second opening 132 can expose the first electrode 201 below.

[0208] S15. A semiconductor layer electrically connected to the first electrode is formed on the side of the etch barrier layer away from the substrate. An overlapping area exists between the second opening, the first electrode, and the semiconductor layer in a direction perpendicular to the plane of the substrate. The first electrode and the semiconductor layer are connected through the second opening to form a photosensitive element located in the display area.

[0209] Specifically, such as Figure 16 As shown, a whole layer of semiconductor material layer (not shown) and a second electrode material layer (not shown) can be prepared on the etch barrier layer 13, and a semiconductor layer 202 and a second electrode 203 are formed by etching the semiconductor material layer and the second electrode material layer.

[0210] In this structure, there is an overlapping area between the second opening 132, the first electrode 201 and the semiconductor layer 202 along the direction perpendicular to the plane of the substrate 10, so that the first electrode 201 and the semiconductor layer 202 can be connected through the second opening 132 to form a photosensitive element 20 structure.

[0211] Optional, such as Figure 16 As shown, the portion of the etch stop layer 13 within the region where the semiconductor layer 202 is located is the first etch stop portion 134, and the portion of the etch stop layer 13 outside the region where the semiconductor layer 202 is located is the second etch stop portion 135. During the etching process of the semiconductor material layer to form the semiconductor layer 202, the etch stop layer 13 not covered by the semiconductor layer 202 (i.e., the second etch stop portion 135) can be over-etched and thinned, so that the thickness H1 of the first etch stop portion 134 is greater than the thickness H2 of the second etch stop portion 135. This results in the first etch stop portion 134 having a larger thickness H1, which is beneficial for protecting the first metal layer 12 below the semiconductor layer 202 and preventing the first metal layer 12 at the semiconductor layer 202 from being damaged by over-etching. This improves the resistance of the photosensitive element 20 to process damage and enhances the reliability and yield of the photosensitive element 20.

[0212] Meanwhile, the second etch barrier portion 135 has a smaller thickness H2, which can reduce the coverage thickness of the first planarization layer 11 in the area where the non-semiconductor layer 202 is located by the second etch barrier portion 135. This can promote the release of outgas from the first planarization layer 11 and reduce the accumulation of interface stress between the first planarization layer 11 and the second etch barrier portion 135, preventing the etch barrier layer 13 from peeling off from the first planarization layer 11.

[0213] Optionally, the thickness H2 of the second etch barrier portion 135 is 1 / 2 to 2 / 3 of the thickness H1 of the first etch barrier portion 134. This ensures that the second etch barrier portion 135 can protect the first planarization layer 11 and the first metal layer 12 it covers, preventing the first planarization layer 11 and the first metal layer 12 below it from being damaged by over-etching. At the same time, it prevents the second etch barrier portion 135 from being too thick and affecting the outgas release of the first planarization layer 11. It also helps to reduce the accumulation of interface stress between the first planarization layer 11 and the second etch barrier portion 135, preventing the etch barrier layer 13 from peeling off from the first planarization layer 11.

[0214] The specific thicknesses of the first etch barrier portion 134 and the second etch barrier portion 135 can be set according to actual needs. For example, if the thickness H1 of the semiconductor material layer is 300 μm, during the process of etching the semiconductor material layer to form the semiconductor layer 202, the etch barrier layer 13 (i.e. the second etch barrier portion 135) not covered by the semiconductor layer 202 is thinned by 100 μm to 200 μm, thereby forming the first etch barrier portion 134 with a thickness H1 of 300 μm and the second etch barrier portion 135 with a thickness H2 of 100 μm to 200 μm, but it is not limited to this.

[0215] S16. A light-emitting element is formed on the side of the photosensitive element that is away from the substrate.

[0216] Specifically, such as Figure 21 As shown, multiple light-emitting elements 30 are arranged in an array on the upper layer of the photosensitive element 20. Pixel circuits (not shown) within the array layer 40 are electrically connected to the light-emitting elements 30. The pixel circuits transmit driving current to the light-emitting elements 30 under the action of signals from driving signal lines (such as scan signal lines, data signal lines, power signal lines, etc.) on the display panel, thereby driving the light-emitting elements 30 to emit light. The light-emitting elements 30 and the pixel circuits electrically connected to them together constitute the sub-pixels of the display panel. Multiple sub-pixels are arranged according to a certain pattern. By precisely controlling the brightness of different sub-pixels, the display of a complete image can be achieved.

[0217] Optionally, after forming the semiconductor layer electrically connected to the first electrode, the method further includes:

[0218] A second planarization layer is formed on the side of the semiconductor layer that is away from the substrate.

[0219] The second planarization layer is etched to form the fifth opening on the second planarization layer.

[0220] An etch barrier layer is etched to form a fourth opening on the second planarization layer.

[0221] A second metal layer is formed on the side of the second planarization layer that is away from the substrate.

[0222] The second metal layer includes a light-emitting element connection portion electrically connected to the light-emitting element, and the first metal layer also includes a pixel circuit connection portion electrically connected to the pixel circuit.

[0223] Along the direction perpendicular to the plane of the substrate, there is an overlapping area between the pixel circuit connection portion, the fourth opening, the fifth opening and the light-emitting element connection portion, and the pixel circuit connection portion and the light-emitting element connection portion are connected through the fourth opening and the fifth opening; along the direction perpendicular to the plane of the substrate, the fifth opening covers the fourth opening.

[0224] Specifically, such as Figure 17 As shown, after forming the semiconductor layer 202, a second planarization layer 15 is prepared on the semiconductor layer 202 to achieve the effect of planarization.

[0225] like Figure 18 As shown, the second planarization layer 15 is etched to form a fifth opening 151 on the second planarization layer 15, wherein the fifth opening 151 is a through hole penetrating the second planarization layer 15.

[0226] like Figure 19 As shown, the etch barrier layer 13 exposed by the fifth opening 151 is etched to form the fourth opening 136 on the etch barrier layer 13.

[0227] like Figure 20 As shown, a second metal layer 16, including a light-emitting element connection portion 161, is formed on the second planarization layer 15.

[0228] The first metal layer 12 also includes a pixel circuit connection portion 124. The light-emitting element connection portion 161 is connected to the pixel circuit connection portion 124 through the fifth opening 151 on the second planarization layer 15 and the fourth opening 136 on the etching barrier layer 13. At this time, the anode 301 of the light-emitting element 30 is connected to the pixel circuit through the light-emitting element connection portion 161 and the pixel circuit connection portion 124 in sequence, thereby realizing the electrical connection between the light-emitting element 30 and the pixel circuit. This structure can decompose the traditional deep hole connection method into a multiple shallow hole connection method, avoiding problems such as uneven etching and poor contact caused by a single through hole needing to penetrate multiple film layers, which is beneficial to improving manufacturing yield and reliability.

[0229] Furthermore, the vertical projection of the fifth opening 151 on the substrate 10 covers the vertical projection of the fourth opening 136 on the substrate 10, which can compensate for process alignment errors and ensure the reliability of the electrical connection between the pixel circuit connection portion 124 and the light-emitting element connection portion 161.

[0230] Optional, such as Figure 20 As shown, when the second metal layer 16 is prepared, the light-emitting element connection portion 161 and the reference voltage signal line VCOM are formed simultaneously. That is, the reference voltage signal line VCOM and the light-emitting element connection portion 161 are both located in the second metal layer 16. This can reduce the number of film layers and help reduce the thickness of the display panel. At the same time, the reference voltage signal line VCOM and the light-emitting element connection portion 161 are prepared in the same process, which can shorten the process time and reduce the manufacturing cost.

[0231] It should be noted that if a fourth opening 136 is formed simultaneously during the etching process of the first opening 131 and the second opening 132 in the etching barrier layer 13, the pixel circuit connection portion 124 exposed by the fourth opening 136 is easily damaged due to over-etching during the subsequent fabrication of the semiconductor layer 202.

[0232] In this embodiment, the etching barrier layer 13 is not etched above the pixel circuit connection portion 124 during the etching process of forming the first opening 131 and the second opening 132; that is, the fourth opening 136 is not formed. Instead, the etching barrier layer 13 is etched after the semiconductor layer 202 is formed to form the fourth opening 136. Thus, during the fabrication of the semiconductor layer 202, the etching barrier layer 13 can protect the pixel circuit connection portion 124, preventing over-etching damage to the pixel circuit connection portion 124 during the fabrication of the semiconductor layer 202.

[0233] Optional, such as Figure 19 As shown, along the direction parallel to the plane where the substrate 10 is located, the shortest distance between the boundary of the fifth opening 151 and the boundary of the fourth opening 136 is d5, where d5 ≥ 1 μm.

[0234] Specifically, such as Figure 19 As shown, the area of ​​the fifth opening 151 is larger than the area of ​​the fourth opening 136, and the fifth opening 151 covers the area where the fourth opening 136 is located. The minimum distance d5 between the boundary of the fifth opening 151 and the boundary of the fourth opening 136 is set to be at least 1μm, so as to ensure that the fifth opening 151 can still completely cover the fourth opening 136 even in the presence of photolithography hole etching errors, thereby ensuring the reliability of the electrical connection between the pixel circuit connection part 124 and the light-emitting element connection part 161.

[0235] Optional, such as Figure 19 As shown, the pixel circuit connection portion 124 covers the fifth opening 151 along a direction perpendicular to the plane of the substrate 10. The shortest distance between the boundary of the fifth opening 151 and the boundary of the pixel circuit connection portion 124 along a direction parallel to the plane of the substrate 10 is d6, where d6 ≥ 1.6 μm.

[0236] Specifically, such as Figure 19 As shown, the fifth opening 151 is set in the area where the pixel circuit connection portion 124 is located, so that the fifth opening 151 only exposes the pixel circuit connection portion 124 and does not expose other structures such as the first planarization layer 11, thereby protecting the first planarization layer 11 during the fabrication of the semiconductor layer 202.

[0237] Meanwhile, setting the minimum distance d6 between the boundary of the fifth opening 151 and the boundary of the pixel circuit connection portion 124 to be at least 1.6μm ensures that even in the event of etching offset error, the pixel circuit connection portion 124 can still be located within the area where the pixel circuit connection portion 124 is located. This protects the first planarization layer 11 while ensuring that the light-emitting element connection portion 161 can form a reliable electrical connection with the pixel circuit connection portion 124 through the fifth opening 151, effectively preventing poor contact caused by the offset of the fifth opening 151.

[0238] It should be noted that other specific structures in the display panel can refer to any of the above embodiments, and will not be repeated here.

[0239] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0240] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate; a first planarization layer on one side of the substrate; a first metal layer on the side of the first planarization layer away from the substrate; a light sensing element in a display area of the display panel; an etching stop layer on the side of the first metal layer away from the substrate; a light emitting element on the side of the light sensing element away from the substrate; the light sensing element comprises a first electrode and a semiconductor layer electrically connected to each other, the first electrode is on the first metal layer, and the semiconductor layer is on the side of the etching stop layer away from the first metal layer; in the display area, the etching stop layer comprises at least one first opening and at least one second opening; in the direction perpendicular to the plane where the substrate is located, the first opening does not overlap the first metal layer, there is an overlapping area between the second opening, the first electrode and the semiconductor layer, and the first electrode and the semiconductor layer are connected through the second opening; the first metal layer further comprises a light sensing element connecting line, a first power signal line and a data signal line which extend along a first direction and are arranged along a second direction; the first direction and the second direction intersect each other; the light sensing element connecting line is connected to the first electrode; in the direction parallel to the plane where the substrate is located, the first opening is located between the data signal line and the first power signal line; and / or, the first opening is located between the light sensing element and the first power signal line; and / or, the first opening is located between the light sensing element connecting line and the first power signal line.

2. The display panel of claim 1, wherein: in the direction parallel to the plane where the substrate is located, the length of the first opening is d1, and d1 is greater than or equal to 2.5 micrometers.

3. The display panel of claim 1, wherein: the area of the first opening is smaller than the area of the second opening.

4. The display panel of claim 1, wherein: in the direction parallel to the plane where the substrate is located, the shortest distance between the first opening and a metal member in the first metal layer is d2, and d2 is greater than or equal to 1.5 micrometers.

5. The display panel of claim 1, wherein: the first power signal line comprises a first wire segment and a second wire segment which are connected to each other, and the first wire segment and the second wire segment are arranged along the first direction; in the second direction, the width of the second wire segment is greater than the width of the first wire segment; in the direction parallel to the plane where the substrate is located, the first opening is located between the light sensing element and the first wire segment; and / or, the first opening is located between the first wire segment and the data signal line; and / or, the first opening is located between the light sensing element connecting line and the second wire segment; and / or, the first opening is located between the data signal line and the second wire segment.

6. The display panel of claim 5, wherein: The first opening between the photosensitive element and the first trace sub-portion is a first type of opening, the first opening between the first trace sub-portion and the data signal line is a second type of opening, the first opening between the photosensitive element connection line and the second trace sub-portion is a third type of opening, and the first opening between the data signal line and the second trace sub-portion is a fourth type of opening; The third type of opening has an area greater than that of the first type of opening and greater than that of the second type of opening; The fourth type of opening has an area greater than that of the first type of opening and greater than that of the second type of opening.

7. The display panel of claim 1, wherein: The etching barrier layer comprises a plurality of the first openings; In a direction parallel to the plane in which the substrate substrate lies, the shortest distance between adjacent first openings is d3, and d3≥1.5μm.

8. The display panel of claim 1, wherein: The display panel further comprises a non-display area on at least one side of the display area; In the non-display area, the etching barrier layer comprises at least one third opening, and the third opening is located in a region other than the region in which the first metal layer lies.

9. The display panel of claim 8, wherein: The area of the first opening is S1, the area of the third opening is S3, and 0.8≤S3 / S1≤1.

2.

10. The display panel of claim 8, wherein: The etching barrier layer comprises a plurality of the first openings and a plurality of the third openings; In a direction parallel to the plane in which the substrate substrate lies, the shortest distance between adjacent first openings is d3, and the shortest distance between adjacent third openings is d4, and 0.8≤d4 / d3≤1.

2.

11. The display panel of claim 8, wherein: The etching barrier layer comprises a plurality of the third openings, and the plurality of third openings are arranged in an array; In a direction parallel to the plane in which the substrate substrate lies, the distance between adjacent third openings is L1, and 15μm≤L1≤25μm.

12. The display panel of claim 1, wherein: The etching barrier layer comprises a first etching barrier sub-portion and a second etching barrier sub-portion; In a direction perpendicular to the plane in which the substrate substrate lies, the first etching barrier sub-portion is arranged to overlap the semiconductor layer; The second etching barrier sub-portion is located in a region other than the region in which the semiconductor layer lies; The thickness of the first etching barrier sub-portion is greater than the thickness of the second etching barrier sub-portion.

13. The display panel of claim 12, wherein: The thickness of the first etching barrier sub-portion is H1, the thickness of the second etching barrier sub-portion is H2, and 1 / 2≤H2 / H1≤2 / 3.

14. The display panel of claim 1, wherein: The display panel further comprises a second planarization layer and a second metal layer; The second planarization layer is located on the side of the semiconductor layer away from the substrate substrate; The second metal layer is located on the side of the second planarization layer away from the substrate substrate; The etching stop layer further comprises a fourth opening, and the second planarization layer comprises a fifth opening; The first metal layer further comprises a pixel circuit connection part electrically connected with the pixel circuit, and the second metal layer comprises a light emitting element connection part electrically connected with the light emitting element; In a direction perpendicular to the plane where the substrate substrate is located, there is an overlapping area between the pixel circuit connection part, the fourth opening, the fifth opening and the light emitting element connection part, and the pixel circuit connection part and the light emitting element connection part are connected through the fourth opening and the fifth opening; In a direction perpendicular to the plane where the substrate substrate is located, the fifth opening covers the fourth opening.

15. The display panel of claim 14, wherein, In a direction parallel to the plane where the substrate substrate is located, the shortest distance between the boundary of the fifth opening and the boundary of the fourth opening is d5, and d5≥1μm.

16. The display panel of claim 14, wherein, In a direction perpendicular to the plane where the substrate substrate is located, the pixel circuit connection part covers the fifth opening; In a direction parallel to the plane where the substrate substrate is located, the shortest distance between the boundary of the fifth opening and the boundary of the pixel circuit connection part is d6, and d6≥1.6μm.

17. The display panel of claim 1, wherein, The areas of at least two of the first openings are different.

18. The display panel of claim 17, wherein, The first metal layer further comprises first power signal lines and data signal lines extending in a first direction and arranged in a second direction; The first direction and the second direction intersect; The areas of at least two of the first openings arranged in the first direction are different; And / or, The areas of at least two of the first openings arranged in the second direction are the same.

19. A display device comprising: A display panel comprising any one of claims 1-18.

20. A method for manufacturing a display panel, characterized in that, A display panel comprising: forming a first planarization layer on the side of the substrate substrate; forming a first metal layer on the side of the first planarization layer away from the substrate substrate, the first metal layer comprising a first electrode; the first metal layer further comprising a light sensing element connection line, first power signal lines and data signal lines extending in a first direction and arranged in a second direction; the first direction and the second direction intersect; the light sensing element connection line is connected with the first electrode; forming an etching stop layer on the side of the first metal layer away from the substrate substrate; etching the etching stop layer to form at least one first opening and at least one second opening in the display area on the etching stop layer; In a direction perpendicular to the plane where the substrate substrate is located, the first opening does not overlap with the first metal layer; The first opening is located between the data signal line and the first power signal line in a direction parallel to a plane in which the substrate substrate is located; and / or, the first opening is located between the photosensitive element and the first power signal line; and / or, the first opening is located between the photosensitive element connecting line and the first power signal line; A semiconductor layer electrically connected with the first electrode is formed on a side of the etching stop layer away from the substrate substrate, and there is an overlapping area between the second opening, the first electrode and the semiconductor layer in a direction perpendicular to a plane in which the substrate substrate is located, the first electrode and the semiconductor layer are connected through the second opening to form a photosensitive element located in the display area; A light-emitting element is formed on a side of the photosensitive element away from the substrate substrate.

21. The manufacturing method of claim 20, wherein, After the semiconductor layer electrically connected with the first electrode is formed, the method further comprises: forming a second planarization layer on a side of the semiconductor layer away from the substrate substrate; etching the second planarization layer to form a fifth opening on the second planarization layer; etching the etching stop layer to form a fourth opening on the etching stop layer; forming a second metal layer on a side of the second planarization layer away from the substrate substrate; The second metal layer comprises a light-emitting element connecting part electrically connected with the light-emitting element, and the first metal layer further comprises a pixel circuit connecting part electrically connected with the pixel circuit; In a direction perpendicular to a plane in which the substrate substrate is located, there is an overlapping area between the pixel circuit connecting part, the fourth opening, the fifth opening and the light-emitting element connecting part, and the pixel circuit connecting part and the light-emitting element connecting part are connected through the fourth opening and the fifth opening; in a direction perpendicular to a plane in which the substrate substrate is located, the fifth opening covers the fourth opening.

22. The manufacturing method of claim 21, wherein, In a direction parallel to a plane in which the substrate substrate is located, the shortest distance between the boundary of the fifth opening and the boundary of the fourth opening is d5, and d5≥1μm.

23. The manufacturing method of claim 21, wherein, In a direction perpendicular to a plane in which the substrate substrate is located, the pixel circuit connecting part covers the fifth opening; In a direction parallel to a plane in which the substrate substrate is located, the shortest distance between the boundary of the fifth opening and the boundary of the pixel circuit connecting part is d6, and d6≥1.6μm.

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