Signal acquisition frequency division processing circuit and data acquisition method

Abstract

The invention relates to the field of transformer monitoring, in particular to a signal acquisition frequency division processing circuit and a data acquisition method. The voltage input module provides voltage signal acquisition following and is divided into two paths to be connected to the filtering module for voltage signal processing. The filtering module is divided into two paths, provides signal filtering and then is respectively connected to the program control discharging module and the pulse detection module; the program-controlled discharge module controls discharge time and current amplitude according to preset parameters, and the output end of the program-controlled discharge module transmits data to the single-chip microcomputer assembly through a data bus; the pulse detection module detects the amplitude and frequency of the pulse signal, generates digital pulse data, and accesses the digital pulse data to the single-chip microcomputer assembly for data acquisition. According to the invention, the accuracy of signal acquisition and processing is improved, so that the system can easily deal with various complex working conditions, the anti-interference capability of the circuit to electromagnetic interference is obviously enhanced, the signal is ensured to be clear and complete in the transmission process, and the accuracy of data acquisition is more accurate through programmable control and cascade amplification design.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of transformer monitoring, and in particular to a signal acquisition frequency division processing circuit and a data acquisition method. BACKGROUND

[0002] With the wide application of electronic devices in industrial control, power monitoring and signal processing fields, the design of circuit architecture is increasingly concerned.

[0003] In the current technical field, the traditional circuit architecture usually adopts a single signal processing path, which is difficult to simultaneously meet the stable collection of power frequency voltage signals and the accurate detection of pulse signals. The existing voltage input module relies on a simple collection circuit, which is easily affected by external electromagnetic interference, resulting in signal distortion. The filtering module has low separation efficiency when processing multi-band signals and fails to effectively suppress noise. The control accuracy of the program-controlled discharge module and the pulse detection module is insufficient, making it difficult to achieve dynamic adjustment and real-time response, which limits the application of the system in complex environments. In addition, the connection relationship between the modules is designed roughly, and the signal transmission loss and interference problem is prominent, which affects the overall performance.

[0004] Therefore, a signal acquisition frequency division processing circuit and a data acquisition method are needed, which can be divided into a low-pass filter unit and a high-pass filter unit, effectively separate power frequency voltage and pulse signals and suppress interference, realize cascade amplification and dynamic adjustment function through single-chip microcomputer control signal port, and effectively collect corresponding data to ensure the stability of data precision. SUMMARY

[0005] The purpose of this section is to summarize some aspects of the embodiments of the present application and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the abstract and title of the specification to avoid obscuring the purpose of this section, abstract and title, and such simplifications or omissions cannot be used to limit the scope of the present application.

[0006] In view of the above prior art, the traditional circuit architecture usually adopts a single signal processing path, which is difficult to simultaneously meet the stable collection of power frequency voltage signals and the accurate detection of pulse signals, and is easily affected by external electromagnetic interference, resulting in signal distortion. The filtering module has low separation efficiency when processing multi-band signals and fails to effectively suppress noise.

[0007] Therefore, the technical problem to be solved by the present application is to design a signal acquisition frequency division processing circuit which can be divided into a low-pass filter unit and a high-pass filter unit, effectively separate power frequency voltage and pulse signals and suppress interference, and realize cascade amplification and dynamic adjustment function through single-chip microcomputer control signal port to meet the existing environmental needs.

[0008] To solve the above technical problems, the present application provides the following technical solutions: a signal acquisition and frequency division processing circuit, comprising,

[0009] A voltage input module, a filter module, a program-controlled discharge module and a pulse detection module;

[0010] The voltage input module provides voltage signal acquisition and follow-up, and is connected to the filter module in two ways for voltage signal processing;

[0011] The filter module is divided into two ways, and after signal filtering, it is connected to the program-controlled discharge module and the pulse detection module respectively;

[0012] The program-controlled discharge module controls the discharge time and current amplitude according to the preset parameters, and the output end is transmitted to the single-chip microcomputer assembly through the data bus;

[0013] The pulse detection module detects the amplitude and frequency of the pulse signal and generates digital pulse data, and the output end is connected to the single-chip microcomputer assembly for data acquisition.

[0014] As an improvement of the present application,

[0015] The voltage input module comprises a voltage acquisition unit and a voltage follow-up unit;

[0016] The voltage acquisition unit is externally connected to a corresponding voltage transformer, and acquires a transformer voltage signal, which is input to the voltage follow-up unit through corresponding terminals of J1;

[0017] The voltage follow-up unit provides high-to-low impedance conversion to reduce signal transmission loss, and the converted signal is connected to the filter module for processing.

[0018] As an improvement of the present application,

[0019] The filter module is provided with a low-pass filter unit and a high-pass filter unit to separate double signals and suppress external interference;

[0020] The output end of the voltage follow-up unit is connected to the input terminal of the low-pass filter unit through a single-core shielded wire;

[0021] A low-pass resistor is arranged in the low-pass filter unit, and the low-pass resistor is connected in parallel with a low-pass capacitor through a welding point;

[0022] The low-pass filter unit receives the power frequency voltage signal delivered by the voltage follow-up unit, and after processing, it is connected to the input terminal of the program-controlled discharge module through the output end lead.

[0023] As an improvement of the present application,

[0024] A high-pass capacitor group is fixedly connected in the high-pass filter unit, and the high-pass capacitor group is connected in parallel with a high-pass resistor through a welding point;

[0025] The high-pass filter unit receives the high-frequency pulse signal transmitted by the voltage follower unit, and is connected to the pulse detection module through an output lead after processing.

[0026] As an improvement of the present application,

[0027] The program-controlled discharge module is provided with a first amplification unit and a second amplification unit.

[0028] The first amplification unit and the second amplification unit are respectively connected to a first single-chip microcomputer control signal port and a second single-chip microcomputer control signal port through a multi-core shielding line.

[0029] The output pin of the first amplification unit is connected to the input pin of the second amplification unit, and the output pin of the second amplification unit is transmitted to the single-chip microcomputer assembly through a data bus.

[0030] As an improvement of the present application,

[0031] The pulse detection module comprises a voltage dividing resistor and a voltage comparator.

[0032] The voltage dividing resistor provides a voltage comparison reference, and cooperates with the voltage comparator to convert the exponential waveform into a square wave level signal.

[0033] The output pin of the voltage comparator is transmitted to the single-chip microcomputer assembly through a data bus.

[0034] As an improvement of the present application,

[0035] The pulse detection module comprises a voltage dividing resistor and a voltage comparator.

[0036] The voltage dividing resistor provides a voltage comparison reference, and cooperates with the voltage comparator to convert the exponential waveform into a square wave level signal.

[0037] The output pin of the voltage comparator is transmitted to the single-chip microcomputer assembly through a data bus.

[0038] In view of the above prior art, the control and detection accuracy of the program-controlled discharge module and the pulse detection module is insufficient, and it is difficult to realize dynamic adjustment and real-time response, which limits the application of the system in complex environments

[0039] To solve the above technical problems, the present application provides the following technical scheme: a data acquisition method, comprising,

[0040] An initial PGA test value is preset, and the M-cycle current effective value and the test amplitude are calculated according to the initial PGA test value.

[0041] A determination threshold of the M-cycle current amplitude is preset, and the determination threshold is compared with the actual amplitude.

[0042] According to the comparison result, the corresponding PGA fixed value is set, and the final effective value and the amplitude of the M-cycle current amplitude are calculated.

[0043] As an improvement of the present application,

[0044] In the determination threshold setting process of the M cycle current amplitude value,

[0045] The threshold is adjusted to three orders of 100MA, 8MA and 0.2MA, and the determination threshold and the actual amplitude are compared in the order;

[0046] When the actual amplitude is greater than 100MA, the PGA constant value is set to 1, and the final calculation is entered;

[0047] When the actual amplitude is less than 100MA, the actual amplitude and 8MA are determined;

[0048] When the actual amplitude is greater than 8MA, the PGA constant value is set to 4, and the final calculation is entered;

[0049] When the actual amplitude is less than 8MA, the actual amplitude and 0.2MA are determined;

[0050] When the actual amplitude is greater than 0.2MA, the PGA constant value is set to 80, and the final calculation is entered;

[0051] When the actual amplitude is less than 0.2MA, the PGA constant value is set to 1600, and the final calculation is entered.

[0052] The beneficial effects of the present application are: greatly improving the accuracy of signal acquisition and processing, enabling the system to easily cope with various complex working conditions such as high noise environment or dynamic voltage change, significantly enhancing the anti-interference ability of the circuit to electromagnetic interference, ensuring that the signal remains clear and complete during transmission, through programmable control and cascade amplification design, giving flexibility and real-time to discharge and pulse detection, making the data acquisition more accurate. BRIEF DESCRIPTION OF DRAWINGS

[0053] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor. Among them:

[0054] Figure 1 The circuit principle architecture planning diagram of the signal acquisition frequency division processing circuit in the present application.

[0055] Figure 2 The voltage input module principle architecture diagram of the signal acquisition frequency division processing circuit in the present application.

[0056] Figure 3The low-pass filter unit principle architecture diagram of the signal acquisition frequency division processing circuit in the application.

[0057] Figure 4 The program-controlled discharge module principle architecture diagram of the signal acquisition frequency division processing circuit in the application.

[0058] Figure 5 The high-pass filter unit principle architecture diagram of the signal acquisition frequency division processing circuit in the application.

[0059] Figure 6 The pulse detection module principle architecture diagram of the signal acquisition frequency division processing circuit in the application.

[0060] Figure 7 The flow determination diagram of the data acquisition method in the application. DETAILED DESCRIPTION

[0061] In order to make the above-mentioned purposes, features and advantages of the application more obvious and easy to understand, the specific embodiments of the application will be described in detail below with reference to the accompanying drawings.

[0062] Embodiment 1

[0063] Reference Figure 1 The embodiment provides a signal acquisition frequency division processing circuit.

[0064] The voltage input module 1 is mainly responsible for collecting the voltage signal output by the external transformer, and provides the collection and following functions of the voltage. The voltage input module 1 is internally provided with an adaptive low-noise differential amplifier and a voltage transformer to assist the voltage import function, and is connected to the secondary winding of the transformer through a twisted shielded wire respectively, so as to ensure the anti-interference and linearity of signal acquisition.

[0065] The voltage input module 1 also includes an adaptive impedance operational amplifier, which realizes the conversion from high impedance to low impedance, effectively reducing the loss in signal transmission. The converted voltage signal includes a 50Hz power frequency voltage signal and a high-frequency pulse signal, and the two signals are output through two independent pins of the J1 terminal in the voltage input module 1 and accessed to the filter module 2.

[0066] The filter module 2 receives the two signals output by the voltage input module 1, and also provides two filter channels with different specifications, which are respectively used for filtering the 50Hz power frequency voltage signal and the high-frequency pulse signal, so as to realize the separation of multi-band signals. The filter module 2 is designed through a shielding shell and a grounding wire, which significantly suppresses external electromagnetic interference.

[0067] After being processed, the 50Hz power frequency voltage signal and the high-frequency pulse signal are also divided into two paths. The 50Hz power frequency voltage signal is connected into the program-controlled discharge module 3, and the high-frequency pulse signal is connected into the pulse detection module 4.

[0068] The program-controlled discharge module 3 is provided with two additional control signal ports for electrically connecting with the single-chip microcomputer and receiving the control signals input by the single-chip microcomputer. In this scheme, the preset parameters can be received through the I2C communication protocol. The program-controlled discharge module 3 receives the power frequency voltage signal output by the low-pass filtering unit 21, and internally adopts a double-signal amplifier architecture layout. The first signal amplification is performed on the input signal through a gain-adjustable circuit for primary amplification, and the second signal amplification ensures that the signal can adapt to the input range of the single-chip microcomputer, so as to realize more accurate discharge control.

[0069] The pulse detection module 4 receives the pulse signal output by the high-pass filtering unit 22, and internally integrates a comparator. The threshold value of the comparator can be adjusted to distinguish between effective pulses and noise. In this scheme, the pulse detection module 4 can be connected with the single-chip microcomputer assembly through the SPI interface, or the appropriate connection mode can be adjusted according to the needs on site.

[0070] The two-way output of the voltage input module 1 is welded to the input end of the filtering module 2 through the J1 terminal, and the low-pass and high-pass outputs of the filtering module 2 are connected to the input ends of the program-controlled discharge module 3 and the pulse detection module 4, respectively.

[0071] The output ends of the program-controlled discharge module 3 and the pulse detection module 4 are connected with the ADC input port and the communication port of the single-chip microcomputer assembly. The entire system operates under the support of a stabilized power supply. During the implementation process, the single-chip microcomputer assembly monitors the state of each module through a real-time interrupt mechanism, and triggers an alarm when an abnormality is detected.

[0072] Embodiment 2

[0073] Reference Figures 1-6 This embodiment is based on the previous embodiment, and differs from the previous embodiment in that:

[0074] The voltage input module 1 includes a voltage acquisition unit 11 and a voltage follower unit 12. The voltage acquisition unit 11 mainly adopts a low-noise differential amplifier in cooperation with a voltage transformer, and is connected to the secondary winding of the transformer through a twisted shielded wire to ensure the anti-interference and linearity of signal acquisition. The voltage follower unit 12 is designed based on a high-input-impedance operational amplifier, and is configured as a unity-gain follower. Through an impedance matching network, the voltage follower unit 12 realizes the conversion from high impedance to low impedance, effectively reducing the loss in signal transmission.

[0075] The 50Hz power frequency voltage signal and the high-frequency pulse signal converted by the voltage follower unit 12 are output through two independent pins of the J1 terminal in the voltage input module 1, and are connected to the filtering module 2.

[0076] The filter module 2 sets low-pass filter unit 21 and high-pass filter unit 22 for 50Hz power frequency voltage signal and high-frequency pulse signal respectively, the 50Hz power frequency voltage signal corresponds to the low-pass filter unit 21, and the high-frequency pulse signal corresponds to the high-pass filter unit 22, and the output end of the voltage follower unit 12 is connected to the input terminal of the low-pass filter unit 21 through a single-core shielded wire.

[0077] The low-pass filter unit 21 adopts a second-order RC low-pass filter circuit, and a low-pass resistor 211 is arranged inside, and a corresponding low-pass capacitor is connected in parallel through a welding point, and is specially arranged for processing the power frequency voltage signal. The high-pass filter unit 22 adopts a similar structure, and a high-pass capacitor group 221 is fixedly connected inside, and a high-pass resistor is connected in parallel through a welding point. In the scheme, the cutoff frequency of the high-pass filter unit 22 can be 100Hz, and can also be adjusted according to the actual situation, so as to separate the pulse signal.

[0078] The low-pass filter unit 21 receives the power frequency voltage signal delivered by the voltage follower unit 12, and after processing, is connected to the input terminal of the program-controlled discharge module 3 through the output end lead, and the high-pass filter unit 22 receives the high-frequency pulse signal delivered by the voltage follower unit 12, and after processing, is connected to the pulse detection module 4 through the output end lead.

[0079] The program-controlled discharge module 3 receives the power frequency voltage signal output by the low-pass filter unit 21, and internally integrates a first amplification unit 31 and a second amplification unit 32. The first amplification unit 31 preliminarily amplifies the input signal through a gain-adjustable circuit, and the output end is connected to the input end of the second amplification unit 32 through a 10cm shielded lead. In the scheme, the first amplification unit 31 and the second amplification unit 32 respectively adopt PGA103 and AD526. Compared with the conventional instrument amplifier composed of ordinary operational amplifiers, both of them provide laser adjustment resistance and other single-chip integrated circuit technologies, so that its active and passive devices are placed on the same chip, and the analog ground and the digital ground are arranged separately, and these devices can be well matched, so that the amplifier has high common-mode rejection. In addition, these devices can maintain matching in a large temperature range, so as to ensure the excellent performance of the instrument amplifier in the whole temperature range.

[0080] The program-controlled discharge module 3 also has a first single-chip microcomputer control signal port 33 and a second single-chip microcomputer control signal port 34, and the two signal control ports respectively input corresponding control signals into PGA103 and AD526, and provide preliminary instruction signals. In the scheme, I2C communication protocol can be selected to receive preset parameters, such as discharge time, current amplitude, etc. The output end of the program-controlled discharge module 3 is connected to the single-chip microcomputer assembly through the No.8 VSEN pin for data acquisition.

[0081] The pulse detection module 4 utilizes the method of resistance voltage division to provide the internal voltage comparator 4 with a voltage comparison reference, so as to convert single exponential or double exponential waveforms into positive square wave level signals through positive or negative comparators. The pulse detection module 4 is also provided with a corresponding matching voltage division resistor 41 for completing the entire pulse detection process.

[0082] The output pin of the voltage comparator 42 in the present scheme is transmitted to the single-chip microcomputer assembly through an SPI interface.

[0083] Embodiment 3

[0084] With reference to Figures 1-7 The present embodiment is based on the previous embodiment, and is different from the previous embodiment in that:

[0085] The data acquisition method involved in the present scheme is applicable to the signal acquisition and frequency division processing circuit mentioned in embodiments 1 and 2, and is applicable to current signal monitoring and analysis in power systems. The method realizes accurate calculation of M-cycle current effective value and amplitude by presetting an initial programmable gain amplifier (PGA) test value, combining a multi-stage determination threshold and dynamically adjusting the PGA setting value.

[0086] The core of the present data acquisition method is to collect and process input signals by using the signal acquisition and frequency division processing circuit, and then analyze the M-cycle current signal by using an adaptive software algorithm. The implementation process starts with presetting an initial PGA test value, which is set by the gain parameter initialized by the single-chip microcomputer assembly. The initial PGA test value is calculated from the analog signal collected by an analog-to-digital converter (ADC) to obtain the effective value and test amplitude of the M-cycle current, and the test amplitude is the maximum absolute value. The calculation result is used as the basic data for subsequent determination.

[0087] Next, the determination thresholds of the M-cycle current amplitude are 100 mA, 8 mA and 0.2 mA, which are three-stage thresholds. These thresholds are stored in the flash memory of the single-chip microcomputer and are dynamically adjusted according to the application scenario. The single-chip microcomputer compares the actual amplitude with the preset threshold to determine the appropriate PGA setting value, and finally calculates the final effective value and amplitude of the M-cycle current amplitude.

[0088] The determination process of the present acquisition method adopts a hierarchical comparison mechanism. The initial comparison uses a threshold of 100 mA. The single-chip microcomputer reads the actual amplitude and compares it with the first-stage threshold of 100 mA. If the actual amplitude is greater than 100 mA, it indicates that the signal amplitude is high, and the system sets the PGA setting value = 1 to avoid signal overload. Then, the system enters the final calculation stage, and the ADC re-samples and calculates the final effective value and amplitude of the M-cycle current.

[0089] If the actual amplitude is less than 100 mA, the system continues to compare the actual amplitude with the second threshold value 8 mA. If the actual amplitude is greater than 8 mA, it indicates that the signal is in the medium amplitude range, the system sets the PGA value = 4, enhances the signal strength and enters the final calculation stage.

[0090] If the actual amplitude is less than 8 mA, the system is further compared with the third threshold value 0.2 mA. If the actual amplitude is greater than 0.2 mA, it indicates that the signal amplitude is low, the system sets the PGA value = 80 to improve the resolution of weak signals, and then enters the final calculation.

[0091] If the actual amplitude is less than 0.2 mA, the system judges it as a very low amplitude signal, sets the PGA value = 1600 to maximize the amplified signal to ensure detectability, and then performs the final calculation.

[0092] The data acquisition method realizes significant technical advantages through hierarchical determination and dynamic PGA adjustment. First, it adapts to the acquisition needs of a wide range of current signals, from weak signals to high amplitude signals, and can accurately measure them, filling the limitations of traditional fixed gain methods. The three-stage threshold design optimizes gain matching, reduces signal saturation and noise amplification, and significantly improves measurement accuracy. The mechanism of real-time adjustment of the PGA value enhances the adaptability of the system, especially for dynamic industrial environments.

[0093] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and not to limit it. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the present application, which should be covered by the scope of the claims of the present application.

Claims

1. A signal acquisition frequency division processing circuit, characterized by: The signal acquisition and frequency division processing circuit comprises a voltage input module (1), a filter module (2), a program-controlled discharge module (3) and a pulse detection module (4). The voltage input module (1) provides voltage signal acquisition and follow-up, and is connected to the filter module (2) in two ways for voltage signal processing. The filter module (2) is divided into two ways, and after signal filtering, it is connected to the program-controlled discharge module (3) and the pulse detection module (4) respectively. The program-controlled discharge module (3) controls the discharge time and current amplitude according to the preset parameters, and the output end is transmitted to the single-chip microcomputer assembly through the data bus. The pulse detection module (4) detects the amplitude and frequency of the pulse signal and generates digital pulse data, and the output end is connected to the single-chip microcomputer assembly for data acquisition.

2. The signal acquisition and frequency division processing circuit according to claim 1, wherein the voltage input module (1) comprises a voltage acquisition unit (11) and a voltage follow-up unit (12); the voltage acquisition unit (11) is externally connected to a corresponding voltage transformer, acquires a transformer voltage signal, and inputs the voltage follow-up unit (12) through corresponding terminals of J1; and the voltage follow-up unit (12) provides high-to-low impedance conversion, reduces signal transmission loss, and converts the signal for processing by the filter module (2).

3. The signal acquisition and frequency division processing circuit according to claim 1, wherein the filter module (2) is provided with a low-pass filter unit (21) and a high-pass filter unit (22) to separate double signals and suppress external interference; the output end of the voltage follow-up unit (12) is connected to the input terminal of the low-pass filter unit (21) through a single-core shielded wire; the low-pass filter unit (21) is provided with a low-pass resistor (211) in it, and the low-pass resistor (211) is connected in parallel with a low-pass capacitor through a welding point; and the low-pass filter unit (21) receives the power frequency voltage signal delivered by the voltage follow-up unit (12), processes it, and then connects it to the input terminal of the program-controlled discharge module (3) through an output end lead.

4. The signal acquisition and frequency division processing circuit according to claim 3, wherein the high-pass filter unit (22) is fixedly connected with a high-pass capacitor group (221) in it, and the high-pass capacitor group (221) is connected in parallel with a high-pass resistor through a welding point; and the high-pass filter unit (22) receives the high-frequency pulse signal delivered by the voltage follow-up unit (12), processes it, and then connects it to the pulse detection module (4) through an output end lead.

5. The signal acquisition and frequency division processing circuit according to claim 4, wherein the program-controlled discharge module (3) is provided with a first amplification unit (31) and a second amplification unit (32); the first amplification unit (31) and the second amplification unit (32) are respectively connected to a first single-chip microcomputer control signal port (33) and a second single-chip microcomputer control signal port (34) through multi-core shielded wires; the output pin of the first amplification unit (31) is connected to the input pin of the second amplification unit (32), and the output pin of the second amplification unit (32) is transmitted to the single-chip microcomputer assembly through a data bus.

6. The signal acquisition and frequency division processing circuit according to claim 5, wherein the pulse detection module (4) comprises a voltage divider resistor (41) and a voltage comparator (42). ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The voltage dividing resistor (41) provides a voltage comparison reference, and cooperates with the voltage comparator (42) to convert the exponential waveform into a square wave level signal; The output pin of the voltage comparator (42) is transmitted to the single-chip microcomputer assembly through a data bus.

7. A data acquisition method characterized by: The signal acquisition and frequency division processing circuit of claim 6, and An initial PGA test value is preset, and the M-cycle current effective value and test amplitude are calculated according to the initial PGA test value; A determination threshold of the M-cycle current amplitude is preset, and the determination threshold is compared with the actual amplitude; According to the comparison result, a corresponding PGA fixed value is set, and the final effective value and amplitude of the M-cycle current amplitude are calculated.

8. The data acquisition method of claim 7, wherein: In the determination threshold setting process of the M-cycle current amplitude, The threshold is adjusted to three orders of 100 MA, 8 MA and 0.2 MA, and the determination threshold is compared with the actual amplitude in the order; When the actual amplitude is greater than 100 MA, the PGA fixed value is set to 1, and the final calculation is entered; When the actual amplitude is less than 100 MA, the actual amplitude and 8 MA are determined; When the actual amplitude is greater than 8 MA, the PGA fixed value is set to 4, and the final calculation is entered; When the actual amplitude is less than 8 MA, the actual amplitude and 0.2 MA are determined; When the actual amplitude is greater than 0.2 MA, the PGA fixed value is set to 80, and the final calculation is entered; When the actual amplitude is less than 0.2 MA, the PGA fixed value is set to 1600, and the final calculation is entered.

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