Novel sputtering wafer precision testing machine and self-adaptive testing method thereof

Abstract

The invention belongs to the technical field of quartz crystal resonator manufacturing, and particularly discloses a novel sputtering wafer precision test machine and a self-adaptive test method thereof, a lower electrode probe of a lower layer test module is fixed below a test seat, a test seat array is provided with a plurality of test heads, and the lower electrode probe and the test heads are arranged in a one-to-one correspondence manner; the upper electrode probes of the upper-layer test module are arranged above the test heads in a one-to-one correspondence manner and can be driven to synchronously move so as to be close to or far away from the test seat; the tester is used for sending a set sweep frequency signal to the to-be-tested wafer to excite the to-be-tested wafer, and is also used for receiving a set signal sent by the excited to-be-tested wafer and calculating set parameters of the to-be-tested wafer; multiple wafers can be tested at the same time through the array type test head and the synchronously-driven upper electrode probe, the intelligent equivalent circuit model and the self-adaptive algorithm are matched, the test efficiency is effectively improved, and the measurement precision is enhanced.

Description

Technical Field

[0001] This invention belongs to the field of quartz crystal resonator manufacturing technology, and particularly relates to a novel precision testing machine for sputtered wafers and its adaptive testing method. Background Technology

[0002] As semiconductor technology advances towards the nanoscale, the continuous shrinking of feature sizes means that even small fluctuations in chip parameters can significantly impact device performance. Therefore, stringent standards are imposed on frequency measurement accuracy and parameter consistency testing. To ensure product yield, high-frequency sampling inspections are required for key parameters such as the chip's resonant frequency, impedance, and dielectric constant.

[0003] However, existing measurement technologies still suffer from numerous bottlenecks: manual probe-based measurements on individual chips are inefficient, with single measurement cycles lasting several minutes, completely failing to meet the rapid testing requirements of modern production lines; human operation inevitably introduces positioning deviations, severely impacting the reliability of measurement data; as chip sizes shrink to millimeter levels and below, it becomes difficult to precisely align the micrometer-level test electrodes with the naked eye, easily leading to probe misalignment or chip breakage, which not only reduces measurement accuracy and stability but also increases production costs. Furthermore, existing testing equipment lacks intelligent parameter calculation capabilities, requiring manual processing of test results, further reducing testing efficiency. These technological shortcomings severely restrict the development of sputtered chip manufacturing towards intelligence and efficiency, urgently necessitating innovative measurement technologies to overcome existing limitations.

[0004] To address the aforementioned issues, existing technologies urgently need improvement. Summary of the Invention

[0005] The purpose of this invention is to provide a novel precision testing machine for sputtered wafers and its adaptive testing method to solve the problems of low testing efficiency, poor measurement accuracy and stability in existing technologies.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows: a novel precision testing machine for sputtered wafers, wherein the upper testing module includes an upper electrode probe; the lower testing module includes a test stand and a lower electrode probe, the lower electrode probe being fixedly disposed on the lower side of the test stand, the test stand array being provided with multiple test heads, the number of lower electrode probes being the same as the number of test heads and their positions corresponding one-to-one; multiple upper electrode probes are provided corresponding to the number of test heads, the multiple upper electrode probes being disposed one-to-one above the test heads, the multiple upper electrode probes being synchronously moved in a vertical direction in a drivable manner to approach or move away from the test stand; it also includes a tester, the tester being electrically connected to the upper testing module and the lower testing module, the tester sending a set sweep frequency signal to the wafer under test through the upper testing module and the lower testing module to excite the wafer under test, the tester is also used to receive the set signal emitted by the excited wafer under test, and calculate the set parameters of the wafer under test based on the set signal emitted by the excited wafer under test.

[0007] Furthermore, the upper test module also includes an upper test board with an integrated switching circuit. Multiple upper electrode probes are fixedly mounted on the bottom surface of the upper test board and electrically connected to the test circuit. The tester controls any upper electrode probe to release a sweep frequency signal through the test circuit of the upper test board.

[0008] Furthermore, it also includes a drive unit, which includes a fixed base and a lifting arm mounted on the fixed base. The lower electrode probe and the test base are installed sequentially from bottom to top on the top surface of the fixed base. The lifting arm is provided with a lifting claw, and the upper test plate is mounted on the lifting claw. The lifting claw can be driven to move in the vertical direction, and the upper test plate moves accordingly so that the upper electrode probe moves closer to or further away from the test base.

[0009] Furthermore, the tester integrates an equivalent circuit model of the chip under test.

[0010] Furthermore, an adaptive testing method for sputtered wafers, based on the novel sputtered wafer precision testing machine described above, includes the following steps:

[0011] S1. Data Preprocessing:

[0012] S11. First, eliminate parasitic parameters by means of open circuit calibration and / or short circuit calibration, and then install the set number of sputtered wafers to be tested into the test head of the test holder one by one.

[0013] S12. Sampling: A sweep frequency signal is sent to any chip under test through the switching circuit of the tester, and the impedance amplitude |Z| corresponding to different sweep frequency signals is extracted.

[0014] S2. Extract the resonant frequency using the three-point interpolation method:

[0015] S21. Extract the series resonant frequency f sThree consecutive frequency points f are selected near the minimum value of impedance amplitude |Z|. 11 f 21 and f 31 The corresponding impedance amplitudes are |Z 11 |,|Z 21 | and |Z 31 |; The resonant frequency f is obtained by fitting a quadratic function. s ;

[0016] S22. Extract the parallel resonant frequency f p Three consecutive frequency points f are selected near the minimum value of impedance amplitude |Z|. 12 f 22 and f 32 The corresponding impedance amplitudes are |Z 12 |,|Z 22 | and |Z 32 |; The resonant frequency f is obtained by fitting a quadratic function. p .

[0017] S3. Input the extracted resonant frequency into the equivalent circuit model to calculate the parameters:

[0018] S31, The static capacitance C0 is obtained according to the following formula:

[0019]

[0020] Among them, f min Im is the minimum frequency value in the input swept frequency signal. (Zmin) f min The imaginary part of the corresponding impedance value;

[0021] S32. Calculate the following dynamic parameters in sequence:

[0022] The real part of the impedance R at the resonant point m It is obtained from the following formula:

[0023]

[0024] Among them, Re(Z) (fs) f is the series resonant frequency. s The real part of the impedance value at that location;

[0025] Dynamic capacitor C m It is obtained from the following formula:

[0026]

[0027] Dynamic inductance L m The following formula is used to obtain:

[0028]

[0029] S4. Verification:

[0030] The theoretical curve of the equivalent circuit model was generated and compared with the measured data to confirm that the error value was less than 1%; then, the theoretical series resonant frequency f was deduced from the measured data. s 理论 And the theoretical parallel resonant frequency f p 理论 and f s with f s 理论 and f p with f p 理论 In comparison, the deviation values ​​were all less than 0.001MHz;

[0031] If either the error value or the deviation value does not meet the expected value, proceed to step S5; otherwise, proceed to step S6.

[0032] Among them, f s 理论 It is obtained from the following formula:

[0033]

[0034] f p 理论 It is obtained from the following formula:

[0035]

[0036] S5. Reduce the sweep step size and / or re-extract the series resonant frequency f using the five-point interpolation method. s and / or parallel resonant frequency f p And repeat steps S3-S4;

[0037] S6. Repeat steps S2-S4 until all sputtered wafers to be tested have been tested, and then output the measured parameters.

[0038] The beneficial effects of this technical solution are as follows:

[0039] Simultaneous testing of multiple wafers is achieved through an array-type test head and synchronously driven upper electrode probes. Combined with an intelligent equivalent circuit model and adaptive algorithm, it solves the problems of low efficiency, large positioning deviation, and cumbersome data processing of manual operation. It has the advantages of improving testing efficiency, enhancing measurement accuracy, and realizing intelligent parameter calculation. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the structure of a novel precision testing machine for sputtered wafers according to the present invention;

[0041] Figure 2This is a front view of a novel precision testing machine for sputtered wafers according to the present invention;

[0042] Figure 3 This is a schematic diagram of the drive unit of the present invention;

[0043] Figure 4 This is a side view of the upper-level test module of the present invention;

[0044] Figure 5 This is a schematic diagram of the structure of the lower electrode probe of the present invention;

[0045] Figure 6 This is a front view of the structure of the test socket of the present invention;

[0046] Figure 7 This is a schematic diagram of the circuit structure of the equivalent circuit model of the present invention;

[0047] Figure 8 This is a hardware circuit block diagram of the tester of the present invention. Detailed Implementation

[0048] The following detailed description illustrates the specific implementation method:

[0049] The reference numerals in the accompanying drawings include: 1. Tester; 2. Upper test plate; 3. Test base; 4. Fixed base; 5. Lifting arm; 6. Lower electrode probe; 7. Upper electrode probe; 8. Display screen; 9. Operation buttons; 10. Lifting claw; 11. Test head.

[0050] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] The basic implementation examples are as follows: Figure 1The image shows a novel precision testing machine for sputtered wafers. The upper testing module includes an upper electrode probe 7; the lower testing module includes a test stand 3 and lower electrode probes 6. The lower electrode probes 6 are fixedly disposed on the lower side of the test stand 3. The test stand 3 is arrayed with multiple test heads 11, the number of lower electrode probes 6 and the number of test heads 11 being the same and their positions corresponding one-to-one. Multiple upper electrode probes 7 are arranged corresponding to the number of test heads 11, each positioned above a test head 11. These multiple upper electrode probes 7 can be driven to move synchronously in the vertical direction to approach or move away from the test stand 3. The machine also includes a tester 1, which is electrically connected to both the upper and lower testing modules. The tester 1 sends a set sweep frequency signal to the wafer under test (WUT) through the upper and lower testing modules to excite the WUT. The tester 1 also receives the set signal emitted by the excited WUT and calculates the set parameters of the WUT based on the set signal emitted by the excited WUT. In a preferred embodiment, the test heads 11 can be arranged in a rectangular or circular array, with a rectangular array being preferred in this embodiment. The spacing between adjacent test heads 11 can be adjusted according to the size of the wafer under test. The tester 1 can include a vector network analyzer or an impedance analyzer, the frequency range of which needs to cover the operating frequency range of the wafer under test. The frequency range of the sweep signal can be adjusted according to the characteristics of the wafer under test. The calculation function of the tester 1 can be implemented through a built-in DSP or FPGA, and the calculation speed needs to meet real-time requirements. By setting multiple synchronously moving upper electrode probes 7 and fixed lower electrode probes 6, parallel testing of multiple sputtered wafers is achieved, significantly improving testing efficiency. The synchronous movement design of the upper electrode probes 7 avoids positioning deviations caused by manual operation, ensuring the reliability of test data. The array design of the test holder 3 makes precise alignment of micron-level electrodes possible, reducing the risk of probe misalignment or wafer breakage. The automated signal excitation and parameter calculation functions of the tester 1 eliminate the influence of human factors on the measurement results, improving measurement accuracy and stability. This tester is particularly suitable for the high-precision, high-efficiency testing needs of sputtered wafers with millimeter-level and smaller dimensions.

[0052] In this embodiment, the upper test module also includes an upper test board 2 with an integrated switching circuit. Multiple upper electrode probes 7 are fixedly mounted on the bottom surface of the upper test board 2 and electrically connected to the test circuit. The tester 1 controls any upper electrode probe 7 to release a sweep frequency signal through the test circuit of the upper test board 2. As a preferred embodiment, the upper test board 2 adopts a multi-layer printed circuit board structure, where the switching circuit uses a matrix switch to select the signal path, specifically including a relay array or semiconductor switching devices. The test circuit includes a signal conditioning module for impedance matching and noise suppression. The upper electrode probe 7 achieves elastic contact with the upper test board 2 through spring pins or a microelectromechanical system (MEMS) structure, ensuring reliable electrical connection. By integrating the switching function with the test structure through integrated design, the positioning deviation problem caused by manual operation is solved. The upper test board 2, as a rigid carrier, ensures the spatial consistency of the probe array, and the switching circuit achieves automatic multi-channel selection, thereby significantly improving measurement efficiency and positioning accuracy. Specifically, by replacing manual intervention with a preset circuit path, visual alignment errors are avoided, while the number of mechanical contacts is reduced, thereby reducing the risk of fragment breakage and improving test stability.

[0053] In this embodiment, a drive unit is also included. The drive unit includes a fixed base 4 and a lifting arm 5 mounted on the fixed base 4. The lower electrode probe 6 and the test seat 3 are mounted sequentially from bottom to top on the top surface of the fixed base 4. The lifting arm 5 is provided with a lifting claw 10, and the upper test plate 2 is mounted on the lifting claw 10. The lifting claw 10 can be driven to move vertically, and the upper test plate 2 moves accordingly to make the upper electrode probe 7 move closer to or away from the test seat 3. Specifically, the fixed base 4 in the drive unit is used to provide a stable mounting base. The lifting arm 5 is fixed to the fixed base 4 by a mechanical connection. In this embodiment, the fixed base 4 is detachably mounted on the top surface of the tester 1, so that the two are organically combined, which facilitates testing and data verification. The lifting claw 10 adopts a precision linear guide mechanism, and the lead screw is driven by a servo motor or stepper motor to achieve precise vertical displacement control. The upper test plate 2 and the lifting claw 10 are rigidly connected to ensure that no horizontal offset occurs during the lifting process. As a preferred embodiment, the lifting arm 5 can be equipped with an optical encoder to provide real-time feedback of position information, forming a closed-loop control system to further improve positioning accuracy. The automated and precise positioning of the upper electrode probe 7 is achieved through an integrated mechanical drive structure. The rigid connection between the fixed base 4 and the lifting arm 5 effectively avoids the mechanical vibration problems inherent in traditional manual operation; the closed-loop control mechanism of the lifting claw 10 eliminates positioning errors caused by transmission gaps; and through optimized mechanical structure design, testing efficiency is significantly improved while ensuring testing accuracy. In this embodiment, both the lower electrode probe and the test base are fixedly installed. The lower electrode probes are electrically connected to the test head one-to-one. The upper electrode probe is driven close to the test head (i.e., the wafer under test). The upper electrode probe can lightly touch the wafer under test or not directly contact it; a gap exists between them. After the upper and lower electrode probes discharge, a piezoelectric effect is formed. Combined with an equivalent circuit model, the testing of the sputtered wafer under test can be completed.

[0054] In this embodiment, the test instrument 1 integrates an equivalent circuit model of the chip under test. As a preferred embodiment, the test instrument 1 also incorporates a signal generator for transmitting sweep signals, a voltage amplifier, a phase detection device, an analog-to-digital converter, and an MCU (microcontroller unit), such as... Figure 8 As shown, the sweep signal generated by the signal generator is amplified and then simultaneously applied to the crystal under test and the equivalent circuit model. The equivalent circuit undergoes phase detection via a phase detection device, and after analog-to-digital conversion, the signal is finally input to the MCU. Specifically, the equivalent circuit model can adopt a modified Butterworth-Van Dyke model (BVD model), including a parallel structure of static capacitor C0, dynamic capacitor Cm, dynamic inductor Lm, and dynamic resistor Rm, as shown below. Figure 7 As shown; the impedance function of the equivalent circuit model is:

[0055]

[0056] By fitting the measured impedance data into this model using the least squares method, R can be extracted. m L m C m Parameters such as C0;

[0057] In a preferred implementation, the signal generator preferably employs direct digital frequency synthesis technology. The voltage amplifier uses a wideband operational amplifier with an adjustable gain range of 20dB to 60dB. The phase detection device is implemented through a quadrature demodulation circuit, achieving a phase measurement accuracy better than 0.1 degrees. The analog-to-digital converter uses a resolution of 16 bits or higher, with a sampling rate of no less than 10MSPS. The MCU incorporates a digital filtering algorithm to calculate impedance parameters in real time. By integrating the equivalent circuit model into the test instrument 1, synchronous excitation and comparison between the wafer under test and the reference model are achieved. The specific workflow is as follows: the swept frequency signal is amplified and simultaneously applied to both the actual wafer and the equivalent model. By comparing the phase response differences between the two, wafer parameter deviations can be quickly identified. The equivalent circuit model serves as a calibration benchmark, effectively eliminating inherent errors in the test system; the synchronous detection mechanism avoids time errors introduced by traditional sequential measurements; and the digital processing improves the accuracy of parameter calculation. Compared with existing technologies, this scheme significantly improves the accuracy of resonant frequency detection, and is particularly suitable for high-precision parameter measurement of micro-sized sputtered wafers.

[0058] This embodiment also provides an adaptive testing method for sputtered wafers. This testing method is based on the novel sputtered wafer precision testing machine described above, and specifically includes the following steps:

[0059] S1. Data Preprocessing:

[0060] S11. First, eliminate the parasitic parameters of the aforementioned precision testing machine by means of open circuit calibration and / or short circuit calibration. Then, install the set number of sputtered wafers to be tested one by one into the test head 11 of the test holder 3. The specific number of sputtered wafers to be tested can be adjusted according to the actual testing requirements to match the number of test heads 11. The number of tests in a single test shall not exceed the total number of test heads 11.

[0061] S12. Sampling: A sweep frequency signal is sent to any chip under test through the switching circuit of tester 1, and the impedance amplitude |Z| corresponding to different sweep frequency signals is extracted; during sampling, the sweep frequency step size is... (For example, with a 10MHz crystal, if Q = 10⁵, the step size ≤ 50Hz); and the number of sampling points ensuring that they fall near the resonant point is at least 5. The specific sampling point distribution in this embodiment is shown in Table 1:

[0062]

[0063] Table 1

[0064] S2. Extract the resonant frequency using the three-point interpolation method:

[0065] S21. Extract the series resonant frequency f s Three consecutive frequency points f are selected near the minimum value of impedance amplitude |Z|. 11 f 21 and f 31 The corresponding impedance amplitudes are |Z 11 |,|Z 21 | and |Z 31 |; The resonant frequency f is obtained by fitting a quadratic function. s Based on the sampling results in Table 1, the series resonant frequency f is extracted. s At that time, f 11 f 21 and f 31 These correspond to 9.998MHz, 9.999MHz, and 10.000MHz respectively; the corresponding |Z 11 |,|Z 21 | and |Z 31 The values ​​of | are 105Ω, 100Ω, and 102Ω, respectively. Assume that the impedance amplitude and frequency satisfy a quadratic relationship:

[0066] |Z(f)|=af 2 +bf+c;

[0067] Substituting the three points into the equations, we obtain the system of equations:

[0068]

[0069] After solving for a, b, and c, we take the derivative of the function and set the derivative to zero, resulting in the following equation:

[0070]

[0071] Substituting the coefficients, we obtain f. s ≈9.9992;

[0072] S22. Extract the parallel resonant frequency f p Three consecutive frequency points f are selected near the minimum value of impedance amplitude |Z|. 12 f 22 and f 32 The corresponding impedance amplitudes are |Z 12 |,|Z 22 | and |Z 32 |; The resonant frequency f is obtained by fitting a quadratic function. p In this embodiment, f 12 f 22 and f 32The values ​​are 10.002MHz, 10.003MHz, and 10.004MHz, respectively. 12 |、|Z 22 | and |Z 32 The values ​​of | are 1500Ω, 1800Ω, and 1750Ω respectively. The specific calculation process is the same as above and will not be repeated here;

[0073] Finally, f is obtained p ≈10.0034;

[0074] S3. Input the extracted resonant frequency into the equivalent circuit model to calculate the parameters:

[0075] S31, The static capacitance C0 is obtained according to the following formula:

[0076]

[0077] Among them, f min Im is the minimum frequency value in the input swept frequency signal. (Zmin) f min The corresponding impedance value Z min The imaginary part; in this embodiment, f min =9.990MHz, Z min =1.2-j1200Ω, and C0≈1.33pF is calculated;

[0078] S32. Calculate the following dynamic parameters in sequence:

[0079] The real part of the impedance R at the resonant point m It is obtained from the following formula:

[0080]

[0081] Among them, Re(Z) (fs) f is the series resonant frequency. s The real part of the impedance value at that location;

[0082] Dynamic capacitor C m It is obtained from the following formula:

[0083]

[0084] Dynamic inductance L m The following formula is used to obtain:

[0085]

[0086] S4. Verification:

[0087] The theoretical curve of the equivalent circuit model was generated and compared with the measured data to confirm that the error value was less than 1%; then, the theoretical series resonant frequency f was deduced from the measured data. s 理论 And the theoretical parallel resonant frequency f p 理论 and f s with f s 理论 and f p with f p 理论 In comparison, the deviation values ​​were all less than 0.001MHz;

[0088] If either the error value or the deviation value does not meet the expected value, proceed to step S5; otherwise, proceed to step S6.

[0089] Among them, f s 理论 It is obtained from the following formula:

[0090]

[0091] f p 理论 It is obtained from the following formula:

[0092]

[0093] S5. Reduce the sweep step size and / or re-extract the series resonant frequency f using the five-point interpolation method. s and / or parallel resonant frequency f p Repeat steps S3-S4; if the error value of the theoretical curve of the generated equivalent circuit model is consistently higher than or equal to 1% after comparing it with the measured data, then it is necessary to simultaneously re-extract the series resonant frequency f. s and parallel resonant frequency f p Then recalculate; if the deviation between the theoretical and measured values ​​of the series resonant frequency is greater than or equal to 0.001MHz, then it is only necessary to re-extract the series resonant frequency f. s Similarly, for parallel resonant frequencies, if either of the aforementioned two does not meet expectations, it should be re-extracted to save computation time and MCU computing power. If the theoretical series resonant frequency f... s 理论 And the theoretical parallel resonant frequency f p 理论 If the difference between the calculated result and the measured value meets the expectation, and the error value of the theoretical curve of the equivalent circuit model is less than 1% after comparison with historical books, then step S5 is skipped and step S6 is directly entered.

[0094] In this embodiment, reducing the sweep step size increases the data point density, and the five-point interpolation method uses least squares to achieve fourth-order polynomial fitting, improving the accuracy of the fitting results and ensuring the accuracy of the final test and calculation results. The verification phase employs a dual verification mechanism: first, the theoretical impedance curve of the equivalent circuit is generated and compared with the measured data in the frequency domain, requiring an error of no more than 1% across the entire frequency band. Second, the calculated data is used for back-calculation, and deviation verification is performed with the actual measured values, with a tolerance standard set at 0.001MHz. When any verification fails, the system automatically reduces the sweep step size and re-extracts the characteristic frequency using the five-point interpolation method. Specifically, the five-point interpolation method selects five consecutive frequency points and constructs an impedance-frequency relationship curve through fourth-order polynomial fitting. The polynomial coefficients are solved using the least squares method, thereby obtaining a more accurate resonant frequency estimate. During the testing process, all wafers use the same verification standard until all tests are completed.

[0095] S6. Repeat steps S2-S4 until all sputtered wafers to be tested have been tested, and then output the measured parameters. The tester 1 in this embodiment is also equipped with a display screen 8 and operation buttons 9. The final data is displayed on the display screen 8, and the operation buttons 9 can not only control the test process, but also switch the types of data displayed on the display screen 8.

[0096] This testing method effectively solves the problems of low efficiency and poor measurement consistency caused by manual operation by establishing a standardized parameter extraction process and combining three-point interpolation and equivalent circuit model verification mechanism. Specifically, the three-point interpolation method significantly improves the extraction accuracy of resonant frequencies through local frequency band fitting, while the step-by-step calculation strategy of dynamic parameters ensures the physical correlation between parameters. The verification process employs a dual verification mechanism, comparing the overall fit between measured and theoretical curves, and verifying the accuracy of key frequency parameters through a reverse calculation method. When a deviation is detected, a high-precision five-point interpolation mode is automatically triggered, thereby controlling the frequency measurement error within 0.001MHz while ensuring testing efficiency. This method significantly improves testing efficiency while maintaining measurement accuracy, and is particularly suitable for batch automated testing of sputtered wafers, avoiding random errors introduced by human operation through a standardized process.

[0097] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0098] The above descriptions are merely embodiments of the present invention. Commonly known structures and characteristics are not described in detail here. Those skilled in the art are aware of all common technical knowledge in the field prior to the application date or priority date, are aware of all existing technologies in that field, and have the ability to apply conventional experimental methods prior to that date. Those skilled in the art can, under the guidance of this application, improve and implement this solution in combination with their own capabilities. Some typical known structures or methods should not be obstacles for those skilled in the art to implement this application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the structure of the present invention. These should also be considered within the scope of protection of the present invention, and will not affect the effectiveness of the implementation of the present invention or the practicality of the patent. The scope of protection claimed in this application should be determined by the content of its claims, and the specific embodiments described in the specification can be used to interpret the content of the claims.

Claims

1. A novel precision testing machine for sputtered wafers, characterized in that, include: The upper-level test module includes the upper electrode probe; The lower-level testing module includes a test base and lower electrode probes. The lower electrode probes are fixedly disposed on the lower side of the test base. The test base array is provided with multiple test heads. The number of lower electrode probes is the same as the number of test heads, and their positions correspond one-to-one. Multiple upper electrode probes are provided corresponding to the number of test heads. The multiple upper electrode probes are disposed one-to-one above the test heads. The multiple upper electrode probes can be driven to move synchronously in the vertical direction to move closer to or away from the test base. The tester is electrically connected to the upper-layer test module and the lower-layer test module. The tester sends a set sweep frequency signal to the chip under test through the upper-layer test module and the lower-layer test module to excite the chip under test. The tester is also used to receive the set signal sent by the excited chip under test and calculate the set parameters of the chip under test based on the set signal sent by the excited chip under test.

2. The novel precision testing machine for sputtered wafers according to claim 1, characterized in that: The upper test module also includes an upper test board with an integrated switching circuit. The plurality of upper electrode probes are fixedly disposed on the bottom surface of the upper test board and electrically connected to the test circuit. The tester controls any one of the upper electrode probes to release a sweep frequency signal through the test circuit of the upper test board.

3. The novel precision testing machine for sputtered wafers according to claim 2, characterized in that: It also includes a drive unit, which includes a fixed base and a lifting arm mounted on the fixed base. The lower electrode probe and the test seat are installed sequentially from bottom to top on the top surface of the fixed base. The lifting arm is provided with a lifting claw. The upper test plate is mounted on the lifting claw. The lifting claw can be driven to move in the vertical direction. The upper test plate moves accordingly so that the upper electrode probe moves closer to or further away from the test seat.

4. A novel precision testing machine for sputtered wafers according to claim 2, characterized in that: The tester integrates an equivalent circuit model of the chip under test.

5. An adaptive testing method for sputtered wafers, the testing method being based on the novel sputtered wafer precision testing machine as described in any one of claims 1-4, characterized in that, Specifically, the following steps are included: S1, Data Preprocessing; S11. First, eliminate parasitic parameters by means of open circuit calibration and / or short circuit calibration, and then install the set number of sputtered wafers to be tested into the test head of the test holder one by one. S12. Sampling: A sweep frequency signal is sent to any chip under test through the switching circuit of the tester, and the impedance amplitude |Z| corresponding to different sweep frequency signals is extracted. S2. Extract the resonant frequency using the three-point interpolation method; S21. Extract the series resonant frequency f s Three consecutive frequency points f are selected near the minimum value of impedance amplitude |Z|. 11 f 21 and f 31 The corresponding impedance amplitudes are |Z 11 |,|Z 21 | and |Z 31 |; The resonant frequency f is obtained by fitting a quadratic function. s ; S22. Extract the parallel resonant frequency f p Three consecutive frequency points f are selected near the minimum value of impedance amplitude |Z|. 12 f 22 and f 32 The corresponding impedance amplitudes are |Z 12 |,|Z 22 | and |Z 32 |; The resonant frequency f is obtained by fitting a quadratic function. p . S3. Input the extracted resonant frequency into the equivalent circuit model to calculate the parameters: S31, The static capacitance C0 is obtained according to the following formula: Among them, f min Im is the minimum frequency value in the input swept frequency signal. (Zmin) f min The imaginary part of the corresponding impedance value; S32. Calculate the following dynamic parameters in sequence: The real part of the impedance R at the resonant point m It is obtained from the following formula: Among them, Re(Z) (fs) f is the series resonant frequency. s The real part of the impedance value at that location; Dynamic capacitor C m It is obtained from the following formula: Dynamic inductance L m The following formula is used to obtain: S4. Verification: The theoretical curve of the equivalent circuit model was generated and compared with the measured data to confirm that the error value was less than 1%; then, the theoretical series resonant frequency f was deduced from the measured data. s 理论 And the theoretical parallel resonant frequency f p 理论 and f s with f s 理论 and f p with f p 理论 In comparison, the deviation values ​​were all less than 0.001MHz; If either the error value or the deviation value does not meet the expected value, proceed to step S5; otherwise, proceed to step S6. Among them, f s 理论 It is obtained from the following formula: f p 理论 It is obtained from the following formula: S5. Reduce the sweep step size and / or re-extract the series resonant frequency f using the five-point interpolation method. s and / or parallel resonant frequency f p And repeat steps S3-S4; S6. Repeat steps S2-S4 until all sputtered wafers to be tested have been tested, and then output the measured parameters.

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