Memory device and operating method thereof

Abstract

A memory device and an operating method thereof are provided. The memory device includes a plurality of nonvolatile memory devices and a memory controller configured to generate a first address and a program command corresponding to a plurality of word lines included in a first super block based on a sequential write request from a host; determining whether to allocate at least one sub-memory block included in the second super block based on data of a word line table, the data of the word line table indicating a word line having a relatively small program time and a first address; and generate at least one second address and at least one erase command corresponding to the allocated at least one sub-memory block to perform an erase operation.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0075289, filed on June 10, 2024, with the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0142309, filed on October 17, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The inventive concept relates to an electronic device, and more specifically, to a storage device and its method of operation for reducing the difference in programming time between word lines and reducing peak power consumption due to erase operations. Background Technology

[0003] Semiconductor memory devices can include volatile memory devices and non-volatile memory devices. Volatile memory devices lose stored data when power is cut off. On the other hand, non-volatile memory devices retain stored data even when power is cut off. Because non-volatile memory devices (such as flash memory devices) are advantageous in terms of integration density, they are well-suited for storage devices requiring large capacities. To increase the capacity of non-volatile memory devices, the process technology has become more refined, and the number of memory blocks in the non-volatile memory device has increased, as has the size of each memory block. As the size of the memory blocks increases, the number of word lines within each memory block also increases, which can lead to differences in programming time between word lines. These differences in programming time between word lines can degrade the data reliability of the non-volatile memory device. Summary of the Invention

[0004] The inventive concept provides a storage device and a method thereof for providing consistent throughput and latency and assigning erase operations to each chip or die.

[0005] According to one embodiment, a storage device includes: a plurality of non-volatile memory devices, each non-volatile memory device including a plurality of memory blocks; and a storage controller configured to provide commands and addresses to a target non-volatile memory device among the plurality of non-volatile memory devices, wherein the storage controller is configured to: receive a write request from a host; generate a programming command and a first address based on the write request from the host, wherein the first address corresponds to a target word line of a first target non-volatile memory device; determine whether to allocate a first target memory block of a second target non-volatile memory device based on a word line table and the target word line of the first address regardless of the request from the host, wherein the word line table includes first data indicating the first word line, wherein the programming time required to program the first word line is less than the reference programming time required to program each word line of the plurality of memory blocks; and, upon determining to allocate the first target memory block, generate an erase command and a second address, wherein the second address corresponds to the first target memory block.

[0006] According to one embodiment, a method of operating a storage device includes: generating a programming command and a first address based on a write request from a host, wherein the first address corresponds to a target word line included in a first superblock; determining whether to allocate a first target memory block included in a second superblock based on a word line table and the target word line of the first address, wherein the word line table includes data indicating word lines, wherein the programming time of each word line is less than a reference programming time; generating a second address and an erase command corresponding to the first target memory block; and scheduling the programming command, the first address, the erase command, and the second address in a scheduling order, wherein the first superblock and the second superblock operate in an interleaved manner.

[0007] According to one embodiment, a storage device includes: a plurality of first non-volatile memory devices, each including a first superblock; a plurality of second non-volatile memory devices, each including a second superblock, wherein the first and second superblocks operate in an interleaved manner; and a storage controller configured to provide commands and addresses to the plurality of first non-volatile memory devices and the plurality of second non-volatile memory devices, wherein the storage controller is further configured to: generate a first address and a programming command based on a sequential write request from a host to sequentially perform programming operations on the first superblock; determine, based on data from a word line table and a first address of a target word line, whether to allocate at least one first target sub-memory block included in the second superblock independently of a request from the host, wherein the word line table includes data indicating the first word lines, wherein the programming time required to program each of the first word lines is less than the reference programming time required to program each word line of the plurality of sub-memory blocks included in the first and second superblocks; and when the at least one first target sub-memory block is allocated for an erase operation, generate at least one second address and at least one erase command corresponding to the allocated at least one first target sub-memory block.

[0008] According to the inventive concept, device performance can be improved by providing consistency in device throughput and latency.

[0009] Furthermore, by reducing the long delays in programming operations that require relatively long programming times, device reliability can be guaranteed.

[0010] Furthermore, by distributing erase operations across chips or dies, peak power consumption during erase operations can be reduced, thereby reducing overall power consumption. Attached Figure Description

[0011] The embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 This is a block diagram of a memory system according to an embodiment.

[0013] Figure 2 This is a block diagram of a non-volatile memory device according to an embodiment.

[0014] Figure 3 This is a circuit diagram of a memory block according to an embodiment.

[0015] Figure 4 This is a block diagram of multiple superblocks according to an embodiment.

[0016] Figure 5 This is a graph showing the programming time of the word line according to an embodiment.

[0017] Figure 6This is a diagram illustrating an example of a word line table according to an embodiment.

[0018] Figure 7 This is a flowchart of the operation of generating a word line table according to an embodiment.

[0019] Figure 8 This is a flowchart of the operation of the storage device according to an embodiment.

[0020] Figure 9A , Figure 9B and Figure 9C This is a diagram illustrating a sequential write operation performed on a superblock and an erase operation performed on a sub-memory block of another superblock.

[0021] Figure 10 This is a diagram illustrating a word line table according to an embodiment.

[0022] Figure 11 This is a flowchart of the operation of the storage device according to an embodiment.

[0023] Figure 12 This is a flowchart of an operation method of a storage device according to an embodiment.

[0024] Figure 13 This is a block diagram of a host storage system according to an embodiment.

[0025] Figure 14 This is a diagram of a data center that utilizes memory devices. Detailed Implementation

[0026] The embodiments are described in detail below with reference to the accompanying drawings.

[0027] The terms “first,” “second,” and “third” as used herein may refer to various different components, regardless of their order and / or importance, and may be used to distinguish one component from another, but do not limit the components. For example, a first user device and a second user device may refer to different user devices, regardless of their order or importance. Without departing from the scope of the claims described herein, in different embodiments, a first component may be referred to as a second component, and a second component may be referred to as a first component.

[0028] Figure 1 This is a block diagram of the memory system 15 according to an embodiment.

[0029] Reference Figure 1The memory system 15 may include a memory device 17 and a memory controller 16. The memory system 15 may support multiple channels CH. The multiple channels may include a first channel CH1 to an m-th channel CHm, where m is a natural number greater than 2. Each of the multiple channels CH may include multiple paths. The multiple paths included in each channel may include a first path to an n-th path, in which each non-volatile memory device is connected to a corresponding channel via a corresponding path in the first path to the n-th path, where n is a natural number greater than 2. The memory device 17 may be connected to the memory controller 16 via the multiple channels CH. The memory system 15 may be a storage device (such as a solid-state drive (SSD)).

[0030] Memory device 17 may include a plurality of non-volatile memory devices NVM. The plurality of non-volatile memory devices may include first non-volatile memory devices NVM11 to mn-th non-volatile memory devices NVMmn. Each of the plurality of non-volatile memory devices NVM can be connected to one of a plurality of channels CH via a corresponding path. For example, non-volatile memory devices NVM11 to NVM1n can be connected to the first channel CH1 via paths W11 to W1n, non-volatile memory devices NVM21 to NVM2n can be connected to the second channel CH2 via paths W21 to W2n, ..., and non-volatile memory devices NVM m1 to NVM mn can be connected to the m-th channel CHm via paths Wm1 to Wmn. Each of the plurality of non-volatile memory devices NVM can receive individual instructions from memory controller 16 and can operate independently according to the instructions. Each of the plurality of non-volatile memory devices NVM can be implemented in a single chip or in a single die. However, the inventive concept is not limited thereto. Each of the multiple non-volatile memory devices (NVMs) may include multiple dies.

[0031] The memory controller 16 may also be referred to as a memory controller. The memory controller 16 controls the overall operation of the memory device 17. The memory controller 16 can send signals to and receive signals from the memory device 17 through multiple channels CH. For example, the memory controller 16 can send a command CMD, an address ADDR, and data DATA to the memory device 17 for write operations of the memory device 17. During read operations of the memory device 17, the memory controller 16 can send a command CMD, an address ADDR, and receive data DATA from the memory device 17. Depending on the channel through which the memory controller 16 sends the command CMD, the command CMD can be one of CMDa to CMDm. Depending on the channel through which the memory controller 16 sends the address ADDR, the address ADDR can be one of ADDRa to ADDRm. Similarly, depending on the channels through which the memory controller 16 and the memory device 17 send and receive data DATA, the data DATA can be one of DATAa to DATAm. For example, the memory controller 16 can send two or more commands, addresses, and data to the memory device 17 for write operations of the memory device 17. For example, memory controller 16 can send two or more commands and addresses to memory device 17 for read operations of memory device 17.

[0032] The memory controller 16 can select a non-volatile memory device from a plurality of non-volatile memory devices via the corresponding channel to which the non-volatile memory device is connected, and send signals to and receive signals from the selected non-volatile memory device. The selected non-volatile memory device may be referred to as the target non-volatile memory device. The memory controller 16 can provide the command CMD and address ADDR to the target non-volatile memory device. For example, the memory controller 16 can select the non-volatile memory device NVM11 from the non-volatile memory devices NVM11 to NVM1n connected to the first channel CH1. The memory controller 16 can send the command CMDa, address ADDRa, and data DATAa to the selected non-volatile memory device NVM11 for a write operation of the selected non-volatile memory device NVM11, or the memory controller 16 can send the command CMDa and address ADDRa via the first channel CH1 and receive data DATAa from the selected non-volatile memory device NVM11 during a read operation of the selected non-volatile memory device NVM11.

[0033] The memory controller 16 can access non-volatile memory devices connected to different channels in parallel. For example, the memory controller 16 can send a command CMDb to a non-volatile memory device connected to a second channel CH2 for a read operation while simultaneously sending a command CMDa to the memory device connected to the first channel CH1 for a read operation, and the memory controller 16 can receive data DATAa from the non-volatile memory device connected to the first channel CH1 and data DATAb from the non-volatile memory device connected to the second channel CH2. Because the memory controller 16 can send commands and address signals and exchange data in parallel with non-volatile memory devices connected to different channels in an interleaving manner, the performance of the memory system 15 can be enhanced. When the memory device 17 operates in an interleaving manner, non-volatile memory devices selected across multiple channels CH can operate in parallel. For example, the memory controller 16 can send multiple commands CMD and addresses ADDR in parallel to non-volatile memory devices connected to different channels CH, and each of the non-volatile memory devices NVM receiving commands, addresses, and / or data can operate independently based on the received commands, addresses, and / or data. The operating periods of a non-volatile memory device (NVM) can overlap at least partially.

[0034] The memory controller 16 can control each of a plurality of non-volatile memory devices (NVMs) for write or read operations. For example, the memory controller 16 can provide data DATAa, command CMDa, and address ADDRa to a non-volatile memory device NVM11 connected to the first channel CH1 via the first channel CH1 to program DATAa into the non-volatile memory device NVM11. For example, the memory controller 16 can provide command CMDb and address ADDRb to a non-volatile memory device NVM21 connected to the second channel CH2 via the second channel CH2 to read data DATAb from the non-volatile memory device NVM21.

[0035] although Figure 1 The memory device 17 is shown to communicate with the memory controller 16 via m channels and the memory device 17 includes n non-volatile memory devices for each channel, but the number of channels and the number of non-volatile memory devices connected to a channel are not limited thereto.

[0036] Figure 2 This is a block diagram of a non-volatile memory device 200 according to an embodiment.

[0037] Reference Figure 2 The non-volatile memory device 200 can correspond to Figure 1One of a plurality of non-volatile memory devices (NVMs) in the system. The non-volatile memory device 200 may include a memory cell array 210, control logic 220, a voltage generator 230, a row decoder 240, and page buffer circuitry 250. The non-volatile memory device 200 may also include data input / output circuitry or an input / output interface.

[0038] The memory cell array 210 includes multiple memory cells, which are connected to a word line WL, a serial select line SSL, a ground select line GSL, and a bit line BL. More specifically, the memory cell array 210 can be connected to a row decoder 240 via the word line WL, the serial select line SSL, and the ground select line GSL, and can be connected to a page buffer circuit 250 via the bit line BL.

[0039] Memory cell array 210 may include multiple memory blocks BLK. The multiple memory blocks may include first memory block BLK1 through z-th memory block BLKz. Each of the multiple memory blocks BLK may have a three-dimensional structure in which memory cells are vertically stacked. Each of the multiple memory blocks BLK may include one or more memory stacks extending vertically from the surface of the substrate. Each memory block includes multiple NAND flash memory cell strings extending vertically (e.g., a third direction). Hereinafter, the multiple NAND flash memory cell strings are referred to as “cell strings”. Cell strings may be spaced apart from each other along the top surface of the substrate in a first direction and a second direction. Row decoder 240 may select memory blocks among the multiple memory blocks BLK to perform programming or reading operations on the selected memory blocks. More specifically, row decoder 240 may select memory blocks among the multiple memory blocks BLK based on the block address of address ADDR received from memory controller 16.

[0040] The memory cell array 210 may include multiple memory cells, each of which may store a different number of data bits. For example, each memory cell may be one of a single-level cell (SLC), a multi-level cell (MLC), and a three-level cell (TLC). An SLC may store one bit of data, an MLC may store two bits of data, and a TLC may store three bits of data. However, the inventive concept is not limited thereto, and the memory cell may be a four-level cell (QLC) that stores four bits of data.

[0041] Multiple memory blocks (BLKs) may include at least one of single-level cell blocks, multi-level cell blocks, three-level cell blocks, and four-level cell blocks. Single-level cell blocks may include SLCs, multi-level cell blocks may include MLCs, three-level cell blocks may include TLCs, and four-level cell blocks may include QLCs. A portion of the multiple memory block BLKs of the memory cell array 210 may include single-level cell blocks, and other portions of the multiple memory blocks may include multi-level cell blocks or three-level cell blocks.

[0042] An erase operation on a memory block of memory cell array 210 can be performed by applying an erase voltage to the memory block. When the erase operation is complete, the memory cells of the memory block can be in an erased state. Subsequently, a programming operation on the memory block of memory cell array 210 can be performed by receiving commands CMD, address ADDR, and data DATA from memory controller 16. For the programming operation, a word line is selected based on address ADDR, and a programming voltage is applied to the selected word line based on data DATA. When the programming operation is complete, the memory cell being programmed can be in a programmed state. The programming state and the erase state can be distinguished based on the threshold voltage of the programmed memory cell.

[0043] Control logic 220 receives commands CMD, address ADDR, and control signals CTRL from memory controller 16, and generates row address X-ADDR and column address Y-ADDR based on the received address. Word lines and bit lines can be selected for read or program operations based on row address X-ADDR and column address Y-ADDR. Control logic 220 also generates internal control signals for writing data DATA into or reading data DATA from memory cell array 210 based on commands CMD, address ADDR, and control signals CTRL.

[0044] Control logic 220 can provide internal control signals to voltage generator 230, line decoder 240, and page buffer circuit 250. For example, control logic 220 can provide the voltage control signal CTRL_vol to voltage generator 230.

[0045] Voltage generator 230 can generate word line voltage VWL and provide it to selected word lines. Voltage generator 230 can also generate several different voltages for programming, reading, and erasing operations on memory cell array 210 based on the voltage control signal CTRL_vol. Word line voltage VWL can be a programming voltage, a pass voltage, a verification voltage, or a read voltage.

[0046] According to an embodiment, voltage generator 230 can generate and provide programming voltage and verification voltage based on a voltage control signal CTRL_vol. The programming voltage and verification voltage can have different voltage levels in different programming cycles. Programming cycles are executed via Incremental Step Pulse Programming (ISPP), in which the programming voltage can increase with the number of programming cycles. For example, voltage generator 230 can provide a first programming voltage with a first voltage level for a first programming cycle and a second programming voltage with a second voltage level for a second programming cycle. When the first and second programming voltages are applied to the first and second programming cycles, the second voltage level can be higher than the first voltage level. A verification voltage can be applied to a selected word line after each of the first and second programming cycles to check whether the programming operation on the memory cell being programmed in the previous programming cycle has been completed or if an additional programming cycle is needed. Programming cycles in which programming voltage and verification voltage are applied to selected word lines can be repeated until the programmed memory cell is verified to be in the target programming state.

[0047] Voltage generator 230 generates programming voltage and verification voltage, and provides the programming voltage and verification voltage to a selected word line chosen from a plurality of word lines WL. The selected word line may include at least one word line selected by a row address X-ADDR generated in row decoder 240 based on address ADDR.

[0048] The line decoder 240 can select a word line among multiple word lines WL based on the line address X-ADDR received from the control logic 220. More specifically, during programming operations, the line decoder 240 can apply a programming voltage to the selected word line. The selected word line may also be referred to as the target word line. Furthermore, the line decoder 240 can select a cell string among multiple cell strings by applying a serial selection voltage on the selected serial selection line SSL and a ground selection voltage on the ground selection line GSL based on the line address X-ADDR received from the control logic 220.

[0049] Page buffer circuit 250 can be connected to memory cell array 210 via bit line BL. Page buffer circuit 250 can select the corresponding bit line in bit line BL based on the column address Y-ADDR received from control logic 220. Page buffer circuit 250 can operate as a sense amplifier to sense data DATA stored in memory cell array 210 during read and program operations. Page buffer circuit 250 can operate as a write driver to drive data DATA to be stored in memory cell array 210 during program operations.

[0050] Page buffer circuit 250 can store data DATA read from memory cell array 210, or temporarily store data DATA to be written to memory cell array 210. Under the control of control logic 220, page buffer circuit 250 can perform a sensing operation based on a verification voltage to sense the sensed value of memory cell array 210. When a verification voltage is applied to a selected word line, page buffer circuit 250 can temporarily store the sensed value sensed from memory cell array 210. The stored sensed value may include a count value. The count value may be the number of active cells among a plurality of memory cells connected to the selected word line.

[0051] When the line decoder 240 applies a programming voltage to the selected word line during a programming operation, the page buffer circuit 250 can apply bit line voltages (such as programming disable voltage and programming voltage) to the bit line BL according to the speed at which the memory cell is programmed.

[0052] Page buffer circuit 250 may include multiple page buffers respectively connected to bit line BL. The multiple page buffers may be arranged to be connected to corresponding bit lines, wherein each page buffer may include multiple latches. In the following, page buffer circuitry may include page buffers connected to each bit line. However, embodiments are not limited thereto. For example, a page buffer may be sequentially connected to multiple different bit lines. Page buffers arranged to be connected to each of the multiple different bit lines may be defined as page buffer cells.

[0053] Figure 3 This is a circuit diagram of the memory block BLKb according to an embodiment.

[0054] Reference Figure 3 A memory block BLKb may include vertically stacked NAND flash memory cells. For example, a memory block BLKb may include multiple NAND strings NS11 to NS33, multiple word lines WL1 to WL8, multiple bit lines BL1 to BL3, ground select lines GSL1, GSL2 and GSL3, multiple string select lines SSL1 to SSL3, and a common source line CSL. The number of NAND flash memory cell strings, word lines, bit lines, ground select lines, and string select lines may vary depending on the size of the memory block BLKb.

[0055] NAND flash memory cell strings NS11, NS21, and NS31 can be disposed between the first bit line BL1 and the common source line CSL; NAND flash memory cell strings NS12, NS22, and NS32 can be disposed between the second bit line BL2 and the common source line CSL; and NAND flash memory cell strings NS13, NS23, and NS33 can be disposed between the third bit line BL3 and the common source line CSL. Each NAND flash memory cell string (e.g., NS11) may include a vertically serially connected string select transistor SST, multiple memory cells MC1 to MC8, and a ground select transistor GST. Hereinafter, the NAND flash memory cell string may be simply referred to as a string.

[0056] NAND flash memory cell strings that are connected to a common bit line form a column. For example, NAND flash memory cell strings NS11, NS21, and NS31 that are connected to the first bit line BL1 can correspond to the first column, NAND flash memory cell strings NS12, NS22, and NS32 that are connected to the second bit line BL2 can correspond to the second column, and NAND flash memory cell strings NS13, NS23, and NS33 that are connected to the third bit line BL3 can correspond to the third column.

[0057] NAND flash memory cell strings connected to a string select line form a row. For example, NAND flash memory cell strings NS11, NS12, and NS13 connected to the first string select line SSL1 can correspond to the first row, NAND flash memory cell strings NS21, NS22, and NS23 connected to the second string select line SSL2 can correspond to the second row, and NAND flash memory cell strings NS31, NS32, and NS33 connected to the third string select line SSL3 can correspond to the third row.

[0058] The serial select transistor SST is connected to serial select lines SSL1 through SSL3. Multiple memory cells MC1 through MC8 are connected to word lines WL1 through WL8, respectively. The ground select transistor GST is connected to ground select lines GSL1, GSL2, and GSL3. The serial select transistor SST is connected to the corresponding bit line, and the ground select transistor GST is connected to the common source line CSL.

[0059] Word lines (e.g., WL1) at the same stack height can be connected together, and string select lines SSL1 to SSL3 at the same stack height can be individually connected to their respective string select transistors. For example, when programming memory cells connected to the first word line WL1 and the first string select line SSL1 for strings NS11, NS12, and NS13, the first word line WL1 and the first string select line SSL1 can be selected. Figure 3 As shown, ground selection lines GSL1, GSL2, and GSL3 can be separated from each other. Alternatively, ground selection lines GSL1, GSL2, and GSL3 can be connected to each other.

[0060] Erasing operations for NAND flash memory can be performed within memory block cells. Programming operations can be performed using page cells corresponding to each word line WL1 through WL8. When the memory cell includes MLC, TLC, or QLC, each word line can store data corresponding to multiple pages. For example, when the memory cell includes MLC, each word line can store data corresponding to the least significant bit (LSB) page and the most significant bit (MSB) page. When the memory cell includes TLC, each word line can store data corresponding to the LSB page, the center significant bit (CSB) page, and the MSB page.

[0061] Figure 4 This is a block diagram of multiple superblocks 410_0 to 410_n-1 according to an embodiment.

[0062] Reference Figures 1 to 4 The memory device 17 may include multiple superblocks 410_0 to 410_n-1 that operate logically in an interleaved manner. Although Figure 4 The figure shows the number of superblocks, n, but the number of superblocks is not limited to this.

[0063] Each of the multiple superblocks 410_0 to 410_n-1 may include multiple sub-memory blocks SUBBLK0, SUBBLK1, SUBBLK2, etc. The multiple sub-memory blocks SUBBLK0, SUBBLK1, SUBBLK2, etc. may be included in... Figure 1 Among the multiple non-volatile memory devices in NVM.

[0064] Despite Figure 4 The diagram shows three sub-memory blocks within each superblock, but the number of sub-memory blocks can vary between superblocks. (See reference...) Figure 1 , Figure 2 and Figure 4The multiple memory blocks BLK included in the non-volatile memory devices NVM11, NVM21 to NVMm1 connected to the first path in memory device 17 can be sub-memory blocks of the first superblock 410_0. The multiple memory blocks BLK NVM12, NVM22 to NVMm2 included in the non-volatile memory device can be sub-memory blocks of the second superblock 410_1. Similarly, the multiple memory blocks BLK NVM1n, NVM2n to NVMmn included in the non-volatile memory device can be sub-memory blocks of the nth superblock 410_n-1. Each superblock of the memory device can include multiple sub-memory blocks SUBBLK0, SUBBLK1, SUBBLK2, etc. A non-volatile memory device including a superblock can be referred to as the i-th non-volatile memory device, where i is a natural number greater than 0. For example, non-volatile memory devices NVM11 to NVMm1 including the first superblock 410_0 can be referred to as first non-volatile memory devices, non-volatile memory devices NVM12 to NVMm2 including the second superblock 410_1 can be referred to as second non-volatile memory devices, and non-volatile memory devices NVM1n to NVMmn including the nth superblock 410_n-1 can be referred to as nth non-volatile memory devices. However, the inventive concept is not limited thereto.

[0065] According to an embodiment, memory controller 16 can provide an address and one or more commands corresponding to each of a selected superblock (e.g., a target superblock) among a plurality of superblocks 410_0 to 410_n-1. One or more commands and addresses are generated in memory controller 16 based on a request from the host. For example, the host can sequentially provide a first request and a second request to memory system 15. Memory controller 16 can provide a first address and one or more first commands corresponding to a first superblock 410_0 to memory device 17 in response to a first request from the host. Then, memory controller 16 can provide a second address and one or more second commands corresponding to a second superblock 410_1 to memory device 17 in response to a second request from the host. Memory controller 16 can provide one or more first commands and a first address, and one or more second commands and a second address, in a scheduled order. For example, memory controller 16 can provide one or more second commands and a second address after providing one or more first commands and a first address.

[0066] According to an embodiment, in response to a write request from the host, the memory controller 16 can provide the address and programming command corresponding to the target word line to the memory device 17. Upon receiving the programming command and address, the target word line can be a selected word line for each of the multiple sub-memory blocks SUBBLK0, SUBBLK1, SUBBLK2, etc., within a target superblock included in multiple superblocks 410_0 to 410_n-1. A specific word line can be selected for each of the multiple sub-memory blocks SUBBLK0, SUBBLK1, SUBBLK2, etc. Programming operations can be performed on the target word lines simultaneously. For example, programming operations can be performed simultaneously on the target word line in sub-memory block SUBBLK0 of the first superblock 410_0, the target word line in sub-memory block SUBBLK1 of the first superblock 410_0, and the target word line in sub-memory block SUBBLK2 of the first superblock 410_0.

[0067] According to an embodiment, the memory controller 16 may sequentially provide addresses and programming commands to the memory device 17 in response to a sequential write request from the host to program multiple word lines WL for each sub-memory block of the target superblock. For example, refer to Figure 3 and Figure 4 When each sub-memory block is as Figure 3 When the diagram shows eight word lines, programming operations can be performed sequentially for each of the multiple sub-memory blocks SUBBLK0, SUBBLK1, SUBBLK2, etc., in descending order from word line WL8 to word line WL1 or in ascending order from word line WL1 to word line WL8. Programming operations for word line WL8 included in each of the multiple sub-memory blocks SUBBLK0, SUBBLK1, SUBBLK2, etc., can be performed simultaneously. When the programming operation for each target word line is completed, the programming operation for the next target word line can be performed.

[0068] Figure 5 This is an example of the programming time for word lines according to an embodiment.

[0069] Reference Figure 5 The programming time required for word lines in the same memory block (or the same sub-memory block) of the first non-volatile memory device NVM11 to the mnth non-volatile memory device NVMmn may vary from one another due to variations in the process technology of the non-volatile memory devices. Programming time can be the time measured from the start to the end of a programming operation. In the standard data specification published by the Joint Electronic Equipment Committee (JEDEC), programming time is defined as "tPROG".

[0070] According to an embodiment, a portion of the word lines WL may require a programming time less than the average programming time. The average programming time can be the average time required to program each word line in the word lines WL. A portion of the word lines WL may require a programming time greater than the average programming time. Most of the digital lines in the word lines WL may require a programming time close to the average programming time.

[0071] According to an embodiment, a portion of the multiple word lines WL may require a minimum programming time. The minimum programming time can be the minimum programming time among the multiple word lines WL. A portion of the multiple word lines WL may require a maximum programming time. The maximum programming time can be the maximum programming time among the multiple word lines WL.

[0072] Because programming time varies for each word line, it can exhibit a Gaussian distribution across different word lines. Furthermore, as the number of memory blocks stacked increases, the size of the memory block can increase. Therefore, the number of word lines in the memory block can increase, and the range of programming time differences between word lines can also increase. Due to the differences in programming time between word lines, the range of programming time fluctuations (or write fluctuations) in non-volatile memory devices can increase, thereby degrading data reliability and the performance of memory system 15.

[0073] Figure 6 This is a diagram illustrating an example of a word line table according to an embodiment.

[0074] Reference Figure 6 The word line table may include data indicating word lines for which a programming time less than a reference programming time is required for each of a plurality of memory blocks. The reference programming time may be the average programming time for each word line of a plurality of non-volatile memory devices. More specifically, the word line table may include addresses of word lines in which the programming time is less than the average programming time (e.g., the word line table may include addresses of specific word lines in which the programming time is less than the average programming time), and / or the word line table may include addresses of word lines in which the programming time is greater than the average programming time.

[0075] The word line table may include data indicating the word line for each sub-memory block included in each superblock that requires less than the average programming time.

[0076] According to an embodiment, the word line table may include data indicating the word line requiring minimum programming time for each sub-memory block included in each superblock.

[0077] Reference Figure 6For example, word lines WLx, WLa, and WLk in the sub-memory blocks SUBBLK0, SUBBLK1 to SUBBLKj of the first superblock SPRBLK0 may require minimum programming time, where j is a natural number greater than 0. Word line WLy in the sub-memory block SUBBLK0 of the second superblock SPRBLK1 may also require minimum programming time. However, the inventive concept is not limited to this. The word line table may also include data indicating word lines requiring minimum programming time in other memory blocks of the memory device 17.

[0078] According to an embodiment, the word line table may include indications for multiple memory blocks (e.g., Figure 2 The word line table contains data for each word line in a memory block (BLK) that requires a programming time less than the average programming time. Optionally, the word line table may include data indicating the word line that requires the minimum programming time for each memory block.

[0079] At least one of the plurality of non-volatile memory devices (NVMs) in memory system 15 may include a word line table. During the power-up sequence of memory system 15, memory controller 16 may load the word line table stored in the non-volatile memory device into the internal memory of memory system 15, which may be implemented as static random access memory (SRAM). Memory controller 16 may control the non-volatile memory device storing the word line table to perform background operations to update the word line table.

[0080] The word line table can be generated during the testing phase of the memory system 15. The word line table can be generated and updated periodically in response to background operations of the memory system 15 based on requests from the host while the memory system 15 is being operated. Alternatively, the word line table can be generated and updated periodically in response to background operations of the memory system 15 while the memory system 15 is being operated, regardless of requests from the host.

[0081] Figure 7 This is a flowchart of generating a word line table according to an embodiment.

[0082] Reference Figure 7In step S110, the memory controller may measure the programming time of each of the multiple word lines included in each of the multiple memory blocks of the non-volatile memory device. For example, the memory controller may measure the programming time of the word line WL in each of the multiple memory blocks BLK of the multiple non-volatile memory devices NVM. The memory controller may measure the programming time by measuring the time interval between a first time point at which the address and programming command corresponding to the word line are provided to the corresponding non-volatile memory device and a second time point at which a response is received from the corresponding non-volatile memory device. Optionally, the memory controller may measure the programming time by measuring the time interval between the first time point at which the memory controller provides the address and programming command to the corresponding non-volatile memory device and a second time point at which the non-volatile memory device returns a response indicating that the programming operation is complete. The non-volatile memory device returns a response signal in response to a response request signal from the memory controller. The memory controller may periodically send the response request signal, in which the period may be preset by the memory controller. Therefore, the second time point may be r times the preset period, at which the memory device returns a response signal for the r-th response request signal. However, the inventive concept is not limited to this.

[0083] In step S120, the storage controller may calculate the average of the multiple programming times measured in step S110. Furthermore, the storage controller may set the average as a reference programming time.

[0084] In step S130, the storage controller may generate a word line table including data indicating word lines for which the programming time required to program each word line is less than a reference programming time. Optionally, the storage controller may generate a word line table including word lines for which the programming time required to program each word line is a minimum programming time.

[0085] The programming time required for most word lines is close to the reference programming time. The memory controller can compare the programming time of the currently selected word line with the average programming time measured across word lines in multiple non-volatile memory devices, and can update the word line table data to indicate that the programming time required for the currently selected word line is relatively small compared to the reference programming time. It can also omit measuring the programming time of the word line to be selected after obtaining the data, or discard the data for word lines that indicate a relatively long programming time.

[0086] Figure 8 This is a flowchart illustrating the operation of a storage device according to an embodiment.

[0087] Reference Figure 8 In step S210, the storage controller may generate a data entry based on a write request from the host, and include data in the data entry. Figure 1The first target non-volatile memory device is defined as the first address corresponding to the target word line in the first target non-volatile memory device and the programming command. The first target non-volatile memory device may be included in a superblock.

[0088] The storage controller can generate a first address and programming commands based on write requests from the host to address multiple first non-volatile memory devices (e.g., Figure 1 The first superblock (e.g., of the non-volatile memory devices NVM11, NVM21 to NVMm1) in the non-volatile memory devices (NVM11, NVM21 to NVMm1) Figure 4 The first superblock (410_0) in the code performs programming operations in an interleaved manner.

[0089] In step S220, the memory controller may, based on the word line table and the target word line of the first address and in response to a request from the host, determine whether to independently allocate the first target memory block in the second target non-volatile memory device included in the non-volatile memory device for the erase operation.

[0090] The word line table may include first data indicating a first word line, in which the first word line requires a first programming time less than that required for a memory block (e.g., Figure 2 The reference programming time required to program each word line of multiple memory blocks (BLKs) within the table. The word line table can correspond to... Figure 6 The word line table shown in the image.

[0091] According to an embodiment, a first superblock may include a first target non-volatile memory device, while a second superblock, distinct from the first superblock, may include a second target non-volatile memory device. The first target memory block may include information about memory blocks pre-allocated for performing erase operations regardless of whether a request is received from the host. The first target memory block may correspond to one of the sub-memory blocks included in one of the superblocks.

[0092] The storage controller can determine, based on the word line table and the target word line of the first address and in response to a request from the host, whether to independently allocate the word line included in the second superblock (e.g., Figure 4 At least one first target sub-memory block in the second superblock 410_1) to perform an erase operation on the first target sub-memory block.

[0093] The word line table may include data indicating that "the programming time required to program each of the word lines is less than the reference programming time required to program each of the multiple sub-memory blocks (e.g., SUBBLK0, SUBBLK1, SUBBLK2, etc.) included in a superblock (e.g., multiple superblocks 410_0, 410_1, ..., 410_n-1)". The word line table may correspond to... Figure 6 The word line table shown in the image.

[0094] The first target sub-memory block may correspond to the first target memory block.

[0095] In step S230, when the first target memory block is allocated for an erase operation, the memory controller can generate a second address and an erase command corresponding to the allocated first target memory block.

[0096] When the first target sub-memory block is allocated for an erase operation, the memory controller can generate a second address and erase command corresponding to the allocated first target sub-memory block.

[0097] As memory block sizes increase due to advancements in the finer manufacturing processes of non-volatile memory devices, the difference in programming time between word lines can be reduced. This allows non-volatile memory devices to maintain consistency in programming time and write throughput, while also improving device latency and performance.

[0098] Furthermore, because erase and programming operations are executed in parallel in different superblocks, programming operations that require relatively long programming time in one superblock can be hidden by erase operations in another superblock that also require long erase time.

[0099] Furthermore, erase operations can be assigned to each chip or die. Therefore, while maintaining a constant write throughput, the peak power consumed during erase operations can be reduced, thereby lowering the power required by the device.

[0100] Figures 9A to 9C This diagram illustrates sequential write operations performed on a superblock and erase operations performed on sub-memory blocks of another superblock. Although in Figures 9A to 9C The diagram shows two superblocks and two sub-memory blocks included in each superblock, but the number of superblocks and sub-memory blocks is not limited to this.

[0101] Reference Figures 9A to 9C The host can provide sequential write requests to the storage device. Based on the sequential write requests from the host, the storage device can perform programming operations on the word lines in a pre-set order for each of multiple operation times ot1, ot2, ..., ota, ...

[0102] Reference Figure 9ADuring operation time ot1, the memory controller can generate a first address and programming command corresponding to the word line WLx in each of the first sub-memory blocks 911 and 912 included in the first superblock 910. The first sub-memory block 911 and the second sub-memory block 912 may be included in the target non-volatile memory device. Optionally, the first sub-memory block 911 may be included in one target non-volatile memory device, and the second sub-memory block 912 may be included in another target non-volatile memory device. Figure 6 As shown, the word line WLx of the first sub-memory block 911 may include word lines requiring minimum programming time. When word line WLx includes word lines requiring minimum programming time, the memory controller may allocate the first sub-memory block 921 of the second superblock 920 for an erase operation. The memory controller may generate a second address and an erase command corresponding to the first sub-memory block 921. The memory controller may schedule a first address and a programming command for performing a programming operation on the first sub-memory block 911 of the first superblock 910. The memory controller may schedule a second address and an erase command for performing an erase operation on the first sub-memory block 921 of the second superblock 920 in a command queue. The memory controller may output the first address and programming command and the second address and erase command sequentially in the scheduling order. For example, the first address and programming command may be output at a first time t11 of operation time ot1, and the second address and erase command may be output at a second time t12 of operation time ot1. However, the inventive concept is not limited thereto. The second address and erase command can be output at the first time t11 of operation time ot1, and the first address and programming command can be output at the second time t12 of operation time ot1. Programming operations for word line WLx can begin at the first time t11 of operation time ot1, and erasing operations for the first sub-memory block 921 can begin at the second time t12 of operation time ot1. The programming and erasing operation periods may at least partially overlap. During the second time t12 of operation time ot1, the second sub-memory block 922 of the second superblock 920 may not be allocated or may be deallocated.

[0103] Reference Figure 9BDuring operation time ot2, the memory controller may generate a first address and programming command corresponding to word line WLx+1 included in the first sub-memory block 911 and the second sub-memory block 912 of the first superblock 910. Word line WLx+1 may include word lines to be programmed after word line WLx. For example, the programming time required to program each of word lines WLx+1 may be a reference programming time, which is the average programming time required to program each of the word lines in the non-volatile memory device. The memory controller may generate the first address and programming command corresponding to word line WLx+1. During operation time ot2, an erase operation on the first sub-memory block 921 of the second superblock 920 is considered complete. When the host provides a request to the memory device to perform a write operation, the memory controller may allocate the first sub-memory block 921 in response to the request and may generate a second address and operation command based on the request from the host to perform an operation on the first sub-memory block 921 in response to the request. The second address may correspond to the allocated first sub-memory block 921. The generated second address and operation command can be scheduled in the command queue of the storage controller. The first address and programming command can be output at the first time t21 of operation time ot2, and programming operation on word line WLx+1 can begin. The second address and operation command can be output at the second time t22 of operation time ot2, and operation on the allocated first sub-memory block 921 can be executed. This operation may include read operations, programming operations, etc.

[0104] Programming operations can be performed on word line WLx+2 following word line WLx+1 in the first sub-memory block 911 and the second sub-memory block 912 included in the first superblock 910. The storage device can receive requests from the host and perform operations on the second superblock 920 in response to requests from the host.

[0105] Reference Figure 9C The memory controller controls the non-volatile memory device to perform operations at operation time 0ta, following operations at times 0t1 and 0t2. At operation time 0ta, the memory controller can generate a first address and programming command corresponding to the word line WLa included in each of the first sub-memory blocks 911 and 912 of the first superblock 910. For example... Figure 6As shown, when the word line WLa of the second sub-memory block 912 includes a word line requiring minimum programming time, the memory controller can allocate the second sub-memory block 922 of the second superblock 920 and generate a second address and erase command corresponding to the second sub-memory block 922. Programming operations for word line WLa can begin at a first time ta1 of operation time ota, and erasing operations for the second sub-memory block 922 can begin at a second time ta2 of operation time ota. Programming operations performed on the first sub-memory blocks 911 and 912 of the first superblock 910 and erasing operations performed on the second sub-memory block 922 of the second superblock 920 can at least partially overlap.

[0106] Each time a target word line based on the first address corresponds to a word line indicated by the first data in the word line table, sub-memory blocks of the second superblock can be allocated one by one. (See reference...) Figure 9A For example, when word line WLx included in the first sub-memory block 911 of the first superblock 910 is selected as the target word line, the first sub-memory block 921 of the second superblock 920 can be allocated. When word line WLa included in the second sub-memory block 912 of the first superblock 910 is selected as the target word line, the second sub-memory block 922 of the second superblock 920 can be allocated. When two or more word lines of the first superblock 910 are indicated by the first data of the word line table, two or more sub-memory blocks of the second superblock 920 can be allocated.

[0107] After the erase operation on the second sub-memory block 922 of the second superblock 920 is completed, the programming operations in the first superblock 910 can be performed sequentially on word lines following word line WLa. When a subsequent word line differs from the word line indicated by the first data in the word line table (e.g., when the target word line differs from the first word line), an operation command and at least one third address corresponding to at least one sub-memory block of the second superblock 920 can be generated and output in response to a request from the host.

[0108] Figure 10 This is a diagram illustrating an example of a word line table according to an embodiment.

[0109] Reference Figure 10 The word line table may include first data indicating first word lines, wherein the programming time required to program each of the first word lines is less than the reference programming time required to program each word line of a plurality of memory blocks. Furthermore, the word line table may also include second data indicating second word lines, wherein the programming time required to program the second word lines is greater than the reference programming time.

[0110] The word line table may include first data and second data for each of the sub-memory blocks included in each superblock, wherein the first data may indicate a first word line in which the programming time required to program each of the first word lines is less than the average programming time, and the second data may indicate a second word line in which the programming time required to program each of the second word lines is greater than the average programming time.

[0111] Optionally, the word line table may include first and second data, wherein the first data indicates a first word line in which the programming time required to program each of the first word lines indicated by the first data is the minimum programming time for each block, and the second data indicates a second word line in which the programming time required to program each of the second word lines indicated by the second data is the maximum programming time for each block.

[0112] Reference Figure 10 The word line table may include first data indicating the first word lines, and the programming time required to program each of the first word lines may be the minimum programming time. For example, Figure 10 The word lines indicate the first data, which can indicate word lines WLx1, WLa1, WLk1, and WLy1. The word line table may include second data indicating second word lines, in which the programming time required to program each second word line can be the maximum programming time. For example, Figure 10 The word lines indicate that the second data can indicate word lines WLx2, WLa2, WLk2, and WLy2. However, the inventive concept is not limited thereto. The word line table may include first data and second data indicating the first and second word lines respectively, wherein the first programming time required to program each of the first word lines may be the minimum programming time, and the second programming time required to program each of the second word lines may be the maximum programming time.

[0113] For each memory block, the word line table may include first data indicating a first word line and second data indicating a second word line, wherein the programming time required to program each line in the first word line is less than the average programming time, and the programming time required to program each line in the second word line may be greater than the average programming time. Optionally, the word line table may include first data and second data indicating the first and second word lines respectively, wherein the first programming time required to program each line in the first word line may be the minimum programming time, and the second programming time required to program each line in the second word line may be the maximum programming time.

[0114] The memory controller can measure the programming time for each word line and generate [something] based on the measured programming time. Figure 10 The character line table.

[0115] Figure 11 This is a flowchart of the operation of the storage device according to an embodiment.

[0116] Reference Figure 11 In step S310, the storage controller can collect and analyze data on the programming time of each word line (W / L). The operation in step S310 can correspond to... Figure 7 The steps for generating a word line table are shown in the figure.

[0117] In step S321, the memory controller may determine whether at least one currently selected target word line is indicated by data from the word line table. When it is determined that at least one currently selected target word line is indicated by data from the word line table, the memory controller may determine that the programming time of at least one currently selected target word line is the shortest among memory blocks.

[0118] When the storage controller determines in step S321 that at least one currently selected target word line has the shortest programming time, it follows the operation in step S322. The storage controller may allocate a second sub-block of the second superblock and may determine whether an erase operation has been completed for the second sub-block. The current sub-block may be included in a superblock (e.g., the first superblock 910), and the second sub-block may be included in another superblock (e.g., the second superblock 920). The operation in step S322 may correspond to... Figures 9A to 9C The operation of the embodiment shown in the figure.

[0119] When it is determined in step S322 that no erasure operation has been performed on the second sub-block previously, the storage controller may execute step S323, in which the storage controller may control the non-volatile memory device to perform an erasure operation on the second sub-block.

[0120] If, in step S322, it is determined that an erasure operation has already been performed on the second sub-block, the storage controller may execute step S324. In step S324, the storage controller may generate a second address and operation commands based on a request from the host to perform operations on the second sub-block other than the erasure operation. The operations performed on the second sub-block may include, for example, a read operation.

[0121] In step S325, the storage controller may generate a first address and programming command based on the write request from the host to perform programming operations on the target word line of the current sub-block.

[0122] The first address and programming commands can be scheduled in the order in which the storage controller performs programming operations, erasure operations and other operations in steps S323, S324 and S325 based on the scheduling order.

[0123] If, in step S321, it is determined that the programming time of at least one currently selected target word line is not the shortest, the storage controller may execute step S331, in which the storage controller may determine whether the programming time of at least one currently selected target word line is the longest. For example, the storage controller may determine whether at least one target word line can be different from the word line indicated by the data in the word line table.

[0124] If, in step S331, it is determined that the programming time of at least one currently selected target word line is not the longest, the memory controller may execute step S332. In step S332, the memory controller may generate an operation command and a third address corresponding to the second memory block included in the second target non-volatile memory device in response to a request from the host, to perform operations on the second sub-block other than an erase operation. Thereafter, the memory controller may sequentially output the third address and operation command, as well as the first address and programming command, according to a scheduled order. For example, when the target word line differs from each of the first and second word lines, the memory controller may sequentially provide the commands and addresses to the first and second target non-volatile memory devices in a scheduled order. Operations performed on the second sub-block may include read operations, external read operations, etc.

[0125] If, in step S331, it is determined that at least one of the currently selected target word lines has the longest programming time, the memory controller may execute step S333. In step S333, the memory controller may maintain the output of the third address and operation command to prevent operation from being performed on the second sub-block. For example, when the target word line is different from the first word line but the same as the second word line, the memory controller may maintain the provision of commands and addresses to the second target non-volatile memory device. Then, the memory controller may generate and output the first address and programming command based on the write request from the host to perform a programming operation on the target word line of the current sub-block. The memory controller may perform operations including acquiring feature commands, setting feature commands, acquiring feature universal internal bus (UIB), setting feature UIB, etc.

[0126] According to an embodiment, when the programming time required to program each word line is relatively small compared to a reference programming time required to program each word line in a non-volatile memory device, programming operations are performed in parallel with erase operations in different sub-blocks. Because the long latency of write operations can be reduced by performing write operations in other sub-blocks without performing erase operations, programming operations performed on word lines where the programming time required to program each word line is relatively long compared to the reference programming time can maintain uniform throughput and latency. Therefore, the performance of the memory device can be improved.

[0127] Furthermore, by performing erase operations sequentially across different sub-blocks, the erase operation units can be distributed across the non-volatile memory device without overlapping erase portions. Therefore, write time consistency is maintained and power consumption can be optimized. Consequently, device reliability is improved and power consumption is reduced.

[0128] Figure 12 This is a flowchart illustrating an operation method of a storage device according to an embodiment.

[0129] Reference Figure 12 In step S410, the storage controller may schedule the order of providing the first address and programming commands corresponding to the target word line included in the first superblock based on the write request from the host.

[0130] In step S420, the memory controller may determine, based on the word line table and the first address of the target word line, whether to independently allocate the first target memory block included in the second superblock. The word line table may include data indicating that the programming time required to program each of the word lines therein is less than a reference programming time for each word line.

[0131] In step S420, the storage controller may further determine whether a target word line is indicated by data in the word line table. If it is determined that the target word line is indicated by data in the word line table, the storage controller may allocate a first target memory block based on the target word line indicated by the data in the word line table. If it is determined that the target word line is not indicated by data in the word line table, the storage controller may allocate a second target memory block included in the second superblock based on the target word line in response to a request from the host.

[0132] In step S430, the memory controller may schedule a second address and an erase command corresponding to the allocated first target memory block for the erase operation. For example, when the target word line is the same as the first word line, the memory controller may allocate the first target memory block to perform an erase operation on the first target memory block.

[0133] The programming operations based on programming commands and the erasure operations based on erasure commands can at least partially overlap.

[0134] The method of operating the storage device may further include providing a first address and programming command and a second address and erase command in a scheduled order (e.g., provided to a first target memory block (e.g., a first target non-volatile memory device) and a second target memory block (e.g., a second target non-volatile memory device) respectively).

[0135] The operation of the storage device may also include updating the word line table in response to an update request from the host or updating the word line table through periodic background operations.

[0136] Updating the word line table may include measuring multiple programming times for multiple word lines, setting the average of the multiple programming times as a reference programming time, and generating a word line table that includes data indicating that the programming time required to program each of the word lines is less than the reference programming time.

[0137] Figure 13 This is a block diagram of a host storage system 2000 according to an embodiment.

[0138] Reference Figure 13 The host-storage system 2000 may include a host 2100 and a storage device 2200.

[0139] The host 2100 may include a host controller 2110 and a host memory 2120.

[0140] The host controller 2110 can manage operations that store data (e.g., write data) in the non-volatile memory (NVM) device 2220 or store data of the NVM 2220 (e.g., read data) in a buffer area.

[0141] The host memory 2120 can be used as a buffer memory for temporarily storing data to be sent to or from the storage device 2200.

[0142] Storage device 2200 may include a storage medium for storing data in response to a request from host 2100. Storage device 2200 may include at least one of SSD, embedded memory, and removable external memory.

[0143] Storage device 2200 may include storage controller 2210 and NVM 2220.

[0144] The storage controller 2210 may include a host interface (IF) 2211, a memory interface 2212, a central processing unit (CPU) 2213, a flash translation layer (FTL) 2214, a packet manager 2215, a buffer memory (BUF MEM) 2216, an error correction code (ECC) engine (ENG) 2217, and an advanced encryption standard (AES) engine 2218.

[0145] The embodiments conceived in this invention can be applied to storage controller 2210.

[0146] Host interface 2211 can send packets to host 2100 and receive packets from host 2100. Packets sent to host interface 2211 may include commands or data to be written to NVM 2220. Packets sent to host 2100 may include responses to commands or data read from NVM 2220.

[0147] The memory interface 2212 can send data to be written to the NVM 2220 or receive data read from the NVM 2220.

[0148] CPU 2213 can perform data write and read operations to control NVM 2220 by executing FTL 2214.

[0149] The FTL 2214 can perform various functions (such as address mapping, wear leveling, and garbage collection).

[0150] Packet manager 2215 can generate packets according to the protocol of the interface negotiated with host 2100, or parse various types of information from packets received from host 2100.

[0151] The buffer memory 2216 can temporarily store data to be written to or read from the NVM 2220.

[0152] The ECC engine 2217 can perform error detection and correction functions on read data read from the NVM 2220.

[0153] The AES engine 2218 can perform at least one of encryption and decryption operations on the data input to the storage controller 2210 using a symmetric key algorithm.

[0154] The number of NVM 2220s can be one or more, depending on the application. (See above reference.) Figure 1 As described above, two or more NVMs 2220 can communicate with the memory interface 2212 through multiple channels. Two or more NVMs 2220 can constitute one or more superblocks.

[0155] Figure 14 This is a diagram of a data center 3000 that utilizes a memory device according to an embodiment.

[0156] Reference Figure 14 Data center 3000 collects various types of data and provides services. Data center 3000 can also be referred to as a data storage center. Data center 3000 may include computing systems for operating search engines and databases. Data center 3000 may include application servers 3100 to 3100n and storage servers 3200 to 3200m.

[0157] Application server 3100 may include processor 3110 and memory 3120, and storage server 3200 may include processor 3210 and memory device 3220. For example, application servers 3100 to 3100n may each include processors 3110 to 3110n, NICs 3140 to 3140n, and switches 3130 to 3130n, and storage servers 3200 to 3200m may each include processors 3210 to 3210m, NICs 3240 to 3240m, and switches 3230 to 3230m. The processor 3210 of storage server 3200 can control the overall operation of storage server 3200 and can access memory device 3220 to execute instructions and / or data loaded into memory device 3220. The operation of storage server 3200 may be similar to the operation of application server 3100. According to an embodiment, application server 3100 may not include storage device 3150. Storage server 3200 may include at least one or more storage devices 3250.

[0158] Application servers 3100 to 3100n and storage servers 3200 to 3200m can communicate with each other via network 3300. Depending on the access method of network 3300, storage servers 3200 to 3200m can be provided as file storage, block storage, or object storage.

[0159] In the following text, application server 3100 and storage server 3200 will be primarily described. The description of application server 3100 can also be applied to another application server 3100n, and the description of storage server 3200 can also be applied to another storage server 3200m.

[0160] Application server 3100 can store data requested by a user or client in one of storage servers 3200 to 3200m via network 3300. Furthermore, application server 3100 can read data requested by a user or client from one of storage servers 3200 to 3200m via network 3300.

[0161] Application server 3100 can access memory 3120n or storage device 3150n included in another application server 3100n via network 3300, or access memory devices 3220 to 3220m or storage devices 3250 to 3250m included in storage servers 3200 to 3200m via network 3400. Application server 3100 can perform various operations on data stored in application servers 3100 to 3100n and / or storage servers 3200 to 3200m.

[0162] The interface 3254 of the storage server 3200 provides a physical connection between the processor 3210 and the controller 3251, as well as a physical connection between the network interface controller (NIC) 3240 and the controller 3251.

[0163] Storage server 3200 may also include switch 3230 and NIC 3240. Switch 3230 may selectively connect processor 3210 to storage device 3250, or may selectively connect NIC 3240 to storage device 3250 under the control of processor 3210.

[0164] Storage devices 3150 to 3150m and 3250 to 3250m can perform operations according to the above reference. Figures 1 to 13 The operation of the described embodiments. Storage devices 3150 to 3150n and 3250 to 3250m may include controllers 3251 to 3251n and 3251 to 3251m, NAND flash memory devices 3252 to 3252n and 3252 to 3252m, dynamic random access memory (DRAM) 3253 to 3253n and 3253 to 3253m, and interface (I / F) 3254 to 3254n and 3254 to 3254m. Controller 3251 may include SRAM. Storage devices 3250 to 3250m may include a security element (SE) for security or privacy.

[0165] Although the inventive concept has been specifically described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device comprising: a plurality of non-volatile memory devices each including a plurality of memory blocks; and a storage controller configured to provide a command and an address to a target non-volatile memory device among the plurality of non-volatile memory devices, wherein the storage controller is configured to: receive a write request from a host; generate a program command and a first address based on the write request from the host, wherein the first address corresponds to a target word line of a first target non-volatile memory device; determine whether to allocate a first target memory block of a second target non-volatile memory device regardless of the request from the host based on a word line table and the target word line of the first address, wherein the word line table includes first data indicating a first word line, wherein a program time required for programming the first word line is less than a reference program time required for programming each word line of the plurality of memory blocks; and generate an erase command and a second address upon determining to allocate the first target memory block, wherein the second address corresponds to the first target memory block. the storage controller is further configured to:

2. The memory device of claim 1, wherein, schedule the program command and the first address; schedule the erase command and the second address; and output the program command and the first address and the erase command and the second address, respectively, in the scheduled order. when an erase operation for the first target memory block is completed, the storage controller is further configured to generate an operation command and the second address based on the request from the host.

3. The memory device of claim 1, wherein, the storage controller is further configured to:

4. The memory device of claim 1, wherein, allocate the first target memory block to perform an erase operation on the first target memory block when the target word line is the same as the first word line; and generate an operation command and a third address corresponding to a second target memory block included in the second target non-volatile memory device in response to the request from the host when the target word line is different from the first word line. the word line table further includes second data indicating a second word line, wherein a program time required for programming the second word line is greater than the reference program time, and 5. The memory device of claim 4, wherein, wherein the storage controller is further configured to: maintain output of the operation command and the third address when the target word line is different from the first word line and the same as the second word line; and sequentially output the operation command and the third address and the program command and the first address in the scheduled order when the target word line is different from each of the first word line and the second word line. the storage controller is further configured to:

6. The memory device of claim 1, wherein, measure a plurality of program times of a plurality of word lines of the plurality of memory blocks; set an average of the plurality of program times as a reference program time; and store data respectively indicating the word lines in the word line table, wherein a program time of each of the word lines is less than the reference program time set as the average. the storage controller is further configured to:

7. The memory device of claim 1, wherein, generate a first address and a program command corresponding to a plurality of word lines included in the first target non-volatile memory device based on a sequential write request from the host; and allocate memory blocks included in the second target non-volatile memory device one by one whenever it is detected that each of target word lines corresponding to the first address corresponds to the first word line. the plurality of non-volatile memory devices include:

8. The storage device of any one of claims 1 to 7, wherein, ​ a plurality of first nonvolatile memory devices including a first super block; and a plurality of second nonvolatile memory devices including a second super block, wherein the first super block and the second super block are operated in an interleaved manner, and wherein the first target nonvolatile memory device includes the plurality of first nonvolatile memory devices, and the second target nonvolatile memory device includes the plurality of second nonvolatile memory devices.

9. The storage device of any one of claims 1 to 7, wherein, The storage controller controls at least one nonvolatile memory device among the plurality of nonvolatile memory devices to store a word line table. 10.An operating method of a storage device, the operating method comprising: generating a program command and a first address based on a write request from a host, wherein the first address corresponds to a target word line included in a first super block; determining whether to allocate a first target memory block included in a second super block based on a word line table and the target word line of the first address, wherein the word line table includes data indicating word lines, wherein a program time of each of the word lines is less than a reference program time; generating a second address and an erase command corresponding to the first target memory block; and scheduling the program command and the first address and the erase command and the second address in a scheduled order, wherein the first super block and the second super block are operated in an interleaved manner.

11. The operating method of claim 10, wherein, The step of determining whether to allocate the first target memory block includes: determining whether the data of the word line table indicates the target word line; allocating the first target memory block when it is determined that the data of the word line table indicates the target word line; and allocating a second target memory block included in the second super block in response to a request from the host when it is determined that the data of the word line table does not indicate the target word line.

12. The operating method of claim 10, further comprising: The first address and the program command and the second address and the erase command are output in the scheduled order.

13. The operating method of claim 12, wherein, The program operation according to the program command and the erase operation according to the erase command at least partially overlap.

14. The operating method of claim 10, wherein, The operating method further includes updating the word line table in response to an update request from the host or while performing a background operation.

15. The operating method of claim 14, wherein, The step of updating the word line table includes: measuring a plurality of program times of a plurality of word lines; setting an average of the plurality of program times as the reference program time; and updating data of the word line table by storing data respectively indicating the word lines in the word line table, wherein a program time of each of the word lines is less than the reference program time set as the average. 16.A storage device comprising: a plurality of first nonvolatile memory devices including a first super block; a plurality of second nonvolatile memory devices including a second super block, wherein the first super block and the second super block are operated in an interleaved manner; and a storage controller configured to provide a command and an address to the plurality of first nonvolatile memory devices and the plurality of second nonvolatile memory devices, wherein the storage controller is further configured to: generate a first address and a program command to sequentially perform a program operation on the first super block based on a sequential write request from a host; determine, based on data of the word line table and a first address of the target word line, whether to allocate at least one first target sub-memory block included in a second super block independently of a request from a host, wherein the word line table includes data indicating a first word line, wherein a programming time required for programming each of the first word line is less than a reference programming time required for programming each word line of a plurality of sub-memory blocks included in the first super block and the second super block; and generate at least one second address and at least one erase command corresponding to the allocated at least one first target sub-memory block when the at least one first target sub-memory block is allocated for an erase operation.

17. The memory device of claim 16, wherein, The storage controller is further configured to: schedule the first address and the programming command and the at least one erase command and the at least one second address; and output the first address and the programming command and the at least one erase command and the at least one second address in the scheduled order.

18. The memory device of claim 17, wherein, At least one of the programming operation according to the programming command and at least one erase operation according to the at least one erase command at least partially overlap.

19. The memory device of claim 16, wherein, The storage controller is further configured to allocate one target sub-memory block whenever the data of the word line table indicates one of the target word line.

20. The memory device of claim 16, wherein, The storage controller is further configured to generate at least one third address and an operation command corresponding to at least one second target sub-memory block included in the second super block based on the request from the host when the target word line is different from the first word line.

Images