parallel-to-serial conversion circuit

Abstract

The application relates to the field of integrated circuit technology and discloses a parallel-serial conversion circuit. The parallel-serial conversion circuit comprises a parallel data storage unit, a parity data exchange unit, a shift unit and a selection output unit. The parallel data storage unit is connected with a parallel data input end and a parallel clock signal end. The parity data exchange unit is connected between the parallel data storage unit and the shift unit and is used for directly outputting parallel data or outputting the parallel data after parity data bit exchange according to a first selection control signal. The shift unit is connected with the parity data exchange unit, the selection output unit and a serial clock signal end. The selection output unit is connected with the shift unit, a serial clock signal input end and a serial data output end and is used for sequentially and serially outputting each bit data in the shift data according to the high and low levels of the serial clock signal. The technical scheme can dynamically configure a specific parallel-serial conversion mode and improves the flexibility of I / O interface use of the FPGA.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a parallel-serial conversion circuit. BACKGROUND

[0002] Field Programmable Gate Arrays (FPGA) emerged as a kind of semi-custom circuit in the field of Application-Specific Integrated Circuit (ASIC), which solved the deficiency of custom circuit and overcame the limitation of the number of gate circuits of the original programmable device.

[0003] FPGA contains a large number of programmable logic units, so that the internal logic function can be reconfigured to adapt to the change of different application scenarios and reconstruct the algorithm design. In addition, FPGA is usually equipped with many high-speed Input / Output (I / O) interfaces, which mainly complete the functions of electrical characteristic conversion and parallel-serial data conversion. Among them, the parallel-serial data conversion function is particularly important. The larger the conversion ratio is, the lower the FPGA logic working frequency is under the same transmission rate, which is of great significance to reduce power consumption and timing convergence.

[0004] Generally, the parallel-serial conversion ratio of I / O interface is a power of 2, such as 2:1, 4:1, 8:1, etc. After the chip design is completed, the parallel-serial conversion mode is also fixed. The use scenarios of FPGA are various, and different users have different requirements for the parallel-serial conversion ratio of I / O interface. However, most parallel-serial conversion circuits only support 2-power conversion, and the support for non-2-power even conversion such as 10:1 parallel-serial conversion is very small, and the support for odd conversion is even less. The parallel-serial mode conversion ratio of I / O interface in FPGA is limited, which leads to the limitation of the use scenarios of I / O interface in FPGA. SUMMARY

[0005] Therefore, the embodiments of the present application provide a parallel-serial conversion circuit, which can dynamically configure the specific parallel-serial conversion ratio according to the actual parallel-serial conversion demand, solve the problem that the parallel-serial mode conversion ratio of I / O interface in FPGA is limited, and improve the flexibility of the use of I / O interface in FPGA.

[0006] In a first aspect, the present application provides a parallel-serial conversion circuit, comprising: a parallel data storage unit, an odd-even data exchange unit, a shift unit and a selection output unit,

[0007] The parallel data storage unit is connected with a parallel data input end and a parallel clock signal end, and is configured to store the to-be-converted parallel data with the parallel clock signal input from the parallel clock signal end.

[0008] The parity data exchange unit is connected between the parallel data storage unit and the shift unit, and is configured to output the parallel data output by the parallel data storage unit directly or output the parallel data output by the parallel data storage unit after parity data bits are exchanged according to a first selection control signal, wherein the first selection control signal is related to a bit width of the parallel data to be converted.

[0009] The shift unit is connected to the parity data exchange unit, the selection output unit, and a serial clock signal input terminal, and is configured to shift the parallel data output by the parity data exchange unit according to a second selection control signal and a third selection control signal and a serial clock signal input from the serial clock signal input terminal to obtain shift data, wherein the second selection control signal and the third selection control signal are generated based on a configurable state machine.

[0010] The selection output unit is connected to the shift unit, the serial clock signal input terminal, and a serial data output terminal, and is configured to output each bit of data in the shift data in sequence according to a high or low level of the serial clock signal.

[0011] In a possible implementation of the first aspect, a data bit width of the parallel data to be converted is N1, and N1 is a positive integer. The serial clock signal is a multiple of the parallel clock signal.

[0012] In a possible implementation of the first aspect, the parallel data storage unit includes a plurality of first-level D flip-flops. A clock terminal of each of the first-level D flip-flops is connected to the parallel clock signal terminal. A data input terminal of each of the first-level D flip-flops is connected to one of the data ports of the parallel data input terminal in sequence. Each of the first-level D flip-flops is configured to store and output one bit of binary data in the parallel data to be converted according to the parallel clock signal. The data bit width N1 of the parallel data to be converted is less than or equal to a number N2 of the first-level D flip-flops, and N2 is a positive integer.

[0013] In a possible implementation of the first aspect, when the bit width of the parallel data to be converted is even, the first selection control signal is at a low level, and the parity data exchange unit is configured to output the parallel data output by the parallel data storage unit directly according to the first selection control signal.

[0014] When the bit width of the parallel data to be converted is odd, the first selection control signal is at a high level, and the parity data exchange unit is configured to output the parallel data output by the parallel data storage unit after parity data bits are exchanged according to the first selection control signal. ​

[0015] In a possible implementation of the first aspect, the parity data switching unit comprises a plurality of first-level selectors, each of the first-level selectors corresponding to one of the first-level D flip-flops, a low-level selection terminal of at least some of the first-level selectors being connected to a data output terminal of a corresponding first-level D flip-flop, a first high-level selection terminal of at least some of the first-level selectors being connected to a data output terminal of a first-level D flip-flop adjacent to the corresponding first-level D flip-flop, and each of the first-level selectors being configured to select one bit of binary data from one of the corresponding first-level D flip-flop and the adjacent first-level D flip-flop according to the first selection control signal.

[0016] In a possible implementation of the first aspect, the shift unit comprises a plurality of second-level D flip-flops and a plurality of second-level selectors, each of the second-level D flip-flops corresponding to one of the first-level selectors and one of the second-level selectors, and each of the second-level selectors being connected between a corresponding first-level selector and a corresponding second-level D flip-flop.

[0017] In a possible implementation of the first aspect, a low-level selection terminal of at least some of the second-level selectors corresponding to odd bits in the parallel data to be converted is connected to a data output terminal of a second-level D flip-flop corresponding to a next odd bit in the parallel data to be converted, a second high-level selection terminal of at least some of the second-level selectors corresponding to the odd bits in the parallel data to be converted is connected to a data output terminal of a corresponding first-level selector, and a selection control signal of the second-level selectors corresponding to the odd bits in the parallel data to be converted is the second selection control signal.

[0018] In a possible implementation of the first aspect, a low-level selection terminal of at least some of the second-level selectors corresponding to even bits in the parallel data to be converted is connected to a data output terminal of a second-level D flip-flop corresponding to a next even bit in the parallel data to be converted, a second high-level selection terminal of at least some of the second-level selectors corresponding to the even bits in the parallel data to be converted is connected to a data output terminal of a corresponding first-level selector, and a selection control signal of the second-level selectors corresponding to the even bits in the parallel data to be converted is the third selection control signal.

[0019] In a possible implementation of the first aspect, the parallel-to-serial conversion circuit further comprises an inverter, an input terminal of the inverter being connected to the serial clock signal terminal.

[0020] a data input terminal of a second-stage D flip-flop corresponding to an odd bit in the parallel data to be converted is connected to a data output terminal of a second-stage selector corresponding to the odd bit in the parallel data to be converted, and a clock terminal of the second-stage D flip-flop corresponding to the odd bit in the parallel data to be converted is connected to an output terminal of the inverter;

[0021] a data input terminal of a second-stage D flip-flop corresponding to an even bit in the parallel data to be converted is connected to a data output terminal of a second-stage selector corresponding to the even bit in the parallel data to be converted, and a clock terminal of the second-stage D flip-flop corresponding to the even bit in the parallel data to be converted is connected to the serial clock signal terminal.

[0022] In a possible implementation of the first aspect, the selection output unit includes a third selector, a high-level selection terminal of the third selector is connected to a data output terminal of the second-stage D flip-flop corresponding to a first odd bit in the parallel data to be converted, a low-level selection terminal of the third selector is connected to a data output terminal of the second-stage D flip-flop corresponding to a first even bit in the parallel data to be converted, and a selection control signal of the third selector is the serial clock signal.

[0023] In a possible implementation of the first aspect, the parallel-to-serial conversion circuit further includes a configuration interface, the configuration interface being configured to configure state jumping and state output of the configurable state machine.

[0024] Compared with the prior art, the application has the beneficial effects that: the parallel-serial conversion circuit provided by the application, wherein the parallel data storage unit is connected with the parallel data input end and the parallel clock signal end, and is used for storing the parallel data to be converted along with the parallel clock signal, so that the parallel data to be converted is captured through the synchronous parallel clock signal, the timing consistency of the data in the storage is ensured, and data conflict or loss is avoided. This design simplifies the data loading process, improves the data throughput efficiency, and is especially suitable for high-frequency parallel data input scenarios. The parity data exchange unit directly outputs or outputs after parity bit exchange according to the first selection control signal, and the first selection control signal is related to the bit width of the parallel data to be converted, so that whether the parallel data to be converted is exchanged according to the conversion requirement of parallel data of different bit widths, the order of the bits of the parallel data to be converted is adjusted dynamically to adapt to different parallel-serial conversion ratio requirements, and the problem of fixed bit width limitation in the traditional design is solved. The shift unit generates shift data by shifting the data along with the serial clock signal according to the second selection control signal and the third selection control signal generated by the configurable state machine. The shift process is controlled through the configurable state machine, so that the second selection control signal and the third selection control signal generated are dynamically adjusted according to the actual parallel-serial conversion requirement, so as to realize data shifting in different parallel-serial conversion modes, and ensure that each bit of the parallel data to be converted can be strictly output according to the timing, thereby providing data basis for subsequent output of the serial bit stream according to the time sequence. The selection output unit outputs each bit data in the shift data in turn along with the high and low levels of the serial clock. Therefore, the serial bit stream can be output in turn by using the edge of the clock to trigger, this design simplifies the output logic, reduces the occupation of hardware resources, reduces the power consumption, and at the same time ensures the accurate synchronization of data output, and improves the reliability of the overall circuit.

[0025] According to the above analysis, the parallel-serial conversion circuit provided by the application can dynamically configure the specific parallel-serial conversion ratio according to the actual parallel-serial conversion requirement through the modular design and the dynamic configuration mechanism, solves the problem that the parallel-serial conversion ratio is limited in the I / O interface of the FPGA, and improves the flexibility of the use of the I / O interface of the FPGA. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 According to some embodiments of the application, a structural block diagram of a parallel-serial conversion circuit is shown;

[0027] Figure 2 According to some embodiments of the application, a circuit diagram of a parallel-serial conversion circuit is shown;

[0028] Figure 3 According to some embodiments of the application, a timing diagram of 8:1 parallel-serial conversion is shown;

[0029] Figure 4 According to some embodiments of the present application, a timing diagram of 7:1 parallel-to-serial conversion is shown.

[0030] Figure 5 According to some embodiments of the present application, a brief flowchart of a state machine is shown.

[0031] Figure 6 According to some embodiments of the present application, a brief flowchart of another state machine is shown.

[0032] Figure 7 According to some embodiments of the present application, a timing diagram of DCI is shown. DETAILED DESCRIPTION

[0033] Illustrative embodiments of the present application include, but are not limited to, a parallel-to-serial conversion circuit.

[0034] In order to make the purposes, technical solutions and advantages of the present application clearer, further detailed description of the present application is made below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0035] In order to solve the technical problem that the parallel-to-serial conversion ratio in the I / O interface of the FPGA is limited in the prior art, resulting in limited use scenarios of the I / O interface of the FPGA, the present application provides a parallel-to-serial conversion circuit, which can dynamically configure the specific parallel-to-serial conversion ratio according to the actual parallel-to-serial conversion requirement through modular design and dynamic configuration mechanism, solves the problem that the parallel-to-serial conversion ratio in the I / O interface of the FPGA is limited, and improves the flexibility of the use of the I / O interface of the FPGA.

[0036] Reference Figure 1 The parallel-to-serial conversion circuit 10 provided by the present application includes a parallel data storage unit 11, a parity data exchange unit 12, a shift unit 13 and a selection output unit 14.

[0037] The parallel data storage unit 11 is connected to a parallel data input end 15 and a parallel clock signal end 17, and is used to store the to-be-converted parallel data with the parallel clock signal PCLK input from the parallel clock signal end 17. Thus, the to-be-converted parallel data is captured through the synchronous parallel clock signal PCLK, ensuring the timing consistency of the data when stored, and avoiding data conflict or loss. This design simplifies the data loading process and improves the data throughput efficiency, and is especially suitable for high-frequency parallel data input scenarios.

[0038] The parity data exchange unit 12 is connected between the parallel data storage unit 11 and the shift unit 13, and is configured to output the parallel data output by the parallel data storage unit 11 directly or after parity data bit exchange according to a first selection control signal, wherein the first selection control signal is related to the bit width of the parallel data to be converted. Thus, according to the conversion requirement of parallel data of different bit widths, it can be selected whether to perform parity exchange on the parallel data to be converted, and by dynamically adjusting the order of the bits of the parallel data to be converted, the problem of fixed bit width limitation in the traditional design is solved.

[0039] The shift unit 13 is connected to the parity data exchange unit 12, the selection output unit 14, and the serial clock signal terminal 18, and is configured to perform data shift on the parallel data output by the parity data exchange unit 12 according to a second selection control signal load_sel and a third selection control signal load_n_sel and a serial clock signal SCLK input by the serial clock signal terminal 18, to obtain shifted data, wherein the second selection control signal load_sel and the third selection control signal load_n_sel are generated based on a configurable state machine. By controlling the shift process through the configurable state machine, the second selection control signal load_sel and the third selection control signal load_n_sel generated can be dynamically adjusted according to the actual parallel-serial conversion requirement, so as to realize data shift in different parallel-serial conversion modes, and ensure that each bit of the parallel data to be converted can be strictly output according to the time sequence, thereby providing a data basis for subsequent output of a serial bit stream according to the time sequence.

[0040] The selection output unit 14 is connected to the shift unit 13, the serial clock signal terminal 18, and the serial data output terminal 19, and is configured to output each bit of data in the shifted data in sequence according to the high and low levels of the serial clock signal SCLK. Thus, the serial bit stream can be output in sequence by using the edge of the clock to trigger, which simplifies the output logic, reduces the occupation of hardware resources, reduces power consumption, and at the same time ensures the accurate synchronization of data output, thereby improving the reliability of the overall circuit.

[0041] In some embodiments, the data bit width of the parallel data to be converted is N1, N1 is a positive integer, and the serial clock signal SCLK is times the frequency of the parallel clock signal PCLK, so as to ensure that each parallel data bit has an independent cycle. For example, assuming that the data bit width of the parallel data to be converted is 8, the serial clock signal SCLK is 4 times the frequency of the parallel clock signal PCLK; for another example, assuming that the data bit width of the parallel data to be converted is 7, the serial clock signal SCLK is 3.5 times the frequency of the parallel clock signal PCLK.

[0042] With reference to the above description, it can be seen that the parallel-serial conversion circuit according to the present application has the following advantages: Figure 1The parallel-serial conversion circuit 10 described above further comprises a configuration interface 16, which is configured to configure the state jump and state output of the configurable state machine. The configuration interface 16 includes but is not limited to DCI, AXIS and APB, etc. The specific content of the state jump and state output of the state machine will be described in detail below, which will not be described here.

[0043] The specific content of the parallel-serial conversion circuit 10 provided by the present application will be described in detail below. Figure 2 The specific content of the parallel-serial conversion circuit 10 provided by the present application will be described in detail below.

[0044] Reference is made to Figure 2 The parallel data storage unit 11 comprises a plurality of first-level D flip-flops 111, the clock end of each first-level D flip-flop is connected to the parallel clock signal end 17, and the data input end of each first-level D flip-flop is connected to one of the data ports of the parallel data input end 15 in sequence, each first-level D flip-flop is used to store and output one bit of binary data in the to-be-converted parallel data with the parallel clock signal PCLK. In addition, the data bit width N1 of the to-be-converted parallel data is less than or equal to the number N2 of the first-level D flip-flops, and N2 is a positive integer. For example, assuming that N2 is 10, N1 can be 10, N1 can also be 9, N1 can also be 8, N1 can also be 7, as long as N1 is less than 10.

[0045] It should be understood that in actual application, the number of N1 and N2 is not limited to Figure 2 10 in the above embodiment, and the specific value of N1 and N2 can be determined according to actual needs.

[0046] Specifically, Figure 2The clock terminal of the first-stage D flip-flop xDFF_data_pclk_sync_0 is connected to the parallel clock signal end 17, and the data input terminal of the first-stage D flip-flop xDFF_data_pclk_sync_0 is connected to the parallel data input end 15 din[0]; the clock terminal of the first-stage D flip-flop xDFF_data_pclk_sync_1 is connected to the parallel clock signal end 17, and the data input terminal of the first-stage D flip-flop xDFF_data_pclk_sync_1 is connected to the parallel data input end 15 din[1]; the clock terminal of the first-stage D flip-flop xDFF_data_pclk_sync_2 is connected to the parallel clock signal end 17, and the data input terminal of the first-stage D flip-flop xDFF_data_pclk_sync_2 is connected to the parallel data input end 15 din[2]; the clock terminal of the first-stage D flip-flop xDFF_data_pclk_sync_3 is connected to the parallel clock signal end 17, and the data input terminal of the first-stage D flip-flop xDFF_data_pclk_sync_3 is connected to the parallel data input end 15 din[3]; the clock terminal of the first-stage D flip-flop xDFF_data_pclk_sync_4 is connected to the parallel clock signal end 17, and the data input terminal of the first-stage D flip-flop xDFF_data_pclk_sync_4 is connected to the parallel data input end 15 din[4]; the clock terminal of the first-stage D flip-flop xDFF_data_pclk_sync_5 is connected to the parallel clock signal end 17, and the data input terminal of the first-stage D flip-flop xDFF_data_pclk_sync_5 is connected to the parallel data input end 15 din[5]; the clock terminal of the first-stage D flip-flop xDFF_data_pclk_sync_6 is connected to the parallel clock signal end 17, and the data input terminal of the first-stage D flip-flop xDFF_data_pclk_sync_6 is connected to the parallel data input end 15 din[6]; the clock terminal of the first-stage D flip-flop xDFF_data_pclk_sync_7 is connected to the parallel clock signal end 17, and the data input terminal of the first-stage D flip-flop xDFF_data_pclk_sync_7 is connected to the parallel data input end 15 din[7]; the clock terminal of the first-stage D flip-flop xDFF_data_pclk_sync_8 is connected to the parallel clock signal end 17, and the data input terminal of the first-stage D flip-flop xDFF_data_pclk_sync_8 is connected to the parallel data input end 15 din[8]; the clock terminal of the first-stage D flip-flop xDFF_data_pclk_sync_9 is connected to the parallel clock signal end 17, and the data input terminal of the first-stage D flip-flop xDFF_data_pclk_sync_9 is connected to the parallel data input end 15 din[9].

[0047] In the case that the bit width of the parallel data to be converted is even, for example, 8, the first selection control signal load is low, and the parity data exchange unit 12 is configured to output the parallel data outputted by the parallel data storage unit 11 directly according to the first selection control signal load.

[0048] In the case that the bit width of the parallel data to be converted is odd, for example, 7, the first selection control signal load is high, and the parity data exchange unit 12 is configured to output the parallel data outputted by the parallel data storage unit 11 after exchanging the parity data bits according to the first selection control signal load, for example, outputting the data A0 inputted by din[0] and the data A1 inputted by din[1] after exchanging, outputting the data A2 inputted by din[2] and the data A3 inputted by din[3] after exchanging, and outputting the data A4 inputted by din[4] and the data A5 inputted by din[5] after exchanging. Figure 2

[0049] Referring to Figure 2 , the parity data exchange unit 12 comprises a plurality of first-level selectors 121, each of which corresponds to a first-level D flip-flop, the low-level selection end of at least part of the first-level selectors is connected to the data output end of the corresponding first-level D flip-flop, the first high-level selection end of at least part of the first-level selectors is connected to the data output end of the first-level D flip-flop adjacent to the corresponding first-level D flip-flop, and each of the first-level selectors is configured to select and output one bit from the one-bit binary data outputted by the corresponding first-level D flip-flop and the one-bit binary data outputted by the adjacent first-level D flip-flop according to the first selection control signal load.

[0050] ​In particular, the first stage selector xMUX_do_d1 corresponds to the first stage D flip-flop xDFF_data_pclk_sync_0; the first stage selector xMUX_d1_d0 corresponds to the first stage D flip-flop xDFF_data_pclk_sync_1; the first stage selector xMUX_d2_d3 corresponds to the first stage D flip-flop xDFF_data_pclk_sync_2; the first stage selector xMUX_d3_d2 corresponds to the first stage D flip-flop xDFF_data_pclk_sync_3; the first stage selector xMUX_d4_d5 corresponds to the first stage D flip-flop xDFF_data_pclk_sync_4; the first stage selector xMUX_d5_d4 corresponds to the first stage D flip-flop xDFF_data_pclk_sync_5; the first stage selector xMUX_d6_d7 corresponds to the first stage D flip-flop xDFF_data_pclk_sync_6; the first stage selector xMUX_d7_d6 corresponds to the first stage D flip-flop xDFF_data_pclk_sync_7; the first stage selector xMUX_d8_d9 corresponds to the first stage D flip-flop xDFF_data_pclk_sync_8; the first stage selector xMUX_d9_d8 corresponds to the first stage D flip-flop xDFF_data_pclk_sync_9.

[0051] The low level selection end of the first level selector xMUX_d0_d1 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_0, the high level selection end of the first level selector xMUX_do_d1 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_1; the low level selection end of the first level selector xMUX_d1_d0 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_1, the high level selection end of the first level selector xMUX_d1_d0 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_0; the low level selection end of the first level selector xMUX_d2_d3 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_2, the high level selection end of the first level selector xMUX_d2_d3 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_3; the low level selection end of the first level selector xMUX_d3_d2 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_3, the high level selection end of the first level selector xMUX_d3_d2 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_2; the low level selection end of the first level selector xMUX_d4_d5 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_4, the high level selection end of the first level selector xMUX_d4_d5 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_5; the low level selection end of the first level selector xMUX_d5_d4 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_5, the high level selection end of the first level selector xMUX_d5_d4 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_4; the low level selection end of the first level selector xMUX_d6_d7 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_6, the high level selection end of the first level selector xMUX_d6_d7 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_7; the low level selection end of the first level selector xMUX_d7_d6 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_7, the high level selection end of the first level selector xMUX_d7_d6 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_6;The low level selection end of the first level selector xMUX_d8_d9 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_9, and the high level selection end of the first level selector xMUX_d8_d9 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_8; the low level selection end of the first level selector xMUX_d9_d8 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_8, and the high level selection end of the first level selector xMUX_d9_d8 is connected to the data output end of the first level D flip-flop xDFF_data_pclk_sync_9.

[0052] With reference to Figure 2 , the shift unit 13 comprises a plurality of second level D flip-flops 132 and a plurality of second level selectors 131, each second level D flip-flop corresponding to each second level selector and each first level selector, and each second level selector being connected between the corresponding first level selector and second level D flip-flop.

[0053] Specifically, the second level D flip-flop xDFF_d0 corresponds to the second level selector xMUX_d0 and the first level selector xMUX_d0_d1; the second level D flip-flop xDFF_d1 corresponds to the second level selector xMUX_d1 and the first level selector xMUX_d1_d0; the second level D flip-flop xDFF_d2 corresponds to the second level selector xMUX_d2 and the first level selector xMUX_d2_d3; the second level D flip-flop xDFF_d3 corresponds to the second level selector xMUX_d3 and the first level selector xMUX_d3_d2; the second level D flip-flop xDFF_d4 corresponds to the second level selector xMUX_d4 and the first level selector xMUX_d4_d5; the second level D flip-flop xDFF_d5 corresponds to the second level selector xMUX_d5 and the first level selector xMUX_d5_d4; the second level D flip-flop xDFF_d6 corresponds to the second level selector xMUX_d6 and the first level selector xMUX_d6_d7; the second level D flip-flop xDFF_d7 corresponds to the second level selector xMUX_d7 and the first level selector xMUX_d7_d6; the second level D flip-flop xDFF_d8 corresponds to the second level selector xMUX_d8 and the first level selector xMUX_d8_d9; and the second level D flip-flop xDFF_d9 corresponds to the second level selector xMUX_d9 and the first level selector xMUX_d9_d8.

[0054] The low level selection end of the second stage selector corresponding to at least part of the odd bit in the parallel data to be converted is connected to the data output end of the second stage D flip-flop corresponding to the next odd bit in the parallel data to be converted; the second high level selection end of the second stage selector corresponding to at least part of the odd bit in the parallel data to be converted is connected to the data output end of the first stage selector corresponding to the second stage selector, and the selection control signal of the second stage selector corresponding to the odd bit in the parallel data to be converted is the second selection control signal load_sel.

[0055] Specifically, the low level selection end of the second stage selector xMUX_d0 corresponding to the first bit data in the parallel data to be converted is connected to the data output end of the second stage D flip-flop xDFF_d2, and the high level selection end of the second stage selector xMUX_d0 is connected to the data output end of the first stage selector xMUX_d0_d1; the low level selection end of the second stage selector xMUX_d2 corresponding to the third bit data in the parallel data to be converted is connected to the data output end of the second stage D flip-flop xDFF_d4, and the high level selection end of the second stage selector xMUX_d2 is connected to the data output end of the first stage selector xMUX_d2_d3; the low level selection end of the second stage selector xMUX_d4 corresponding to the fifth bit data in the parallel data to be converted is connected to the data output end of the second stage D flip-flop xDFF_d6, and the high level selection end of the second stage selector xMUX_d6 is connected to the data output end of the first stage selector xMUX_d4_d5; the low level selection end of the second stage selector xMUX_d6 corresponding to the seventh bit data in the parallel data to be converted is connected to the data output end of the second stage D flip-flop xDFF_d8, and the high level selection end of the second stage selector xMUX_d6 is connected to the data output end of the first stage selector xMUX_d6_d7; the low level selection end of the second stage selector xMUX_d8 corresponding to the ninth bit data in the parallel data to be converted is connected to the high level, and the high level selection end of the second stage selector xMUX_d8 is connected to the data output end of the first stage selector xMUX_d8_d9.

[0056] The low level selection end of the second stage selector corresponding to at least part of the even bit in the parallel data to be converted is connected to the data output end of the second stage D flip-flop corresponding to the next even bit in the parallel data to be converted; the second high level selection end of the second stage selector corresponding to at least part of the even bit in the parallel data to be converted is connected to the data output end of the first stage selector corresponding to the second stage selector; and the selection control signal of the second stage selector corresponding to the even bit in the parallel data to be converted is the third selection control signal load_n_sel.

[0057] In particular, the low level selection end of the second level selector xMUX_d1 corresponding to the second bit data in the parallel data to be converted is connected to the data output end of the second level D flip-flop xDFF_d3, and the high level selection end of the second level selector xMUX_d1 is connected to the data output end of the first level selector xMUX_d1_d0.

[0058] The low level selection end of the second level selector xMUX_d3 corresponding to the fourth bit data in the parallel data to be converted is connected to the data output end of the second level D flip-flop xDFF_d5, and the high level selection end of the second level selector xMUX_d3 is connected to the data output end of the first level selector xMUX_d3_d2.

[0059] The low level selection end of the second level selector xMUX_d5 corresponding to the sixth bit data in the parallel data to be converted is connected to the data output end of the second level D flip-flop xDFF_d7, and the high level selection end of the second level selector xMUX_d5 is connected to the data output end of the first level selector xMUX_d5_d4.

[0060] The low level selection end of the second level selector xMUX_d7 corresponding to the eighth bit data in the parallel data to be converted is connected to the data output end of the second level D flip-flop xDFF_d9, and the high level selection end of the second level selector xMUX_d7 is connected to the data output end of the first level selector xMUX_d7_d6.

[0061] The low level selection end of the second level selector xMUX_d9 corresponding to the tenth bit data in the parallel data to be converted is connected to the high level, and the high level selection end of the second level selector xMUX_d9 is connected to the data output end of the first level selector xMUX_d9_d8.

[0062] Continuing to refer to Figure 2 The parallel-to-serial conversion circuit 10 described above further comprises an inverter, the input end of the inverter is connected to the serial clock signal end 18. The data input end of the second level D flip-flop corresponding to the odd bit data in the parallel data to be converted is connected to the data output end of the second level selector corresponding to the odd bit data in the parallel data to be converted, and the clock end of the second level D flip-flop corresponding to the odd bit data in the parallel data to be converted is connected to the output end of the inverter.

[0063] In particular, the data input terminal of the second-stage D flip-flop xDFF_d0 is connected to the data output terminal of the second-stage selector xMUX_d0, and the clock terminal of the second-stage D flip-flop xDFF_d0 is connected to the output terminal of the inverter; the data input terminal of the second-stage D flip-flop xDFF_d2 is connected to the data output terminal of the second-stage selector xMUX_d2, and the clock terminal of the second-stage D flip-flop xDFF_d2 is connected to the output terminal of the inverter; the data input terminal of the second-stage D flip-flop xDFF_d4 is connected to the data output terminal of the second-stage selector xMUX_d4, and the clock terminal of the second-stage D flip-flop xDFF_d4 is connected to the output terminal of the inverter; the data input terminal of the second-stage D flip-flop xDFF_d6 is connected to the data output terminal of the second-stage selector xMUX_d6, and the clock terminal of the second-stage D flip-flop xDFF_d6 is connected to the output terminal of the inverter; the data input terminal of the second-stage D flip-flop xDFF_d8 is connected to the data output terminal of the second-stage selector xMUX_d8, and the clock terminal of the second-stage D flip-flop xDFF_d8 is connected to the output terminal of the inverter.

[0064] The data input terminal of the second-stage D flip-flop corresponding to the even bit in the parallel data to be converted is connected to the data output terminal of the second-stage selector corresponding to the even bit in the parallel data to be converted, and the clock terminal of the second-stage D flip-flop corresponding to the even bit in the parallel data to be converted is connected to the serial clock signal terminal 18.

[0065] In particular, the data input terminal of the second-stage D flip-flop xDFF_d1 is connected to the data output terminal of the second-stage selector xMUX_d1, and the clock terminal of the second-stage D flip-flop xDFF_d1 is connected to the serial clock signal terminal 18;

[0066] The data input terminal of the second-stage D flip-flop xDFF_d3 is connected to the data output terminal of the second-stage selector xMUX_d3, and the clock terminal of the second-stage D flip-flop xDFF_d3 is connected to the serial clock signal terminal 18;

[0067] The data input terminal of the second-stage D flip-flop xDFF_d5 is connected to the data output terminal of the second-stage selector xMUX_d5, and the clock terminal of the second-stage D flip-flop xDFF_d5 is connected to the serial clock signal terminal 18;

[0068] The data input terminal of the second-stage D flip-flop xDFF_d7 is connected to the data output terminal of the second-stage selector xMUX_d7, and the clock terminal of the second-stage D flip-flop xDFF_d7 is connected to the serial clock signal terminal 18;

[0069] The data input terminal of the second-stage D flip-flop xDFF_d9 is connected to the data output terminal of the second-stage selector xMUX_d9, and the clock terminal of the second-stage D flip-flop xDFF_d9 is connected to the serial clock signal terminal 18.

[0070] Continuing to refer toFigure 2 The selection output unit 14 includes a third selector, a high level selection end of the third selector is connected to a data output end of the second stage D flip-flop corresponding to the first odd bit in the parallel data to be converted, a low level selection end of the third selector is connected to a data output end of the second stage D flip-flop corresponding to the first even bit in the parallel data to be converted, and a selection control signal of the third selector is the serial clock signal SCLK.

[0071] Specifically, the high level selection end of the third selector xMUX_qout is connected to the data output end of the second stage D flip-flop xDFF_d0 corresponding to the first bit data in the parallel data to be converted, and the low level selection end of the third selector xMUX_qout is connected to the data output end of the second stage D flip-flop xDFF_d1 corresponding to the second bit data in the parallel data to be converted.

[0072] It should be noted that, Figure 2 The parallel-serial conversion circuit 10 in the above embodiment is taken as an example in which the parallel data input end 15 includes 10 data input ports, and in actual applications, the number of circuit elements in the parallel-serial conversion circuit 10 provided by the present application can be determined according to actual needs.

[0073] The principle of the parallel-serial conversion circuit 10 shown in the above embodiment will be described in detail below by taking the parallel-serial conversion of the I / O interface 8:1 of the FPGA and the 7:1 parallel-serial conversion as examples, and by taking the timing diagrams shown in Figure 3 and Figure 4 as examples. Figure 2 Figure 2

[0074] For the 8:1 parallel-serial conversion mode:

[0075] 1. First, the programmable logic will pass the data to the parallel-serial conversion circuit, the port is din in the circuit diagram shown in Figure 2 Assuming that the first data is [A7, A6, A5, A4, A3, A2, A1, A0], it is synchronized with the xDFF_data_pclk_sync_* dff in the pclk domain for one beat, and the pclk_sync* in the timing diagram is obtained. Next, the pclk_sync* signal will first pass through the selector named xMUX_d*_d*, and the purpose is to exchange the odd and even positions in the data bits [A7, A6, A5, A4, A3, A2, A1, A0]. For the even mode, no exchange is needed, so the selection end load signal of the selector is low.

[0076] ​​2、Next, the pclk_sync* signal reaches the selector xMUX_d*, which is mainly used to load the parallel data [A7, A6, A5, A4, A3, A2, A1, A0] into the xDFF_d* registers in the sclk clock domain, for example: for the selectors xMUX_d1, xMUX_d3, xMUX_d5, xMUX_d7 with odd ends, the selection signal is load_n_sel, which is high, and the odd data [A7, A5, A3, A1] in the corresponding parallel data is selected into xDFF_d1, xDFF_d3, xDFF_d5, xDFF_d7 to obtain the signals d_1, d_3, d_5, d_7; for the selectors xMUX_d0, xMUX_d2, xMUX_d4, xMUX_d6 with even ends, the selection signal is load_n, which is high, and the even data [A6, A4, A2, A0] in the corresponding parallel data is selected into xDFF_d0, xDFF_d2, xDFF_d4, xDFF_d6 to obtain the signals d_0, d_2, d_4, d_6. It should be noted that the clock used by xDFF_d1, xDFF_d3, xDFF_d5, xDFF_d7 is the positive edge of sclk, and the clock used by xDFF_d0, xDFF_d2, xDFF_d4, xDFF_d6 is the negative edge of sclk.

[0077] 3、In a pclk cycle, load_n_sel will only be pulled up once, so in the remaining time in the pclk cycle (except for the sclk cycle when load_n_sel is pulled up, 1 pclk cycle corresponds to 4 sclk cycles), the data of xDFF_d7 will reach xDFF_d5, the data of xDFF_d5 will reach xDFF_d3, the data of xDFF_d3 will reach xDFF_d1, and the data of xDFF_d1 will reach the low-level selection end of xMUX_qout; similarly, in a pclk cycle, load_sel will only be pulled up once, so in the remaining time in the pclk cycle (except for the sclk cycle when load_sel is pulled up, 1 pclk cycle corresponds to 4 sclk cycles), the data of xDFF_d6 will reach xDFF_d4, the data of xDFF_d4 will reach xDFF_d2, the data of xDFF_d2 will reach xDFF_d0, and the data of xDFF_d0 will reach the high-level selection end of xMUX_qout; it should be noted that load_sel_n is generated at the negative edge of sclk, and load_sel is generated at the positive edge of sclk.

[0078] 4、After the above processing, xDFF_d* odd data will reach the low level selection end of xMUX_qout in 4 sclk cycles; xDFF_d* even data will reach the high level selection end of xMUX_qout in 4 sclk cycles. The selection end of xMUX_qout is the sclk clock positive edge, and in 4 sclk cycles, its high and low levels will be flipped four times in turn, and in the first high level, data A0 is sent out, in the first low level, data A1 is sent out, in the second high level, data A2 is sent out, in the second low level, data A3 is sent out, in the third high level, data A4 is sent out, in the third low level, data A5 is sent out, in the fourth high level, data A6 is sent out, and in the fourth low level, data A7 is sent out. Through the above four steps, the conversion of pclk domain data is completed

[0079] 5、The above processes 1~4 are cycled to convert the subsequent data.

[0080] For 7:1 parallel-serial conversion mode:

[0081] 1、First, the programmable logic will pass the data to the parallel-serial conversion circuit, the port is din in the circuit diagram shown in Figure 2 Assuming that the first data is [A6, A5, A4, A3, A2, A1, A0], it is synchronized with xDFF_data_pclk_sync_* in the pclk domain, and the pclk_sync* in the timing diagram is obtained; next, the pclk_sync* signal will first pass through the selector named xMUX_d*_d*, and the purpose is to exchange the odd and even positions in the data bit [A6, A5, A4, A3, A2, A1, A0], for odd mode, it needs to be exchanged once every pclk cycle, and the first pclk data domain is low;

[0082] 2、Next, the pclk_sync* signal reaches the selector xMUX_d*, which is mainly used to load the parallel data [A6, A5, A4, A3, A2, Al, A0] into the xDFF_d* registers in the sclk clock domain. For example, for the selectors xMUX_d1, xMUX_d3, xMUX_d5, and xMUX_d7 with odd ends, the selection signal is load_n_sel, which is high, and the odd data [A7, A5, A3, Al] in the corresponding parallel data is selected into the xDFF_d1, xDFF_d3, xDFF_d5, and xDFF_d7 registers to obtain the signals d_1, d_3, d_5, and d_7. For the selectors xMUX_d0, xMUX_d2, xMUX_d4, and xMUX_d6 with even ends, the selection signal is load_n, which is high, and the even data [A6, A4, A2, A0] in the corresponding parallel data is selected into the xDFF_d0, xDFF_d2, xDFF_d4, and xDFF_d6 registers to obtain the signals d_0, d_2, d_4, and d_6. Figure 4 As can be seen, when load is low, the data synchronized to the registers d_7, d_5, d_3, and d_1 is the even part of the 8-bit data, i.e., [A7, A5, A3, Al], and the data synchronized to the registers d_6, d_4, d_2, and d_0 is the odd part of the 8-bit data, i.e., [A6, A4, A2, A0]. It should be noted that the clock used by the xDFF_d1, xDFF_d3, xDFF_d5, and xDFF_d7 registers is the positive edge of sclk, and the clock used by the xDFF_d0, xDFF_d2, xDFF_d4, and xDFF_d6 registers is the negative edge of sclk.

[0083] 3、In a pclk cycle, load_n_sel will only be pulled high once, so in the remaining time in the pclk cycle (except for the sclk cycle in which load_n_sel is pulled high, 1 pclk cycle corresponds to 3.5 sclk cycles), the data of xDFF_d5 will reach xDFF_d3, the data of xDFF_d3 will reach xDFF_d1, and the data of xDFF_d1 will reach the low-level selection end of xMUX_qout; similarly, in a pclk cycle, load_sel will only be pulled high once, so in the remaining time in the pclk cycle (except for the sclk cycle in which load_sel is pulled high, 1 pclk cycle corresponds to 3.5 sclk cycles), the data of xDFF_d6 will reach xDFF_d4, the data of xDFF_d4 will reach xDFF_d2, the data of xDFF_d2 will reach xDFF_d0, and the data of xDFF_d0 will reach the high-level selection end of xMUX_qout. It should be noted that load_sel_n is generated at the negative edge of sclk clock, and load_sel signal is generated at the positive edge of sclk clock.

[0084] 4、After the above processing, the xDFF_d* odd data will reach the low-level selection end of xMUX_qout in 3.5 sclk cycles; the xDFF_d* even data will reach the high-level selection end of xMUX_qout in 3.5 sclk cycles. The selection end of xMUX_qout is the positive edge of sclk clock, and in 3.5 sclk cycles, its high and low levels will be flipped 3.5 times in turn, with the first high-level sending out data A0, the first low-level sending out data A1, the second high-level sending out data A2, the second low-level sending out data A3, the third high-level sending out data A4, the third low-level sending out data A5, and the fourth high-level sending out data A6. Thus, the conversion of a pclk domain data is completed;

[0085] 5、The programmable logic will transfer the second parallel data to the parallel-serial circuit, and the port is Figure 1 In the circuit, din, assuming the second number of data is [B6, B5, B4, B3, B2, B1, B0], it is synchronized by xDFF_data_pclk_sync_* (* represents a number to avoid repeated writing) dff in the pclk domain for one beat, obtaining pclk_sync* in the timing diagram; next, the pclk_sync* signal will first pass through the selector named xMUX_d*_d*, the purpose of which is to exchange the odd and even positions in the data bits [B6, B5, B4, B3, B2, B1, B0]. For the odd mode, this needs to be exchanged once every pclk cycle, and the second pclk data domain is high;

[0086] 6、Next, the pclk_sync* signal reaches the selector xMUX_d*, which is mainly used to load the parallel data [B6, B5, B4, B3, B2, B1, B0] into the xDFF_d* registers in the sclk clock domain, for example: for the selectors xMUX_d1, xMUX_d3, xMUX_d5, xMUX_d7 with odd ends, the selection signal is load_n_sel, which is high, and the odd data [A7, A5, A3, A1] in the corresponding parallel data is selected into the xDFF_d1, xDFF_d3, xDFF_d5, xDFF_d7, to obtain the signals d_1, d_3, d_5, d_7; for the selectors xMUX_d0, xMUX_d2, xMUX_d4, xMUX_d6 with even ends, the selection signal is load_n, which is high, and the even data [A6, A4, A2, A0] in the corresponding parallel data is selected into the xDFF_d0, xDFF_d2, xDFF_d4, to obtain the signals d_0, d_2, d_4. From Figure 4 It can be seen that when load is high, the data synchronized to the registers d_7, d_5, d_3, d_1 is the even part of the 8-bit data, i.e. [B6, B4, B2, B0], and the data synchronized to the registers d_6, d_4, d_2, d_0 is the odd part of the 8-bit data, i.e. [B7, B5, B3, B1], which is the biggest difference from even conversion, and the reason is reflected in steps 4 and 8. It should be noted that the clock used by xDFF_d1, xDFF_d3, xDFF_d5, xDFF_d7 is the positive edge of sclk, and the clock used by xDFF_d0, xDFF_d2, xDFF_d4, xDFF_d6 is the negative edge of sclk.

[0087] 7、In a pclk cycle, load_n_sel will only be pulled high once, so in the remaining time of the pclk cycle (except for the sclk cycle when load_n_sel is pulled high, 1 pclk cycle corresponds to 3.5 sclk cycles), the data of xDFF_d7 will reach xDFF_d5, the data of xDFF_d5 will reach xDFF_d3, the data of xDFF_d3 will reach xDFF_d1, and the data of xDFF_d1 will reach the low-level selection end of xMUX_qout; similarly, in a pclk cycle, load_sel will only be pulled high once, so in the remaining time of the pclk cycle (except for the sclk cycle when load_sel is pulled high, 1 pclk cycle corresponds to 3.5 sclk cycles), the data of xDFF_d4 will reach xDFF_d2, the data of xDFF_d2 will reach xDFF_d0, and the data of xDFF_d0 will reach the high-level selection end of xMUX_qout; it should be noted that load_sel_n is generated at the negative edge of the sclk clock, and load_sel is generated at the positive edge of the sclk clock.

[0088] 8、After step 7, the xDFF_d* odd data will reach the low-level selection end of xMUX_qout in 3.5 sclk cycles; the xDFF_d* even data will reach the high-level selection end of xMUX_qout in 3.5 sclk cycles. The selection end of xMUX_qout is the positive edge of the sclk clock, and in 3.5 sclk cycles, its high and low levels will cycle and flip four times, with the first low-level sending out data B0, the first high-level sending out data B1, the second low-level sending out data B2, the second high-level sending out data B3, the third low-level sending out data B4, the third high-level sending out data B5, and the fourth low-level sending out data B6. Thus, the conversion of the second pclk domain data is completed;

[0089] 9、Repeat steps 1-8 to convert subsequent data.

[0090] The state machine will be described in detail below with reference to the flowcharts shown in Figure 5 and Figure 6 .

[0091] Figure 5 The state machine shown in the figure has a total of 8 states, each of which is uniquely identified by a one-hot code. When Figure 2The shown parallel-serial conversion circuit 10 is reset complete, the state jumps at each edge of the clock, by default, the state machine jumps from state 1 to state 2, 7 periods later, jumps to state 8, 8 periods later, jumps back to state 1. It should be noted that when the DCI interface is enabled, the next state is determined by the DCI configuration, for example: the current state is IDLE, the DCI interface is enabled, the next state is configured as 010, then the next state is state 4: F010 instead of state 1: F001. In addition, in different states, the control signals load, load_sel and load_n_sel can be output by DCI configuration.

[0092] Figure 6 The shown state machine is also a total of 8 states, for the DCI interface is not enabled, the state machine adjusts in the default state sequence, each state corresponds to a fast clock, that is SCLK, Figure 6 The shown state machine can output the control signals load, load_sel and load_n_sel required for 8:1 parallel-serial conversion, which can be seen in detail in Figure 6 When the DCI interface is enabled, the adjustment of the state and the control signals load, load_sel and load_n_sel output by each state are determined by the value configured by the DCI interface, for example, the state machine itself is in state 3, by default the next state is 4, but after the DCI interface is enabled and the state is configured as state 1, then the next state is state 1.

[0093] Figure 7DCI timing diagram is shown, wherein rstn is a DCI interface reset signal, when rstn is low, the DCI interface is restored to the default value, and the DCI interface does not work. dci_clk is a DCI interface clock signal; dci_io_sel is a DCI interface selection signal. dci_wren is a DCI interface write enable signal, when dci_wren is high, it indicates that the DCI interface is writing. dci_addr[3:0] is a DCI interface address signal, used to select the address of the register group required by the current slave to be configured. dci_wdata[2:0] is a DCI interface write data, used to configure the state value of the current slave register group. addr1 is the first DCI interface address information, for example, 4'd0; addr2 is the second DCI interface address information, for example, 4'd1; addr3 is the third DCI interface address information, for example, 4'd2; addr4 is the fourth DCI interface address information, for example, 4'd3. data1 is the first DCI interface data information, for example, 3'd0; data2 is the second DCI interface data information, for example, 3'd1; data3 is the third DCI interface data information, for example, 3'd2; data4 is the fourth DCI interface data information, for example, 3'd3.

[0094] FPGA has rich IO resources, each IO has a dynamic configurable parallel-serial circuit, they share a DCI interface (dci_io_sel is independent for each IO), through dci_io_sel to select the current configuration IO, this design is conducive to saving FPGA logic resources. At the same time, the frequency of dci_clk clock can be customized by the user, according to the power consumption and mode to choose flexibly. When dci_wren is high, according to the corresponding address, write the data containing state information and load signal information into the corresponding register, control the output of the load signal, so as to realize the configuration of different parallel-serial modes.

[0095] According to the above detailed introduction of the technical scheme of the application, the parallel data storage unit 11 in the parallel-serial conversion circuit 10 provided by the application is connected with the parallel data input end 15 and the parallel clock signal end 17, and is used for storing the to-be-converted parallel data along with the parallel clock signal PCLK, so as to capture the to-be-converted parallel data through the synchronous parallel clock signal PCLK, ensure the timing consistency of the data in the storage process, and avoid data conflict or loss. This design simplifies the data loading process, improves the data throughput efficiency, and is especially suitable for high-frequency parallel data input scenarios. The parity data exchange unit 12 directly outputs or outputs after parity bit exchange according to the first selection control signal load, and the first selection control signal load is related to the bit width of the to-be-converted parallel data, so that whether the to-be-converted parallel data is exchanged according to the conversion requirement of the parallel data of different bit widths, the order of the bits of the to-be-converted parallel data is adjusted dynamically to adapt to different parallel-serial conversion ratio requirements, and the problem of fixed bit width limitation in the traditional design is solved. The shift unit 13 generates shift data by shifting the data along with the serial clock signal SCLK according to the second selection control signal load_sel and the third selection control signal load_n_sel generated by the configurable state machine. The shift process is controlled through the configurable state machine, so that the second selection control signal load_sel and the third selection control signal load_n_sel generated can be dynamically adjusted according to the actual parallel-serial conversion requirement, so as to realize the data shift in different parallel-serial conversion modes, and ensure that each bit of the to-be-converted parallel data can be strictly output according to the timing, thereby providing a data basis for subsequent output of the serial bit stream according to the time sequence. The selection output unit 14 outputs each bit of data in the shift data in sequence along with the high and low levels of the serial clock. Therefore, the serial bit stream can be output in sequence through the edge trigger of the clock. This design simplifies the output logic, reduces the occupation of hardware resources, reduces power consumption, and at the same time ensures the accurate synchronization of data output and improves the reliability of the overall circuit.

[0096] In summary, the parallel-serial conversion circuit 10 provided by the application can dynamically configure the specific parallel-serial conversion ratio according to the actual parallel-serial conversion requirement through the modular design and the dynamic configuration mechanism, solves the problem that the parallel-serial conversion ratio is limited in the I / O interface of the FPGA, and improves the flexibility of the use of the I / O interface of the FPGA.

[0097] Embodiments of the mechanisms disclosed herein can be implemented in hardware, software, firmware, or combinations thereof. Embodiments of the application can be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0098] It should be noted that each unit / module mentioned in each device embodiment of the present application is a logical unit / module, and in physical form, one logical unit / module can be a physical unit / module, or a part of a physical unit / module, or be realized in a combination of multiple physical unit / modules, and the physical realization form of these logical units / modules is not the most important, and the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that the above-mentioned device embodiments do not have other units / modules.

[0099] It should be noted that in the examples and descriptions of the present patent, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including one" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0100] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it should be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present application.

Claims

1. A parallel-to-serial conversion circuit, characterized by comprising: The parallel data storage unit, the parity data exchange unit, the shift unit and the selection output unit are included. The parallel data storage unit is connected with a parallel data input end and a parallel clock signal end, and is used for storing the parallel data to be converted according to the parallel clock signal input from the parallel clock signal end. The parity data exchange unit is connected between the parallel data storage unit and the shift unit, and is used for directly outputting the parallel data output from the parallel data storage unit or outputting the parallel data output from the parallel data storage unit after exchanging the parity data bit according to the first selection control signal, wherein the first selection control signal is related to the bit width of the parallel data to be converted. The shift unit is connected with the parity data exchange unit, the selection output unit and a serial clock signal end, and is used for shifting the parallel data output from the parity data exchange unit according to the second selection control signal and the third selection control signal to obtain the shift data according to the serial clock signal input from the serial clock signal end, wherein the second selection control signal and the third selection control signal are generated based on the configurable state machine. The selection output unit is connected with the shift unit, the serial clock signal input end and a serial data output end, and is used for sequentially outputting each bit data in the shift data according to the high and low levels of the serial clock signal. The parallel data storage unit includes a plurality of first-level D flip-flops, the clock end of each first-level D flip-flop is connected with the parallel clock signal end, the data input end of each first-level D flip-flop is sequentially connected with one data port of the parallel data input end, each first-level D flip-flop is used for storing and outputting one bit binary data in the parallel data to be converted according to the parallel clock signal, and the data bit width N1 of the parallel data to be converted is less than or equal to the number N2 of the first-level D flip-flops, wherein N2 is a positive integer.

2. The parallel-to-serial conversion circuit of claim 1, wherein, The data bit width of the parallel data to be converted is N1, N1 is a positive integer, the serial clock signal is the parallel clock signal multiplied by .

3. The parallel-to-serial conversion circuit of claim 2, wherein, In the case that the bit width of the parallel data to be converted is even, the first selection control signal is low, and the parity data exchange unit is used for directly outputting the parallel data output from the parallel data storage unit according to the first selection control signal.

4. The parallel-to-serial conversion circuit of claim 1, wherein, In the case that the bit width of the parallel data to be converted is odd, the first selection control signal is high, and the parity data exchange unit is used for outputting the parallel data output from the parallel data storage unit after exchanging the parity data bit according to the first selection control signal. ​ 5. The parallel-to-serial conversion circuit of claim 3, wherein, The parity data switching unit comprises a plurality of first-stage selectors, each of the first-stage selectors corresponds to a first-stage D flip-flop, a low-level selection end of at least part of the first-stage selectors is connected to a data output end of the corresponding first-stage D flip-flop, a first high-level selection end of at least part of the first-stage selectors is connected to a data output end of a first-stage D flip-flop adjacent to the corresponding first-stage D flip-flop, and each of the first-stage selectors is used for selecting one bit from binary data output by the corresponding first-stage D flip-flop and binary data output by the adjacent first-stage D flip-flop according to the first selection control signal.

6. The parallel-to-serial conversion circuit of claim 5, wherein, The shift unit comprises a plurality of second-stage D flip-flops and a plurality of second-stage selectors, each of the second-stage D flip-flops corresponds to each of the second-stage selectors and each of the first-stage selectors, and each of the second-stage selectors is connected between the corresponding first-stage selector and the second-stage D flip-flop.

7. The parallel-to-serial conversion circuit of claim 6, wherein, A low-level selection end of at least part of the second-stage selectors corresponding to odd bits in the to-be-converted parallel data is connected to a data output end of a second-stage D flip-flop corresponding to a next odd bit in the to-be-converted parallel data, a second high-level selection end of at least part of the second-stage selectors corresponding to the odd bits in the to-be-converted parallel data is connected to a data output end of the first-stage selector corresponding to the second-stage selector, and a selection control signal of the second-stage selector corresponding to the odd bits in the to-be-converted parallel data is the second selection control signal. A low-level selection end of at least part of the second-stage selectors corresponding to even bits in the to-be-converted parallel data is connected to a data output end of a second-stage D flip-flop corresponding to a next even bit in the to-be-converted parallel data, a second high-level selection end of at least part of the second-stage selectors corresponding to the even bits in the to-be-converted parallel data is connected to a data output end of the first-stage selector corresponding to the second-stage selector, and a selection control signal of the second-stage selector corresponding to the even bits in the to-be-converted parallel data is the third selection control signal.

8. The parallel-to-serial conversion circuit of claim 7, wherein, The circuit further comprises an inverter, an input end of the inverter is connected to the serial clock signal end; A data input end of the second-stage D flip-flop corresponding to the odd bits in the to-be-converted parallel data is connected to a data output end of the second-stage selector corresponding to the odd bits in the to-be-converted parallel data, and a clock end of the second-stage D flip-flop corresponding to the odd bits in the to-be-converted parallel data is connected to an output end of the inverter; A data input end of the second-stage D flip-flop corresponding to the even bits in the to-be-converted parallel data is connected to a data output end of the second-stage selector corresponding to the even bits in the to-be-converted parallel data, and a clock end of the second-stage D flip-flop corresponding to the even bits in the to-be-converted parallel data is connected to the serial clock signal end.

9. The parallel-to-serial conversion circuit of claim 6, wherein, The selection output unit comprises a third selector, a high level selection end of the third selector is connected to a data output end of the second stage D flip-flop corresponding to a first odd bit in the parallel data to be converted, a low level selection end of the third selector is connected to a data output end of the second stage D flip-flop corresponding to a first even bit in the parallel data to be converted, and a selection control signal of the third selector is the serial clock signal.

10. The parallel-to-serial conversion circuit of claim 1, wherein, A configuration interface is also included for configuring state jumps and state outputs of the configurable state machine.

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