Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and is used for reducing the voltage drop of common voltage in the transmission process and improving the brightness uniformity of the display panel. The display panel comprises a display area and a non-display area; the display area comprises a plurality of sub-pixels, and each sub-pixel comprises a pixel driving circuit and a light-emitting element which are electrically connected; a common branch line electrically connected to the plurality of sub-pixels; the common branch lines and the pixel driving circuits are staggered in the thickness direction of the display panel.

Description

[0001] The present application is a divisional application of parent application CN116312255A, the original parent application date is April 13, 2023, the application number is: 202310399448.4, and the invention name is: display panel and display device. TECHNICAL FIELD The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the continuous development of display technology, consumers' requirements for display screens are constantly improving. At present, various types of displays including liquid crystal display screens and organic light-emitting display screens are emerging in an endless stream and developing rapidly. On this basis, 3D display, touch display technology, curved display, ultra-high resolution display, and anti-peep display technologies are constantly emerging.

[0003] However, the current display panel has the problem of poor brightness uniformity. SUMMARY

[0004] Therefore, the display panel and the display device provided by the embodiments of the present application can reduce the voltage drop of the common voltage in the transmission process, improve the brightness uniformity of the display panel.

[0005] In one aspect, the present application provides a display panel, comprising: a display area and a non-display area; The display area comprises: a plurality of sub-pixels, each sub-pixel comprising a pixel driving circuit and a light-emitting element electrically connected; a common branch line electrically connected to the plurality of sub-pixels; In the thickness direction of the display panel, the common branch line and the pixel driving circuit are staggered with each other.

[0006] In another aspect, the present application provides a display device comprising the above-mentioned display panel.

[0007] The display panel and the display device provided by the embodiments of the present application can reduce the voltage drop of the common voltage in the transmission process by arranging the common branch line in the display area of the display panel, and the common branch line is electrically connected to the plurality of sub-pixels, which can improve the brightness consistency of the plurality of sub-pixels located at different positions in the display area, thereby improving the display uniformity of the display panel.

[0008] Furthermore, in the thickness direction of the display panel, the common branch line and the pixel driving circuit are staggered with each other, which can avoid the mutual interference between the common voltage transmitted by the common branch line and the signals transmitted by other structures in the pixel driving circuit for transmitting different signals, can reduce the coupling capacitance between the common branch line and the pixel driving circuit, and improve the accuracy of the signals. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A top view schematic diagram of a display panel provided in an embodiment of the present invention; Figure 2 An equivalent circuit diagram of a sub-pixel is provided for an embodiment of the present invention; Figure 3 for Figure 2 A wiring diagram of a pixel driving circuit is shown. Figure 4 A cross-sectional schematic diagram of a display panel provided in an embodiment of the present invention; Figure 5 A top view schematic diagram of another display panel provided in an embodiment of the present invention; Figure 6 This is a partially enlarged schematic diagram of the display area of ​​a display panel provided in an embodiment of the present invention; Figure 7 for Figure 6 A top view of a semiconductor layer in a semiconductor structure; Figure 8 for Figure 6 A top view of the first metal layer in the process; Figure 9 for Figure 6 A top view of the second metal layer in the process; Figure 10 for Figure 6 A top view of the third metal layer in the process; Figure 11 for Figure 6 A top view of the fourth metal layer in the process; Figure 12 for Figure 6 A top view of the fifth metal layer in the process; Figure 13 for Figure 6 A schematic diagram of a cross-section along BB'; Figure 14 A partially enlarged schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention; Figure 15 for Figure 14 A top view of the fourth metal layer in the process; Figure 16 forFigure 14 A top view of the fifth metal layer; Figure 17 for Figure 14 A schematic diagram of a cross section along CC'; Figure 18 A top view schematic diagram of another display panel provided in an embodiment of the present invention; Figure 19 A partially enlarged schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention; Figure 20 for Figure 19 A top view of a semiconductor layer in a semiconductor structure; Figure 21 for Figure 19 A top view of the second metal layer in the process; Figure 22 for Figure 19 A top view of the fourth metal layer in the middle; Figure 23 for Figure 19 A top view of the third metal layer in the process; Figure 24 for Figure 19 A schematic diagram of a cross-section along DD'; Figure 25 A partially enlarged schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention; Figure 26 for Figure 25 A schematic diagram of a cross-section along EE'; Figure 27 A partially enlarged schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention; Figure 28 for Figure 27 A top view of a semiconductor layer in a semiconductor structure; Figure 29 for Figure 27 A top view of the fourth metal layer in the process; Figure 30 A partially enlarged schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention; Figure 31 for Figure 30 A top view of the fourth metal layer in the process; Figure 32 A schematic diagram of yet another display panel provided in an embodiment of the present invention; Figure 33 A top view schematic diagram of another display panel provided in an embodiment of the present invention; Figure 34 A top view schematic diagram of another display panel provided in an embodiment of the present invention; Figure 35 A top view of a display panel according to another embodiment of the present application is provided. Figure 36 A top view of a display panel according to another embodiment of the present application is provided. Figure 35 An enlarged view of the middle region R is provided. Figure 37 A cross-sectional view of a display panel according to another embodiment of the present application is provided. Figure 38 A top view of a display panel according to another embodiment of the present application is provided. Figure 39 A top view of a display panel according to another embodiment of the present application is provided. Figure 40 A top view of a display panel according to another embodiment of the present application is provided. Figure 38 An enlarged view of the middle region Q is provided. Figure 41 A top view of a display device according to an embodiment of the present application is provided. DETAILED DESCRIPTION

[0011] In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0012] It should be clear that the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0013] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0014] It should be understood that the term "and / or" used herein only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " herein generally represents an "or" relationship between the front and rear associated objects.

[0015] The embodiments of the present application provide a display panel, as shown in Figure 1 The display panel 100 according to an embodiment of the present application is provided, as shown in Figure 1 A top view of a display panel according to another embodiment of the present application is provided. Figure 1As shown, the display area AA includes a sub-pixel 1 and a common branch 2 for transmitting a common voltage. The common branch 2 is electrically connected to a plurality of sub-pixels 1 located at different positions within the display area AA to provide the common voltage to the plurality of sub-pixels 1 at different positions. In an embodiment of the present application, the common voltage required by the plurality of sub-pixels 1 at different positions within the display area AA is the same. The sub-pixel 1 needs to receive a plurality of voltages when working. Among them, part of the voltages can be common voltages shared by the plurality of sub-pixels 1.

[0016] The following describes the common voltage required by the sub-pixel 1 in combination with Figure 2 The circuit diagram of the sub-pixel 1 shown above illustrates the common voltage required by the sub-pixel 1, Figure 2 An equivalent circuit diagram of a sub-pixel 1 provided by an embodiment of the present application, the sub-pixel 1 includes a pixel driving circuit 10 and a light emitting element 11 electrically connected. The pixel driving circuit 10 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor C. The signals required by the sub-pixel 1 to work include a first scan signal S1, a second scan signal S2, a light emitting control signal E, a data voltage Data, a first power voltage PVEE, a second power voltage PVDD and a reference voltage Vref.

[0017] Specifically, the first transistor T1 is configured to provide the second power voltage PVDD to the second node N2 under the control of the light emitting control signal E; the second transistor T2 is configured to provide the data voltage Data to the second node N2 under the control of the second scan signal S2; the third transistor T3 is configured to electrically connect the second node N2 and the third node N3 under the control of the first node N1; the fourth transistor T4 is configured to electrically connect the third node N3 and the first node N1 under the control of the second scan signal S2; the fifth transistor T5 is configured to provide the reference voltage Vref to the first node N1 under the control of the first scan signal S1; the sixth transistor T6 is configured to electrically connect the third node N3 and the fourth node N4 under the control of the light emitting control signal E; the seventh transistor T7 is configured to provide the reference voltage Vref to the fourth node N4 under the control of the second scan signal S2. The first electrode of the light emitting element 11 is configured to receive the first power voltage PVEE, and the second electrode is electrically connected to the fourth node N4. The first plate of the storage capacitor C is configured to receive the second power voltage PVDD, and the second plate is electrically connected to the first node N1.

[0018] The pixel driving circuit 10 operates in three phases: a reset phase, a charging phase, and a light-emitting phase. During the reset phase, the fifth transistor T5 is turned on in response to the first scan signal S1, and the reference voltage Vref resets the first node N1 through the fifth transistor T5. During the charging phase, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on in response to the second scan signal S2, and the data voltage Data is written to the second node N2 through the second transistor T2. In this phase, the third transistor T3 is turned on. The potential of the first node N1 continuously changes until the potential Vref of the first node N1 reaches a certain value. N1 Change to V N1 =Data-|Vth|, where Vth is the threshold voltage of the third transistor T3. The reference voltage Vref resets the fourth node N4 through the seventh transistor T7. During the light-emitting phase, the first transistor T1, the sixth transistor T6, and the third transistor T3 are turned on, and the current path between the second power supply voltage PVDD and the first power supply voltage PVEE is opened, thus lighting up the light-emitting element 11.

[0019] based on Figure 2 The circuit configuration of the sub-pixel 1 shown in this embodiment of the invention allows the first power supply voltage PVEE required for the operation of multiple sub-pixels 1 located at different positions in the display area AA to be the same, and / or the reference voltage Vref required for the operation of multiple sub-pixels 1 located at different positions in the display area AA to be the same. That is, in this embodiment of the invention, the common voltage includes the aforementioned first power supply voltage PVEE and / or reference voltage Vref. The data voltage Data, the first scan signal S1, the second scan signal S2, and the light emission control signal E are non-common voltages. For example, this embodiment of the invention allows the first power supply voltage PVEE required for the operation of all sub-pixels 1 within the display area AA to be the same, and / or the reference voltage Vref required for the operation of all sub-pixels 1 within the display area AA to be the same.

[0020] Optional, combined Figure 2 and Figure 3 As shown, Figure 3 for Figure 2 The diagram shows a wiring schematic of a pixel driving circuit. The display area also includes a first scan line 31 for transmitting the first scan signal S1, a second scan line 32 for transmitting the second scan signal S2, a light emission control signal line 33 for transmitting the light emission control signal E, a data line 34 for transmitting the data voltage Data, and a second power supply line 35 for transmitting the second power supply voltage PVDD.

[0021] For example, in combination Figure 3 and Figure 4 As shown, Figure 4This is a cross-sectional schematic diagram of a display panel provided in an embodiment of the present invention. The display panel includes a substrate 41 and an array film layer 42 and a display film layer 43 formed on the same side of the substrate 41. The display film layer 43 is located on the side of the array film layer 42 away from the substrate 41. The pixel driving circuit 10, the first scan line, the second scan line, the light emission control signal line, the data line, and the second power supply line are all located in the array film layer 42. For example, as shown... Figure 4 As shown, common branch 2 is also located in array film layer 42.

[0022] Optional, such as Figure 4 As shown, the array film layer 42 includes a first insulating layer IS1, a semiconductor layer S, a second insulating layer IS2, a first metal layer M1, a third insulating layer IS3, a second metal layer M2, a fourth insulating layer IS4, a third metal layer M3, a fifth insulating layer IS5, a fourth metal layer M4, a sixth insulating layer IS6, a fifth metal layer M5, and a passivation layer PV, which are sequentially formed on one side of the substrate 41. The pixel driving circuit 10, the first scan line, the second scan line, the light emission control signal line, the data line, the second power line, and the common branch line 2 can be respectively set in the corresponding conductive layers in the array film layer 42 according to different design requirements. The specific wiring in the array film layer 42 will be introduced later, and will not be repeated here.

[0023] like Figure 4 As shown, the display film layer 43 includes a pixel definition layer 431 and a light-emitting element 11. The light-emitting element 11 includes a first electrode 111, a light-emitting layer 110, and a second electrode 112. The second electrode 112 is electrically connected to the pixel driving circuit 10. Optionally, as... Figure 4 As shown, the pixel driving circuit 10 is electrically connected to the second electrode 112 via a connection electrode 12. The connection electrode 12 includes a first sub-connection electrode 121, a second sub-connection electrode 122, and a third sub-connection electrode 123 stacked together. The pixel defining layer 431 includes an opening 4310 that exposes at least a portion of the second electrode 112. At least a portion of the light-emitting layer 110 is located within the opening 4310. Figure 4 As shown, a planarization layer PLN is also included between the second electrode 112 and the passivation layer PV. It should be noted that, for the sake of simplicity in the illustration, [the following text is incomplete and requires further context]. Figure 4 Only the sixth transistor T6, which is electrically connected to the light-emitting element 11, is shown in the pixel driving circuit 10. The other thin-film transistors in the pixel driving circuit 10 are shown in... Figure 3 Not shown in the image.

[0024] In this embodiment of the invention, along the thickness direction h3 of the display panel, the common branch 2 is offset from the pixel driving circuit 10. It should be noted that, in this embodiment of the invention, the region where the pixel driving circuit 10 is located is the region where each thin-film transistor and storage capacitor C is located within the pixel driving circuit 10.Figure 2 Taking the pixel driving circuit 10 with a 7T1C structure having seven thin-film transistors and one storage capacitor as an example, combined with... Figure 3 As shown, the region PA where the pixel driving circuit 10 is located is Figure 3 The area enclosed by the dashed box. The common branch 2 is offset from the pixel driving circuit 10, that is, the common branch 2 is offset from each thin-film transistor in the pixel driving circuit 10, and also offset from the storage capacitor C in the pixel driving circuit 10.

[0025] In this embodiment of the invention, by setting a common branch line 2 in the display area AA of the display panel, and electrically connecting the common branch line 2 to multiple sub-pixels 1, the voltage drop of the common voltage during transmission can be reduced, the brightness consistency of multiple sub-pixels 1 located at different positions in the display area AA can be improved, thereby enhancing the display uniformity of the display panel.

[0026] Furthermore, along the thickness direction h3 of the display panel, by staggering the common branch 2 and the pixel driving circuit 10, the common voltage transmitted by the common branch 2 can avoid mutual interference between the common voltage transmitted by the common branch 2 and other structures in the pixel driving circuit 10 that transmit different signals, thereby reducing the coupling capacitance between the common branch 2 and the pixel driving circuit 10 and improving the accuracy of the signal.

[0027] It should be understood that Figure 2 The equivalent circuit diagram of sub-pixel 1 shown, and Figure 3 The wiring diagrams of the pixel driving circuit 10 shown are all schematic diagrams. In this embodiment of the invention, the equivalent circuit diagram of the sub-pixel 1 and the wiring of the pixel driving circuit 10 can be designed in other ways according to different needs. This embodiment of the invention does not limit this.

[0028] For example, in an embodiment of the invention, the common branch 2 includes a first power line and / or a reference voltage line. Optionally, as... Figure 5 As shown, Figure 5 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention. The display area AA includes a first electrode 111 and a common branch line 2. The first electrode 111 is used to transmit the aforementioned first power supply voltage PVEE. For example, as shown... Figure 5 As shown, in this embodiment of the invention, the first electrode 111 can be configured as a planar structure covering the display area AA, with different light-emitting elements ( Figure 5 The first electrodes 111 (not shown) can be electrically connected to each other.

[0029] like Figure 5 As shown, the common branch 2 includes a first power line 21. The first power line 21 is electrically connected to the light-emitting element in the sub-pixel to provide the light-emitting element with the aforementioned first power supply voltage PVEE. Figure 5As shown, the non-display area NA includes a first power bus 51. Exemplarily, the first power line 21 and the first electrode 111 can be electrically connected to the first power bus 51 in the non-display area NA.

[0030] If the load of the first power bus 51 is large, the first power bus 51 will generate obvious heat during the operation of the display panel, especially in the narrow area of the first power bus 51, which will cause the first power bus 51 to be overheated and have a high risk of burning. By arranging the first power line 21 in the display area AA in the array film layer 42, the embodiments of the present application can reduce the voltage drop of the first power voltage PVEE during transmission, and further compress the width of the first power bus 51 without increasing the load of the first power bus 51, so as to reduce the burning risk of the first power bus 51 and improve the reliability of the display panel while realizing the narrow frame design of the display panel. Moreover, by arranging the first power line 21 in the array film layer 42, the embodiments of the present application can integrate the first power line 21 into the process of other structures in the array film layer 42, so as to avoid increasing the process complexity of the display panel.

[0031] Optionally, as shown in Figure 5 The first power line 21 includes a first sub-power line 2101 and / or a second sub-power line 2102, the first sub-power line 2101 extends along a first direction h1, and the second sub-power line 2102 extends along a second direction h2. Figure 5 and Figure 6 As shown, Figure 6 is a partial enlarged view of the display area of the display panel provided by the embodiments of the present application, in which two pixel drive circuit rows arranged along the second direction h2 are taken as an example, each pixel drive circuit row includes seven pixel drive circuits arranged along the first direction h1, and each pixel drive circuit can be arranged in the manner shown in Figure 3 In the Figure 6 , the first power line 21 includes the first sub-power line 2101 and the second sub-power line 2102 electrically connected to each other, so as to further increase the conduction path of the first power voltage PVEE in the array film layer, reduce the voltage drop of the first power voltage PVEE during transmission, and avoid the case that the load of the first power bus 51 is too large, which is conducive to further reducing the width of the first power bus 51 and realizing the narrow frame design of the display panel.

[0032] Exemplarily, as shown in Figure 6As shown, a portion of the first sub power line 2101 is located between two pixel drive circuits 10 adjacent in the second direction h2, and a portion of the second sub power line 2102 is located between two pixel drive circuits 10 adjacent in the first direction h1. The first sub power line 2101 and the second sub power line 2102 are staggered with respect to each other.

[0033] Optionally, as shown in Figure 5 and Figure 6 , the embodiment of the present application can make one second sub power line 2102 electrically connected with at least two first sub power lines 2101, and / or make one first sub power line 2101 electrically connected with at least two second sub power lines 2102, i.e. in the display area AA, the first power line 21 is arranged in a grid shape in the array film layer, so as to further increase the conduction path of the first power voltage PVEE and reduce the voltage drop of the first power voltage PVEE in the propagation process.

[0034] As shown in Figure 4 , Figure 6 and Figure 7 , Figure 7 is a top view schematic diagram of a semiconductor layer in Figure 6 , the semiconductor layer S includes an active layer of a thin film transistor. The active layer includes a channel region, a source region and a drain region of each thin film transistor. Optionally, as shown in Figure 7 , the semiconductor layer S includes a first channel region S10, a first doped region S11 and a second doped region S12 located on both sides of the first channel region S10, a second channel region S20, a third doped region S21 and a fourth doped region S22 located on both sides of the second channel region S20, a third channel region S30, a fifth doped region S31 and a sixth doped region S32 located on both sides of the third channel region S30, a fourth channel region S40, a seventh doped region S41 and an eighth doped region S42 located on both sides of the fourth channel region S40, a fifth channel region S50, a ninth doped region S51 and a tenth doped region S52 located on both sides of the fifth channel region S50, a sixth channel region S60, an eleventh doped region S61 and a twelfth doped region S62 located on both sides of the sixth channel region S60, a seventh channel region S70, a thirteenth doped region S71 and a fourteenth doped region S72 located on both sides of the seventh channel region S70. One of the two doped regions located on both sides of each channel region is a source region, and the other is a drain region. The source region and the drain region are doped with impurities. The impurities include P-type impurities or N-type impurities. Exemplarily, the semiconductor layer S includes any one or more of low-temperature polycrystalline silicon, amorphous silicon, and oxide semiconductor layers.

[0035] As shown in Figure 6 and Figure 8 , Figure 8 is a top view schematic diagram of a semiconductor layer in Figure 6Fig. 6 is a top view of a first metal layer in the pixel driving circuit of Fig. 1. The first metal layer Ml includes the light emitting control signal line 33, the first plate C1 of the storage capacitor C, the gate G2 of the second transistor T2, the gate G4 of the fourth transistor T4, the gate G5 of the fifth transistor T5, and the gate G7 of the seventh transistor T7. The gate G2 of the second transistor T2 and the gate G4 of the fourth transistor T4 are connected.

[0036] Fig. 7 is a top view of a second metal layer in the pixel driving circuit of Fig. 1. The second metal layer M2 includes the reference voltage line 22 and the second plate C2 of the storage capacitor C. Exemplarily, the second plates C2 of the storage capacitors C of different pixel driving circuits are electrically connected. Figure 6 、 Figure 7 and Figure 8 Fig. 8 is a top view of a third metal layer in the pixel driving circuit of Fig. 1. The third metal layer M3 includes the first scan line 31, the second scan line 32, and the second power line 35 extending along the first direction h1. The second power line 35 is used to transmit the second power voltage PVDD.

[0037] Fig. 9 is a top view of a fourth metal layer in the pixel driving circuit of Fig. 1. The fourth metal layer M4 includes the data line 34 and the second power line 35 extending along the second direction h2. The second power line 35 is used to transmit the second power voltage PVDD. The second power line 35 extending along the second direction h2 is electrically connected with the second power line 35 extending along the first direction h1 in the third metal layer M3. Figure 6 Figure 9 Fig. 10 is a top view of a fifth metal layer in the pixel driving circuit of Fig. 1. The fifth metal layer M5 includes the first power line 33 and the second power line 35 extending along the second direction h2. The second power line 35 is used to transmit the second power voltage PVDD. The second power line 35 extending along the second direction h2 is electrically connected with the second power line 35 extending along the first direction h1 in the third metal layer M3. Figure 9 Figure 6 Fig. 11 is a top view of a sixth metal layer in the pixel driving circuit of Fig. 1. The sixth metal layer M6 includes the first power line 33 and the second power line 35 extending along the second direction h2. The second power line 35 is used to transmit the second power voltage PVDD. The second power line 35 extending along the second direction h2 is electrically connected with the second power line 35 extending along the first direction h1 in the third metal layer M3.

[0038] Fig. 12 is a top view of a seventh metal layer in the pixel driving circuit of Fig. 1. The seventh metal layer M7 includes the first power line 33 and the second power line 35 extending along the second direction h2. The second power line 35 is used to transmit the second power voltage PVDD. The second power line 35 extending along the second direction h2 is electrically connected with the second power line 35 extending along the first direction h1 in the third metal layer M3. Figure 10 Figure 10 Fig. 13 is a top view of an eighth metal layer in the pixel driving circuit of Fig. 1. The eighth metal layer M8 includes the first power line 33 and the second power line 35 extending along the second direction h2. The second power line 35 is used to transmit the second power voltage PVDD. The second power line 35 extending along the second direction h2 is electrically connected with the second power line 35 extending along the first direction h1 in the third metal layer M3. Figure 6 Fig. 14 is a top view of a ninth metal layer in the pixel driving circuit of Fig. 1. The ninth metal layer M9 includes the first power line 33 and the second power line 35 extending along the second direction h2. The second power line 35 is used to transmit the second power voltage PVDD. The second power line 35 extending along the second direction h2 is electrically connected with the second power line 35 extending along the first direction h1 in the third metal layer M3.

[0039] Figure 6 Fig. 15 is a top view of a tenth metal layer in the pixel driving circuit of Fig. 1. The tenth metal layer M10 includes the first power line 33 and the second power line 35 extending along the second direction h2. The second power line 35 is used to transmit the second power voltage PVDD. The second power line 35 extending along the second direction h2 is electrically connected with the second power line 35 extending along the first direction h1 in the third metal layer M3. Figure 11 Figure 11 Fig. 16 is a top view of an eleventh metal layer in the pixel driving circuit of Fig. 1. The eleventh metal layer M11 includes the first power line 33 and the second power line 35 extending along the second direction h2. The second power line 35 is used to transmit the second power voltage PVDD. The second power line 35 extending along the second direction h2 is electrically connected with the second power line 35 extending along the first direction h1 in the third metal layer M3. Figure 6 Fig. 17 is a top view of a twelfth metal layer in the pixel driving circuit of Fig. 1. The twelfth metal layer M12 includes the first power line 33 and the second power line 35 extending along the second direction h2. The second power line 35 is used to transmit the second power voltage PVDD. The second power line 35 extending along the second direction h2 is electrically connected with the second power line 35 extending along the first direction h1 in the third metal layer M3.

[0040] ​​​​​Exemplarily, the first sub power supply line 2101 and the second sub power supply line 2102 can be arranged in different layers. As shown in Figure 6 , Figure 11 and Figure 12 , Figure 12 is a top view of the fifth metal layer in Figure 6 , the first sub power supply line 2101 can be arranged in the fifth metal layer M5, and the second sub power supply line 2102 can be arranged in the fourth metal layer M4, i.e., the second sub power supply line 2102 is arranged in the same layer as the data line 34 and the second power supply line 35 extending along the second direction h2.

[0041] Exemplarily, as shown in Figure 6 and Figure 13 , Figure 13 is a cross-sectional view along BB' in Figure 6 , the first sub power supply line 2101 and the second sub power supply line 2102 are electrically connected through the connection hole K21 penetrating the sixth insulating layer IS6.

[0042] Optionally, as shown in Figure 3 and Figure 10 , the third metal layer M3 further includes a first connection part X1. The first connection part X1 is electrically connected with the second power supply voltage line 35 extending along the first direction h1, and one end of the first connection part X1 is electrically connected with the second plate C2 of the capacitor C arranged in the second metal layer M2 through the first via hole H11 penetrating the third insulating layer (not shown). The other end of the first connection part X1 is electrically connected with the first doped region S11 of the semiconductor layer S through the second via hole H12, to transmit the second power supply voltage PVDD to the source or the drain of the first transistor T1. The second via hole H12 penetrates the fourth insulating layer (not shown), the third insulating layer (not shown) and the second insulating layer (not shown).

[0043] As shown in Figure 3 and Figure 10 , the third metal layer M3 further includes a second connection part X2, one end of the second connection part X2 is electrically connected with the data line 34 arranged in the fourth metal layer M4 through the third via hole H21 penetrating the fifth insulating layer (not shown). The other end of the second connection part X2 is electrically connected with the third doped region S21 in the semiconductor layer S through the fourth via hole H22 penetrating the fourth insulating layer (not shown), the third insulating layer (not shown) and the second insulating layer (not shown), to transmit the data voltage to the source or the drain of the second transistor T2.

[0044] As shown in Figure 3 and Figure 10As shown, the third metal layer M3 further includes a third connecting portion X3. One end of the third connecting portion X3 is electrically connected to the seventh doped region S41 and the tenth doped region S52 of the semiconductor layer S through a fifth via hole H31 penetrating through a fourth insulating layer (not shown), a third insulating layer (not shown) and a second insulating layer (not shown). The other end of the third connecting portion X3 is electrically connected to the first plate C1 of the capacitor C located in the first metal layer M1 through a sixth via hole H32 penetrating through the fourth insulating layer, the second metal layer and the third insulating layer, wherein the part of the first plate C1 overlapping with the third channel region S30 is reused as the gate G3 of the third transistor T3.

[0045] In combination Figure 9 As shown, the second plate C2 of the capacitor C located in the second metal layer M2 includes an opening O, and the sixth via hole H32 and the opening O overlap along the thickness direction h3 of the display panel.

[0046] For example, the area of the opening O is greater than or equal to the area of the sixth via hole H32, Figure 9 For example, the area of the opening O is greater than the area of the sixth via hole H32. The normal projection of the sixth via hole H32 on the plane where the substrate is located is located in the opening O.

[0047] As shown in Figure 3 As shown, the second power voltage line 35 located in the third metal layer M3 extending along the first direction h1 is electrically connected to the second power voltage line 35 located in the fourth metal layer M4 extending along the second direction h2 through a seventh via hole H4. The seventh via hole H4 penetrates through a fifth insulating layer (not shown).

[0048] Alternatively, the first sub power line 2101 and the second sub power line 2102 can be arranged in the same layer in the embodiment of the present application. For example, as shown in Figure 14 、 Figure 15 、 Figure 16 and Figure 17 As shown, Figure 14 is another partial enlarged schematic view of the display area of the display panel provided by the embodiment of the present application, Figure 15 is a top view schematic view of the fourth metal layer in Figure 14 , Figure 16 is a top view schematic view of the fifth metal layer in Figure 14 , Figure 17 is a sectional view along CC' in Figure 14 The embodiment of the present application can arrange the first sub power line 2101 and the second sub power line 2102 in the fifth metal layer M5. In this way, when manufacturing the display panel, the same material can be used to simultaneously manufacture the first sub power line 2101 and the second sub power line 2102 in the same process flow, so as to improve the process efficiency.

[0049] For example,Figure 14 The semiconductor layer, the first metal layer, the second metal layer and the third metal layer in the display panel can be arranged as described in the embodiments of the display panel, which will not be repeated here. Figure 7 , Figure 8 , Figure 9 and Figure 10 .

[0050] It should be noted that the arrangement of the first scan line 31, the second scan line 32 and the light-emitting control signal line 33 shown in Figure 3 , Figure 6 and Figure 14 is only an example, and the film layer position or structure of the first scan line 31, the second scan line 32 and the light-emitting control signal line 33 can be adjusted according to different design requirements, which is not limited in the embodiments of the present application. For example, in addition to the single-layer structure of the first scan line 31, the second scan line 32 and the light-emitting control signal line 33 shown in Figure 3 , Figure 6 and Figure 14 , at least one of the first scan line 31, the second scan line 32 and the light-emitting control signal line 33 can be arranged as a double-layer or multi-layer structure including at least two metal layers to reduce the resistance of the corresponding signal line.

[0051] For example, as shown in Figure 18 , Figure 18 is another top view of a display panel provided by the embodiments of the present application, the display area AA includes a common branch line 2, the common branch line 2 includes a reference voltage line 22, and the reference voltage line 22 provides the above-mentioned reference voltage Vref to a pixel driving circuit (not shown). Taking the pixel driving circuit 10 shown in Figure 18 as an example, the reference voltage line 22 is electrically connected to the fifth transistor T5 and / or the seventh transistor T7 in the pixel driving circuit 10. Figure 2

[0052] Optionally, as shown in Figure 18 , the reference voltage line 22 includes a first sub-reference voltage line 2201 and / or a second sub-reference voltage line 2202, the first sub-reference voltage line 2201 extends along a first direction h1, the second sub-reference voltage line 2202 extends along a second direction h2, and the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 are electrically connected. For example, as shown in Figure 18 ​As shown, a second sub-reference voltage signal line 2202 can be electrically connected to at least two first sub-reference voltage signal lines 2201, and a first sub-reference voltage signal line 2201 can be electrically connected to at least two second sub-reference voltage signal lines 2202, so that the reference voltage line 22 has a grid-like shape, which is beneficial to further increase the conduction path of the reference voltage Vref, reduce the voltage drop of the reference voltage Vref during transmission, and improve the brightness consistency of sub-pixels located at different positions in the display area AA.

[0053] For example, such as Figure 18 As shown, the non-display area NA also includes a reference voltage bus 52, and the reference voltage line 22 is electrically connected to the reference voltage bus 52 and the pixel driving circuit.

[0054] like Figure 18 As shown, the non-display area NA includes a first sub-non-display area NA1, and the first sub-non-display area NA1 includes a scan driving circuit 6. The scan driving circuit 6 is connected to the scan lines in the display area AA. Figure 18 Electrical connections (not shown). For example, the scan lines include the first scan signal line and / or the second scan signal line described above.

[0055] In related technologies, the reference voltage bus 52 is usually integrated into the scan driving circuit 6, resulting in a larger width of the first sub-non-display area NA1, which is not conducive to the narrow bezel design of the display panel. This embodiment of the invention reduces the voltage drop of the reference voltage Vref during transmission by setting a grid-like reference voltage line 22 in the display area AA. Based on this, this embodiment of the invention can reduce the width of the reference voltage bus 52 integrated in the scan driving circuit 6, or, as... Figure 18 As shown, in this embodiment of the invention, a reference voltage bus may not be required in the scan drive circuit 6. Figure 18 As shown, the non-display area NA also includes a second sub-non-display area NA2. The second sub-non-display area NA2 does not include the aforementioned scan drive circuit 6, and the reference voltage bus 52 is located in the second sub-non-display area NA2. This configuration helps to reduce the width of the first sub-non-display area NA1 occupied by the scan drive circuit 6, which is beneficial to increasing the area ratio of the display area AA in the display panel, that is, increasing the screen ratio of the display panel.

[0056] For example, Figure 19 As shown, Figure 19 This is a partially enlarged schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention, wherein two rows of pixel driving circuits are arranged along the second direction h2, and each row of pixel driving circuits includes seven pixel driving circuits arranged along the first direction h1, as illustrated. Each pixel driving circuit can be arranged according to... Figure 3 Configure it as shown in the diagram. Figure 19In some embodiments, the reference voltage line 22 includes a first sub-reference voltage line 2201 and a second sub-reference voltage line 2202. The first sub-reference voltage line 2201 is arranged between two adjacent pixel driving circuits 10 in the second direction h2. The second sub-reference voltage line 2202 is arranged between two adjacent pixel driving circuits 10 in the first direction h1. The first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 are staggered with the pixel driving circuits 10 in the thickness direction h3 of the display panel.

[0057] As shown in FIG. 2B, the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 are arranged in different film layers and are electrically connected through a connection portion K22. Figure 18 Figure 19 As shown in FIG. 2B, the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 are arranged in different film layers and are electrically connected through a connection portion K22.

[0058] As shown in FIG. 2B, the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 are arranged in different film layers and are electrically connected through a connection portion K22. Figure 19 Figure 20 As shown in FIG. 2B, the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 are arranged in different film layers and are electrically connected through a connection portion K22. Figure 20 Figure 19 As shown in FIG. 2B, the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 are arranged in different film layers and are electrically connected through a connection portion K22.

[0059] As shown in FIG. 2B, the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 are arranged in different film layers and are electrically connected through a connection portion K22. Figure 20 As shown in FIG. 2B, the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 are arranged in different film layers and are electrically connected through a connection portion K22. Figure 9 Figure 21 As shown in FIG. 2B, the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 are arranged in different film layers and are electrically connected through a connection portion K22. Figure 21 Figure 21 As shown in FIG. 2B, the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 are arranged in different film layers and are electrically connected through a connection portion K22. Figure 19 ​​​​​A top view of the second metal layer in the diagram shows that when the reference voltage line 22 is disposed in the second metal layer M2, the distance between the storage capacitors C of two adjacent pixel driving circuits 10 on the second direction h2 is d1. When the reference voltage line is disposed in the semiconductor layer S, that is, after removing the reference voltage line in the second metal layer M2, the distance between the storage capacitors C of two adjacent pixel driving circuits 10 on the second direction h2 is d2, where d2 < d1. This allows the pixel driving circuits 10 in the display area AA to be disposed more compactly on the second direction h2, which is beneficial for increasing the number of pixels per inch (PPI) of the display panel. For example, the portion of the semiconductor layer S used to form the first sub-reference voltage line 2201 can be produced using a heavily doped process.

[0060] When the first sub-reference voltage line 2201 is disposed on the same layer as the active layer of the thin-film transistor, embodiments of the present invention can make the first sub-reference voltage line 2201 electrically connected to the active layers of the thin-film transistors of two adjacent pixel driving circuits. The two adjacent pixel driving circuits are arranged along the extending direction of the first sub-reference voltage line 2201. For example, as shown... Figure 19 and Figure 20 As shown, the first sub-reference voltage line 2201 extends along the first direction h1. The ninth doped region S51 in the active layer of the pixel driving circuit adjacent to it on the first direction h1 is electrically connected through the first sub-reference voltage line 2201. The ninth doped region S51 is used to form the fifth transistor T5 in the pixel driving circuit. Optionally, as... Figure 19 and Figure 20 As shown, in this embodiment of the invention, multiple active layers arranged along the first direction h1 can be electrically connected to the same first sub-reference voltage line 2201.

[0061] Optional, such as Figure 22 As shown, Figure 22 for Figure 19 A top view of the fourth metal layer. In this embodiment of the invention, the second sub-reference voltage line 2202, the data line 34, and the second power line 35 extending along the second direction h2 can be disposed in the same layer of the fourth metal layer M4, so as to avoid the need to set an additional film layer in the display panel. On the one hand, the second sub-reference voltage line 2202, the data line 34, and the second power line 35 can be formed in the same process using the same material. On the other hand, it is also beneficial to reduce the thickness of the display panel.

[0062] For example, Figure 19 The first scan line 31, the second scan line 32, and the light emission control signal line 33 can be referenced. Figure 6 and Figure 14 The settings are as shown, and will not be repeated here.

[0063] Optional, such asFigure 23 and Figure 24 as shown, Figure 23 is Figure 19 a top view schematic diagram of the third metal layer in the Figure 24 is Figure 19 a cross-sectional schematic diagram along DD', the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 are electrically connected through the connection part K22. Exemplarily, as shown in Figure 24 , the connection part K22 includes the electrically connected first sub-connection hole K221, the connection line 220 and the second sub-connection hole K222. The first sub-connection hole K221 penetrates the second insulating layer IS2, the third insulating layer IS3 and the fourth insulating layer IS4, and the second sub-connection hole K222 penetrates the fifth insulating layer IS5. As shown in Figure 23 and Figure 24 , the connection line 220 is located in the third metal layer M3.

[0064] Exemplarily, as shown in Figure 25 and Figure 26 as shown, Figure 25 is a partial enlarged schematic diagram of a display area of yet another display panel provided by the embodiment of the present application, wherein two pixel driving circuit rows arranged along a second direction h2 are taken as an example, and each pixel driving circuit row includes seven pixel driving circuits arranged along a first direction h1 as an example, wherein each pixel driving circuit can be arranged in the manner shown in Figure 3 as shown, Figure 26 is Figure 25 a cross-sectional schematic diagram along EE', in Figure 25 , the common branch line 2 includes the first power line 21 and the reference voltage line 22, and along the thickness direction h3 of the display panel, the embodiment of the present application can make the first power line 21 and the reference voltage line 22 partially overlap, so as to avoid increasing the planar space occupied by the first power line 21 and the reference voltage line 22, and facilitate increasing the PPI of the display panel.

[0065] Exemplarily, when the first power line 21 includes a first sub-power line 2101 and a second sub-power line 2102, and the reference voltage line 22 includes a first sub-reference voltage line 2201 and a second sub-reference voltage line 2202, as shown in Figure 25 and Figure 26 , along the thickness direction h3 of the display panel, the embodiment of the present application can make the first sub-power line 2101 partially overlap with the first sub-reference voltage line 2201, and make the second sub-power line 2102 partially overlap with the second sub-reference voltage line 2202.

[0066] Exemplarily, in Figure 25 , the embodiment of the present application can make the first sub-reference voltage line 2201 be located in the semiconductor layer S, and make the second sub-reference voltage line 2202 be located in the fourth metal layer M4. Optionally,Figure 25 The arrangement of each structure in the semiconductor layer S in the first metal layer M1 can be performed in the manner shown in FIG. 2A. Figure 20 The arrangement of each structure in the semiconductor layer S in the first metal layer M1 can be performed in the manner shown in FIG. 2A. Figure 25 The arrangement of each structure in the fourth metal layer M4 in the semiconductor layer S can be performed in the manner shown in FIG. 2D. Figure 22 The arrangement of each structure in the fourth metal layer M4 in the semiconductor layer S can be performed in the manner shown in FIG. 2D. Figure 24 As shown in FIG. 2E, the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 are electrically connected through the connection line 220, the first sub-connection hole K221 and the second sub-connection hole K222.

[0067] Optionally, in the semiconductor layer S, the first sub-power supply line 2101 and the second sub-power supply line 2102 can be arranged in the fifth metal layer M5. As an example, Figure 25 The arrangement of each structure in the fifth metal layer M5 in the semiconductor layer S can be performed in the manner shown in FIG. 2F. Figure 25 The arrangement of each structure in the fifth metal layer M5 in the semiconductor layer S can be performed in the manner shown in FIG. 2F. Figure 16 The arrangement of each structure in the fifth metal layer M5 in the semiconductor layer S can be performed in the manner shown in FIG. 2F.

[0068] It should be noted that, Figure 6 , Figure 14 , Figure 19 and Figure 25 are only examples of the present embodiments, in which the reference voltages required for resetting the first node N1 and the fourth node N4 are the same. When the reference voltages required for resetting the first node N1 and the fourth node N4 are different, for example, when the first reference voltage Vref1 required for resetting the first node N1 is different from the second reference voltage Vref2 required for resetting the fourth node N4, in combination with Figure 27 and Figure 28 , Figure 27 is another partial enlarged view of the display area of the display panel provided by the present embodiments, in which two pixel driving circuit rows arranged along the second direction h2 are taken as an example, and each pixel driving circuit row includes seven pixel driving circuits arranged along the first direction h1. Figure 28 is a top view of the semiconductor layer in Figure 27 In the semiconductor layer S, the reference voltage line 22 includes the first reference voltage line 221 and the second reference voltage line 222, the first reference voltage line 221 is used to transmit the first reference voltage Vref1, and the second reference voltage line 222 is used to transmit the second reference voltage Vref2. Figure 27

[0069] ​Optionally, the first reference voltage line 221 comprises a first sub-reference voltage line 2201 extending along the first direction h1 and a second sub-reference voltage line 2202 extending along the second direction h2, both of which are electrically connected and transmit the first reference voltage Vref1. The second reference voltage line 222 comprises a first sub-reference voltage line 2201 extending along the first direction h1 and a second sub-reference voltage line 2202 extending along the second direction h2, both of which are electrically connected and transmit the second reference voltage Vref2.

[0070] As shown in Figure 27 and Figure 28 , the first sub-reference voltage line 2201 of the first reference voltage line 221 and the first sub-reference voltage line 2201 of the second reference voltage line 222 can be arranged simultaneously between two pixel driving circuits arranged adjacently in the second direction h2, wherein the first sub-reference voltage line 2201 of the first reference voltage line 221 is electrically connected with the ninth doped region S51 of the fifth transistor T5 of the pixel driving circuit located below, and the first sub-reference voltage line 2201 of the second reference voltage line 222 is electrically connected with the thirteenth doped region S71 of the seventh transistor T7 of the pixel driving circuit located above.

[0071] Optionally, as shown in Figure 27 and Figure 29 , Figure 29 as Figure 27 a top view schematic diagram of the fourth metal layer in , the second sub-reference voltage line 2202 of the first reference voltage line 221 and the second sub-reference voltage line 2202 of the second reference voltage line 222 can be arranged alternately between different pixel driving circuits arranged adjacently in the first direction h1.

[0072] Optionally, as shown in Figure 27 , the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 comprised by the first reference voltage line 221 are electrically connected through the connection part K31, and the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 comprised by the second reference voltage line 222 are electrically connected through the connection part K32. Wherein the connection part K31 and the connection part K32 can be arranged in the same manner as the connection part K22 shown in Figure 24 .

[0073] Optionally, as shown in Figure 6 , Figure 14 , Figure 19 , Figure 25 and Figure 27 , the plurality of pixel driving circuits 10 comprise a first pixel driving circuit 101, a second pixel driving circuit 102 and a third pixel driving circuit 103; Figure 6 , Figure 14 , Figure 19 ,Figure 25 and Figure 27 The first pixel driving circuit 101, the second pixel driving circuit 102 and the third pixel driving circuit 103 are arranged along the first direction h1 as an example. Along the first direction h1, the distance d12 between the first pixel driving circuit 101 and the second pixel driving circuit 102 is greater than or equal to the distance d23 between the second pixel driving circuit 102 and the third pixel driving circuit 103. In combination with Figure 7 As shown in the figure, in the embodiment of the present application, the distance between the two adjacent pixel driving circuits along the first direction h1 is the distance between the first channel region S10 of one of the pixel driving circuits and the sixth channel region S60 of the other pixel driving circuit in the semiconductor layer S. The distance between the two adjacent pixel driving circuits along the second direction h2 is the distance between the ninth doped region S51 of one of the pixel driving circuits and the thirteenth doped region S71 of the other pixel driving circuit. In the embodiment of the present application, the part of the common branch line 2 is located between the first pixel driving circuit 101 and the second pixel driving circuit 102. That is, the part of the common branch line 2 is located between the two adjacent pixel driving circuits with larger distance. The embodiment of the present application can leave space for the setting of the common branch line 2 by adjusting the distance between the part of the pixel driving circuits, so that the distance d12 between the first pixel driving circuit 101 and the second pixel driving circuit 102 is greater than or equal to the distance d23 between the second pixel driving circuit 102 and the third pixel driving circuit 103, which can reduce the wiring difficulty of the common branch line 2. Moreover, the embodiment of the present application can also be beneficial to weaken the influence of the common branch line 2 on the pixel driving circuit 10 by setting the common branch line 2 between the first pixel driving circuit 101 and the second pixel driving circuit 102.

[0074] For example, the embodiment of the present application can set N as an integer greater than or equal to 2, so as to reduce the pressure drop of the corresponding common voltage in the transmission process by using the common branch line 2, while avoiding adjusting the distance between too many pixel driving circuits 10, so that the distance between the two adjacent pixel driving circuits 10 can be set smaller, so as to improve the PPI of the display panel.

[0075] For example, as Figure 6 , Figure 14 , Figure 19 , Figure 25 and Figure 27As shown, the common branch 2 includes a first sub-common branch 201 and a second sub-common branch 202 electrically connected. The first sub-common branch 201 extends along a first direction h1, and the second sub-common branch 202 extends along a second direction h2. The statement that N pixel driving circuits 10 are included between two adjacent common branches 2 means that N pixel driving circuits 10 are included between two adjacent first sub-common branches 201, or N pixel driving circuits 10 are included between two adjacent second sub-common branches 202. When the common branch 2 includes a first power line 21, as... Figure 6 , Figure 14 and Figure 25 As shown, the first sub-common branch 201 includes the aforementioned first sub-power line 2101, and the second sub-common branch 202 includes the aforementioned second sub-power line 2102. When the common branch 2 includes the reference voltage line 22, as... Figure 6 , Figure 14 , Figure 19 and Figure 25 As shown, the first sub-common branch 201 includes the aforementioned first sub-reference voltage line 2201, and the second sub-common branch 202 includes the aforementioned second sub-reference voltage line 2202. Figure 6 , Figure 14 , Figure 19 and Figure 25 The diagram illustrates a spacing of three pixel driving circuits 10 between two adjacent second sub-common branches 202, i.e., N=3.

[0076] For example, such as Figure 30 As shown, Figure 30 This is a partially enlarged schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention, wherein two rows of pixel driving circuits are arranged along the second direction h2, and each row of pixel driving circuits includes seven pixel driving circuits arranged along the first direction h1, as illustrated. Each pixel driving circuit can be arranged according to... Figure 3 The display panel is configured as shown, including a gap region GA located between two adjacent pixel driving circuits 10; the common branch line 2 includes a first power line 21 and a reference voltage line 22, which are located in different gap regions GA.

[0077] Exemplarily, when the first power supply line 21 comprises the first sub power supply line 2101 and / or the second sub power supply line 2102, and the reference voltage line 22 comprises the first sub reference voltage line 2201 and / or the second sub reference voltage line 2202, the first power supply line 21 and the reference voltage line 22 are located in different gap areas GA, which comprises that the first sub power supply line 2101 and the first sub reference voltage line 2201 are located in different gap areas GA, or the second sub power supply line 2102 and the second sub reference voltage line 2202 are located in different gap areas GA. In this way, the first sub power supply line 2101 and the first sub reference voltage line 2201 can be dispersedly arranged at different positions in the display area AA, or the second sub power supply line 2102 and the second sub reference voltage line 2202 can be dispersedly arranged at different positions in the display area AA, so as to reduce the coupling between the first power supply voltage PVEE and the reference voltage Vref.

[0078] It should be noted that, Figure 30 It should be noted that, Figure 30 It should be noted that,

[0079] Exemplarily, when the first power supply line 21 comprises the first sub power supply line 2101 and / or the second sub power supply line 2102, and the reference voltage line 22 comprises the first sub reference voltage line 2201 and / or the second sub reference voltage line 2202, the first power supply line 21 and the reference voltage line 22 are located in different gap areas GA, which comprises that the first sub power supply line 2101 and the first sub reference voltage line 2201 are located in different gap areas GA, or the second sub power supply line 2102 and the second sub reference voltage line 2202 are located in different gap areas GA. In this way, the first sub power supply line 2101 and the first sub reference voltage line 2201 can be dispersedly arranged at different positions in the display area AA, or the second sub power supply line 2102 and the second sub reference voltage line 2202 can be dispersedly arranged at different positions in the display area AA, so as to reduce the coupling between the first power supply voltage PVEE and the reference voltage Vref. Figure 30

[0080] Exemplarily, when the first power supply line 21 comprises the first sub power supply line 2101 and / or the second sub power supply line 2102, and the reference voltage line 22 comprises the first sub reference voltage line 2201 and / or the second sub reference voltage line 2202, the first power supply line 21 and the reference voltage line 22 are located in different gap areas GA, which comprises that the first sub power supply line 2101 and the first sub reference voltage line 2201 are located in different gap areas GA, or the second sub power supply line 2102 and the second sub reference voltage line 2202 are located in different gap areas GA. In this way, the first sub power supply line 2101 and the first sub reference voltage line 2201 can be dispersedly arranged at different positions in the display area AA, or the second sub power supply line 2102 and the second sub reference voltage line 2202 can be dispersedly arranged at different positions in the display area AA, so as to reduce the coupling between the first power supply voltage PVEE and the reference voltage Vref.

[0081] Exemplarily, the first power line 21 and the reference voltage line 22 located in different gap areas GA can be arranged in the same layer according to the embodiments of the present application. As shown in Figure 30 and Figure 31 , as shown in Figure 31 , as shown in Figure 30 , a top view schematic diagram of the fourth metal layer in the display panel, the second sub-reference voltage line 2202 and the second sub-power line 2102 can be arranged in the same layer in the fourth metal layer M4 according to the embodiments of the present application. In this way, the second sub-reference voltage line 2202 and the second sub-power line 2102 can be formed simultaneously in the same process by using the same material, which is beneficial to simplify the manufacturing process of the display panel and reduce the thickness of the display panel.

[0082] Exemplarily, as shown in Figure 32 , as shown in Figure 32 , a schematic diagram of another display panel provided by the embodiments of the present application, a plurality of data lines 34 described above include at least an inner data line 341 and at least one edge data line 342, the edge data line 342 is located on the side of the inner data line 341 close to the edge E of the display panel; the display area AA further includes a connection line 3 electrically connected to the edge data line 342; as shown in Figure 32 , the end D1 of the connection line 3 close to the non-display area AA is located on the side of the edge data line 342 close to the inner data line 341. The connection line 3 is electrically connected to the pad 53 and the corresponding edge data line 342. The arrangement of the connection line 3 can avoid arranging the fan-out line electrically connected to the edge data line 342 in the non-display area NA, so as to reduce the number of fan-out lines arranged in the non-display area NA, and further reduce the width of the non-display area NA. In particular, when the display panel is arranged to have a shape with a rounded corner as shown in Figure 32 , the arrangement of the connection line 3 can reduce the width of the non-display area NA located at the rounded corner.

[0083] Exemplarily, as shown in Figure 32 , the embodiments of the present application can arrange at least part of the connection line 3 between the adjacent two pixel driving circuits 10.

[0084] Exemplarily, as shown in Figure 32 , the connection line 3 includes a first sub-connection line 301 and a second sub-connection line 302 electrically connected; the first sub-connection line 301 extends along a first direction h1, and the second sub-connection line 302 extends along a second direction h2.

[0085] When arranging the first sub-connection line 301, optionally, the first sub-connection line 301 and the first sub-power line 2101 described above can be arranged in the same layer in different gap areas GA according to the embodiments of the present application, so as to simplify the manufacturing process of the display panel and reduce the thickness of the display panel. Exemplarily, the first sub-connection line 301 and the first sub-power line 2101 can be arranged in the same layer in the fifth metal layer M5 described above.

[0086] In the setting of the second sub-connection line 302, optionally, the embodiment of the present application can make the second sub-connection line 302 and the second sub-common branch line 202 in the same layer, so as to simplify the manufacturing process of the display panel, and reduce the thickness of the display panel. Wherein, the second sub-common branch line 202 includes the second sub-power line 2102 and / or the second sub-reference voltage line 2202. Optionally, as shown in Figure 33 Figure 33 Another top view schematic diagram of the display panel provided by the embodiment of the present application is shown, wherein the second sub-common branch line 202 includes the second sub-power line 2102, the second sub-connection line 302 is arranged in the fourth metal layer M4 with the second sub-power line 2102, and the second sub-connection line 302 and the second sub-power line 2102 are respectively located in different gap areas GA.

[0087] Alternatively, the embodiment of the present application can also make the first sub-connection line 301 and the first sub-common branch line 201 in different layers, and at least partially overlap along the thickness direction h3 of the display panel; and / or make the second sub-connection line 302 and the second sub-common branch line 202 in different layers, and at least partially overlap along the thickness direction h3 of the display panel. As shown in Figure 34 Figure 34 Another top view schematic diagram of the display panel provided by the embodiment of the present application is shown, wherein the first sub-common branch line 201 includes the first sub-reference voltage line 2201, the second sub-common branch line 202 includes the second sub-power line 2102, the first sub-connection line 301 is located in the fifth metal layer M5, the first sub-reference voltage line 2201 is located in the semiconductor layer S, and the first sub-connection line 301 and the first sub-reference voltage line 2201 at least partially overlap along the thickness direction h3 of the display panel. And, the second sub-connection line 302 is located in the sixth metal layer M6, the second sub-power line 2102 is located in the fourth metal layer M4, and the second sub-connection line 302 and the second sub-power line 2102 at least partially overlap along the thickness direction h3 of the display panel as an example. As shown in Figure 34 The first sub-connection line 301 and the second sub-connection line 302 are electrically connected through the connection hole K3.

[0088] Optionally, as shown in Figure 35 and Figure 36 Figure 35 Another top view schematic diagram of the display panel provided by the embodiment of the present application is shown, Figure 36 Figure 35 An enlarged schematic diagram of the middle area R, the display area AA also includes a touch electrode 6. As an example, in combination with Figure 37 shown,​​​​Figure 37 A cross-sectional view of another display panel according to an embodiment of the present application is provided. The touch electrode 6 is located on the side of the light emitting element 11 away from the substrate 41. As shown, the touch electrode 6 includes a driving electrode 601 and a sensing electrode 602. Along the thickness direction h3 of the display panel, the touch electrode 6 and the common branch line 2 at least partially overlap. In this way, the light transmittance area in the display area AA is increased. When the display panel is used for fingerprint recognition, the common branch line 2 does not affect the light transmittance of the display panel, and the fingerprint recognition sensitivity of the display panel is ensured based on the arrangement provided by the embodiment of the present application. For example, as shown, the common branch line 2 extends along the extension direction of the edge of the touch electrode 6 at least in part to increase the overlapping area of the common branch line 2 and the touch electrode 6, and ensure the light transmittance area in the display area AA. Figure 35 Figure 35

[0089] Optionally, as shown in FIGS. 6 and 7, the touch electrode 6 has an opening 60 and a cross touch grid line 61. The opening 60 exposes at least part of the second electrode 112 of the light emitting element 11 to avoid affecting the light emission of the sub-pixel due to the arrangement of the touch electrode 6. As shown in FIGS. 8, 9 and 10, along the thickness direction h3 of the display panel, the touch grid line 61 in the touch electrode 6 and the common branch line 2 at least partially overlap to increase the light transmittance area in the display area AA. Figure 36 Figure 40 Figure 35 Figure 36 Figure 37

[0090] As shown in FIGS. 11 and 12, the display panel further includes an encapsulation layer 44 and a touch layer 45. The touch layer 45 is located on the side of the encapsulation layer 44 away from the display film layer 43. The touch layer 44 includes the above-mentioned touch electrode 6. The touch electrode 6 and the common branch line 2 are separated by the encapsulation layer 44. For example, as shown in FIG. 13, the encapsulation layer 44 includes a first inorganic encapsulation layer 441, an organic encapsulation layer 440 and a second inorganic encapsulation layer 442 arranged in layers. Based on this arrangement, the touch electrode 6 and the common branch line 2 have a large distance therebetween, which is beneficial to reduce the coupling interference therebetween. Figure 37 Figure 37 It should be noted that, in order to more clearly show the relative positions of the second electrode 112, the touch electrode 6 and the common branch line 2, the pixel driving circuit is not shown in FIGS. 14 and 15. In addition,

[0091] Figure 36 Figure 6 Figure 14 Figure 19 Figure 25 Figure 27 ​​​​​​​​​​​​​​The shape of the common branch line 2 shown is only one example, and during the design of the display panel, the shape of the common branch line 2 can be designed according to the shape of the touch electrode and the shape of the gap of the pixel driving circuit 10.

[0092] As shown in Figure 5 and Figure 18 , the non-display area NA includes the common bus 5 and the pad 53; the common bus 5 is electrically connected to the corresponding common branch line 2. Specifically, the common bus 5 includes the first power bus 51 and / or the reference voltage bus 52. When the common bus 5 is arranged, the common bus 5 and the pad 53 are located on both sides of the display area AA along the second direction h2. In this way, compared with arranging the common bus 5 and the pad 53 on the same side of the display area AA, the width of the non-display area NA on one side of the display area AA can be avoided to be too large. As shown in Figure 5 , the first power bus 51 and the pad 53 are located on both sides of the display area AA along the second direction h2. As shown in Figure 18 , the reference voltage bus 52 and the pad 53 are located on both sides of the display area AA along the second direction h2.

[0093] As shown in Figure 5 and Figure 18 , the width W5 of the common bus 5 is greater than or equal to the width W2 of the common branch line 2. In this way, it is beneficial to reduce the voltage drop of the signal transmitted by the common bus 5 during propagation. Optionally, the common branch line 2 and the common bus 5 can be arranged on the same layer, or the common branch line 2 and the common bus 5 can be arranged on different layers, and the embodiments of the present application do not limit this.

[0094] As shown in Figure 5 and 18 , the non-display area NA includes a first sub-non-display area NA1 and a second sub-non-display area NA2, and the first sub-non-display area NA1 includes the scan driving circuit 6. The second sub-non-display area NA2 includes a common connection line 7, and the common connection line 7 is electrically connected to the corresponding common bus 5 and the common branch line 2. As an example, the common connection line 7 includes a power connection line 71 or a reference voltage connection line 72. The power connection line 71 is electrically connected to the first power bus 51 and the first power line 21, and the reference voltage connection line 72 is electrically connected to the reference voltage bus 52 and the reference voltage line 22. Figure 5 Taking the power connection line 71 electrically connecting the first power bus 51 and the first power line 21 as an example, Figure 18The reference voltage bus 52 and the above-mentioned reference voltage line 22 are electrically connected by the reference voltage connection line 72. According to the arrangement provided by the embodiment of the present application, the common connection line 7 electrically connecting the common bus 5 and the common branch line 2 can be arranged to avoid the scan driving circuit 6, which is advantageous for reducing the width of the first sub-non-display area NA1 where the scan driving circuit 6 is located.

[0095] As shown in Figure 38 , Figure 38 Fig. 6 is a schematic view of another display panel provided by an embodiment of the present application. The non-display area NA includes a special-shaped non-display area NA31 and a regular non-display area NA32. The line width W31 of the common bus 5 in the special-shaped non-display area NA31 is greater than or equal to the line width W32 of the common bus 5 in the regular non-display area NA32. The edge of the special-shaped non-display area NA2 includes a curve, and the edge of the regular non-display area NA3 includes a straight line. For a display panel with a round rectangular shape as shown in Figure 38 , the special-shaped non-display area NA2 can correspond to the round area of the display panel, and the regular non-display area NA3 can correspond to the area where the long side or the short side of the display panel is located. Generally, the space in the special-shaped non-display area NA2 is more abundant than the space in the regular non-display area NA3. By setting the line width W31 of the common bus 5 in the special-shaped non-display area NA2 to be greater than or equal to the line width W32 of the common bus 5 in the regular non-display area NA3, the line width of the common bus 5 can be set as large as possible in the existing wiring space, which is advantageous for reducing the resistance of the common bus 5 and the voltage drop of the signal transmitted by the common bus 5 in the transmission process.

[0096] As shown in Figure 39 , Figure 39 Fig. 7 is a schematic view of another display panel provided by an embodiment of the present application. The common bus 5 includes a first sub-common bus 501 and a second sub-common bus 502 which are electrically connected. The width of the first sub-common bus 501 is less than or equal to the width of the second sub-common bus 502. Such an arrangement is advantageous for reducing the space of the non-display area NA occupied by the first sub-common bus 501 and leaving space for the arrangement of other wires. Figure 39 Optionally, in the embodiment of the present application, the common branch line 2 is electrically connected to at least the first sub-common bus 501. Such an arrangement is advantageous for reducing the load of the first sub-common bus 501 with a smaller width, so as to weaken the heating degree of the first sub-common bus 501 in the working process of the display panel, which is advantageous for improving the reliability of the first sub-common bus 501.

[0097] As shown in Figure 40 , Figure 40 Fig. 8 is a schematic view of another display panel provided by an embodiment of the present application.Figure 38 An enlarged schematic view of the middle region Q, the common bus 5 includes an opening 50. The opening 50 can be arranged to discharge the gas released by the organic layer located below the common bus 5, avoid the bulging problem caused by the overflow of the gas in the common bus 5, and improve the reliability of the display panel. In addition, the opening 50 can also reduce the overlapping area of the common bus 5 and other wirings, thereby reducing the coupling between the common bus 5 and the other wirings.

[0098] The embodiment of the present application also provides a display device, as shown in Figure 41 Figure 41 A schematic view of a display device provided by the embodiment of the present application, which includes the display panel 100 described above. The specific structure of the display panel 100 has been described in detail in the above embodiment, and will not be repeated here. Of course, Figure 41 The display device shown in the figure is only a schematic illustration, and the display device can be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic paper, or a television.

[0099] The above merely provides the preferred embodiments of the present application but not for limiting the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.​

Claims

1. A display panel, characterized in that, Includes display area and non-display area; The display area includes: Multiple sub-pixels, each sub-pixel including an electrically connected pixel driving circuit and a light-emitting element; each light-emitting element including a first electrode, the first electrodes of different light-emitting elements being electrically connected; A common branch line is electrically connected to multiple of the said sub-pixels; The non-display area includes a common bus; the common bus is electrically connected to the common branch line. The common branch line includes a reference voltage line; the reference voltage line is electrically connected to the pixel driving circuit. The reference voltage line includes a first sub-reference voltage line and a second sub-reference voltage line that are electrically connected; the first sub-reference voltage line extends along a first direction, and the second sub-reference voltage line extends along a second direction; the first direction and the second direction intersect. The display panel also includes a data line electrically connected to the pixel driving circuit; The second sub-reference voltage line is arranged on the same layer as the data line.

2. The display panel according to claim 1, characterized in that, Along the thickness direction of the display panel, the first sub-reference voltage line and / or the second sub-reference voltage line of the common branch are offset from the pixel driving circuit.

3. The display panel according to claim 1, characterized in that, The plurality of pixel driving circuits includes a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit; the distance between the first pixel driving circuit and the second pixel driving circuit is greater than or equal to the distance between the second pixel driving circuit and the third pixel driving circuit. The portion of the common branch is located between the first pixel driving circuit and the second pixel driving circuit.

4. The display panel according to any one of claims 1-3, characterized in that, Between two adjacent common branches, there are N pixel driving circuits, where N is an integer greater than or equal to 1.

5. The display panel according to claim 1, characterized in that, The common branch line also includes a first power line; the first power line is electrically connected to the first electrode of the light-emitting element; the first power line includes a second sub-power line; the second sub-power line and the second sub-reference voltage line extend along a second direction; the first direction intersects the second direction; The display panel includes a gap region located between two adjacent pixel driving circuits; the second sub-power line and the second sub-reference voltage line are located in different gap regions.

6. The display panel according to claim 1, characterized in that, The pixel driving circuit includes multiple thin-film transistors, and the first sub-reference voltage line is disposed on the same layer as the active layer of the thin-film transistors.

7. The display panel according to claim 6, characterized in that, The first sub-reference voltage line is electrically connected to the active layer of the thin-film transistor of two adjacent pixel driving circuits, wherein the two adjacent pixel driving circuits are arranged along the extension direction of the first sub-reference voltage line.

8. The display panel according to any one of claims 1-7, characterized in that, The first power line includes a second sub-power line; the second sub-power line and the second sub-reference voltage line extend along a second direction; the first direction intersects the second direction; The second sub-reference voltage line and the second sub-power line are arranged on the same layer.

9. The display panel according to any one of claims 1-7, characterized in that, The first power line includes a first sub-power line and a second sub-power line that are electrically connected; the reference voltage line includes a first sub-reference voltage line and a second sub-reference voltage line that are electrically connected; the first sub-power line and the first sub-reference voltage line extend along a first direction, and the second sub-power line and the second sub-reference voltage line extend along a second direction; the first direction and the second direction intersect.

10. The display panel according to claim 1, characterized in that, The non-display area includes a first power bus and pads; the first power bus is electrically connected to the first power line. The first power bus and the pads are located on both sides of the display area.

11. The display panel according to claim 1, characterized in that, The display area also includes: Multiple data lines are arranged along a first direction, and the data lines are electrically connected to the pixel driving circuit; the multiple data lines include an inner data line and at least one edge data line, and the edge data line is located on the side of the inner data line close to the edge of the display panel; A connecting line is electrically connected to the edge data line; the end of the connecting line near the non-display area is located on the side of the edge data line near the inner data line.

12. The display panel according to claim 11, characterized in that, The connecting line includes a first sub-connecting line and a second sub-connecting line that are electrically connected; the common branch line includes a first sub-common branch line and a second common branch line that are electrically connected. The first sub-connecting line and the first sub-common branch line extend along a first direction, and the second sub-connecting line and the second sub-common branch line extend along a second direction; the first direction and the second direction intersect. The second sub-connecting line is installed on the same layer as the second sub-common branch line.

13. The display panel according to claim 1, characterized in that, The non-display area includes irregularly shaped non-display areas and regular non-display areas; The line width of the common bus in the irregular non-display area is greater than or equal to the line width of the common bus in the regular non-display area.

14. The display panel according to any one of claims 1-13, characterized in that, The display area includes scan lines; The non-display area includes a first sub-non-display area and a second sub-non-display area. The first sub-non-display area includes a scan driving circuit, which is electrically connected to the scan line. The second sub-display area includes a common connection line, which electrically connects the common bus and the common branch line.

15. The display panel according to claim 14, characterized in that, The common bus includes an opening.

16. The display panel according to any one of claims 1-2, characterized in that, The reference voltage line includes a first reference voltage line and a second reference voltage line; both the first reference voltage line and the second reference voltage line include a first sub-reference voltage line electrically connected and extending along the first direction and a second sub-reference voltage line extending along the second direction.

17. A display device, characterized in that, Includes the display panel as described in any one of claims 1-16.

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