Scanning driver and electronic device

Abstract

The invention provides a scan driver and an electronic device. The scan driver includes a cell stage including a plurality of stages configured to receive a plurality of clock signals and sequentially output a plurality of scan signals. The cell stage includes one shared circuit and a plurality of buffer circuits corresponding to the plurality of stages, respectively. The sharing circuit includes: a first transistor configured to supply a start signal to a first node based on a first clock signal received from a first clock line; a second transistor configured to supply a first clock signal to a second node based on a voltage of the first node; and a third transistor configured to supply a gate low voltage to the second node based on the first clock signal. Each of the plurality of buffer circuits is directly connected to the first node and the second node, and outputs a plurality of scan signals.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0073406, filed on June 5, 2024, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] Embodiments of the disclosure relate to a scan driver, a display device including the scan driver, and an electronic device including the display device. BACKGROUND

[0004] As information technology advances, the demand for display devices capable of displaying images has increased in various applications. For example, display devices can be included in various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart televisions. Display devices can include light emitting elements in which each of a plurality of pixels of a display panel can emit light by itself, thereby displaying images without a backlight unit that provides light to the display panel.

[0005] A display device includes a plurality of pixels, data lines and gate lines connected to the plurality of pixels, a data driver that supplies a data voltage to the data lines, and a scan driver that supplies a scan signal to the gate lines. The data driver and the scan driver can drive the plurality of pixels according to a predetermined frequency. SUMMARY

[0006] Embodiments of the disclosure provide a scan driver that can reduce the area of a non-display region and power consumption, a display device including the scan driver, and an electronic device including the display device.

[0007] According to embodiments of the disclosure, a scan driver includes a unit stage including a plurality of stages configured to receive a plurality of clock signals including a first clock signal and sequentially output a plurality of scan signals. The unit stage includes one shared circuit and a plurality of buffer circuits corresponding to the plurality of stages, respectively. The shared circuit includes a first transistor configured to supply a start signal to a first node based on a first clock signal received from a first clock line, a second transistor configured to supply the first clock signal to a second node based on a voltage of the first node, and a third transistor configured to supply a gate low voltage to the second node based on the first clock signal. Each of the plurality of buffer circuits is directly connected to the first node and the second node and outputs the plurality of scan signals.

[0008] In an embodiment, each of the plurality of buffer circuits includes: a fourth transistor configured to supply a gate high voltage to an output node of the respective stage of the buffer circuit based on a voltage of the second node; a fifth transistor configured to supply one of the plurality of clock signals to the output node of the respective stage of the buffer circuit; and a sixth transistor configured to supply a voltage of the first node to a gate electrode of the fifth transistor based on a gate low voltage.

[0009] In an embodiment, each of the plurality of buffer circuits further includes: a first capacitor connected between the second node and an input terminal of the gate high voltage; and a second capacitor connected between the gate electrode of the fifth transistor and the output node of the respective stage of the buffer circuit.

[0010] In an embodiment, the scan driver further includes: a metal layer disposed on the substrate; an active layer disposed on the metal layer and including a semiconductor region of the first transistor; a first gate layer disposed on the active layer and including a gate electrode of the first transistor and a first electrode of the first capacitor; a second gate layer disposed on the first gate layer and including a second electrode of the first capacitor; a third gate layer disposed on the second gate layer; a first source metal layer disposed on the third gate layer; and a second source metal layer disposed on the first source metal layer and including a plurality of clock lines configured to supply the plurality of clock signals.

[0011] In an embodiment, the scan driver further includes: a first node electrode disposed in the second gate layer and corresponding to the first node; a first connection electrode disposed in the first source metal layer and electrically connecting the first transistor, the first node electrode, and the sixth transistor of the first stage among the plurality of stages; a second connection electrode disposed in the first source metal layer and electrically connecting the first node electrode and the sixth transistor of the second stage among the plurality of stages; and a third connection electrode disposed in the first source metal layer and electrically connecting the first node electrode and the sixth transistor of the third stage among the plurality of stages.

[0012] In an embodiment, the first node electrode is disposed between the plurality of clock lines and does not overlap the second source metal layer.

[0013] In an embodiment, the scan driver further includes: a first node electrode disposed in the second source metal layer and corresponding to the first node; a first connection electrode disposed in the first source metal layer and electrically connecting the first transistor, the first node electrode, and a sixth transistor of a first stage among the plurality of stages; a second connection electrode disposed in the first source metal layer and electrically connecting the first node electrode and a sixth transistor of a second stage among the plurality of stages; and a third connection electrode disposed in the first source metal layer and electrically connecting the first node electrode and a sixth transistor of a third stage among the plurality of stages.

[0014] In an embodiment, the scan driver further includes: a second node electrode disposed in the second gate layer and corresponding to the second node; a fourth connection electrode disposed in the first source metal layer and electrically connecting the second node electrode and a gate electrode of a fourth transistor of a first stage among the plurality of stages; a fifth connection electrode disposed in the first source metal layer and electrically connecting the second node electrode and a gate electrode of a fourth transistor of a second stage among the plurality of stages; and a sixth connection electrode disposed in the first source metal layer and electrically connecting the second node electrode and a gate electrode of a fourth transistor of a third stage among the plurality of stages.

[0015] In an embodiment, the first capacitor of each of the plurality of buffer circuits includes: a first electrode disposed in the first gate layer and including a gate electrode of the fourth transistor; and a second electrode disposed in the second gate layer and overlapping the first electrode.

[0016] In an embodiment, the scan driver further includes: a seventh connection electrode disposed in the first source metal layer and electrically connecting a first electrode of a fifth transistor of a first stage among the plurality of stages and the second clock line; and an eighth connection electrode disposed in the first source metal layer and electrically connecting a second electrode of the fifth transistor of the first stage and an output node of the first stage. The second capacitor of the first stage can include: a first electrode disposed in the first gate layer and including a gate electrode of the fifth transistor; and a second electrode disposed in the second gate layer and electrically connected to the eighth connection electrode.

[0017] In an embodiment, each of the plurality of stages includes one of the first transistor, the second transistor, and the third transistor, respectively.

[0018] In an implementation, the multiple levels may include four or more levels, each of the three levels may include one of the first transistor, the second transistor, and the third transistor, and the remaining levels may include dummy units arranged on the same layer as the first transistor, the second transistor, and the third transistor.

[0019] According to embodiments of this disclosure, a scan driver includes a first stage, a second stage, and a third stage, each stage including a shared circuit and a plurality of buffer circuits configured to sequentially output a plurality of scan signals. The shared circuit includes: a first transistor configured to supply a start signal to a first node based on a first clock signal among a plurality of clock signals; a second transistor configured to supply the first clock signal to a second node based on a voltage of the first node; and a third transistor configured to supply a gate low voltage to the second node based on the first clock signal. The buffer circuit of each of the first, second, and third stages includes: a fourth transistor configured to supply a gate high voltage to the output node of the corresponding stage of the buffer circuit based on a voltage of the second node; a fifth transistor configured to supply one of a plurality of clock signals to the output node; and a sixth transistor configured to supply the voltage of the first node to the gate electrode of the fifth transistor based on a gate low voltage.

[0020] In one embodiment, the scan driver further includes: a metal layer disposed on a substrate; an active layer disposed on the metal layer and including a semiconductor region of a first transistor; a first gate layer disposed on the active layer and including a gate electrode of the first transistor and a first electrode of a first capacitor; a second gate layer disposed on the first gate layer and including a second electrode of the first capacitor; a third gate layer disposed on the second gate layer; a first source metal layer disposed on the third gate layer; and a second source metal layer disposed on the first source metal layer and including a plurality of clock lines configured to supply a plurality of clock signals.

[0021] In one embodiment, the scan driver further includes: a first connection electrode disposed in a first source metal layer and electrically connected to a first transistor and a sixth transistor of a first stage; and a first node electrode disposed in a second gate layer, connected to the first connection electrode, and corresponding to a first node. The first node electrode may be disposed between multiple clock lines and may not overlap with the second source metal layer.

[0022] According to an embodiment of this disclosure, a display device includes: a display panel including a plurality of data lines to which a plurality of data voltages are applied, a plurality of gate lines intersecting the plurality of data lines, and a plurality of pixels connected to the plurality of data lines and the plurality of gate lines, wherein a plurality of gate signals are applied to the plurality of gate lines; a data driver configured to supply a plurality of data voltages to the plurality of data lines; and a scan driver configured to sequentially supply a plurality of gate signals to the plurality of gate lines. The scan driver includes a first stage, a second stage, and a third stage, the first stage, the second stage, and the third stage including a shared circuit and a plurality of buffer circuits configured to sequentially output a plurality of scan signals. The shared circuit includes: a first transistor configured to supply a start signal to a first node based on a first clock signal among a plurality of clock signals received from a first clock line among a plurality of clock lines; a second transistor configured to supply the first clock signal to a second node based on the voltage of the first node; and a third transistor configured to supply a gate low voltage to the second node based on the first clock signal. Each of the multiple buffer circuits is directly connected to the first node and the second node, and is configured to output the first gate signal of the multiple gate signals to the first gate line of the multiple gate lines.

[0023] In one embodiment, the scan driver further includes: a metal layer disposed on a substrate; an active layer disposed on the metal layer and including a semiconductor region of a first transistor; a first gate layer disposed on the active layer and including a gate electrode of the first transistor and a first electrode of a first capacitor; a second gate layer disposed on the first gate layer and including a second electrode of the first capacitor; a third gate layer disposed on the second gate layer; a first source metal layer disposed on the third gate layer; and a second source metal layer disposed on the first source metal layer and including a plurality of clock lines configured to supply a plurality of clock signals.

[0024] In an embodiment, a pixel includes: a first pixel transistor configured to control a drive current flowing through a light-emitting element; a second pixel transistor configured to supply a data voltage, one of a plurality of data voltages, to a first electrode of the first pixel transistor based on a first gate signal; a third pixel transistor configured to electrically connect a second electrode and a gate electrode of the first pixel transistor based on a second gate signal, one of a plurality of gate signals; a fourth pixel transistor configured to supply an initialization voltage to the gate electrode of the first pixel transistor based on a third gate signal, one of a plurality of gate signals; and a fifth pixel transistor configured to supply a drive voltage to the first electrode of the first pixel transistor based on a light-emitting signal.

[0025] In an embodiment, the display device further includes: a first node electrode disposed in a second gate layer and corresponding to a first node; a second gate line among a plurality of gate lines disposed in a third gate layer and configured to supply a second gate signal; and a light-emitting line disposed in the third gate layer and configured to supply a light-emitting signal.

[0026] In an embodiment, the display device further includes: a first node electrode disposed in a second source metal layer and corresponding to a first node; a second gate line among a plurality of gate lines disposed in a second gate layer and configured to supply a second gate signal; and a light-emitting line disposed in a third gate layer and configured to supply a light-emitting signal.

[0027] According to embodiments of this disclosure, an electronic device includes: a display device; and a power supply configured to provide power to the display device. The display device includes: a display panel including a plurality of data lines to which a plurality of data voltages are applied, a plurality of gate lines intersecting the plurality of data lines, and a plurality of pixels connected to the plurality of data lines and the plurality of gate lines, wherein a plurality of gate signals are applied to the plurality of gate lines; a data driver configured to supply the plurality of data voltages to the plurality of data lines; and a scan driver configured to sequentially supply the plurality of gate signals to the plurality of gate lines. The scan driver includes a first stage, a second stage, and a third stage, the first stage, the second stage, and the third stage including a shared circuit and a plurality of buffer circuits configured to sequentially output the plurality of scan signals. The shared circuitry includes: a first transistor configured to supply a start signal to a first node based on a first clock signal among a plurality of clock signals received from a first clock line among a plurality of clock lines; a second transistor configured to supply the first clock signal to a second node based on the voltage of the first node; and a third transistor configured to supply a gate low voltage to the second node based on the first clock signal. Each of the plurality of buffer circuits is directly connected to the first and second nodes and is configured to output a first gate signal among a plurality of gate signals to a first gate line among a plurality of gate lines.

[0028] In the display device according to the embodiment, since multiple stages within a unit level share some transistors, the number of transistors in the gate driver can be reduced, thereby reducing the area of ​​the non-display area and reducing power consumption. Attached Figure Description

[0029] The above and other features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0030] Figure 1 This is a perspective view of a display device according to an embodiment;

[0031] Figure 2 This is a block diagram illustrating a display device according to an embodiment;

[0032] Figure 3 This is a circuit diagram illustrating the pixels of a display device according to an embodiment;

[0033] Figure 4 This is a block diagram illustrating a scan driver of a display device according to an embodiment;

[0034] Figure 5 This is a circuit diagram of the first unit level of the scan driver in a display device according to an embodiment;

[0035] Figure 6 This is a layout diagram of the first unit level of the scan driver in a display device according to an embodiment;

[0036] Figure 7 The illustration is based on the implementation method. Figure 6 A layout diagram of the metal layer, active layer and first gate layer of the first unit level in a display device;

[0037] Figure 8 The illustration is based on the implementation method. Figure 6 A layout diagram of the metal layer, active layer, first gate layer, second gate layer and third gate layer of the first unit level in a display device;

[0038] Figure 9 The illustration is based on the implementation method. Figure 6 A layout diagram of the first source metal layer and the second source metal layer in the first unit level of the display device;

[0039] Figure 10 The illustration is based on the implementation method. Figure 6 A cross-sectional view of a portion of the first unit level in a display device;

[0040] Figure 11 The illustration is based on the implementation method. Figure 6 A cross-sectional view of another part of the first unit level in the display device;

[0041] Figure 12 This is a cross-sectional view illustrating a portion of the first unit level in a display device according to an embodiment;

[0042] Figure 13 This is a block diagram illustrating a scan driver of a display device according to an embodiment;

[0043] Figure 14 This is a circuit diagram of the first unit level of the scan driver in a display device according to an embodiment;

[0044] Figure 15 This is a simplified illustration of the first unit level of the scan driver in a display device according to an embodiment; and

[0045] Figure 16 This is a block diagram illustrating an electronic device according to an embodiment. Detailed Implementation

[0046] Embodiments of this disclosure will be described more fully below with reference to the accompanying drawings. Throughout the specification and drawings, similar reference numerals may refer to similar elements.

[0047] In this document, when two or more elements or values ​​are described as substantially the same or substantially equal to each other, it is to be understood that the elements or values ​​are equivalent to each other, are equal to each other within measurement error, or, if the measurements are unequal, are sufficiently close in value to be functionally equal to each other, as will be understood by those skilled in the art. For example, taking into account the measurement and the error associated with a particular number of measurements (e.g., limitations of the measurement system), the term "about" as used herein includes said value and means within an acceptable range of deviation for a particular value as determined by those skilled in the art. For example, "about" may mean within one or more standard deviations, as will be understood by those skilled in the art. Furthermore, it is to be understood that while a parameter may be described herein as having a "about" specific value, depending on the implementation, the parameter may be precisely a specific value or approximate a specific value within measurement error, as will be understood by those skilled in the art. Other uses of these terms and similar terms used to describe relationships between components should be interpreted in a similar manner.

[0048] It will be understood that when a component, such as a membrane, region, layer, or element, is referred to as being "on" another component, "connected" to another component, "linked" to another component, or "adjacent" to another component, that component can be directly on, directly connected to, directly linked to, or directly adjacent to the other component, or there may be intervening components. It will also be understood that when a component is referred to as "covering" another component, that component can be the only component covering the other component, or one or more intervening components can also cover the other component. Other terms used to describe relationships between components can be interpreted in a similar manner.

[0049] It will also be understood that, unless the context explicitly indicates otherwise, the description of a feature or aspect in each embodiment can be used for other similar features or aspects in other embodiments. Therefore, all features and structures described herein can be mixed and matched in any desired manner.

[0050] Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” as used herein are intended to also include the plural forms.

[0051] It will be understood that the terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, an element that is “first” in one embodiment may be described as a “second” element in another embodiment.

[0052] When a feature is perceived as extending, protruding, or otherwise following a particular direction, it will be understood that the feature may follow said direction in a negative direction, i.e., the opposite direction. Therefore, a feature is not limited to following exactly one direction, and may follow an axis formed by that one direction, unless the context clearly indicates otherwise.

[0053] Figure 1 This is a perspective view illustrating a display device according to an embodiment.

[0054] refer to Figure 1 The display device 10 is a device for displaying moving images (e.g., video) or still images, and can be used as a display screen in various electronic products such as televisions, laptop computers, monitors, billboards and Internet of Things (IoT) devices, as well as in portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices and ultra-mobile PCs (UMPCs).

[0055] The display device 10 may include a display panel 100, a data driver 200 (also called a data driver circuit), a timing controller 300 (also called a timing controller circuit), a power supply unit 400 (also called a power supply circuit), a data circuit board 500, a control circuit board 600, and a scan driver 800 (also called a scan driver circuit).

[0056] The display panel 100 may have a rectangular planar surface with a relatively long side in the X-axis direction and a relatively short side in the Y-axis direction intersecting the X-axis direction. The corners where the long side in the X-axis direction and the short side in the Y-axis direction intersect may be rounded to have a predetermined curvature, or may be formed as right angles. The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be formed as, for example, other polygonal shapes, circular shapes, or elliptical shapes. The display panel 100 may be formed as flat, but is not limited to this. For example, the display panel 100 may include bent surface portions formed at its left and right distal ends and having constant or variable curvature. The display panel 100 may be flexibly formed into bent, curved, folded, or rolled shapes.

[0057] Display panel 100 may include a display area DA in which an image is displayed and a non-display area NDA arranged around the display area DA in which no image is displayed. The display area DA may occupy most of the area of ​​display panel 100. The display area DA may be located at or near the center of display panel 100. The display area DA may include multiple pixels of the displayed image.

[0058] Each of the plurality of pixels may include a light-emitting element that emits light. The light-emitting element may include, but is not limited to, at least one of an organic light-emitting diode containing an organic light-emitting layer, a quantum dot light-emitting diode containing a quantum dot light-emitting layer, an inorganic light-emitting diode containing an inorganic semiconductor, and a micro light-emitting diode (microLED).

[0059] The non-display area NDA can be arranged adjacent to the display area DA. The non-display area NDA can be an area outside the display area DA. The non-display area NDA can surround the display area DA. The non-display area NDA can be an edge area of ​​the display panel 100.

[0060] The non-display area NDA may include a scan driver 800, fan-out lines, and pad portions. The scan driver 800 supplies scan signals to the gate lines of the display area DA. The scan driver 800 may be located on the left and right edges of the non-display area NDA, but is not limited thereto. The fan-out lines may electrically connect the data driver 200 and the data lines of the display area DA. The pad portions may be electrically connected to the data circuit board 500. The pad portions may be located at the lower edge of the display panel 100, but are not limited thereto.

[0061] The data driver 200 can output signals and voltages to drive the display panel 100. The data driver 200 can supply data voltage to data lines. The data driver 200 can supply power voltage to power lines and can supply scan control signals to the scan driver 800. In one embodiment, the data driver 200 can be formed as an integrated circuit (IC) and mounted on the data circuit board 500 using a chip-on-film (COF) method. In another embodiment, the data driver 200 can be mounted in the non-display area NDA of the display panel 100 using, for example, a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method.

[0062] The timing controller 300 can be mounted on the control circuit board 600 and can receive digital video data and timing synchronization signals supplied from the display driving system or graphics device via connectors provided on the control circuit board 600. The timing controller 300 can align the digital video data to fit the pixel arrangement structure based on the timing synchronization signals and can supply the aligned digital video data to the data driver 200. The timing controller 300 can generate data control signals and scan control signals based on the timing synchronization signals. The timing controller 300 can control the supply timing of the data voltage to the data driver 200 based on the data control signals and control the supply timing of the scan signals to the scan driver 800 based on the scan control signals.

[0063] The power supply unit 400 can be mounted on the control circuit board 600 and can supply power voltage to the display panel 100 and the data driver 200. For example, the power supply unit 400 can generate a drive voltage, a common voltage, an initialization voltage, a bias voltage, a gate high voltage, a gate low voltage, or a reference voltage. The power supply unit 400 can drive multiple pixels and the data driver 200 by supplying power voltage.

[0064] Data circuit board 500 may be disposed on a pad portion located at one edge of display panel 100. Data circuit board 500 may be attached to the pad portion using a conductive adhesive member such as an anisotropic conductive film. Data circuit board 500 may be electrically connected to signal lines of display panel 100 via the anisotropic conductive film. Display panel 100 may receive data voltage and power supply voltage via data circuit board 500. For example, data circuit board 500 may be a flexible film such as a flexible printed circuit board, a rigid printed circuit board, or a chip-on-film.

[0065] The control circuit board 600 can be attached to the data circuit board 500 using low-resistance and high-reliability materials such as anisotropic conductive film or self-assembling anisotropic conductive adhesive (SAP). The control circuit board 600 can be electrically connected to the data circuit board 500. The control circuit board 600 can be a flexible printed circuit board or a rigid printed circuit board.

[0066] Figure 2 This is a block diagram illustrating a display device according to an embodiment.

[0067] refer to Figure 2 The display panel 100 may include a display area DA and a non-display area NDA. The display area DA may include multiple pixels SP, multiple gate lines GL, multiple light emission control lines EML, multiple data lines DL, and multiple voltage lines VL.

[0068] Each of the multiple pixels SP can be connected to a gate line GL, a data line DL, a light-emitting control line EML, and a voltage line VL. Each of the multiple pixels SP may include at least one transistor, a light-emitting element, and a capacitor.

[0069] Multiple gate lines GL can extend in the X-axis direction and can be spaced apart from each other in the Y-axis direction, which intersects the X-axis direction. Multiple gate lines GL can sequentially supply gate signals to multiple pixels SP.

[0070] Multiple emission control lines (EMLs) can extend in the X-axis direction and can be spaced apart from each other in the Y-axis direction. Multiple emission control lines (EMLs) can sequentially supply emission signals to multiple pixels (SPs).

[0071] Multiple data lines DL can extend in the Y-axis direction and can be spaced apart from each other in the X-axis direction. The data lines DL can supply data voltage (e.g., analog data voltage) received from the data driver 200 to the pixels SP. The data voltage determines the brightness of each of the multiple pixels SP.

[0072] Multiple voltage lines VL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction. The multiple voltage lines VL may supply power voltage to multiple pixels SP. The power supply voltage may include at least one of, for example, a drive voltage, a common voltage, an initialization voltage, a bias voltage, a gate high voltage, a gate low voltage, and a reference voltage. For example, the drive voltage may be a high potential voltage of the light-emitting element driving the pixel SP, and the common voltage may be a low potential voltage of the light-emitting element driving the pixel SP.

[0073] The data driver 200 converts digital video data DATA into analog data voltage and supplies the analog data voltage to the data line DL. The gate signal of the gate driver 810 selects the pixel SP to which the data voltage is supplied, and the selected pixel SP can receive the data voltage through the data line DL.

[0074] The timing controller 300 can receive digital video data DATA and timing signals from the graphics device 700. For example, the graphics device 700 can be a graphics card of the display device 10, but is not limited thereto. The timing controller 300 can generate a data control signal DCS based on the timing signals and supply the digital video data DATA and the data control signal DCS to the data driver 200, thereby controlling the operating timing of the data driver 200. The timing controller 300 can generate a gate control signal GCS based on the timing signals and supply the gate control signal GCS to the gate driver 810, thereby controlling the operating timing of the gate driver 810. The timing controller 300 can generate a light emission control signal ECS based on the timing signals and supply the light emission control signal ECS to the light emission control driver 820, thereby controlling the operating timing of the light emission control driver 820. The timing controller 300 can change the driving frequency of the display panel 100 based on the input frequency of the digital video data DATA of the graphics device 700.

[0075] The power supply unit 400 can be disposed on the data circuit board 500 and can supply power voltage to the data driver 200 and the display panel 100. The power supply unit 400 can generate a driving voltage and supply it to the driving voltage line, and can generate a common voltage and supply it to the common electrode of the light-emitting elements of the pixel SP. The power supply unit 400 can generate an initialization voltage and supply it to the initialization voltage line, and can generate a bias voltage and supply it to the bias voltage line. The power supply unit 400 can generate a gate high voltage and supply it to the gate high voltage line, generate a gate low voltage and supply it to the gate low voltage line, and generate a reference voltage and supply it to the reference voltage line.

[0076] In one embodiment, the gate driver 810 may be arranged outside one side of the display area DA or on one side of the non-display area NDA, and the light-emitting control driver 820 may be arranged outside the other side of the display area DA or on the other side of the non-display area NDA, but this disclosure is not limited thereto. In another embodiment, the gate driver 810 and the light-emitting control driver 820 may be arranged on one side or the other side of the non-display area NDA.

[0077] Gate driver 810 may include multiple transistors that generate gate signals based on gate control signals GCS. Light emission control driver 820 may include multiple transistors that generate light emission signals based on light emission control signals ECS. For example, the transistors of gate driver 810 and light emission control driver 820 may be formed on the same layer as the transistors of each of the multiple pixels SP. Gate driver 810 may supply gate signals to gate line GL, and light emission control driver 820 may supply light emission signals to light emission control line EML.

[0078] Figure 3 This is a circuit diagram illustrating the pixels of a display device according to an embodiment.

[0079] refer to Figure 3 The display panel 100 may include a plurality of pixels SP arranged along a plurality of rows and columns. Each of the plurality of pixels SP may be connected to a first gate line GWL, a second gate line GCL, a third gate line GIL, a fourth gate line GBL, a light emission control line EML, a data line DL, a drive voltage line VDL, a first initialization voltage line VIL1, a second initialization voltage line VIL2, a bias voltage line VBL, and a low potential line VSL.

[0080] A pixel SP may include a light-emitting element ED and a pixel circuit for driving the light-emitting element ED. The pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8, as well as a capacitor C1.

[0081] The first transistor T1 controls the drive current supplied to the light-emitting element ED. The first transistor T1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 may be connected to a third pixel node PN3, the first electrode of the first transistor T1 may be connected to a first pixel node PN1, and the second electrode of the first transistor T1 may be connected to a second pixel node PN2. For example, the first electrode of the first transistor T1 may be a source electrode, and the second electrode of the first transistor T1 may be a drain electrode, but it is not limited to these.

[0082] The first transistor T1 can control the source-drain current Isd (hereinafter referred to as the "drive current") based on the data voltage applied to the gate electrode of the first transistor T1. The drive current Isd flowing through the channel of the first transistor T1 is proportional to the square of the difference between the voltage Vsg between the source electrode and the gate electrode of the first transistor T1 and the threshold voltage Vth (Isd = k × (Vsg - Vth)). 2 Here, k is a scaling factor determined by the structure and physical characteristics of the first transistor T1, Vsg is the source-gate voltage of the first transistor T1, and Vth is the threshold voltage of the first transistor T1.

[0083] A light-emitting element (ED) can emit light by receiving a driving current Isd. The amount of light emitted from the ED, or the brightness of the ED, is proportional to the magnitude of the driving current Isd. The ED may include a first electrode, a second electrode, and a light-emitting layer disposed between the first and second electrodes. The first electrode of the ED may be connected to a fourth pixel node PN4. The first electrode of the ED may be electrically connected to the second electrode of a sixth transistor T6 and the first electrode of a seventh transistor T7 via the fourth pixel node PN4. The second electrode of the ED may be electrically connected to a low-potential line VSL and may receive a low-potential voltage from the low-potential line VSL. For example, the first electrode of the ED may be an anode electrode or a pixel electrode, and the second electrode of the ED may be a cathode electrode or a common electrode, but is not limited thereto.

[0084] The second transistor T2 can be turned on via a first gate signal on the first gate line GWL, and is electrically connected to the data line DL and the first pixel node PN1, which is the first electrode of the first transistor T1. The first gate line GWL may correspond to a scan write line. The second transistor T2 can be turned on based on the first gate signal, thereby supplying a data voltage to the first pixel node PN1. The gate electrode of the second transistor T2 may be connected to the first gate line GWL, the first electrode of the second transistor T2 may be connected to the data line DL, and the second electrode of the second transistor T2 may be connected to the first pixel node PN1. The second electrode of the second transistor T2 can be electrically connected via the first pixel node PN1 to the first electrode of the first transistor T1, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8. For example, the first electrode of the second transistor T2 may be the source electrode, and the second electrode of the second transistor T2 may be the drain electrode, but is not limited thereto.

[0085] The third transistor T3 can be turned on via the second gate signal of the second gate line GCL, and can be electrically connected to the second pixel node PN2, which is the second electrode of the first transistor T1, and the third pixel node PN3, which is the gate electrode of the first transistor T1. The gate electrode of the third transistor T3 can be connected to the second gate line GCL, the first electrode of the third transistor T3 can be connected to the second pixel node PN2, and the second electrode of the third transistor T3 can be connected to the third pixel node PN3. The first electrode of the third transistor T3 can be electrically connected to the second electrode of the first transistor T1 and the first electrode of the sixth transistor T6 via the second pixel node PN2. The second electrode of the third transistor T3 can be electrically connected to the gate electrode of the first transistor T1, the first electrode of the fourth transistor T4, and the first capacitor electrode of the capacitor C1 via the third pixel node PN3. For example, the first electrode of the third transistor T3 can be the drain electrode, and the second electrode of the third transistor T3 can be the source electrode, but it is not limited to these.

[0086] The fourth transistor T4 can be turned on via the third gate signal of the third gate line GIL, and can be electrically connected to the third pixel node PN3, which serves as the gate electrode of the first transistor T1, and the first initialization voltage line VIL1. The fourth transistor T4 can be turned on based on the third gate signal, thereby initializing the voltage of the gate electrode of the first transistor T1 to the first initialization voltage. The gate electrode of the fourth transistor T4 can be connected to the third gate line GIL, the first electrode of the fourth transistor T4 can be connected to the third pixel node PN3, and the second electrode of the fourth transistor T4 can be connected to the first initialization voltage line VIL1. The first electrode of the fourth transistor T4 can be electrically connected via the third pixel node PN3 to the gate electrode of the first transistor T1, the second electrode of the third transistor T3, and the first capacitor electrode of the capacitor C1. For example, the first electrode of the fourth transistor T4 can be the drain electrode, and the second electrode of the fourth transistor T4 can be the source electrode, but is not limited thereto.

[0087] The fifth transistor T5 can be turned on by the light emission signal of the light emission control line EML, and can be electrically connected to the driving voltage line VDL and the first pixel node PN1, which is the first electrode of the first transistor T1. The gate electrode of the fifth transistor T5 can be connected to the light emission control line EML, the first electrode of the fifth transistor T5 can be connected to the driving voltage line VDL, and the second electrode of the fifth transistor T5 can be connected to the first pixel node PN1. The second electrode of the fifth transistor T5 can be electrically connected to the first electrode of the first transistor T1, the second electrode of the second transistor T2, and the second electrode of the eighth transistor T8 through the first pixel node PN1. For example, the first electrode of the fifth transistor T5 can be the source electrode, and the second electrode of the fifth transistor T5 can be the drain electrode, but it is not limited to these.

[0088] The sixth transistor T6 can be turned on by the light emission signal of the light emission control line EML, and can be electrically connected to the second pixel node PN2, which is the second electrode of the first transistor T1, and the fourth pixel node PN4, which is the first electrode of the light emission element ED. The gate electrode of the sixth transistor T6 can be connected to the light emission control line EML, the first electrode of the sixth transistor T6 can be connected to the second pixel node PN2, and the second electrode of the sixth transistor T6 can be connected to the fourth pixel node PN4. The first electrode of the sixth transistor T6 can be electrically connected to the second electrode of the first transistor T1 and the first electrode of the third transistor T3 through the second pixel node PN2. The second electrode of the sixth transistor T6 can be electrically connected to the first electrode of the light emission element ED and the first electrode of the seventh transistor T7 through the fourth pixel node PN4. For example, the first electrode of the sixth transistor T6 can be the source electrode, and the second electrode of the sixth transistor T6 can be the drain electrode, but it is not limited to these.

[0089] When the fifth transistor T5, the first transistor T1, and the sixth transistor T6 are all turned on, the drive current Isd can be supplied to the light-emitting element ED.

[0090] The seventh transistor T7 can be turned on via the fourth gate signal of the fourth gate line GBL, and can be electrically connected to the second initialization voltage line VIL2 and the fourth pixel node PN4, which serves as the first electrode of the light-emitting element ED. The seventh transistor T7 can be turned on based on the fourth gate signal, thereby initializing the voltage of the first electrode of the light-emitting element ED to the second initialization voltage. Here, the second initialization voltage of the second initialization voltage line VIL2 may be different from the first initialization voltage of the first initialization voltage line VIL1. In an embodiment, the second initialization voltage may be the same as the first initialization voltage. The gate electrode of the seventh transistor T7 can be connected to the fourth gate line GBL, the first electrode of the seventh transistor T7 can be connected to the fourth pixel node PN4, and the second electrode of the seventh transistor T7 can be connected to the second initialization voltage line VIL2. The first electrode of the seventh transistor T7 can be electrically connected to the first electrode of the light-emitting element ED and the second electrode of the sixth transistor T6 via the fourth pixel node PN4. For example, the first electrode of the seventh transistor T7 may be the source electrode, and the second electrode of the seventh transistor T7 may be the drain electrode, but is not limited thereto.

[0091] The eighth transistor T8 can be turned on via the fourth gate signal of the fourth gate line GBL, and is electrically connected to the bias voltage line VBL and the first pixel node PN1, which serves as the first electrode of the first transistor T1. The gate electrode of the eighth transistor T8 can be connected to the fourth gate line GBL, the first electrode of the eighth transistor T8 can be connected to the bias voltage line VBL, and the second electrode of the eighth transistor T8 can be connected to the first pixel node PN1. The second electrode of the eighth transistor T8 can be electrically connected via the first pixel node PN1 to the first electrode of the first transistor T1, the second electrode of the second transistor T2, and the second electrode of the fifth transistor T5. For example, the first electrode of the eighth transistor T8 can be the source electrode, and the second electrode of the eighth transistor T8 can be the drain electrode, but is not limited thereto. In some embodiments, the eighth transistor T8 may be omitted.

[0092] The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may comprise silicon-based semiconductor regions. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may comprise semiconductor regions made of low-temperature polycrystalline silicon (LTPS). Semiconductor regions made of LTPS can have high electron mobility and excellent conduction characteristics. Therefore, in an embodiment, the display device 10 includes the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8, which have excellent conduction characteristics, thereby stably and efficiently driving a plurality of pixels SP.

[0093] The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be p-type transistors. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can each output the current flowing into their first electrode to their second electrode based on a low gate voltage applied to their gate electrode.

[0094] The third transistor T3 and the fourth transistor T4 may include oxide-based semiconductor regions. For example, the third transistor T3 and the fourth transistor T4 may have a coplanar structure in which the gate electrode is disposed above the oxide-based semiconductor region. Transistors with a coplanar structure can have excellent leakage current characteristics and can be driven at low frequencies, thereby reducing power consumption. Therefore, in an embodiment, the display device 10 includes a third transistor T3 and a fourth transistor T4 with excellent leakage current characteristics, thereby preventing leakage current from flowing inside the pixel SP and stably maintaining the voltage inside the pixel SP.

[0095] The third transistor T3 and the fourth transistor T4 can be n-type transistors. For example, the third transistor T3 and the fourth transistor T4 can each output the current flowing into their first electrode to their second electrode based on a high gate voltage applied to their gate electrode.

[0096] Capacitor C1 can be connected between the third pixel node PN3, which serves as the gate electrode of the first transistor T1, and the driving voltage line VDL. For example, the first capacitor electrode of capacitor C1 can be connected to the third pixel node PN3, and the second capacitor electrode of capacitor C1 can be connected to the driving voltage line VDL, thereby maintaining the potential difference between the driving voltage line VDL and the gate electrode of the first transistor T1.

[0097] Figure 4 This is a block diagram illustrating a scan driver of a display device according to an embodiment.

[0098] refer to Figure 4 The first clock line CKL1, the second clock line CKL2, the third clock line CKL3, and the fourth clock line CKL4 can supply the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 to multiple STG stages, respectively. The gate high voltage line VGHL can supply the gate high voltage VGH to the STG stage, and the gate low voltage line VGLL can supply the gate low voltage VGL to the STG stage.

[0099] Gate driver 810 may include multiple unit-level USGs. Since multiple stage STGs within a unit-level USG share some transistors, the number of transistors in gate driver 810 is reduced, thereby reducing the area of ​​the non-display area (NDA) and reducing power consumption. In an embodiment, the stage STG can generate and supply scan write signals to... Figure 3 The first gate line GWL or scan write line. In an implementation, the STG stage can supply the scan signal to... Figure 3 The second gate line GCL, the third gate line GIL, and the fourth gate line GBL.

[0100] For example, in one implementation, the gate driver 810 may include multiple cell-level USGs. By sharing certain transistors among the multiple stage STGs within each cell-level USG, the number of transistors within the gate driver 810 is reduced, which reduces the space required in the non-display area NDA and lowers power consumption. The stage STGs are configured to generate transistors capable of supplying power to areas such as... Figure 3 The scan write signal is shown as either the first gate line GWL or the scan write line. Additionally, the STG stage can provide the scan signal to... Figure 3 The diagram shows the second gate line GCL, the third gate line GIL, and the fourth gate line GBL.

[0101] A unit-level USG may include a first unit-level USG1 and a second unit-level USG2.

[0102] The first unit level USG1 may include a first level STG1, a second level STG2, and a third level STG3, but the number of levels STG in the unit level USG is not limited to this.

[0103] The first stage STG1 can be connected to the start line STL and can receive the start signal FLM. The first stage STG1 can receive the first clock signal CK1 and the second clock signal CK2, the gate high voltage VGH and the gate low voltage VGL, and supply the first scan write signal GW1 to the first scan write line GWL1.

[0104] The second stage STG2 can receive the third clock signal CK3, the gate high voltage VGH and the gate low voltage VGL, and supply the second scan write signal GW2 to the second scan write line GWL2.

[0105] The third stage STG3 can receive the fourth clock signal CK4, the gate high voltage VGH and the gate low voltage VGL, and supply the third scan write signal GW3 to the third scan write line GWL3.

[0106] The second unit level USG2 may include the fourth level STG4, the fifth level STG5, and the sixth level STG6.

[0107] The fourth stage STG4 can receive the third scan write signal GW3 from the third stage STG3 as a carry signal. The fourth stage STG4 can receive the first clock signal CK1 and the fourth clock signal CK4, the gate high voltage VGH and the gate low voltage VGL, and supply the fourth scan write signal GW4 to the fourth scan write line GWL4.

[0108] The fifth stage STG5 can receive the second clock signal CK2, the gate high voltage VGH and the gate low voltage VGL, and supply the fifth scan write signal GW5 to the fifth scan write line GWL5.

[0109] The sixth stage STG6 can receive the third clock signal CK3, the gate high voltage VGH and the gate low voltage VGL, and supply the sixth scan write signal GW6 to the sixth scan write line GWL6.

[0110] Figure 5 This is a circuit diagram of the first unit level of the scan driver in a display device according to an embodiment.

[0111] refer to Figure 5 The first unit level USG1 may include the first level STG1, the second level STG2, and the third level STG3.

[0112] The first-level STG1, second-level STG2, and third-level STG3 can share a shared unit SHR (also called a shared circuit) and can each include a buffer unit BUF (also called a buffer circuit). Therefore, a unit-level USG can include one shared unit SHR and multiple buffer units BUF. The shared unit SHR is a buffer control unit that controls the output signal of the buffer units BUF. Each unit-level USG can also be called a unit-level circuit.

[0113] The shared unit SHR may include a first transistor T1, a second transistor T2, and a third transistor T3.

[0114] The first transistor T1 can supply the start signal FLM to the first node N1 based on the first clock signal CK1. The buffer unit BUF of each of the first stage STG1, the second stage STG2, and the third stage STG3 can be directly connected to the first node N1. The first transistor T1 may include a first sub-transistor T1-1 and a second sub-transistor T1-2 connected in series between the input terminal of the start signal FLM and the first node N1.

[0115] The second transistor T2 can supply the first clock signal CK1 to the second node N2 based on the voltage of the first node N1. The buffer unit BUF of each of the first stage STG1, the second stage STG2, and the third stage STG3 can be directly connected to the second node N2.

[0116] The third transistor T3 can supply a low gate voltage VGL to the second node N2 based on the first clock signal CK1.

[0117] The buffer unit BUF of each of the first-level STG1, second-level STG2, and third-level STG3 may include a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, as well as a first capacitor C1 and a second capacitor C2. The buffer unit BUF of each of the first-level STG1, second-level STG2, and third-level STG3 may output a first scan write signal GW1, a second scan write signal GW2, and a third scan write signal GW3 through an output node, respectively.

[0118] The fourth transistor T4 can supply a gate high voltage VGH to the output node based on the voltage of the second node N2.

[0119] The fifth transistor T5 of the first-stage STG1 can supply the second clock signal CK2 to the output node based on the voltage of the second electrode of the sixth transistor T6. The fifth transistor T5 of the second-stage STG2 can supply the third clock signal CK3 to the output node based on the voltage of the second electrode of the sixth transistor T6. The fifth transistor T5 of the third-stage STG3 can supply the fourth clock signal CK4 to the output node based on the voltage of the second electrode of the sixth transistor T6.

[0120] The sixth transistor T6 can supply the voltage of the first node N1 to the gate electrode of the fifth transistor T5 based on the low gate voltage VGL.

[0121] By connecting a first capacitor C1 between the second node N2 and the input terminal of the gate high voltage VGH, a potential difference can be maintained between the second node N2 and the input terminal of the gate high voltage VGH.

[0122] By connecting a second capacitor C2 between the output terminal and the gate electrode of the fifth transistor T5, a potential difference can be maintained between the output terminal and the gate electrode of the fifth transistor T5.

[0123] Therefore, according to embodiments of this disclosure, since a cell-level USG includes a shared cell SHR and multiple buffer cells BUF, the number of transistors in the gate driver 810 is reduced. This reduces the area and power consumption of the non-display area NDA.

[0124] Figure 6 This is a layout diagram of the first unit level of the scan driver in a display device according to an embodiment. Figure 7 The illustration is based on the implementation method. Figure 6 The layout diagram of the metal layer, active layer and first gate layer of the first unit level in the display device. Figure 8 The illustration is based on the implementation method. Figure 6 The layout diagram of the metal layer, active layer, first gate layer, second gate layer and third gate layer of the first unit level in the display device. Figure 9 The illustration is based on the implementation method. Figure 6 The layout diagram of the first source metal layer and the second source metal layer of the first unit level in the display device. Figure 10 The illustration is based on the implementation method. Figure 6 A cross-sectional view of a portion of the first unit level in a display device. Figure 11 The illustration is based on the implementation method. Figure 6 A cross-sectional view of another part of the first unit level in the display device.

[0125] refer to Figures 6 to 11 The first unit level USG1 may include a first level STG1, a second level STG2, and a third level STG3. The first level STG1, the second level STG2, and the third level STG3 may be connected to the first clock line CKL1, the second clock line CKL2, the third clock line CKL3, the fourth clock line CKL4, the gate high voltage line VGHL, and the gate low voltage line VGLL.

[0126] The gate low voltage line VGLL can be disposed on the second source metal layer SDL2 and extend in the Y-axis direction. The first clock line CKL1 can be disposed to the right of the gate low voltage line VGLL in the second source metal layer SDL2 and extend in the Y-axis direction. The second clock line CKL2 can be disposed to the right of the first clock line CKL1 in the second source metal layer SDL2 and extend in the Y-axis direction. The third clock line CKL3 can be disposed to the right of the second clock line CKL2 in the second source metal layer SDL2 and extend in the Y-axis direction. The fourth clock line CKL4 can be disposed to the right of the third clock line CKL3 in the second source metal layer SDL2 and extend in the Y-axis direction. The gate high voltage line VGHL can be disposed to the right of the fourth clock line CKL4 in the second source metal layer SDL2 and extend in the Y-axis direction.

[0127] Multiple first node electrodes NDE1, as well as first connecting electrodes CNE1, second connecting electrodes CNE2, and third connecting electrodes CNE3, can be arranged between the second clock line CKL2 and the third clock line CKL3. These multiple first node electrodes NDE1, first connecting electrodes CNE1, second connecting electrodes CNE2, and third connecting electrodes CNE3 can be arranged in the Y-axis direction and electrically connected to each other. Here, the first node electrode NDE1 can be connected to... Figure 5 The first node N1 corresponds to this. Therefore, in this embodiment, the plurality of first node electrodes NDE1, as well as the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3, do not overlap with the second source metal layer SDL2. Thus, the interconnection between the first node N1 and the second source metal layer SDL2 can be reduced.

[0128] The first-level STG1, second-level STG2, and third-level STG3 can share a shared unit SHR, and each can include a buffer unit BUF. The shared unit SHR can include a first transistor T1, a second transistor T2, and a third transistor T3. Each of the first transistor T1, the second transistor T2, and the third transistor T3 can be arranged in one region of the first-level STG1, the second-level STG2, and the third-level STG3. Figures 6 to 8In this embodiment, the first transistor T1 may be arranged in the first stage STG1, the second transistor T2 may be arranged in the third stage STG3, and the third transistor T3 may be arranged in the second stage STG2, but the positions of the first transistor T1, the second transistor T2, and the third transistor T3 are not limited thereto. For example, in one embodiment, the first transistor T1 may be arranged in one of the first stage STG1, the second stage STG2, and the third stage STG3, the second transistor T2 may be arranged in another of the first stage STG1, the second stage STG2, and the third stage STG3, and the third transistor T3 may be arranged in yet another of the first stage STG1, the second stage STG2, and the third stage STG3.

[0129] The first transistor T1 may include a first sub-transistor T1-1 and a second sub-transistor T1-2 connected in series. Each of the first sub-transistor T1-1 and the second sub-transistor T1-2 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of each of the first sub-transistor T1-1 and the second sub-transistor T1-2 may be disposed in an active layer ACTL, and the gate electrode of each of the first sub-transistor T1-1 and the second sub-transistor T1-2 may be disposed in a first gate layer GTL1. The gate electrode of each of the first sub-transistor T1-1 and the second sub-transistor T1-2 may overlap with the semiconductor region. A first metal layer BML1 may be disposed in the metal layer BML and overlap with the semiconductor region of the first sub-transistor T1-1 and the semiconductor region of the second sub-transistor T1-2. The first metal layer BML1 may be electrically connected to the gate electrode of the first sub-transistor T1-1 and the gate electrode of the second sub-transistor T1-2.

[0130] The gate electrode of the first sub-transistor T1-1 and the gate electrode of the second sub-transistor T1-2 can be integrally formed and electrically connected to the first clock line CKL1. The first electrode of the first sub-transistor T1-1 can be electrically connected to the start line STL through the fifth connection electrode CNE5 of the first source metal layer SDL1. The second electrode of the first sub-transistor T1-1 and the first electrode of the second sub-transistor T1-2 can be integrally formed. The second electrode of the second sub-transistor T1-2 can be electrically connected to the first node electrode NDE1 of the second gate layer GTL2 through the first connection electrode CNE1 of the first source metal layer SDL1.

[0131] The second transistor T2 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the second transistor T2 may be arranged in the active layer ACTL, and the gate electrode of the second transistor T2 may be arranged in the first gate layer GTL1. The gate electrode of the second transistor T2 may overlap with the semiconductor region.

[0132] The first electrode of the second transistor T2 can be electrically connected to the first clock line CKL1 via the thirteenth connection electrode CNE13 of the first source metal layer SDL1. The second electrode of the second transistor T2 can be electrically connected to the second node electrode NDE2 of the second gate layer GTL2 via the fourteenth connection electrode CNE14 of the first source metal layer SDL1. Here, the second node electrode NDE2 can be connected to... Figure 5 This corresponds to the second node N2 in the first stage STG1. The second node electrode NDE2 can be electrically connected to the gate electrode of the fourth transistor T4 of the first stage STG1 through the sixth connection electrode CNE6 of the first source metal layer SDL1. The second node electrode NDE2 can be electrically connected to the gate electrode of the fourth transistor T4 of the second stage STG2 through the tenth connection electrode CNE10 of the first source metal layer SDL1. The second node electrode NDE2 can be electrically connected to the gate electrode of the fourth transistor T4 of the third stage STG3 through the fourteenth connection electrode CNE14.

[0133] The third transistor T3 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the third transistor T3 may be arranged in the active layer ACTL, and the gate electrode of the third transistor T3 may be arranged in the first gate layer GTL1. The gate electrode of the third transistor T3 may overlap with the semiconductor region.

[0134] The gate electrode of the third transistor T3 can be electrically connected to the first clock line CKL1 via the ninth connection electrode CNE9 of the first source metal layer SDL1. The first electrode of the third transistor T3 can be electrically connected to the gate low voltage line VGLL via the fourth connection electrode CNE4 of the first source metal layer SDL1. The second electrode of the third transistor T3 can be electrically connected to the second node electrode NDE2 of the second gate layer GTL2 via the tenth connection electrode CNE10.

[0135] The buffer unit BUF of the first-stage STG1 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2.

[0136] The fourth transistor T4 of the first stage STG1 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the fourth transistor T4 may be disposed in the active layer ACTL, and the gate electrode of the fourth transistor T4 may be disposed in the first gate layer GTL1. The gate electrode of the fourth transistor T4 may overlap with the semiconductor region. A third metal layer BML3 may be disposed in the metal layer BML and overlap with the semiconductor region of the fourth transistor T4. The third metal layer BML3 may be electrically connected to the gate electrode of the fourth transistor T4 via a sixth connection electrode CNE6.

[0137] The gate electrode of the fourth transistor T4 can be electrically connected to the second node electrode NDE2 via the sixth connection electrode CNE6. The first electrode of the fourth transistor T4 can be electrically connected to the gate high voltage line VGHL via the sixteenth connection electrode CNE16 of the first source metal layer SDL1. The second electrode of the fourth transistor T4 can be integrally formed with the second electrode of the fifth transistor T5. The second electrode of the fourth transistor T4 can be electrically connected to the first gate connection electrode GNE1 of the third gate layer GTL3 via the seventeenth connection electrode CNE17 of the first source metal layer SDL1. Here, the first gate connection electrode GNE1 can be... Figure 5 The output node of the first stage STG1 corresponds to the first scan write signal GW1, and the first scan write signal GW1 can be supplied to the first scan write line GWL1.

[0138] The fifth transistor T5 of the first stage STG1 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the fifth transistor T5 may be disposed in the active layer ACTL, and the gate electrode of the fifth transistor T5 may be disposed in the first gate layer GTL1. The gate electrode of the fifth transistor T5 may overlap with the semiconductor region. A fourth metal layer BML4 may be disposed in the metal layer BML and overlap with the semiconductor region of the fifth transistor T5. The fourth metal layer BML4 may be electrically connected to the gate electrode of the fifth transistor T5 via a seventh connection electrode CNE7.

[0139] The gate electrode of the fifth transistor T5 can be electrically connected to the second electrode of the sixth transistor T6 via the seventh connection electrode CNE7. The first electrode of the fifth transistor T5 can be electrically connected to the second clock line CKL2 via the eighth connection electrode CNE8 of the first source metal layer SDL1. The second electrode of the fifth transistor T5 can be integrally formed with the second electrode of the fourth transistor T4. The second electrode of the fifth transistor T5 can be electrically connected to the first gate connection electrode GNE1 via the seventeenth connection electrode CNE17.

[0140] The sixth transistor T6 of the first stage STG1 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the sixth transistor T6 may be disposed in the active layer ACTL, and the gate electrode of the sixth transistor T6 may be disposed in the first gate layer GTL1. The gate electrode of the sixth transistor T6 may overlap with the semiconductor region. The second metal layer BML2 may be disposed in the metal layer BML and overlap with the semiconductor region of the sixth transistor T6. The second metal layer BML2 may be electrically connected to the gate electrode of the sixth transistor T6 through the fourth connection electrode CNE4 of the first source metal layer SDL1.

[0141] The gate electrode of the sixth transistor T6 can be electrically connected to the gate low voltage line VGLL via the fourth connection electrode CNE4. The first electrode of the sixth transistor T6 can be electrically connected to the first node electrode NDE1 via the first connection electrode CNE1. The second electrode of the sixth transistor T6 can be electrically connected to the gate electrode of the fifth transistor T5 via the seventh connection electrode CNE7.

[0142] The first capacitor C1 of the first stage STG1 can be connected between the second node N2 and the input terminal of the gate high voltage VGH. The first electrode of the first capacitor C1 may include the gate electrode of the fourth transistor T4, and the second electrode of the first capacitor C1 can be arranged in the second gate layer GTL2. The second electrode of the first capacitor C1 can be electrically connected to the gate high voltage line VGHL through the sixteenth connection electrode CNE16.

[0143] The second capacitor C2 of the first stage STG1 can be connected between the output terminal and the gate electrode of the fifth transistor T5. The first electrode of the second capacitor C2 may include the gate electrode of the fifth transistor T5, and the second electrode of the second capacitor C2 may be arranged in the second gate layer GTL2. The second electrode of the second capacitor C2 can be electrically connected to the first gate connection electrode GNE1 through the seventeenth connection electrode CNE17.

[0144] The buffer unit BUF of the second-stage STG2 may include a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6, as well as a first capacitor C1 and a second capacitor C2.

[0145] The fourth transistor T4 of the second-stage STG2 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the fourth transistor T4 may be disposed in the active layer ACTL, and the gate electrode of the fourth transistor T4 may be disposed in the first gate layer GTL1. The gate electrode of the fourth transistor T4 may overlap with the semiconductor region. A third metal layer BML3 may be disposed in the metal layer BML and overlap with the semiconductor region of the fourth transistor T4. The third metal layer BML3 may be electrically connected to the gate electrode of the fourth transistor T4 via a tenth connection electrode CNE10.

[0146] The gate electrode of the fourth transistor T4 can be electrically connected to the second node electrode NDE2 via the tenth connection electrode CNE10. The first electrode of the fourth transistor T4 can be electrically connected to the gate high voltage line VGHL via the sixteenth connection electrode CNE16. The second electrode of the fourth transistor T4 can be integrally formed with the second electrode of the fifth transistor T5. The second electrode of the fourth transistor T4 can be electrically connected to the second gate connection electrode GNE2 of the third gate layer GTL3 via the eighteenth connection electrode CNE18 of the first source metal layer SDL1. Here, the second gate connection electrode GNE2 can be connected to... Figure 5The output node of the second stage STG2 corresponds to that of the second stage STG2, and the second scan write signal GW2 can be supplied to the second scan write line GWL2.

[0147] The fifth transistor T5 of the second-stage STG2 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the fifth transistor T5 may be disposed in the active layer ACTL, and the gate electrode of the fifth transistor T5 may be disposed in the first gate layer GTL1. The gate electrode of the fifth transistor T5 may overlap with the semiconductor region. A fourth metal layer BML4 may be disposed in the metal layer BML and overlap with the semiconductor region of the fifth transistor T5. The fourth metal layer BML4 may be electrically connected to the gate electrode of the fifth transistor T5 via the eleventh connection electrode CNE11.

[0148] The gate electrode of the fifth transistor T5 can be electrically connected to the second electrode of the sixth transistor T6 via the eleventh connection electrode CNE11. The first electrode of the fifth transistor T5 can be electrically connected to the third clock line CKL3 via the twelfth connection electrode CNE12 of the first source metal layer SDL1. The second electrode of the fifth transistor T5 can be integrally formed with the second electrode of the fourth transistor T4. The second electrode of the fifth transistor T5 can be electrically connected to the second gate connection electrode GNE2 via the eighteenth connection electrode CNE18.

[0149] The sixth transistor T6 of the second stage STG2 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the sixth transistor T6 may be disposed in the active layer ACTL, and the gate electrode of the sixth transistor T6 may be disposed in the first gate layer GTL1. The gate electrode of the sixth transistor T6 may overlap with the semiconductor region. A second metal layer BML2 may be disposed in the metal layer BML and overlap with the semiconductor region of the sixth transistor T6. The second metal layer BML2 may be electrically connected to the gate electrode of the sixth transistor T6 via a fourth connection electrode CNE4.

[0150] The gate electrode of the sixth transistor T6 can be electrically connected to the gate low voltage line VGLL via the fourth connection electrode CNE4. The first electrode of the sixth transistor T6 can be electrically connected to the first node electrode NDE1 via the second connection electrode CNE2. The second electrode of the sixth transistor T6 can be electrically connected to the gate electrode of the fifth transistor T5 via the eleventh connection electrode CNE11.

[0151] The first capacitor C1 of the second stage STG2 can be connected between the second node N2 and the input terminal of the gate high voltage VGH. The first electrode of the first capacitor C1 may include the gate electrode of the fourth transistor T4, and the second electrode of the first capacitor C1 may be arranged in the second gate layer GTL2. The second electrode of the first capacitor C1 can be electrically connected to the gate high voltage line VGHL through the sixteenth connection electrode CNE16.

[0152] The second capacitor C2 of the second stage STG2 can be connected between the output terminal and the gate electrode of the fifth transistor T5. The first electrode of the second capacitor C2 may include the gate electrode of the fifth transistor T5, and the second electrode of the second capacitor C2 may be arranged in the second gate layer GTL2. The second electrode of the second capacitor C2 can be electrically connected to the second gate connection electrode GNE2 through the eighteenth connection electrode CNE18.

[0153] The buffer unit BUF of the third-level STG3 may include a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6, as well as a first capacitor C1 and a second capacitor C2.

[0154] The fourth transistor T4 of the third stage STG3 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the fourth transistor T4 may be disposed in the active layer ACTL, and the gate electrode of the fourth transistor T4 may be disposed in the first gate layer GTL1. The gate electrode of the fourth transistor T4 may overlap with the semiconductor region. The third metal layer BML3 may be disposed in the metal layer BML and overlap with the semiconductor region of the fourth transistor T4. The third metal layer BML3 may be electrically connected to the gate electrode of the fourth transistor T4 via the fourteenth connection electrode CNE14.

[0155] The gate electrode of the fourth transistor T4 can be electrically connected to the second node electrode NDE2 via the fourteenth connection electrode CNE14. The first electrode of the fourth transistor T4 can be electrically connected to the gate high voltage line VGHL via the sixteenth connection electrode CNE16. The second electrode of the fourth transistor T4 can be integrally formed with the second electrode of the fifth transistor T5. The second electrode of the fourth transistor T4 can be electrically connected to the third gate connection electrode GNE3 of the third gate layer GTL3 via the nineteenth connection electrode CNE19 of the first source metal layer SDL1. Here, the third gate connection electrode GNE3 can be connected to... Figure 5 The output node of the third stage STG3 corresponds to that of the third stage STG3, and the third scan write signal GW3 can be supplied to the third scan write line GWL3.

[0156] The fifth transistor T5 of the third-stage STG3 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the fifth transistor T5 may be disposed in the active layer ACTL, and the gate electrode of the fifth transistor T5 may be disposed in the first gate layer GTL1. The gate electrode of the fifth transistor T5 may overlap with the semiconductor region. A fourth metal layer BML4 may be disposed in the metal layer BML and overlap with the semiconductor region of the fifth transistor T5. The fourth metal layer BML4 may be electrically connected to the gate electrode of the fifth transistor T5 through the twentieth connection electrode CNE20 of the first source metal layer SDL1.

[0157] The gate electrode of the fifth transistor T5 can be electrically connected to the second electrode of the sixth transistor T6 via the twentieth connection electrode CNE20. The first electrode of the fifth transistor T5 can be electrically connected to the fourth clock line CKL4 via the fifteenth connection electrode CNE15 of the first source metal layer SDL1. The second electrode of the fifth transistor T5 can be integrally formed with the second electrode of the fourth transistor T4. The second electrode of the fifth transistor T5 can be electrically connected to the third gate connection electrode GNE3 via the nineteenth connection electrode CNE19.

[0158] The sixth transistor T6 of the third stage STG3 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the sixth transistor T6 may be disposed in the active layer ACTL, and the gate electrode of the sixth transistor T6 may be disposed in the first gate layer GTL1. The gate electrode of the sixth transistor T6 may overlap with the semiconductor region. A second metal layer BML2 may be disposed in the metal layer BML and overlap with the semiconductor region of the sixth transistor T6. The second metal layer BML2 may be electrically connected to the gate electrode of the sixth transistor T6 via a fourth connection electrode CNE4.

[0159] The gate electrode of the sixth transistor T6 is electrically connected to the gate low voltage line VGLL via the fourth connection electrode CNE4. The first electrode of the sixth transistor T6 is electrically connected to the first node electrode NDE1 via the third connection electrode CNE3. The second electrode of the sixth transistor T6 is electrically connected to the gate electrode of the fifth transistor T5 via the twentieth connection electrode CNE20.

[0160] The first capacitor C1 of the third stage STG3 can be connected between the second node N2 and the input terminal of the gate high voltage VGH. The first electrode of the first capacitor C1 may include the gate electrode of the fourth transistor T4, and the second electrode of the first capacitor C1 may be arranged in the second gate layer GTL2. The second electrode of the first capacitor C1 can be electrically connected to the gate high voltage line VGHL through the sixteenth connection electrode CNE16.

[0161] The second capacitor C2 of the third stage STG3 can be connected between the output terminal and the gate electrode of the fifth transistor T5. The first electrode of the second capacitor C2 may include the gate electrode of the fifth transistor T5, and the second electrode of the second capacitor C2 may be arranged in the second gate layer GTL2. The second electrode of the second capacitor C2 can be electrically connected to the third gate connection electrode GNE3 through the nineteenth connection electrode CNE19.

[0162] The first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6 of the first unit stage USG1 may comprise silicon-based semiconductor regions. For example, the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6 may comprise semiconductor regions made of low-temperature polycrystalline silicon (LTPS). Semiconductor regions made of low-temperature polycrystalline silicon can have high electron mobility and excellent conduction characteristics. Therefore, in an embodiment, the display device 10 includes first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6 with excellent conduction characteristics, thereby stably and efficiently driving the scan driver 800.

[0163] In this implementation, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be p-type transistors. For example, a p-type transistor may output current flowing into the first electrode to the second electrode based on a low gate voltage applied to the gate electrode.

[0164] In an embodiment, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may include an oxide-based semiconductor region. For example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may have a coplanar structure in which the gate electrode is disposed above the oxide-based semiconductor region. Transistors with a coplanar structure may have excellent leakage current characteristics and can be driven at low frequencies, thereby reducing power consumption. Therefore, in an embodiment, the display device 10 includes transistors with excellent leakage current characteristics, which prevents leakage current from flowing inside the scan driver 800 and stably maintains the voltage inside the scan driver 800.

[0165] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be an n-type transistor. For example, an n-type transistor can output current flowing into the first electrode to the second electrode based on a high gate voltage applied to the gate electrode.

[0166] exist Figure 10 In the display panel 100, a substrate SUB, a metal layer BML, a buffer layer BF, an active layer ACTL, a first gate insulating layer GI1, a first gate layer GTL1, a second gate insulating layer GI2, a second gate layer GTL2, a first interlayer insulating layer ILD1, a third gate layer GTL3, a second interlayer insulating layer ILD2, a first source metal layer SDL1, a first via layer VIA1, and a second source metal layer SDL2 may be included.

[0167] The substrate SUB can be a base substrate or a base component. The substrate SUB can be a flexible substrate that is bendable, foldable, rollable, etc. For example, in an embodiment, the substrate SUB may include a polymer resin, such as polyimide (PI), but is not limited thereto. In an embodiment, the substrate SUB may include a glass material or a metal material.

[0168] The metal layer BML can be disposed on the substrate SUB. The metal layer BML may include a third metal layer BML3 and a fourth metal layer BML4. The third metal layer BML3 may overlap with the semiconductor region ACT4 of the fourth transistor T4, and the fourth metal layer BML4 may overlap with the semiconductor region ACT5 of the fifth transistor T5.

[0169] The buffer layer BF may be disposed on the metal layer BML. For example, the buffer layer BF may include an inorganic membrane capable of preventing the penetration of air or moisture. For example, the buffer layer BF may include multiple inorganic membranes stacked alternately.

[0170] The active layer ACTL can be disposed on the buffer layer BF. The active layer ACTL can include a silicon-based material. For example, the active layer ACTL can be made of low-temperature polycrystalline silicon (LTPS). The active layer ACTL can include the semiconductor region ACT4 of the fourth transistor T4, the first electrode SE4 and the second electrode DE4, and the semiconductor region ACT5 of the fifth transistor T5, the first electrode SE5 and the second electrode DE5.

[0171] The first gate insulating layer GI1 can be disposed on the active layer ACTL. The first gate insulating layer GI1 can insulate the active layer ACTL and the first gate layer GTL1 from each other.

[0172] A first gate layer GTL1 may be disposed on a first gate insulating layer GI1. The first gate layer GTL1 may include a first electrode C1a of a first capacitor C1 and a first electrode C2a of a second capacitor C2. The first electrode C1a of the first capacitor C1 may include the gate electrode GE4 of a fourth transistor T4, and the first electrode C2a of the second capacitor C2 may include the gate electrode GE5 of a fifth transistor T5.

[0173] The second gate insulating layer GI2 can be disposed on the first gate layer GTL1. The second gate insulating layer GI2 can insulate the first gate layer GTL1 and the second gate layer GTL2 from each other.

[0174] The second gate layer GTL2 may be disposed on the second gate insulating layer GI2. The second gate layer GTL2 may include the second electrode C1b of the first capacitor C1 and the second electrode C2b of the second capacitor C2. The second electrode C1b of the first capacitor C1 may overlap with the first electrode C1a, and the second electrode C2b of the second capacitor C2 may overlap with the first electrode C2a.

[0175] The first interlayer insulating layer ILD1 can be disposed on the second gate layer GTL2. The first interlayer insulating layer ILD1 can insulate the second gate layer GTL2 and the third gate layer GTL3 from each other.

[0176] The third gate layer GTL3 may be disposed on the first interlayer insulating layer ILD1. The third gate layer GTL3 may include a first gate connection electrode GNE1. The first gate connection electrode GNE1 may be connected to... Figure 5 The output node of the first stage STG1 corresponds to the first scan write signal GW1, and the first scan write signal GW1 can be supplied to the first scan write line GWL1.

[0177] The second interlayer insulating layer ILD2 can be disposed on the third gate layer GTL3. The second interlayer insulating layer ILD2 can insulate the third gate layer GTL3 and the first source metal layer SDL1 from each other.

[0178] The first source metal layer SDL1 may be disposed on the second interlayer insulating layer ILD2. The first source metal layer SDL1 may include an eighth connection electrode CNE8, a sixteenth connection electrode CNE16, and a seventeenth connection electrode CNE17. The eighth connection electrode CNE8 may be electrically connected to the second clock line CKL2 and the first electrode SE5 of the fifth transistor T5. The sixteenth connection electrode CNE16 may be electrically connected to the gate high voltage line VGHL and the first electrode SE4 of the fourth transistor T4. The seventeenth connection electrode CNE17 may be electrically connected to the second electrode DE4 of the fourth transistor T4, the second electrode DE5 of the fifth transistor T5, the second electrode C2b of the second capacitor C2, and the first gate connection electrode GNE1.

[0179] The first via layer VIA1 can be disposed on the first source metal layer SDL1. The first via layer VIA1 can insulate the first source metal layer SDL1 and the second source metal layer SDL2 from each other.

[0180] The second source metal layer SDL2 may be disposed on the first via layer VIA1. The second source metal layer SDL2 may include the gate high voltage line VGHL and the second clock line CKL2.

[0181] exist Figure 11 In the first connection electrode CNE1, the first electrode SE6 of the sixth transistor T6 of the first stage STG1 and the first node electrode NDE1 can be electrically connected.

[0182] The second connection electrode CNE2 can be electrically connected to the first electrode SE6 of the sixth transistor T6 of the second stage STG2, which is separated from each other in the Y-axis direction by the first node electrode NDE1 and the second stage STG2.

[0183] The third connection electrode CNE3 can be electrically connected to the first electrode SE6 and the first node electrode NDE1 of the sixth transistor T6 of the third stage STG3.

[0184] refer to Figure 3 , Figure 8 , Figure 9 and Figure 11 The second gate line GCL may include a first portion GCL1, a second portion GCL2, and a third portion GCL3. The first portion GCL1 of the second gate line GCL may be disposed in the third gate layer GTL3 and extend in the X-axis direction. The first portion GCL1 of the second gate line GCL may intersect with the first node electrode NDE1, which overlaps with the first stage STG1 and the second stage STG2.

[0185] The second portion GCL2 of the second gate line GCL can be disposed in the third gate layer GTL3 and spaced apart from the first portion GCL1. The second portion GCL2 of the second gate line GCL can be branched into multiple branches.

[0186] The third part GCL3 of the second gate line GCL can be arranged in the first source metal layer SDL1 and electrically connected to the first part GCL1 and the second part GCL2.

[0187] The light-emitting control line EML may include a first portion EML1, a second portion EML2, and a third portion EML3. The first portion EML1 of the light-emitting control line EML may be disposed in the third gate layer GTL3 and extend in the X-axis direction. The first portion EML1 of the light-emitting control line EML may intersect with the first node electrode NDE1, which overlaps with the first stage STG1 and the second stage STG2.

[0188] The second part of the light-emitting control line EML, EML2, can be arranged in the first gate layer GTL1, extending in the X-axis direction and spaced apart from the first part EML1.

[0189] The third part of the light-emitting control line EML, EML3, can be arranged in the first source metal layer SDL1 and electrically connected to the first part EML1 and the second part EML2.

[0190] Figure 12This is a cross-sectional view illustrating a portion of the first unit level in a display device according to an embodiment. Figure 12 The display device 10 has a similar Figure 11 The display device 10 has different configurations of the first node electrode NDE1 and the first portion GCL1 of the second gate line GCL. For ease of explanation, previous references will be briefly described or omitted. Figure 11 Further description of the components and technical aspects described.

[0191] refer to Figure 12 The first portion GCL1 of the second gate line GCL can be disposed in the second gate layer GTL2 and extends in the X-axis direction. The first portion GCL1 of the second gate line GCL can intersect with the first node electrode NDE1.

[0192] The first portion of the light-emitting control line EML, EML1, may be disposed in the third gate layer GTL3 and extend in the X-axis direction. The first portion of the light-emitting control line EML, EML1, may intersect with the first node electrode NDE1.

[0193] The first node electrode NDE1 can be arranged in the second source metal layer SDL2. (Reference) Figure 8 The first node electrode NDE1 can extend in the Y-axis direction. The first node electrode NDE1 can be electrically connected to the first electrode SE6 of the sixth transistor T6 of the first stage STG1 via the first connection electrode CNE1 of the first source metal layer SDL1. The first node electrode NDE1 can be electrically connected to the first electrode SE6 of the sixth transistor T6 of the second stage STG2 via the second connection electrode CNE2 of the first source metal layer SDL1. The first node electrode NDE1 can be electrically connected to the first electrode SE6 of the sixth transistor T6 of the third stage STG3 via the third connection electrode CNE3 of the first source metal layer SDL1.

[0194] The first node electrode NDE1 can be arranged in the second source metal layer SDL2. Therefore, the connections with the second gate line GCL and the light-emitting control line EML can be reduced.

[0195] Figure 13 This is a block diagram illustrating a scan driver of a display device according to an embodiment.

[0196] refer to Figure 13 The first clock line CKL1, the second clock line CKL2, the third clock line CKL3, and the fourth clock line CKL4 can supply the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 to multiple STG stages, respectively. The gate high voltage line VGHL can supply the gate high voltage VGH to the STG stage, and the gate low voltage line VGLL can supply the gate low voltage VGL to the STG stage.

[0197] Gate driver 810 may include multiple cell-level USGs. Since multiple stage STGs within a cell-level USG share some transistors, the number of transistors in gate driver 810 is reduced. Therefore, the area and power consumption of the non-display area NDA can be reduced. In an embodiment, the stage STG can generate a scan write signal and supply the scan write signal to... Figure 3 The first gate line GWL or scan write line. In an implementation, the STG stage can supply the scan signal to... Figure 3 The second gate line GCL, the third gate line GIL, and the fourth gate line GBL.

[0198] For example, in one implementation, the gate driver 810 may be configured to include multiple unit-level USGs. Within each unit-level USG, several STGs may be configured to share specific transistors to effectively reduce the total number of transistors required by the gate driver 810. This reduction in the number of transistors not only saves valuable space within the non-display area NDA but also reduces power consumption, thereby contributing to a more efficient design.

[0199] Each STG within the unit-level USG can generate a scan write signal that can be routed to the first gate line GWL or to the scan write line, such as Figure 3 The diagram in the middle illustrates this. Furthermore, the STG level can also be configured to transmit scan signals to, including... Figure 3 The additional gate lines shown are the second gate line GCL, the third gate line GIL, and the fourth gate line GBL. This signal output capability supports the coordinated operation of various gate lines within the display device 10, which improves its performance and reliability.

[0200] A unit-level USG may include a first unit-level USG1 and a second unit-level USG2.

[0201] The first unit level USG1 may include the first level STG1, the second level STG2, the third level STG3, and the fourth level STG4, but the number of levels STG in the unit level USG is not limited to this.

[0202] The first stage STG1 can be connected to the start line STL and can receive the start signal FLM. The first stage STG1 can receive the first clock signal CK1 and the fourth clock signal CK4, the gate high voltage VGH and the gate low voltage VGL, and supply the first scan write signal GW1 to the first scan write line GWL1.

[0203] The second stage STG2 can receive the second clock signal CK2, the gate high voltage VGH and the gate low voltage VGL, and supply the second scan write signal GW2 to the second scan write line GWL2.

[0204] The third stage STG3 can receive the third clock signal CK3, the gate high voltage VGH and the gate low voltage VGL, and supply the third scan write signal GW3 to the third scan write line GWL3.

[0205] The fourth stage STG4 can receive the fourth clock signal CK4, the gate high voltage VGH and the gate low voltage VGL, and supply the fourth scan write signal GW4 to the fourth scan write line GWL4.

[0206] The second unit level USG2 may include the fifth level STG5, the sixth level STG6, the seventh level STG7, and the eighth level STG8.

[0207] The fifth stage STG5 can receive the fourth scan write signal GW4 from the fourth stage STG4 as a carry signal. The fifth stage STG5 can receive the first clock signal CK1 and the fourth clock signal CK4, the gate high voltage VGH and the gate low voltage VGL, and supply the fifth scan write signal GW5 to the fifth scan write line GWL5.

[0208] The sixth stage STG6 can receive the second clock signal CK2, the gate high voltage VGH and the gate low voltage VGL, and supply the sixth scan write signal GW6 to the sixth scan write line GWL6.

[0209] The seventh stage STG7 can receive the third clock signal CK3, the gate high voltage VGH and the gate low voltage VGL, and supply the seventh scan write signal GW7 to the seventh scan write line GWL7.

[0210] The eighth stage STG8 can receive the fourth clock signal CK4, gate high voltage VGH and gate low voltage VGL, and supply the eighth scan write signal GW8 to the eighth scan write line GWL8.

[0211] In this article, the first scan write signal GW1 to the eighth scan write signal GW8 can also be referred to as the first scan signal to the eighth scan signal, respectively.

[0212] Figure 14 This is a circuit diagram of the first unit level of the scan driver in a display device according to an embodiment.

[0213] refer to Figure 14 The first unit level USG1 may include the first level STG1, the second level STG2, the third level STG3, and the fourth level STG4.

[0214] The first-level STG1, second-level STG2, third-level STG3, and fourth-level STG4 can share a shared unit SHR, and each can include a buffer unit BUF. Therefore, a unit-level USG can include one shared unit SHR and multiple buffer units BUF.

[0215] The shared unit SHR may include a first transistor T1, a second transistor T2, and a third transistor T3.

[0216] The first transistor T1 can supply the start signal FLM to the first node N1 based on the fourth clock signal CK4. The buffer unit BUF of each of the first stage STG1, the second stage STG2, the third stage STG3, and the fourth stage STG4 can be directly connected to the first node N1. The first transistor T1 may include a first sub-transistor T1-1 and a second sub-transistor T1-2 connected in series between the input terminal of the start signal FLM and the first node N1.

[0217] The second transistor T2 can supply the fourth clock signal CK4 to the second node N2 based on the voltage of the first node N1. The buffer unit BUF of each of the first stage STG1, the second stage STG2, the third stage STG3, and the fourth stage STG4 can be directly connected to the second node N2.

[0218] The third transistor T3 can supply the gate low voltage VGL to the second node N2 based on the fourth clock signal CK4.

[0219] The buffer unit BUF of each of the first-level STG1, second-level STG2, third-level STG3, and fourth-level STG4 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2. The buffer unit BUF of each of the first-level STG1, second-level STG2, third-level STG3, and fourth-level STG4 may output a first scan write signal GW1, a second scan write signal GW2, a third scan write signal GW3, and a fourth scan write signal GW4 through an output node.

[0220] The fourth transistor T4 can supply a gate high voltage VGH to the output node based on the voltage of the second node N2.

[0221] The fifth transistor T5 of the first-stage STG1 supplies the first clock signal CK1 to the output node based on the voltage of the second electrode of the sixth transistor T6. The fifth transistor T5 of the second-stage STG2 supplies the second clock signal CK2 to the output node based on the voltage of the second electrode of the sixth transistor T6. The fifth transistor T5 of the third-stage STG3 supplies the third clock signal CK3 to the output node based on the voltage of the second electrode of the sixth transistor T6. The fifth transistor T5 of the fourth-stage STG4 supplies the fourth clock signal CK4 to the output node based on the voltage of the second electrode of the sixth transistor T6.

[0222] The sixth transistor T6 can supply the voltage of the first node N1 to the gate electrode of the fifth transistor T5 based on the low gate voltage VGL.

[0223] A first capacitor C1 can be connected between the second node N2 and the input terminal of the gate high voltage VGH. By connecting the first capacitor C1 between the second node N2 and the input terminal of the gate high voltage VGH, a potential difference can be maintained between the second node N2 and the input terminal of the gate high voltage VGH.

[0224] By connecting a second capacitor C2 between the output terminal and the gate electrode of the fifth transistor T5, a potential difference can be maintained between the output terminal and the gate electrode of the fifth transistor T5.

[0225] Therefore, in this implementation, since a single-cell USG includes a shared cell SHR and multiple buffer cells BUF, the number of transistors in the gate driver 810 is reduced. This reduces the area and power consumption of the non-display area NDA.

[0226] Figure 15 This is a simplified illustration of the first unit level of the scan driver in a display device according to an embodiment.

[0227] refer to Figure 15 The first unit level USG1 may include the first level STG1, the second level STG2, the third level STG3, and the fourth level STG4.

[0228] The first-level STG1, second-level STG2, third-level STG3, and fourth-level STG4 can share a shared unit SHR, and each can include a buffer unit BUF. Therefore, a unit-level USG can include one shared unit SHR, a dummy unit DUM, and multiple buffer units BUF. The shared unit SHR can include a first transistor T1, a second transistor T2, and a third transistor T3. Figure 15In this design, shared cells SHR are divided and arranged in the first-level STG1, second-level STG2, and third-level STG3, meaning that each of the first-level STG1, second-level STG2, and third-level STG3 includes a first transistor T1, a second transistor T2, and a third transistor T3, respectively, and the fourth-level STG4 may include dummy cells DUM in the space where the shared cells SHR are arranged. The first-level STG1 may include one of the first transistor T1, second transistor T2, and third transistor T3, and a buffer cell BUF; the second-level STG2 may include another of the first transistor T1, second transistor T2, and third transistor T3, and a buffer cell BUF; and the third-level STG3 may include yet another of the first transistor T1, second transistor T2, and third transistor T3, and a buffer cell BUF. The fourth-level STG4 may include dummy cells DUM and buffer cells BUF. The dummy cells DUM may be arranged taking into account the pattern density of the areas where the shared cells SHR are not arranged. The dummy cells DUM may be arranged on the same layer as the first transistor T1, second transistor T2, and third transistor T3.

[0229] Therefore, three of the first stage STG1, second stage STG2, third stage STG3, and fourth stage STG4 can respectively include the first transistor T1, the second transistor T2, and the third transistor T3, and the remaining stage can include a dummy cell DUM. Since a single-stage USG includes a shared cell SHR and multiple buffer cells BUF, the number of transistors in the gate driver 810 is reduced. Therefore, the area and power consumption of the non-display area NDA can be reduced.

[0230] For example, in one implementation, the first-level STG1, second-level STG2, third-level STG3, and fourth-level STG4 can be designed to share a single shared cell SHR while each level contains its own buffer cell BUF. This configuration allows each cell level USG to include a shared cell SHR, a dummy cell DUM, and multiple buffer cells BUF, resulting in a more efficient layout and reduced requirements for additional components. The shared cell SHR itself may include a first transistor T1, a second transistor T2, and a third transistor T3 distributed throughout the first-level STG1, second-level STG2, and third-level STG3. For example, each of the first three levels may include one of these transistors and a buffer cell BUF. Conversely, the fourth-level STG4 may include a dummy cell DUM in a location where a portion of the shared cell SHR is also positioned, resulting in a balanced layout distribution.

[0231] In this arrangement, the first stage STG1 may include one of the first transistor T1, the second transistor T2, and the third transistor T3, as well as a buffer unit BUF. Similarly, the second stage STG2 and the third stage STG3 may each accommodate another of the plurality of transistors and their corresponding buffer units BUF. However, the fourth stage STG4 may include a dummy unit DUM and a buffer unit BUF, instead of one of the plurality of transistors from the shared unit SHR. The placement of the dummy unit DUM helps maintain pattern density consistency in areas where there are no components from the shared unit SHR, and the dummy unit DUM can be arranged on the same layer as the first transistor T1, the second transistor T2, and the third transistor T3, thereby contributing to a uniform circuit layout.

[0232] Therefore, the first stage STG1, the second stage STG2, and the third stage STG3 of the four stages can each include one of the first transistor T1, the second transistor T2, and the third transistor T3, while the remaining stage STG4 can include a dummy cell DUM. The configuration of one cell stage USG containing a single shared cell SHR and multiple buffer cells BUF effectively reduces the overall number of transistors required in the gate driver 810. Therefore, this implementation saves space in the non-display area NDA and reduces power consumption.

[0233] Figure 16 This is a block diagram illustrating an electronic device according to an embodiment.

[0234] refer to Figure 16 In an embodiment, the electronic device 900 may include a processor 910, a memory device 920, a storage device 930, an input / output (“I / O”) device 940, a power supply 950, and a display device 960. Here, the display device 960 may be related to a reference device. Figures 1 to 15 Corresponding to the described display device 10. The electronic device 900 may also include multiple ports for communication with video cards, sound cards, memory cards, universal serial bus (“USB”) devices, etc. In one embodiment, the electronic device 900 may be implemented as a television. In another embodiment, the electronic device 900 may be implemented as a smartphone. However, the embodiments are not limited thereto. For example, in one embodiment, the electronic device 900 may be implemented as a cellular phone, video phone, smartboard, smartwatch, tablet PC (“PC”), car navigation system, computer monitor, laptop computer, head-mounted display (e.g., helmet-mounted display”), etc.

[0235] Processor 910 can perform various computing functions. In embodiments, processor 910 may be, for example, a microprocessor, a central processing unit (“CPU”), an application processor (“AP”), etc. Processor 910 may be connected to other components via, for example, an address bus, a control bus, a data bus, etc. In embodiments, processor 910 may be connected to an expansion bus such as a peripheral component interconnect (“PCI”) bus.

[0236] The memory device 920 may store data for the operation of the electronic device 900. In embodiments, the memory device 920 may include at least one non-volatile memory device such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, and / or at least one volatile memory device such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile DRAM device, and the like.

[0237] In one embodiment, storage device 930 may include a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, a CD-ROM device, etc. In another embodiment, I / O device 940 may include input devices such as a keyboard, keypad, mouse device, touchpad, touch screen, etc., and output devices such as a printer, speaker, etc.

[0238] Power supply 950 provides power for the operation of electronic device 900. Power supply 950 can also provide power to display device 960. Display device 960 can be connected to other components via a bus or other communication link. In some embodiments, display device 960 may be included in I / O device 940. As is customary in the art of this disclosure, embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry, such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, units, and / or modules implemented by microprocessors or the like, the blocks, units, and / or modules may be programmed with software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module may be implemented by dedicated hardware, or as a combination of dedicated hardware performing some functions and processors (e.g., one or more programmed microprocessors and associated circuitry) performing other functions.

[0239] While this disclosure has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as defined in the appended claims. The embodiments of this disclosure described herein should be considered in a descriptive sense only and not for limiting purposes.

Claims

1. A scan driver, comprising: The unit level comprises multiple stages configured to receive multiple clock signals, including a first clock signal, and sequentially output multiple scan signals. The unit level includes a shared circuit and multiple buffer circuits corresponding to the plurality of levels. The shared circuit includes: A first transistor, configured to supply a start signal to a first node based on a first clock signal received from a first clock line; A second transistor, configured to supply the first clock signal to a second node based on the voltage of the first node; and A third transistor, configured to supply a gate low voltage to the second node based on the first clock signal. Each of the plurality of buffer circuits is directly connected to the first node and the second node, and outputs the plurality of scan signals.

2. The scan driver according to claim 1, wherein, Each of the plurality of buffer circuits includes: A fourth transistor, configured to supply a gate high voltage to the output node of the corresponding stage of the buffer circuit based on the voltage of the second node; A fifth transistor, configured to supply one of the plurality of clock signals to the output node of a corresponding stage of the buffer circuit; and A sixth transistor, configured to supply the voltage of the first node to the gate electrode of the fifth transistor based on the gate low voltage.

3. The scan driver according to claim 2, wherein, Each of the plurality of buffer circuits further includes: A first capacitor is connected between the second node and the input terminal of the gate high voltage; and A second capacitor is connected between the gate electrode of the fifth transistor and the output node of the corresponding stage of the buffer circuit.

4. The scan driver according to claim 3, further comprising: A metal layer disposed on a substrate; An active layer is disposed on the metal layer and includes the semiconductor region of the first transistor; A first gate layer is disposed on the active layer and includes the gate electrode of the first transistor and the first electrode of the first capacitor. A second gate layer is disposed on the first gate layer and includes the second electrode of the first capacitor; A third gate layer is disposed on the second gate layer; A first source metal layer is disposed on the third gate layer; as well as A second source metal layer is disposed on the first source metal layer and includes a plurality of clock lines configured to supply the plurality of clock signals.

5. The scan driver according to claim 4, further comprising: The first node electrode is disposed in the second gate layer and corresponds to the first node; A first connection electrode is disposed in the first source metal layer and electrically connects the first transistor, the first node electrode, and the sixth transistor of the first stage of the plurality of stages. The second connection electrode is disposed in the first source metal layer and electrically connects the first node electrode and the sixth transistor of the second stage of the plurality of stages; as well as The third connection electrode is disposed in the first source metal layer and electrically connects the first node electrode and the sixth transistor of the third stage among the plurality of stages.

6. The scan driver according to claim 5, wherein, The first node electrode is arranged between the plurality of clock lines and does not overlap with the second source metal layer.

7. The scan driver according to claim 4, further comprising: The first node electrode is disposed in the second source metal layer and corresponds to the first node; A first connection electrode is disposed in the first source metal layer and electrically connects the first transistor, the first node electrode, and the sixth transistor of the first stage of the plurality of stages. The second connection electrode is disposed in the first source metal layer and electrically connects the first node electrode and the sixth transistor of the second stage of the plurality of stages; as well as The third connection electrode is disposed in the first source metal layer and electrically connects the first node electrode and the sixth transistor of the third stage among the plurality of stages.

8. The scan driver according to claim 4, further comprising: The second node electrode is disposed in the second gate layer and corresponds to the second node; A fourth connection electrode is disposed in the first source metal layer and electrically connects the second node electrode and the gate electrode of the fourth transistor of the first stage of the plurality of stages. A fifth connection electrode is disposed in the first source metal layer and electrically connected to the second node electrode and the gate electrode of the fourth transistor of the second stage of the plurality of stages; as well as A sixth connection electrode is disposed in the first source metal layer and electrically connects the second node electrode and the gate electrode of the fourth transistor of the third stage of the plurality of stages.

9. The scan driver according to claim 4, wherein, The first capacitor of each of the plurality of buffer circuits includes: A first electrode, disposed in the first gate layer, and including the gate electrode of the fourth transistor; and The second electrode is disposed in the second gate layer and overlaps with the first electrode.

10. The scan driver according to claim 4, further comprising: A seventh connection electrode is disposed in the first source metal layer and electrically connected to the second clock line and the first electrode of the fifth transistor of the first stage of the plurality of stages; as well as The eighth connection electrode is disposed in the first source metal layer and electrically connects the second electrode of the fifth transistor of the first stage to the output node of the first stage. The second capacitor of the first stage includes: A first electrode, disposed in the first gate layer, and including the gate electrode of the fifth transistor; and The second electrode is disposed in the second gate layer and is electrically connected to the eighth connection electrode.

11. The scan driver according to claim 1, wherein, Each of the plurality of stages includes one of the first transistor, the second transistor, and the third transistor.

12. The scan driver according to claim 11, wherein, When the plurality of levels comprises four or more levels, each of the three levels comprises one of the first transistor, the second transistor, and the third transistor, and the remaining levels comprise dummy units arranged on the same layer as the first transistor, the second transistor, and the third transistor.

13. A scan driver, comprising: The system comprises a first stage, a second stage, and a third stage, each including a shared circuit and multiple buffer circuits configured to sequentially output multiple scan signals. The shared circuit includes: A first transistor, configured to supply a start signal to a first node based on a first clock signal among a plurality of clock signals; A second transistor, configured to supply the first clock signal to a second node based on the voltage of the first node; and A third transistor, configured to supply a gate low voltage to the second node based on the first clock signal, and The buffer circuit of each of the first, second, and third stages includes: A fourth transistor, configured to supply a gate high voltage to the output node of the corresponding stage of the buffer circuit based on the voltage of the second node; A fifth transistor, configured to supply one of the plurality of clock signals to the output node; and A sixth transistor, configured to supply the voltage of the first node to the gate electrode of the fifth transistor based on the gate low voltage.

14. The scan driver of claim 13, further comprising: A metal layer disposed on a substrate; An active layer is disposed on the metal layer and includes the semiconductor region of the first transistor; A first gate layer is disposed on the active layer and includes the gate electrode of the first transistor and the first electrode of the first capacitor. A second gate layer is disposed on the first gate layer and includes the second electrode of the first capacitor; A third gate layer is disposed on the second gate layer; A first source metal layer is disposed on the third gate layer; as well as A second source metal layer is disposed on the first source metal layer and includes a plurality of clock lines configured to supply the plurality of clock signals.

15. The scan driver of claim 14, further comprising: A first connection electrode is disposed in the first source metal layer and electrically connects the first transistor and the sixth transistor of the first stage. as well as A first node electrode is disposed in the second gate layer, connected to the first connection electrode, and corresponding to the first node. The first node electrode is arranged between the plurality of clock lines and does not overlap with the second source metal layer.

16. An electronic device comprising: Display device; as well as A power supply configured to provide power to the display device. The display device includes: The display panel includes multiple data lines to which multiple data voltages are applied, multiple gate lines intersecting the multiple data lines, and multiple pixels connected to the multiple data lines and the multiple gate lines, wherein multiple gate signals are applied to the multiple gate lines; A data driver configured to supply the plurality of data voltages to the plurality of data lines; and A scan driver configured to sequentially supply the plurality of gate signals to the plurality of gate lines, respectively. The scan driver includes a first stage, a second stage, and a third stage. The first stage, the second stage, and the third stage include a shared circuit and multiple buffer circuits configured to sequentially output multiple scan signals. The shared circuit includes: A first transistor, configured to supply a start signal to a first node based on a first clock signal among a plurality of clock signals received from a first clock line among a plurality of clock lines; A second transistor, configured to supply the first clock signal to a second node based on the voltage of the first node; and A third transistor, configured to supply a gate low voltage to the second node based on the first clock signal. Each of the plurality of buffer circuits is directly connected to the first node and the second node, and is configured to output the first gate signal among the plurality of gate signals to the first gate line among the plurality of gate lines.

17. The electronic device of claim 16, further comprising: A metal layer disposed on a substrate; An active layer is disposed on the metal layer and includes the semiconductor region of the first transistor; A first gate layer is disposed on the active layer and includes the gate electrode of the first transistor and the first electrode of the first capacitor. A second gate layer is disposed on the first gate layer and includes the second electrode of the first capacitor; A third gate layer is disposed on the second gate layer; A first source metal layer is disposed on the third gate layer; as well as A second source metal layer is disposed on the first source metal layer and includes the plurality of clock lines configured to supply the plurality of clock signals.

18. The electronic device according to claim 17, wherein, The pixels include: A first pixel transistor is configured to control the drive current flowing through a light-emitting element; The second pixel transistor is configured to supply a data voltage from the plurality of data voltages to the first electrode of the first pixel transistor based on the first gate signal; A third pixel transistor is configured to electrically connect the second electrode and the gate electrode of the first pixel transistor based on a second gate signal among the plurality of gate signals; A fourth pixel transistor, configured to supply an initialization voltage to the gate electrode of the first pixel transistor based on a third gate signal among the plurality of gate signals; and A fifth pixel transistor, the fifth pixel transistor being configured to supply a driving voltage to the first electrode of the first pixel transistor based on a light-emitting signal.

19. The electronic device of claim 18, further comprising: The first node electrode is disposed in the second gate layer and corresponds to the first node; The second gate line among the plurality of gate lines is disposed in the third gate layer and configured to supply the second gate signal; as well as The light-emitting line is disposed in the third gate layer and configured to supply the light-emitting signal.

20. The electronic device of claim 18, further comprising: The first node electrode is disposed in the second source metal layer and corresponds to the first node; The second gate line among the plurality of gate lines, the second gate line being disposed in the second gate layer and configured to supply the second gate signal; as well as The light-emitting line is disposed in the third gate layer and configured to supply the light-emitting signal.

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