Sorting and screening method and device for large-capacity memory wafers

Abstract

The invention belongs to the technical field of circuit testing, and discloses a sorting, testing and screening method and device for large-capacity memory wafers, the device comprises a probe card, a test excitation circuit and a multi-version management circuit are integrated on the probe card, during working, dynamic adjustable power supply parameters are provided for the memory wafers to be tested, and the test excitation circuit and the multi-version management circuit are integrated on the probe card; the method comprises the following steps: acquiring a to-be-tested memory wafer, generating an interface time sequence meeting the working requirement of the to-be-tested memory wafer, starting the to-be-tested memory wafer to work based on a power supply parameter and the interface time sequence, carrying out contact test and device ID identification on the to-be-tested memory wafer, loading a performance test mirror image according to the device ID to carry out multi-stage sorting, and outputting a contact test result and a multi-stage sorting result. A single probe card can store a plurality of sets of test programs, the test of different types of memories can be supported without physically replacing jigs, and the hardware reconstruction cost of test program switching in an ATE scheme is eliminated.

Description

Technical Field

[0001] This invention belongs to the field of circuit testing technology, specifically a sorting and screening method and apparatus for large-capacity memory wafers. Background Technology

[0002] With the development of semiconductor process technology, circuit integration and speed are constantly increasing, storage capacity is growing larger, and functions are becoming more complex. The ratio of leads to internal components is decreasing, making testing increasingly difficult, and the proportion of testing in total cost is constantly increasing. This problem has become even more severe with the emergence of microsystem-integrated products and SiP circuits.

[0003] Traditional testing technology for ultra-large-scale complex circuits primarily relies on Automatic Test Equipment (ATE), supplemented by board-level functional verification. However, both domestically and internationally, testing technology consistently lags behind design and manufacturing advancements. On one hand, ATE struggles to keep pace with circuit development in terms of speed, accuracy, storage capacity, and signal channels. This is particularly true for system-integrated products, which are characterized by ultra-high performance, ultra-large storage, and ultra-high-speed interfaces, making ATE testing technology insufficient for their needs. On the other hand, the high price of high-performance ATEs is prohibitive, resulting in high testing costs. For large-capacity memories, full-scan functional testing is excessively time-consuming, making the testing costs prohibitive.

[0004] Large-capacity memory is an essential component of modern information processing systems. Traditional testing of large-capacity memory was primarily conducted by chip manufacturers, focusing on targeted testing based on the chip's internal testability logic and fixed tape-out process. However, with the rise of advanced packaging technology-driven microsystem integration, the focus has shifted from traditional chip manufacturers to system integrators. Memory wafers often undergo multiple back-end processes such as thinning, refactoring, dicing, and rewiring to achieve integration with other chips or multiple memory chips. Functional performance testing during this process is crucial, directly determining the yield of the integrated product. When original chip manufacturer test vectors or test cases are unavailable, full-capacity scan testing is the most reliable and prudent method, especially in telecommunications, automotive, aerospace, and other fields. Traditional ATE-based memory testing methods suffer from harsh testing environments, high costs, long development cycles, and long-term testing failures, making them unfeasible for system integrators or impossible to implement in the short term. Summary of the Invention

[0005] This invention provides a sorting and screening method and apparatus for large-capacity memory wafers, which solves the problems of traditional memory testing methods based on ATE equipment, such as harsh testing environment, high investment cost, long development cycle, and failure to converge after long-term testing.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A sorting and screening method for high-capacity memory wafers includes: Provide dynamically adjustable power parameters to the memory under test wafer and generate interface timings that meet the operating requirements of the memory under test wafer; The memory wafer under test begins operation based on power parameters and interface timing; Perform contact testing and device ID identification on the memory wafer under test; Multi-level sorting is performed based on the device ID loaded with the performance test image; Output contact test results and multi-level sorting results.

[0007] Preferably, the contact testing and device ID identification of the memory wafer under test specifically involves: Using the header image file, we complete the contact test of the differential pins. At the same time, by testing the connectivity of the differential pins of the memory wafer under test, we identify different memory wafers under test, record them as different ID numbers, and complete the contact test of all remaining pins of the memory wafer under test with that ID number.

[0008] Preferably, the steps for completing the differential pin contact test using the header image file are as follows: By detecting predefined differential pins, the process terminates and marks the fault when the pin connectivity test fails, and outputs the contact test result when the pin connectivity test succeeds.

[0009] Preferably, the step of multi-level sorting based on the device ID and performance test image is as follows: Test images are loaded in descending order of performance level based on device ID. If the current level test passes, the sorting process stops and the sorting level is recorded. Otherwise, the system is automatically reconfigured to the next level image until sorting is complete.

[0010] Preferably, each performance level test image contains an independent traversal test algorithm, and the DUT is automatically marked as scrap when all level tests fail.

[0011] An apparatus for implementing the above method, characterized in that it comprises: Probe card; The probe card integrates a test excitation circuit and a multi-version management circuit. The test excitation circuit is used to provide dynamically adjustable power parameters to the memory wafer under test and generate interface timing that meets the operating requirements of the memory wafer under test. The multi-version management circuit is used to perform contact testing and device ID identification on the memory wafer under test, and to perform multi-level sorting based on the device ID loaded with the performance test image.

[0012] Preferably, the test stimulus generation circuit includes an FPGA, a programmable clock module, and a power self-test module; The FPGA directly drives the I / O ports of the memory under test wafer. The programmable clock module generates single-ended or differential clock signals to generate interface timing that meets the operating requirements of the memory under test wafer. The power self-test module monitors the power supply status of the memory under test wafer in real time through an analog-to-digital converter.

[0013] Preferably, the programmable clock module dynamically adjusts its output frequency during operation to provide differentiated clock signals for test images of different performance levels.

[0014] Preferably, the power supply self-test module synchronously performs power supply voltage closed-loop control and contact pulse detection, and triggers a contact test failure determination when an abnormal current pulse is detected.

[0015] Preferably, the multi-version management circuit performs multi-level sorting based on the device ID and loads the performance test image as follows: In the performance test programs for different memory under test (DUT) wafers and different performance sorting functions, the corresponding clock frequency is configured first, the functional core is initialized, and the memory traversal test algorithm is completed. When the test result is correct, the program stops. When the test result is incorrect, the reconfiguration register is configured, the next BOOT address is set to the header address of the lower-level performance test image file of the DUT with this ID number, and the IPROOG command is started to make the FPGA automatically restart until the program at the lowest performance level is completed and all tests are stopped.

[0016] Compared with existing technologies, the present invention has the following advantages: The present invention provides a sorting and screening method for high-capacity memory wafers. By dynamically adjusting power parameters and interface timing, it ensures successful startup of the wafer under test, eliminating invalid operations caused by power / timing mismatch in traditional testing. The contact testing and ID recognition synchronization mechanism directly extracts device characteristic parameters when verifying physical connections, forming a unique identifier and driving subsequent processes, avoiding breakpoint delays caused by manual intervention. ID-triggered multi-level sorting automatically loads the corresponding test image, and all classification judgments can be completed in a single contact. It integrates the discrete manual operation, equipment configuration, and result translation links in traditional testing into a coherent process that is executed autonomously. While eliminating human error and information loss, it achieves wafer-level testing with zero breakpoints and zero transfer of personnel.

[0017] This invention also provides a sorting and screening device for high-capacity memory wafers. It uses probe cards to replace the signal generation and power management modules of traditional ATE equipment. Through the test excitation generation circuit, it can directly adapt to memory wafers of different specifications, solve the equipment compatibility problem caused by the fixed power parameters of traditional ATE, and generate customized interface timing. It breaks through the limitation of ATE preset test vectors and realizes full-capacity scan testing. Through multi-version management circuit, a single probe card can store multiple test programs. It can support the testing of different types of memory without physical replacement of fixtures, and eliminate the hardware reconstruction cost of test program switching in ATE solutions.

[0018] Furthermore, the test stimulus generation circuit includes an FPGA, a programmable clock module, and a power self-test module. The FPGA directly drives the I / O ports of the memory under test wafer. The programmable clock module generates single-ended or differential clock signals to generate interface timing that meets the operating requirements of the memory under test wafer. The power self-test module monitors the power supply status of the memory under test wafer in real time through an analog-to-digital converter. Through the collaborative mechanism of the FPGA, clock module, and power self-test module, the problems of insufficient timing accuracy, clock compatibility, and power stability risks in traditional testing are solved.

[0019] Furthermore, the programmable clock module dynamically adjusts the output frequency during operation to provide differentiated clock signals for test images of different performance levels. The dynamic adjustment of the clock frequency enables a single system to adapt to multi-performance level testing, avoiding downtime losses caused by replacing test fixtures in traditional solutions.

[0020] Furthermore, the power self-test module simultaneously performs closed-loop control of power supply voltage and contact pulse detection. When an abnormal current pulse is detected, a contact test failure judgment is triggered. The dual detection mechanism of the power self-test module simultaneously solves two types of faults: electrical connection failure and poor physical contact.

[0021] Furthermore, during the contact testing phase, the device ID is determined by detecting predefined differential pins. When the pin connectivity test fails, the process is terminated and the fault is marked. The predefined differential pin detection mechanism solves the problem of automatic identification in multi-model wafer mixed testing scenarios. Attached Figure Description

[0022] Figure 1 This is a flowchart of a sorting and sieving method for high-capacity memory wafers according to the present invention; Figure 2 This is a circuit diagram for generating test excitations in an embodiment of the present invention; Figure 3 This is a multi-version management circuit according to an embodiment of the present invention; In the diagram, 1-first path, 2-second path, 3-third path, 4-fourth path, 5-fifth path, 6-base clock, 7-sixth path. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0024] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0025] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0026] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings.

[0027] like Figure 1 As shown, this invention provides a sorting and screening method for high-capacity memory wafers, comprising: S1: Provides dynamically adjustable power parameters to the memory under test wafer and generates interface timings that meet the operating requirements of the memory under test wafer; S2: The memory wafer under test begins operation based on power parameters and interface timing; S3: Perform contact testing and device ID identification on the memory wafer under test; S4: Perform multi-level sorting based on the device ID loaded with the performance test image; S5: Outputs contact test results and multi-level sorting results.

[0028] By dynamically adjusting power parameters and interface timing, the successful startup of the wafer under test is ensured, eliminating invalid operations caused by power / timing mismatch in traditional testing. The contact testing and ID recognition synchronization mechanism directly extracts device characteristic parameters when verifying physical connections, forming a unique identifier and driving subsequent processes, avoiding breakpoint delays caused by manual intervention. ID-triggered multi-level sorting automatically loads the corresponding test image, and all grade judgments can be completed in a single contact. The discrete manual operation, equipment configuration, and result translation links in traditional testing are integrated into a coherent process that is executed autonomously. While eliminating human error and information loss, wafer-level testing with zero breakpoints and zero transfers is achieved.

[0029] The present invention also provides a sorting and screening device for high-capacity memory wafers, comprising: Probe card; The probe card integrates a test excitation circuit and a multi-version management circuit. The test excitation circuit is used to provide dynamically adjustable power parameters to the memory wafer under test and generate interface timing that meets the operating requirements of the memory wafer under test. The multi-version management circuit is used to perform contact testing and device ID identification on the memory wafer under test, and to perform multi-level sorting based on the device ID loaded with the performance test image.

[0030] This patent proposes a sorting and screening method for large-capacity memory wafers. By replacing the signal generation and power management modules of traditional ATE (Automatic Test Equipment) machines with probe cards, the method directly adapts to memory wafers of different specifications through test stimulus generation circuits. This solves the equipment compatibility problem caused by the fixed power parameters of traditional ATE machines and generates customized interface timings, breaking through the limitations of ATE preset test vectors and realizing full-capacity scan testing. Through multi-version management circuits, a single probe card can store multiple test programs, supporting the testing of different memory models without the need for physical fixture replacement. This eliminates the hardware reconfiguration cost of test program switching in ATE solutions. This patent proposes a sorting and screening method for large-capacity memory wafers. This method uses an FPGA-centered test stimulus generation circuit on the probe card and a system design based on multiple boots and multi-version management to get rid of dependence on ATE test equipment and realize full-capacity functional performance testing of large-capacity memory on wafers. It has the characteristics of low cost, high efficiency and wide applicability.

[0031] The detailed steps are as follows: The test stimulus generation circuit includes an FPGA (Field Programmable Gate Array), a programmable clock module, and a power self-test module; The FPGA directly drives the I / O ports of the memory under test wafer. The programmable clock module generates single-ended or differential clock signals to generate interface timing that meets the operating requirements of the memory under test wafer. The power self-test module monitors the power supply status of the memory under test wafer in real time through an analog-to-digital converter.

[0032] The programmable clock module dynamically adjusts its output frequency during operation to provide differentiated clock signals for test images of different performance levels.

[0033] The power self-test module synchronously performs power voltage closed-loop control and contact pulse detection. When an abnormal current pulse is detected, it triggers a contact test failure determination.

[0034] In the performance test programs for different memory under test (DUT) wafers and different performance sorting functions, the corresponding clock frequency is configured first, the functional core is initialized, and the memory traversal test algorithm is completed. When the test result is correct, the program stops. When the test result is incorrect, the reconfiguration register is configured, the next BOOT address is set to the header address of the next-level performance test image file of the DUT with this ID number, and the IPROOG command (FPGA's internal configuration access port) is started to make the FPGA automatically restart. This continues until the program at the lowest performance level is completed and all tests stop. During the contact test phase, the device ID is determined by detecting predefined differential pins. When the pin connectivity test fails, the process is terminated and the fault is marked.

[0035] The specific steps for multi-level sorting based on automatically loading performance test images using IDs are as follows: Test images are loaded in descending order of performance level. If the current level of test passes, the process stops and the sorting level is recorded. Otherwise, the system is automatically reconfigured to the next level image until sorting is complete.

[0036] Each performance level test image contains an independent traversal test algorithm. When all level tests fail, the DUT is automatically marked as scrap.

[0037] Another embodiment of the present invention provides a sorting and screening method for large-capacity memory wafers, which solves the problems of harsh testing environment, high investment cost, long development cycle and non-convergence of long-term testing in traditional ATE-based memory testing methods. This method enables the testing and sorting of large-capacity memory wafers, including: The sorting and screening method for high-capacity memory wafers is to arrange system functional components such as FPGA-centered test stimulus generation circuits and multi-version management circuits on the probe card, and to achieve full-function coverage testing of devices from static to dynamic by using specific software testing procedures.

[0038] Test stimulus generation circuit design The FPGA-centric test stimulus circuit design directly connects the I / O ports to the I / O terminals of the DUT; the FPGA receives a continuous and stable clock input from an external crystal oscillator or a clock circuit that automatically outputs upon power-on; an external clock generator controlled by the FPGA or an internal PLL and DCM generates a programmable single-ended or differential clock to provide power for the FPGA functional modules and the DUT; an external ADC controlled by the FPGA or the FPGA's built-in ADC enables DUT power supply self-testing and analog signal acquisition testing; the FPGA is powered by an independent DC-DC / LDO regulated power supply with default power-on output, and the DUT uses a programmable power supply circuit with software-controllable output; the corresponding memory controller IP and test top-level logic are instantiated within the FPGA.

[0039] like Figure 2 As shown, the external power supply provides input to two power conversion circuits through the sixth path 7; the first power conversion generates the fixed voltage power supply required by the FPGA; the clock circuit generates the basic clock 6 required for FPGA operation; the FPGA controls the second power conversion circuit through the fourth path 4, controlling the output switch of the power supply on one hand, and the output voltage amplitude and overcurrent protection threshold of the power supply on the other hand, to meet the testing requirements of the DUT under different operating conditions; the second power conversion circuit outputs power to the DUT through the second path 2; the ADC samples back the output power voltage of the second power conversion circuit, on the one hand to meet the precise control of the power supply voltage, and on the other hand, to detect the pulse output by the DUT from the second path 2 during contact testing, to meet the contact testing requirements; the FPGA has two built-in controllers to control the DUT under different operating conditions. First, the IO detection logic control is used to control the timing of the FPGA output IO to realize the contact test of IO connectivity; second, the memory controller logic is used for DUT functional performance testing, and performs DUT read and write operations by generating interface timing that meets the DUT's operating requirements.

[0040] Multi-version software management circuit design Sufficient capacity SPI FLASH or parallel FLASH is used as the FPGA's configuration memory. Multiple FLASH chips can be connected in series or parallel to form a large-capacity configuration memory. FPGA configuration uses a master-serial or master-parallel loading method, automatically loading and running the program from the FLASH upon power-up. The FLASH firmware uses a multi-BOOT configuration method. The header image file implements contact testing, while other image files implement sorting tests for different DUTs or different performance levels of the same DUT. The probe card loads the header image file by default upon power-up, implementing contact test control within this image file. In this program, different DUTs are identified by testing the connectivity of their different pins, recording them as different ID numbers, and completing the contact test of all remaining pins of the DUT with that ID number. When this program... When the contact test result is correct, the reconfiguration register is configured, the next BOOT address is set to the header address of the highest performance test image file of this DUT ID, and the IPROOG command is started to automatically restart the FPGA. When the test result is incorrect, the program stops. In the performance test programs for different DUTs and different performance sorting functions, the corresponding clock frequency is configured first, the functional core is initialized, and the memory traversal test algorithm is completed. When the test result is correct, the program stops. When the test result is incorrect, the reconfiguration register is configured, the next BOOT address is set to the header address of the lower-level performance test image file of this DUT ID, and the IPROOG command is started to automatically restart the FPGA, until the program at the lowest performance level is completed and all tests stop.

[0041] During the ID identification phase, different wafers or different DIEs on the same wafer are detected in any predetermined order, and identification is performed by the different characteristic pins of each detected object. The test codes for different wafers are independent, and different code segments are found by accessing different FLASH addresses. For the test of a certain wafer, the test code is performed sequentially from the highest performance test code to the lowest performance test code. If the test is correct, the DUT is selected as the performance level and the test stops. If the test fails, the next lower performance test is performed until the end.

[0042] For sorting and sieving probe cards used in high-capacity memory wafers, the testing process and results indication is designed to provide a better human-machine interface. Typically, LED displays indicate the status transitions and results of the testing process, offering advantages such as simplicity and low dependence on external devices, making them suitable for production lines with low levels of automation. Alternatively, the process and results can be displayed on a computer screen via a communication interface connecting the FPGA to the computer, enabling full output of the testing process and results. This approach offers advantages such as comprehensive information, strong scalability, and a high degree of automation.

[0043] The FPGA on Probe Card sorting and screening probe card developed using the related technologies of this invention can achieve 100% functional coverage, has high design feasibility, low dependence on other testing equipment, high degree of automation, high versatility, and low cost, especially for very large-scale integrated circuits with integrated large-capacity memory and highly complex timing processors.

[0044] Although embodiments of the present invention have been described above in conjunction with the accompanying drawings, the present invention is not limited to the specific embodiments and application fields described above. The specific embodiments described above are merely illustrative and instructive, and not restrictive. Those skilled in the art, guided by the specification, can make many other modifications without departing from the scope of the claims of the present invention, and all of these modifications are within the scope of protection of the present invention.

Claims

1. A sorting and screening method for high-capacity memory wafers, characterized in that, include: Provide dynamically adjustable power parameters to the memory under test wafer and generate interface timings that meet the operating requirements of the memory under test wafer; The memory wafer under test begins operation based on power parameters and interface timing; Perform contact testing and device ID identification on the memory wafer under test; Multi-level sorting is performed based on the device ID loaded with the performance test image; Output contact test results and multi-level sorting results.

2. The sorting and screening method for high-capacity memory wafers according to claim 1, characterized in that, The specific steps for contact testing and device ID identification of the memory wafer under test are as follows: Using the header image file, we complete the contact test of the differential pins. At the same time, by testing the connectivity of the differential pins of the memory wafer under test, we identify different memory wafers under test, record them as different ID numbers, and complete the contact test of all remaining pins of the memory wafer under test with that ID number.

3. The sorting and screening method for high-capacity memory wafers according to claim 2, characterized in that, The specific steps for completing the differential pin contact test using the header image file are as follows: By detecting predefined differential pins, the process terminates and marks the fault when the pin connectivity test fails, and outputs the contact test result when the pin connectivity test succeeds.

4. The sorting and screening method for high-capacity memory wafers according to claim 2, characterized in that, The specific steps for multi-level sorting based on the device ID and loading the performance test image are as follows: Test images are loaded in descending order of performance level based on device ID. If the current level test passes, the sorting process stops and the sorting level is recorded. Otherwise, the system is automatically reconfigured to the next level image until sorting is complete.

5. The sorting and screening method for high-capacity memory wafers according to claim 4, characterized in that, Each performance level test image contains an independent traversal test algorithm. When all level tests fail, the DUT is automatically marked as scrap.

6. An apparatus for implementing the method according to any one of claims 1-5, characterized in that, include: Probe card; The probe card integrates a test excitation circuit and a multi-version management circuit. The test excitation circuit is used to provide dynamically adjustable power parameters to the memory wafer under test and generate interface timing that meets the operating requirements of the memory wafer under test. The multi-version management circuit is used to perform contact testing and device ID identification on the memory wafer under test, and to perform multi-level sorting based on the device ID loaded with the performance test image.

7. A sorting and screening device for high-capacity memory wafers according to claim 6, characterized in that, The test stimulus generation circuit includes an FPGA, a programmable clock module, and a power self-test module; The FPGA directly drives the I / O ports of the memory under test wafer. The programmable clock module generates single-ended or differential clock signals to generate interface timing that meets the operating requirements of the memory under test wafer. The power self-test module monitors the power supply status of the memory under test wafer in real time through an analog-to-digital converter.

8. A sorting and screening method for high-capacity memory wafers according to claim 7, characterized in that, The programmable clock module dynamically adjusts its output frequency during operation to provide differentiated clock signals for test images of different performance levels.

9. A sorting and screening method for high-capacity memory wafers according to claim 7, characterized in that, The power self-test module synchronously performs power voltage closed-loop control and contact pulse detection. When an abnormal current pulse is detected, it triggers a contact test failure determination.

10. A sorting and screening method for high-capacity memory wafers according to claim 6, characterized in that, The multi-version management circuit performs multi-level sorting based on the device ID and loads the performance test image. The specific steps are as follows: In the performance test programs for different memory under test (DUT) wafers and different performance sorting functions, the corresponding clock frequency is configured first, the functional core is initialized, and the memory traversal test algorithm is completed. When the test result is correct, the program stops. When the test result is incorrect, the reconfiguration register is configured, the next BOOT address is set to the header address of the lower-level performance test image file of the DUT with this ID number, and the IPROOG command is started to make the FPGA automatically restart until the program at the lowest performance level is completed and all tests are stopped.

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