Semiconductor device

Abstract

A semiconductor device is provided with substrates (50, 60), a semiconductor element (40), and a resin molded body (30). The insulating base material (51, 61) of the substrate (50, 60) has an exposed surface (511, 611) exposed from the surface metal body (52, 62) on which the pattern is formed. The semiconductor device is provided with a fragile layer (101) which is laminated on at least a part of the exposed surfaces (511, 611), is interposed between the insulating base material (51, 61) and the resin molded body (30), and has a lower yield point than the insulating base material (51, 61). Consequently, in the semiconductor device, thermal stress acting on the insulating substrate can be reduced.

Description

Technical Field

[0001] The disclosures in this specification relate to semiconductor devices. Background Technology

[0002] Patent Document 1 discloses a semiconductor device comprising a substrate having wiring disposed on the surface of an insulating layer (insulating substrate) and a heat dissipation layer disposed on the back side of the insulating layer, a semiconductor element connected to the wiring, and a resin molded body sealing the substrate and the semiconductor element. Reference to prior art documents is used to explain the technical elements in this specification.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: International Publication No. 2017 / 119226 Summary of the Invention

[0006] In Patent Document 1, a portion of the insulating substrate is exposed from the wiring. For example, the insulating substrate is exposed between the wiring connected to the upper arm IGBT and the wiring connected to the lower arm IGBT. When the insulating substrate is resin, the insulation distance can be ensured by solid insulation by tightly bonding the resin molded body to the insulating substrate.

[0007] In the molding of resin molded bodies, curing processes such as heating are required to stop the reaction of unreacted portions. The resin molded body is fully cured through this curing process, and its coefficient of linear expansion is smaller after curing compared to before curing. Before curing, the coefficient of linear expansion of the resin molded body is larger than that of the wiring and the resin-containing insulating substrate. Therefore, as the resin temperature decreases before curing, i.e., as the resin molded body shrinks, thermal stress may concentrate at three points: the insulating substrate, the wiring, and the resin molded body. Under these circumstances, or under other unmentioned circumstances, semiconductor devices require further improvements.

[0008] One object of this disclosure is to provide a semiconductor device capable of reducing thermal stress acting on an insulating substrate.

[0009] As a publicly disclosed method, a semiconductor device includes:

[0010] A substrate having an insulating substrate comprising resin, a surface metal body disposed on the surface of the insulating substrate and patterned thereon, and a back metal body disposed on the back side of the insulating substrate.

[0011] A semiconductor device having a first main electrode and a second main electrode disposed on a surface opposite to the first main electrode in the thickness direction, and electrically connected to a surface metal body; and

[0012] A resin molded body that seals a substrate and semiconductor components;

[0013] The insulating substrate has an exposed surface that protrudes from the surface metal body.

[0014] The semiconductor device has a fragile layer that is stacked on at least a portion of the exposed surface and sandwiched between an insulating substrate and a resin molded body, and has a lower yield point than the insulating substrate.

[0015] According to the publicly available semiconductor device, thermal stress acting on the insulating substrate can be reduced by causing the fragile layer to deform significantly beyond its yield point, i.e., by plastic deformation.

[0016] As a publicly disclosed method, a semiconductor device includes:

[0017] A substrate having an insulating substrate comprising resin, a surface metal body disposed on the surface of the insulating substrate and patterned thereon, and a back metal body disposed on the back side of the insulating substrate.

[0018] A semiconductor device having a first main electrode and a second main electrode disposed on a surface opposite to the first main electrode in the thickness direction, and electrically connected to a surface metal body; and

[0019] A resin molded body that seals a substrate and semiconductor components;

[0020] The insulating substrate has an exposed surface that protrudes from the surface metal body.

[0021] The semiconductor device includes an interlayer comprising any one of polyamide-imide, polyamide, and polyimide, which is laminated on at least a portion of the exposed surface and disposed between an insulating substrate and a resin molded body.

[0022] According to the disclosed semiconductor device, the thermal stress acting on the insulating substrate can be reduced by the plastic deformation of the intercalation layer.

[0023] The various methods disclosed in this specification employ different technical means to achieve their respective purposes. The purposes, features, and effects disclosed in this specification will become clearer upon reference to the following detailed description and the accompanying drawings. Attached Figure Description

[0024] Figure 1 This is a diagram showing the power conversion circuit and drive system of the semiconductor device according to the first embodiment.

[0025] Figure 2 It is a three-dimensional diagram representing a semiconductor device.

[0026] Figure 3 It is a three-dimensional cross-sectional view of a semiconductor device.

[0027] Figure 4 This is a cross-sectional view of a semiconductor device.

[0028] Figure 5 This is a top view showing the substrate on the drain electrode side.

[0029] Figure 6 This is a top view showing the substrate on the source electrode side.

[0030] Figure 7 It is Figure 4 An enlarged cross-sectional view of region VII shown.

[0031] Figure 8 It is a graph showing the relationship between stress and strain for the fragile layer and the insulating substrate.

[0032] Figure 9 It is a cross-sectional view showing the state of the resin-filled part during the molding of the resin molded body.

[0033] Figure 10 It is Figure 9 The enlarged cross-sectional view of region X shown.

[0034] Figure 11 It is a cross-sectional view showing the shrinkage of the resin molded body before curing.

[0035] Figure 12 It is Figure 11 An enlarged cross-sectional view of region XII shown.

[0036] Figure 13 This is a sectional view representing a reference example.

[0037] Figure 14 This is a sectional view representing a modified example. Detailed Implementation

[0038] Hereinafter, several embodiments will be described based on the accompanying drawings. Furthermore, for corresponding components in each embodiment, repeated descriptions are sometimes omitted by using the same reference numerals. In each embodiment, where only a portion of the structure is described, the structures of other previously described embodiments can be applied to the other parts of the structure. Moreover, not only combinations of structures explicitly shown in the descriptions of each embodiment, but also combinations of structures from multiple embodiments can be partially combined with each other, even if not explicitly shown, as long as the combination does not particularly hinder the process.

[0039] (First Implementation)

[0040] The semiconductor device in this embodiment is applied, for example, to a mobile body driven by a rotary electric motor. Examples of mobile bodies include electric vehicles such as battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), and plug-in hybrid electric vehicles (PHEVs), electric aircraft such as drones and electric vertical take-off and landing aircraft (eVTOLs), ships, construction machinery, and agricultural machinery. BEV is an abbreviation for Battery Electric Vehicle. HEV is an abbreviation for Hybrid Electric Vehicle. eVTOL is an abbreviation for electronic vertical take-off and landing aircraft. Examples of its application to vehicles will be described below.

[0041] <Vehicle drive system>

[0042] like Figure 1 As shown, the vehicle's drive system 1 includes a DC power supply 2, an electric generator 3, and a power conversion circuit 4.

[0043] DC power supply 2 is a DC voltage source composed of rechargeable and discharging secondary batteries. Examples of secondary batteries include lithium-ion batteries and nickel-metal hydride batteries. Electric generator 3 is a three-phase AC rotating electric motor. Electric generator 3 functions as the vehicle's driving force, i.e., an electric motor. During regeneration, electric generator 3 functions as a generator. Power conversion circuit 4 performs power conversion between DC power supply 2 and electric generator 3.

[0044] <Power Conversion Circuits>

[0045] Figure 1 An example of power conversion circuit 4 is shown. Figure 1 The illustrated power conversion circuit 4 includes a smoothing capacitor 5 and an inverter 6.

[0046] The smoothing capacitor 5 primarily smooths the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to the P-line 7 (high-potential side) and the N-line 8 (low-potential side). The P-line 7 is connected to the positive terminal of the DC power supply 2, and the N-line 8 is connected to the negative terminal of the DC power supply 2. The positive terminal of the smoothing capacitor 5 is connected to the P-line 7 between the DC power supply 2 and the inverter 6. The negative terminal of the smoothing capacitor 5 is connected to the N-line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel with the DC power supply 2.

[0047] Inverter 6 is a DC-AC conversion circuit. Under the switching control of the control circuit, inverter 6 converts DC voltage into three-phase AC voltage and outputs it to the electric generator 3. Thus, the electric generator 3 is driven to produce a specified torque. During regenerative braking of the vehicle, inverter 6, under the switching control of the control circuit, converts the three-phase AC voltage generated by the rotational force from the wheels into DC voltage and outputs it to line P 7. In this way, inverter 6 performs bidirectional power conversion between the DC power supply 2 and the electric generator 3.

[0048] Inverter 6 is configured as a three-phase upper and lower arm circuit 9. The upper and lower arm circuit 9 is sometimes referred to as a bridge arm. The upper and lower arm circuit 9 each have an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H as the P line 7 side. Hereinafter, the upper arm 9H and the lower arm 9L will sometimes be referred to simply as arm 9H and 9L.

[0049] The connection point between the upper arm 9H and the lower arm 9L, i.e., the midpoint of the upper and lower arm circuit 9, is connected to the winding 3a of the corresponding phase in the electric generator 3 via the output line 10. The inverter 6 has six arms 9H and 9L. Each arm 9H and 9L is configured to have a switching element. The number of switching elements constituting each arm 9H and 9L is not particularly limited. There can be one or more (e.g., two). In many cases, multiple switching elements connected in parallel are turned on and off at the same timing by a common gate drive signal (drive voltage).

[0050] The illustrated switching element is an n-channel MOSFET11. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. In the upper arm 9H, the drain of MOSFET11 is connected to the P-line 7. In the lower arm 9L, the source of MOSFET11 is connected to the N-line 8. Furthermore, the source of MOSFET11 in the upper arm 9H and the drain of MOSFET11 in the lower arm 9L are interconnected.

[0051] A return current diode 12 is connected in reverse parallel to each MOSFET 11. The diode 12 can be a parasitic diode (body diode) of the MOSFET 11 or an external diode. The anode of the diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode of the diode 12 is connected to the drain of the corresponding MOSFET 11.

[0052] Furthermore, the switching element is not limited to MOSFET11. For example, IGBT can also be used. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. In the case of IGBT, a return diode is also connected in reverse parallel.

[0053] The power conversion circuit 4 may also include a converter. The converter is a DC-DC converter circuit configured to convert DC voltage, for example, into DC voltages of different values. The converter is located between the DC power supply 2 and the smoothing capacitor 5. The converter may be configured, for example, to include a reactor and the aforementioned upper and lower arm circuits 9. With this structure, step-up and step-down voltage conversion is possible. The power conversion circuit 4 may also include a filter capacitor. The filter capacitor is located between the DC power supply 2 and the converter.

[0054] The power conversion circuit 4 can also include a buffer circuit. The buffer circuit is connected in parallel with the upper and lower arm circuits 9. The buffer circuit reduces the inductance of the upper and lower arm circuits 9. The buffer circuit absorbs the transient high voltage generated when the switching elements (MOSFET11) constituting the upper and lower arm circuits 9 are switched, i.e., the so-called switching surge. As a result, the inverter 6 can perform high-speed switching.

[0055] The power conversion circuit 4 may also include a drive circuit for the switching elements that constitute the inverter 6, etc. Based on the drive command from the control circuit, the drive circuit supplies a drive voltage to the gate of the corresponding arm's MOSFET 11. By applying the drive voltage, the drive circuit drives the corresponding MOSFET 11, i.e., performs on / off driving. The drive circuit is sometimes referred to as a driver.

[0056] The power conversion circuit 4 may also include a control circuit for the switching elements. The control circuit generates drive commands to operate the MOSFET 11 and outputs them to the drive circuit. The control circuit generates drive commands, for example, based on torque requirements input from a higher-level ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

[0057] Various sensors are used, such as current sensors, rotation angle sensors, and voltage sensors. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the electric generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit is configured to include a processor and memory. PWM is an abbreviation for Pulse Width Modulation.

[0058] Semiconductor Devices

[0059] Figure 2 This is a three-dimensional diagram representing an example of a semiconductor device. Figure 3 This is a three-dimensional cross-sectional view of a semiconductor device. Figure 3 In the middle, it is shown that along Figure 2 The cross section of line III-III. Figure 4 Is with Figure 3 The corresponding two-dimensional sectional view. Figure 5 This is a top view showing the substrate on the drain electrode side. Figure 6 This is a top view showing the substrate on the source electrode side. Figure 5 and Figure 6 The surface metal body is shown in the image. Figure 5 and Figure 6 The semiconductor element, conductive spacer, connector, P terminal, N terminal and O terminal are shown together.

[0060] Hereinafter, the thickness direction of the semiconductor element (semiconductor substrate) is defined as the Z direction. A direction orthogonal to the Z direction is defined as the Y direction. A direction orthogonal to both the Z and Y directions is defined as the X direction. The X, Y, and Z directions are mutually orthogonal in position. Unless otherwise specified, the shape viewed from above in the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the top view shape. Sometimes, the top view from the Z direction is simply referred to as the top view.

[0061] Semiconductor device 20 constitutes the aforementioned upper and lower arm circuits 9, i.e., inverter 6. The illustrated semiconductor device 20 constitutes one of the upper and lower arm circuits 9, i.e., one phase of the upper and lower arm circuit 9. Semiconductor device 20 is sometimes referred to as a semiconductor module, power module, etc. Figures 2-6 As shown, the semiconductor device 20 includes a resin molded body 30, a semiconductor element 40, a substrate 50, 60, a conductive spacer 70, a connector 75, and an external connection terminal 80.

[0062] The resin molded body 30 seals a portion of the other elements constituting the semiconductor device 20. The remaining portions of the other elements are exposed outside the resin molded body 30. The resin molded body 30 is formed using a resin material. An example resin molded body 30 is made of epoxy resin and formed by transfer molding. Such a resin molded body 30 is sometimes referred to as molding resin, sealing resin body, etc.

[0063] The resin molded body 30 has a generally rectangular shape when viewed from above. As the surfaces constituting the outer contour, the resin molded body 30 has a front surface 301, a back surface 302, and side surfaces 303, 304, 305, and 306. The back surface 302 is the surface opposite to the front surface 301 in the Z direction. The front surface 301 and the back surface 302 are, for example, flat surfaces. The side surface 304 is the surface opposite to the side surface 303 in the Y direction. The side surface 306 is the surface opposite to the side surface 305 in the X direction.

[0064] Semiconductor element 40 is formed by forming a switching element on a semiconductor substrate made of silicon (Si) or a wide-bandgap semiconductor with a wider bandgap than silicon. Examples of wide-bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. Semiconductor element 40 is sometimes referred to as a power element or a semiconductor chip.

[0065] The illustrated semiconductor element 40 is formed by forming the aforementioned n-channel MOSFET 11 on a semiconductor substrate made of SiC. The MOSFET 11 has a vertical structure so that the main current flows in the thickness direction (Z direction) of the semiconductor element 40 (semiconductor substrate). The semiconductor element 40 has main electrodes for switching elements on both sides in its thickness direction (Z direction). As main electrodes, the semiconductor element 40 has a drain electrode 41 on one side and a source electrode 42 on the back side. In the case where the diode 12 is a parasitic diode, the source electrode 42 also serves as the anode electrode, and the drain electrode 41 also serves as the cathode electrode. The diode 12 can also be configured on a different chip than the MOSFET 11. The drain electrode 41 is the main electrode on the high-potential side, and the source electrode 42 is the main electrode on the low-potential side.

[0066] Semiconductor element 40 is generally rectangular in shape when viewed from above. Semiconductor element 40 has pads 43 formed on the back side at a different location than the source electrode 42. The source electrode 42 and pads 43 are exposed from a protective film (not shown) formed on the back side of the semiconductor substrate. Drain electrode 41 is formed on almost the entire surface of one side. Source electrode 42 is formed on a portion of the back side of semiconductor element 40. Pads 43 are signal electrodes. Pads 43 include pads for the gate electrode. The illustrated pads 43 are formed in the Y direction at an end opposite to the region where the source electrode 42 is formed.

[0067] Semiconductor device 20 includes a plurality of semiconductor elements 40. The plurality of semiconductor elements 40 may comprise various types of semiconductor elements with different specifications. Alternatively, as in the illustrated semiconductor device 20, all semiconductor elements 40 may have identical structures. The plurality of semiconductor elements 40 includes a semiconductor element 40H constituting the upper arm 9H and a semiconductor element 40L constituting the lower arm 9L. Sometimes semiconductor element 40H is referred to as the upper arm element, and semiconductor element 40L as the lower arm element.

[0068] Semiconductor elements 40H and 40L are arranged in the Y direction. Semiconductor elements 40H and 40L are arranged at approximately the same position in the Z direction. The drain electrode 41 of semiconductor elements 40H and 40L faces the substrate 50. The source electrode 42 of semiconductor elements 40H and 40L faces the substrate 60. When the number of switching elements constituting each arm 9H and 9L is, for example, two, the semiconductor device 20 includes two semiconductor elements 40H and two semiconductor elements 40L. The two semiconductor elements 40H are arranged in the X direction. Similarly, the two semiconductor elements 40L are arranged in the X direction.

[0069] Semiconductor element 40H is configured with pad 43 on side 303 relative to source electrode 42. Semiconductor element 40L is configured with pad 43 on side 304 relative to source electrode 42.

[0070] Substrates 50 and 60 are arranged in the Z direction to sandwich a plurality of semiconductor elements 40. Substrates 50 and 60 are arranged with at least a portion facing each other in the Z direction. When viewed from above, substrates 50 and 60 completely enclose the plurality of semiconductor elements 40. Substrate 50 is disposed on the drain electrode 41 side. Substrate 60 is disposed on the source electrode 42 side. Substrate 50 is electrically connected to the drain electrode 41, providing wiring functionality. Substrate 60 is electrically connected to the source electrode 42, providing wiring functionality. Substrates 50 and 60 provide heat dissipation functionality for dissipating heat generated by the semiconductor elements 40.

[0071] Substrate 50 includes an insulating substrate 51, a surface metal body 52, and a back metal body 53. Substrate 60 includes an insulating substrate 61, a surface metal body 62, and a back metal body 63. The insulating substrates 51 and 61 are resin substrates containing resin as a material. The illustrated insulating substrates 51 and 61 contain epoxy resin as a material. The insulating substrate 51 electrically separates the surface metal body 52 from the back metal body 53. The insulating substrate 61 electrically separates the surface metal body 62 from the back metal body 63.

[0072] Surface metal bodies 52 and 62 and back metal bodies 53 and 63 are provided in the form of metal plates or metal foils. Surface metal bodies 52 and 62 and back metal bodies 53 and 63 are made of metals with good electrical and thermal conductivity, such as Cu or Al. Surface metal bodies 52 and 62 are patterned. Surface metal bodies 52 and 62 may also have a Ni-based, Au, or other coating on their metal surfaces. Surface metal body 52 has P-wires 521 and relay wires 522. P-wires 521 and relay wires 522 are electrically separated by a predetermined gap. A resin molded body 30 is filled in this gap.

[0073] P-wire 521 is connected to P-terminal 81 and the drain electrode 41 of semiconductor element 40H. P-wire 521 electrically connects P-terminal 81 to the drain electrode 41 of semiconductor element 40H. Relay wire 522 is connected to the drain electrode 41, connector 75, and O-terminal 83 of semiconductor element 40L. Relay wire 522 electrically connects O-terminal 83 to the drain electrode 41 of semiconductor element 40L. The illustrated P-wire 521 is approximately rectangular in shape when viewed from above. The relay wire 522 is also approximately rectangular in shape when viewed from above. P-wire 521 and relay wire 522 are arranged in the Y direction.

[0074] P terminal 81 is connected in P wiring 521 near the end on side 303. O terminal 83 is connected in relay wiring 522 near the end on side 304. The drain electrode 41 of semiconductor element 40H is connected to P wiring 521 at a position closer to relay wiring 522 than the junction of P terminal 81. The drain electrode 41 of semiconductor element 40L is connected to relay wiring 522 at a position closer to P wiring 521 than the junction of O terminal 83. Connector 75 is connected to relay wiring 522 at a position closer to P wiring 521 than semiconductor element 40L.

[0075] The surface metal body 62 has an N-wire 621 and a relay wire 622. The N-wire 621 and the relay wire 622 are electrically separated by a defined gap. A resin molded body 30 is filled in this gap. The N-wire 621 is connected to the N terminal 82 and the source electrode 42 of the semiconductor element 40L. The N-wire 621 electrically connects the N terminal 82 to the source electrode 42 of the semiconductor element 40L. The relay wire 622 is connected to the source electrode 42 of the semiconductor element 40H and the connector 75. The relay wire 622 electrically connects the source electrode 42 of the semiconductor element 40H to the drain electrode 41 of the semiconductor element 40L via the connector 75.

[0076] The illustrated N-wire 621 has a generally U-shaped form when viewed from above. The N-wire 621 has a base extending in the X direction and a pair of extension portions connected to the base and extending from both ends of the base in the Y direction. A relay wire 622 is disposed between the pair of extension portions of the N-wire 621. The relay wire 622 has a shape similar to or the same as home plate in a baseball when viewed from above. The base of the N-wire 621 and the relay wire 622 are arranged in the Y direction. The extension portions of the N-wire 621 and the relay wire 622 are arranged in the X direction.

[0077] The source electrode 42 of semiconductor element 40L is connected to the base of N-wire 621. N-terminal 82 is connected to an extension portion of N-wire 621. Semiconductor element 40L is connected in N-wire 621 near the end on side 304. N-terminal 82 is connected in N-wire 621 near the end on side 303. The source electrode 42 of semiconductor element 40H is connected to relay wiring 622. Connector portion 75 is connected to relay wiring 622 at a position closer to the base of N-wire 621 than semiconductor element 40H.

[0078] Back metal bodies 53 and 63 are electrically separated from surface metal bodies 52 and 62 via insulating substrates 51 and 61. The illustrated back metal bodies 53 and 63 are so-called full-surface conductive bodies disposed over approximately the entire back surface of the insulating substrates 51 and 61. Back metal body 53 protrudes from one side 301 of the resin molded body 30, and back metal body 63 protrudes from the back side 302. Back metal body 53 is exposed approximately coplanarly with respect to one side 301. Back metal body 63 is exposed approximately coplanarly with respect to the back side 302.

[0079] The conductive spacer 70 provides a spacer function between the semiconductor element 40 and the substrate 60 to ensure a specified spacing. For example, the conductive spacer 70 ensures the height of the corresponding signal terminal 84 for electrical connection to the pad 43 of the semiconductor element 40. The conductive spacer 70 is located midway between the source electrode 42 of the semiconductor element 40 and the substrate 60 in the electrical and thermal conduction path, providing wiring and heat dissipation functions. The conductive spacer 70 is made of a metal material with good electrical and thermal conductivity, such as Cu. The conductive spacer 70 may also have a coating on its surface. The conductive spacer 70 is a columnar body with a generally rectangular shape when viewed from above, having approximately the same size as the source electrode 42.

[0080] The conductive spacer 70 is sometimes referred to as a terminal, wiring block, metal block, etc. The semiconductor device 20 has the same number of conductive spacers 70 as the semiconductor element 40. Specifically, it has two conductive spacers 70. One of the conductive spacers 70 electrically connects the source electrode 42 of the semiconductor element 40H to the relay wiring 622. The other conductive spacer 70 electrically connects the source electrode 42 of the semiconductor element 40L to the N wiring 621.

[0081] Connector 75 electrically connects relay cables 522 and 622. That is, connector 75 electrically connects the upper arm 9H and the lower arm 9L. Connector 75 is disposed between semiconductor element 40H and semiconductor element 40L. When viewed from above, connector 75 is positioned in the overlapping area of ​​relay cables 522 and 622. The illustrated connector 75 is a metal columnar body disposed independently of surface metal bodies 52 and 62. Connector 75 extends along the Z-direction. One end of connector 75 is connected to relay cable 522, and the other end of connector 75 is connected to relay cable 622.

[0082] The connector 75 can also be continuously and integrally connected to the surface metal bodies 52 and 62. That is, the connector 75 can also be integrally provided on the surface metal bodies 52 and 62 as part of the substrates 50 and 60. Alternatively, a part of the connector 75 can be set as part of the substrate 50, and another part of the connector 75 can be set as part of the substrate 60.

[0083] External connection terminal 80 is a terminal used to electrically connect semiconductor device 20 to external devices. External connection terminal 80 is formed using a highly conductive metal material such as Cu. External connection terminal 80 is, for example, a substrate. External connection terminal 80 is sometimes referred to as a lead, etc. External connection terminal 80 includes P terminal 81, N terminal 82, O terminal 83, and signal terminal 84. P terminal 81, N terminal 82, and O terminal 83 are electrically connected to the main electrode of semiconductor element 40, and are therefore sometimes referred to as main terminals. P terminal 81 and N terminal 82 are sometimes referred to as power terminals.

[0084] P-terminal 81 is connected near one end of P-wiring 521 in the Y direction. A portion of P-terminal 81 is covered by resin molding 30, and another portion of P-terminal 81 protrudes outward from resin molding 30. The engagement portion of P-terminal 81 that engages with P-wiring 521 is covered by resin molding 30. The illustrated P-terminal 81 generally extends along the Y direction. P-terminal 81 protrudes from side 303. Semiconductor device 20 has two P-terminals 81.

[0085] The N-terminal 82 is connected to the extension portion of the N-wire 621. A portion of the N-terminal 82 is covered by the resin molding body 30, and another portion of the N-terminal 82 protrudes outward from the resin molding body 30. The engagement portion of the N-terminal 82 that engages with the N-wire 621 is covered by the resin molding body 30. The illustrated N-terminal 82 extends generally in the Y direction along the same direction as the P-terminal 81. The N-terminal 82 protrudes from the side 303. The semiconductor device 20 has two N-terminals 82 respectively connected to the extension portion of the N-wire 621.

[0086] Terminal 83 is connected near one end of the trunk wiring 522 in the Y direction. A portion of terminal 83 is covered by resin molding 30, and another portion of terminal 83 protrudes outward from resin molding 30. The engagement portion of terminal 83 that engages with trunk wiring 522 is covered by resin molding 30. The illustrated terminal 83 generally extends in the Y direction in the direction opposite to that of terminal 81 and terminal 82. Terminal 83 protrudes from side 304.

[0087] Signal terminal 84 is electrically connected to the pad 43 of the corresponding semiconductor element 40. Signal terminal 84 includes a signal terminal connected to the pad 43 of semiconductor element 40H and a signal terminal connected to the pad 43 of semiconductor element 40L. The illustrated signal terminal 84 is connected to the corresponding pad 43 via a bonding line (not shown). Signal terminal 84 generally extends along the Y direction when viewed from above. A portion of signal terminal 84, including the connection portion connected to the pad 43, is covered by the resin molded body 30, while another portion protrudes from the resin molded body 30.

[0088] Signal terminals 84 connected to pads 43 of semiconductor element 40H protrude outward from side 303 toward the resin molded body 30. P terminals 81, N terminals 82, and signal terminals 84 on the upper arm 9H side are arranged along the X direction. N terminals 82, P terminals 81, signal terminals 84, and P terminals 81, N terminals 82 are arranged sequentially in the X direction. Signal terminals 84 connected to pads 43 of semiconductor element 40L protrude outward from side 304 toward the resin molded body 30. O terminals 83 and signal terminals 84 on the lower arm 9L side are arranged along the X direction. O terminals 83, signal terminals 84, and O terminals 83 are arranged sequentially in the X direction.

[0089] Semiconductor device 20 includes bonding material 90. Bonding material 90 can be solder or a sintered material. The drain electrode 41 of semiconductor element 40 is connected to surface metal body 52 via bonding material 90. The source electrode 42 of semiconductor element 40 is connected to conductive spacer 70 via bonding material 90. Conductive spacer 70 is connected to surface metal body 62 via bonding material 90. Connector portion 75 is connected to surface metal bodies 52 and 62 via bonding material 90. Furthermore, the multiple bonding materials 90 can be made of the same material, or some bonding materials 90 can be made of a different material than the others.

[0090] P-terminals 81, N-terminals 82, and O-terminals 83 can also be connected to the corresponding surface metal bodies 52 and 62 via the aforementioned bonding material 90. P-terminals 81, N-terminals 82, and O-terminals 83 can also be solid-state bonded to the corresponding surface metal bodies 52 and 62. Solid-state bonding methods include ultrasonic bonding, room-temperature bonding, friction stirring bonding, diffusion bonding, and friction pressing.

[0091] As described above, in the semiconductor device 20, the resin molded body 30 seals a plurality of semiconductor elements 40 constituting the upper and lower arm circuits 9 of one phase. The resin molded body 30 integrally seals a portion of each of the plurality of semiconductor elements 40, a portion of the substrate 50, a portion of the substrate 60, a plurality of conductive spacers 70, a connector portion 75, and a portion of the external connection terminal 80. The resin molded body 30 seals insulating substrates 51 and 61 and surface metal bodies 52 and 62 in the substrates 50 and 60.

[0092] Semiconductor element 40 is disposed between substrates 50 and 60 in the Z direction. Semiconductor element 40 is sandwiched between the opposing substrates 50 and 60. This allows heat from semiconductor element 40 to be dissipated to both sides in the Z direction. Semiconductor device 20 has a two-sided heat dissipation structure. Backside metal body 53 is exposed from resin molded body 30 approximately coplanar with respect to one side 301. Backside metal body 63 is exposed from resin molded body 30 approximately coplanar with respect to the backside 302. The exposed backside metal bodies 53 and 63 improve heat dissipation.

[0093] <Three key points, vulnerable layer, roughened section>

[0094] exist Figure 5 and Figure 6 The image also shows a fragile layer. Figure 7 It is Figure 4 An enlarged view of region VII, indicated by the single-dotted line. Figure 8 This is a graph showing the stress-strain relationship for fragile layers and insulating substrates. Figure 8 In the diagram, solid lines represent the vulnerable layer, and dashed lines represent the insulating substrate. For convenience, in... Figures 2-6 The roughening part is omitted in the representation.

[0095] like Figure 4 , Figure 5 and Figure 7 As shown, the insulating substrate 51 has an exposed surface 511 that protrudes from the surface metal body 52. ​​The exposed surface 511 has a wiring gap exposed portion 5111 and an outer peripheral exposed portion 5112. The wiring gap exposed portion 5111 is the portion exposed through the gap between adjacent wiring gaps. The wiring gap exposed portion 5111 is exposed through the gap between the P-wire 521 and the relay wire 522. The outer peripheral exposed portion 5112 is the portion of the insulating substrate 51 that protrudes from the surface metal body 52 at its outer peripheral edge. The outer peripheral exposed portion 5112 is provided along the outer peripheral edge of the insulating substrate 51.

[0096] like Figure 4 , Figure 6 and Figure 7As shown, the insulating substrate 61 has an exposed surface 611 that protrudes from the surface metal body 62. The exposed surface 611 has a wiring gap exposed portion 6111 and an outer peripheral exposed portion 6112. The wiring gap exposed portion 6111 is the portion exposed through the gap between adjacent wiring gaps. The wiring gap exposed portion 6111 is exposed through the gap between the N-wire 621 and the relay wire 622. The outer peripheral exposed portion 6112 is the portion of the insulating substrate 61 that protrudes from the surface metal body 62 at its outer peripheral edge. The outer peripheral exposed portion 6112 is provided along the outer peripheral edge of the insulating substrate 61.

[0097] like Figure 7 As illustrated, the semiconductor device 20 includes a triple point 100 comprising a resin molded body 30, an insulating substrate 61, and a surface metal body 62. The triple point 100 is formed by exposing the insulating substrate 61 with an exposed surface 611. The triple point 100 includes a resin molded body 30, an insulating substrate 61, and an N-wire 621 in the exposed portion 6111, and a resin molded body 30, an insulating substrate 61, and a relay wire 622 in the exposed portion 6112. The triple point 100 also includes a resin molded body 30, an insulating substrate 61, and a surface metal body 62 (N-wire 621) in the exposed portion 6112.

[0098] Although not illustrated, the semiconductor device 20 includes a triple point 100 comprising a resin molded body 30, an insulating substrate 51, and a surface metal body 52. ​​The triple point 100 includes a resin molded body 30, an insulating substrate 51, and a P-wire 521 in the exposed portion 5111, and a resin molded body 30, an insulating substrate 51, and a relay wire 522 in the exposed portion 5112. The triple point 100 also includes a resin molded body 30, an insulating substrate 51, and a P-wire 521 in the exposed portion 5112, and a resin molded body 30, an insulating substrate 51, and a relay wire 522 in the exposed portion 5112.

[0099] In the structure with the aforementioned three-point junction 100, thermal stress is concentrated at the three-point junction 100. To reduce the thermal stress acting on the three-point junction 100, the semiconductor device 20 further includes a fragile layer 101. The fragile layer 101 is laminated on at least a portion of the exposed surfaces 511, 611 of the insulating substrates 51, 61, and sandwiched between the insulating substrates 51, 61 and the resin molded body 30. An example of the fragile layer 101 is disposed at the exposed portions 5111, 6111 of the wiring.

[0100] The vulnerable layer 101 is more vulnerable than the insulating substrates 51 and 61. For example... Figure 8As shown, the yield stress YS1 of the fragile layer 101 is less than the yield stress YS2 of the insulating substrates 51 and 61. That is, the yield point of the fragile layer 101 is lower than the yield points of the insulating substrates 51 and 61. Furthermore, the Young's modulus YM1 of the illustrated fragile layer 101 is less than the Young's modulus YM2 of the insulating substrate 61. The fragile layer 101 is formed using a material with a lower yield point than the insulating substrates 51 and 61 and a smaller Young's modulus than the insulating substrate 61. The fragile layer 101 may be composed of, for example, any one of polyamide-imide, polyamide, and polyimide.

[0101] The glass transition point (Tg) of the fragile layer 101 can be higher than that of the resin molded body 30. Therefore, the resin molded body 30 can be formed while the fragile layer 101 is fully cured. Thus, it is possible to prevent the formation of the resin molded body 30 in an incompletely cured state, which would reduce the overall strength of the fragile layer 101 due to shrinkage of the resin molded body 30 before curing.

[0102] Semiconductor device 20 also includes a low-density adhesion portion and a high-density adhesion portion with a higher adhesion force relative to the resin molded body 30 than the low-density adhesion portion. The illustrated semiconductor device 20 includes roughened portions 54 and 64 as high-density adhesion portions and unroughened portions 55 and 65 as low-density adhesion portions. Substrate 50 has roughened portions 54 and unroughened portions 55. Roughened portion 54 is the roughened portion of the upper surface of surface metal body 52. ​​Unroughened portion 55 is the unroughened portion of the upper surface of surface metal body 52, i.e., the portion other than roughened portion 54. Substrate 60 has roughened portions 64 and unroughened portions 65. Roughened portion 64 is the roughened portion of the upper surface of surface metal body 62. Unroughened portion 65 is the unroughened portion of the upper surface of surface metal body 62, i.e., the portion other than roughened portion 64. For example, the portions where bonding material 90 is disposed are unroughened portions 55 and 65.

[0103] Roughened portions 54 and 64 can be formed by laser irradiation, sandblasting, blackening treatment, roughening plating, etc. The roughened portions 54 and 64 shown are formed by laser irradiation. Roughened portions 54 and 64 can be obtained by irradiating the coating formed on the surface of the surface metal bodies 52 and 62 with a pulsed laser, forming a roughened oxide film originating from the main metal constituting the coating and having fine unevenness on the surface. For example... Figure 7 As shown, the same roughened portion 71 is also provided on the side of the conductive spacer 70.

[0104] The roughened portion 54 is provided such that it overlaps with at least a portion of the exposed portion 6111 of the wiring interlocking when viewed from above in the Z direction. The roughened portion 54 is located opposite the exposed portion 6111 of the wiring interlocking. Although not shown in the figure, the roughened portion 64 is provided such that it overlaps with at least a portion of the exposed portion 5111 of the wiring interlocking when viewed from above. The roughened portion 64 is located opposite the exposed portion 5111 of the wiring interlocking. The fragile layer 101 is provided opposite to the roughened portions 54 and 64 in the Z direction. The roughened portion 64 is also formed on the outer periphery of the patterned surface metal bodies 52 and 62.

[0105] <Effects of the fragile layer>

[0106] Figure 9 It is a cross-sectional view showing the state of the resin-filled part during the molding of the resin molded body. Figure 9 The state before contraction is shown. Figure 10 It is Figure 9 The image shows an enlarged view of region X. Figure 11 It is a cross-sectional view showing the shrinkage state of the resin molded body before curing. Figure 12 It is Figure 11 The diagram shows an enlarged view of region XII. Figure 9 and Figure 11 All images show the state before curing.

[0107] In the molding of the resin molded body 30, a curing process, such as heating, is required to stop the reaction of unreacted portions. The resin molded body 30 is completely cured through the curing process, and after the curing process, the coefficient of linear expansion of the resin molded body 30 is smaller than that before the curing process. Before the curing process, the coefficient of linear expansion of the resin molded body 30 is larger than that of the surface metal bodies 52 and 62 (wiring) and the resin-containing insulating substrates 51 and 61.

[0108] In the illustrated semiconductor device 20, the coefficient of linear expansion of the resin molded body 30 after curing is 14 × 10⁻⁶. -6 The coefficient of linear expansion of the resin molded body 30 before curing is approximately 20 × 10⁻⁶ K. -6 The coefficient of linear expansion for insulating substrates 51 and 61 is approximately 14 × 10⁻⁶ K. -6 The coefficient of linear expansion of the surface metal bodies 52 and 62 is approximately 16.5 × 10⁻⁶ K. -6 / K or so.

[0109] Before forming the resin molded body 30, a fragile layer 101 is formed by coating any one of polyamide-imide, polyamide, and polyimide onto the exposed surfaces 511 and 611 of the insulating substrates 51 and 61. The example of the fragile layer 101 is formed on the exposed portions 5111 and 6111 between wiring wires. Furthermore, with the fragile layer 101 formed, if resin is injected into the cavity of a mold (not shown) and pressure is applied, then... Figure 9 and Figure 10 As shown, the resin travels through every corner of the cavity. The fragile layer 101 is sandwiched between the exposed wiring portions 5111 and 6111 of the resin molded body 30 and the insulating substrates 51 and 61.

[0110] As described above, before the curing process, the coefficient of linear expansion of the resin molded body 30 is greater than that of the surface metal bodies 52 and 62 and the resin-containing insulating substrates 51 and 61. Therefore, when the temperature of the resin molded body 30 decreases after pressure holding and before the curing process, the resin molded body 30 moves along... Figure 11 The arrows indicate shrinkage (thermal shrinkage). Thermal stress tends to concentrate at the three-point 100. In particular, roughened portions 54 and 64 are provided on the opposing surfaces of the exposed portions 5111 and 6111 between the wiring sections. That is, the adhesion to the resin molded body 30 is improved. Therefore, on the opposite side of the roughened portions 54 and 64, the tensile force generated by resin shrinkage is higher, and thermal stress is more likely to concentrate at the three-point 100.

[0111] If the resin molded body 30 shrinks, the fragile layer 101, whose Young's modulus is smaller than that of the insulating substrates 51 and 61, undergoes elastic deformation. The fragile layer 101 deforms significantly beyond its yield point. In other words, the fragile layer 101... Figure 12 The figure shows significant deformation in the Z direction. The fragile layer 101 mitigates the tensile force associated with resin shrinkage.

[0112] Figure 13 This is a sectional view representing a reference example. Figure 13 Corresponding to Figure 12 In the semiconductor device 20R of the reference example, the fragile layer 101 is not provided on the exposed portion 6111 between wirings. Other structures are the same as those of the semiconductor device 20. In the structure shown in the reference example, if the resin molded body 30... Figure 13 As the arrows indicate contraction, thermal stress concentrates at the three-point point 100. This can potentially lead to cracks in the insulating substrates 51 and 61.

[0113] <Summary of the First Implementation>

[0114] The semiconductor device 20 of this embodiment includes substrates 50 and 60, a semiconductor element 40, and a resin molded body 30. The insulating substrates 51 and 61 of the substrates 50 and 60 have exposed surfaces 511 and 611. The semiconductor device 20 includes a fragile layer 101, which is stacked on at least a portion of the exposed surfaces 511 and 611 and sandwiched between the insulating substrates 51 and 61 and the resin molded body 30, and has a lower yield point than the insulating substrates 51 and 61. Therefore, during the shrinkage of the resin molded body 30 before curing, the fragile layer 101 deforms significantly beyond its yield point, i.e., undergoes plastic deformation. This reduces the thermal stress acting on the insulating substrates 51 and 61.

[0115] As illustrated, the structure can also be configured such that the Young's modulus of the fragile layer 101 is smaller than that of the insulating substrates 51 and 61. Since the fragile layer 101 is softer than the insulating substrates 51 and 61, thermal stress can be reduced through elastic deformation of the fragile layer 101 during the shrinkage of the resin molded body 30 before curing. By providing a fragile layer 101 with a lower yield point and a smaller Young's modulus than the insulating substrates 51 and 61, deformation can be achieved in both the elastic and plastic regions, effectively reducing the thermal stress acting on the insulating substrates 51 and 61. Alternatively, the structure can be configured such that the Young's modulus of the fragile layer 101 is greater than or equal to that of the insulating substrates 51 and 61.

[0116] As illustrated, in a structure where surface metal bodies 52 and 62 have a first wiring and a second wiring disposed next to the first wiring at a predetermined gap, the fragile layer 101 can also be stacked and disposed on the exposed wiring portions 5111 and 6111 exposed through the gap. In the illustrated semiconductor device 20, for example, P wiring 521 and N wiring 621 correspond to the first wiring, and relay wirings 522 and 622 correspond to the second wiring.

[0117] At the exposed portions 5111 and 6111 between the wirings, a triple point 100 based on the first wiring, the insulating substrates 51 and 61, and the resin molded body 30, and a triple point 100 based on the second wiring, the insulating substrates 51 and 61, and the resin molded body 30 are formed. Furthermore, since the wirings are located on both sides, stress tends to concentrate. However, by providing the fragile layer 101, the thermal stress acting on the insulating substrates 51 and 61 at the exposed portions 5111 and 6111 between the wirings can be reduced.

[0118] As illustrated, the substrate may also include a first substrate and a second substrate arranged to sandwich the semiconductor element 40. Furthermore, the first substrate may have exposed wiring portions, and the second substrate may have low-density and high-density portions on its opposing surface opposite the first substrate. The high-density portion is arranged to overlap with the exposed wiring portions when viewed from above, and has a higher adhesion force relative to the resin molded body compared to the low-density portion. In the illustrated semiconductor device 20, one of the substrates 50 and 60 corresponds to the first substrate, and the other corresponds to the second substrate.

[0119] As described above, if there is a high-density area on the opposing surfaces of the exposed portion between the wiring, the tensile force acting on the exposed portion side of the wiring becomes higher. However, by providing the fragile layer 101, the thermal stress acting on the insulating substrates 51 and 61 due to the deformation of the fragile layer 101 can be reduced. In the semiconductor device 20 with a two-sided heat dissipation structure, the insulation reliability can be improved.

[0120] As illustrated, the high-density areas can be roughened into roughened areas 54 and 64, and the low-density areas can be unroughened into unroughened areas 55 and 65. The roughened areas 54 and 64 can improve the adhesion to the resin molded body 30.

[0121] As illustrated, the brittle layer 101 may comprise any one of polyamide-imide, polyamide, and polyimide. The brittle layer 101 comprising these resins has a lower yield point compared to the insulating substrates 51 and 61 comprising epoxy resin. Furthermore, the brittle layer 101 has a lower Young's modulus compared to the insulating substrates 51 and 61. Therefore, the aforementioned effects are achieved.

[0122] The semiconductor device 20 of this embodiment includes substrates 50 and 60, a semiconductor element 40, and a resin molded body 30. The insulating substrates 51 and 61 of the substrates 50 and 60 have exposed surfaces 511 and 611. The semiconductor device 20 includes an intercalation layer comprising any one of polyamide-imide, polyamide, and polyimide, which is laminated on at least a portion of the exposed surfaces 511 and 611 and sandwiched between the insulating substrates 51 and 61 and the resin molded body 30. During the shrinkage of the resin molded body 30 before curing, the intercalation layer deforms significantly beyond its yield point, i.e., undergoes plastic deformation. This reduces the thermal stress acting on the insulating substrates 51 and 61.

[0123] <Variation Example>

[0124] The high-density adhesion portion is not limited to the roughened portions 54 and 64. For example, a material with better adhesion to the resin molded body 30 than the insulating substrates 51 and 61 may also be applied.

[0125] Examples of high-density sections (roughened sections 54, 64) are shown, but the invention is not limited to these examples. A structure without high-density sections may also be provided.

[0126] An example is shown where the vulnerable layer 101 is provided on the exposed portions 5111 and 6111 between wiring sections, but this is not a limitation. It may also be provided on the peripheral exposed portions 5112 and 6112. For example, as... Figure 14 As shown, it can also be provided on both the exposed wiring portions 5111 and 6111 and the exposed peripheral portions 5112 and 6112. The fragile layer 101 can also be provided on other surfaces that the resin molded body 30 contacts.

[0127] While an example of a semiconductor device 20 having two substrates 50 and 60 is shown, it is not limited to this. The semiconductor device 20 may also have only one substrate. For example, it may be configured such that the substrate is disposed on the drain electrode 41 side, the drain electrode 41 is connected to a first wiring of the substrate, and the source electrode 42 is connected to a second wiring of the substrate via a metal plate such as a clip or a bonding wire. By providing a fragile layer 101 on the exposed portion between the first and second wirings, the fragile layer 101 deforms significantly beyond the yield point during the shrinkage of the resin molded body 30 before curing, thereby reducing the thermal stress acting on the insulating substrate.

[0128] (Other implementation methods)

[0129] The disclosure in this specification and accompanying drawings is not limited to the illustrated embodiments. This disclosure includes illustrated embodiments and modifications made by those skilled in the art based on them. For example, this disclosure is not limited to the combinations of devices and / or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure may have additional portions that can be added to the embodiments. The disclosure includes schemes that omit devices and / or elements of the embodiments. This disclosure includes substitutions or combinations of devices and / or elements between one embodiment and other embodiments. The scope of the disclosure is not limited to the description of the embodiments. Several technical scopes of the disclosure are expressed by the description in the claims, and should be understood to also include all modifications within the meaning and scope equivalent to the description in the claims.

[0130] The disclosure in the specification and drawings is not limited to the claims. The disclosure includes the technical ideas described in the claims, and further encompasses a wider variety of technical ideas than those described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification and drawings, without being limited to the claims.

[0131] When referring to an element or layer as "on," "connected to," "linked to," or "combined with," it sometimes means that it is directly on, connected to, linked to, or combined with other elements or layers, and sometimes there are intervening elements or intervening layers. Conversely, when referring to an element as "directly on," "directly connected to," "directly linked to," or "directly combined with" other elements or layers, there are no intervening elements or intervening layers. Other terms used to describe relationships between elements should be interpreted in the same way (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.). As used in this specification, the term "and / or" includes any and all combinations related to one or more of the associated listed items. That is, the description of A and / or B refers to at least one of A and B.

[0132] To facilitate the description of the relationship between one element or feature and other elements or features as illustrated in the figures, spatially relative terms such as "inner," "outer," "back," "lower," "lower," "upper," and "higher" are used. These spatially relative terms are intended to encompass not only the orientations depicted in the figures but also different orientations of the device during use or operation. For example, when the device in the figure is flipped, the element described as "lower" or "directly below" other elements or features will face "upper" of those other elements or features. Therefore, the term "lower" can encompass both upward and downward orientations. The device may also face other directions (it may rotate 90 degrees or rotate in other directions), and the spatially relative descriptions used in this specification should be interpreted accordingly.

[0133] As a semiconductor device 20, an example of a 2-in-1 package providing one phase of upper and lower arm circuit 9 is shown, but it is not limited thereto. The semiconductor device 20 may be, for example, a 1-in-1 package providing one arm, or a 6-in-1 package.

Claims

1. A semiconductor device, characterized in that, have: A substrate having an insulating substrate comprising resin, a surface metal body disposed on the surface of the insulating substrate and patterned thereon, and a back metal body disposed on the back side of the insulating substrate; A semiconductor element having a first main electrode and a second main electrode disposed on a surface opposite to the first main electrode in the thickness direction, and electrically connected to the surface metal body; as well as A resin molded body that seals the substrate and the semiconductor element; The insulating substrate has an exposed surface that protrudes from the surface metal body. The semiconductor device has a fragile layer that is stacked on at least a portion of the exposed surface and sandwiched between the insulating substrate and the resin molded body, and has a lower yield point than the insulating substrate.

2. The semiconductor device according to claim 1, characterized in that, The Young's modulus of the fragile layer is smaller than that of the insulating substrate.

3. The semiconductor device according to claim 1 or 2, characterized in that, The surface metal body has a first wiring and a second wiring disposed next to the first wiring at a predetermined gap. The fragile layer is stacked on the exposed surface and exposed through the gap in the wiring section.

4. The semiconductor device according to claim 3, characterized in that, The substrate includes a first substrate and a second substrate arranged such that the semiconductor element is sandwiched between the second and first substrates in the thickness direction. The first substrate has the exposed portion between the wirings. The second substrate has a low-density portion and a high-density portion on the opposing surface opposite to the first substrate. The high-density portion is arranged to overlap with the exposed portion between the wiring when viewed from above along the thickness direction of the substrate. The adhesion force of the high-density portion relative to the resin molded body is higher than the adhesion force of the low-density portion relative to the resin molded body.

5. The semiconductor device according to claim 4, characterized in that, The high-density region is a roughened region, and the low-density region is a non-roughened region.

6. The semiconductor device according to claim 1 or 2, characterized in that, The fragile layer comprises any one of polyamide-imide, polyamide, and polyimide.

7. A semiconductor device, characterized in that, have: A substrate having an insulating substrate comprising resin, a surface metal body disposed on the surface of the insulating substrate and patterned thereon, and a back metal body disposed on the back side of the insulating substrate; A semiconductor element having a first main electrode and a second main electrode disposed on a surface opposite to the first main electrode in the thickness direction, and electrically connected to the surface metal body; as well as A resin molded body that seals the substrate and the semiconductor element; The insulating substrate has an exposed surface that protrudes from the surface metal body. The semiconductor device includes an intercalation layer comprising any one of polyamide-imide, polyamide, and polyimide, which is laminated on at least a portion of the exposed surface and disposed between the insulating substrate and the resin molded body.

Images