A heterogeneous stacked packaging substrate and its fabrication method

Abstract

This invention relates to the field of packaging substrates, and particularly to a heterogeneous stacked packaging substrate and its manufacturing method. The packaging substrate contains a glass core plate, and one or more first core plates are located between the surface of the packaging substrate and the glass core plate; one or more circuit layers are located between the glass core plate and the first core plates; one or more circuit layers are located between the first core plates; one or more circuit layers are located between the first core plates and the surface of the substrate; the packaging substrate contains metal pillars that connect the circuit layers. By using different dielectric materials and different core plates during the packaging substrate manufacturing process, the warping caused by expansion and contraction of the dielectric materials during stacking, as well as stress or temperature changes, can be effectively solved, effectively ensuring the flatness of large-size substrates during processing. This achieves a process where the upper layer has thin circuitry and the lower layer has thick circuitry, greatly improving the feasibility of manufacturing large-size packaging substrates.

Description

Technical Field

[0001] This invention relates to the field of packaging substrates, and in particular to a heterogeneous stacked packaging substrate and its manufacturing method. Background Technology

[0002] With the miniaturization of semiconductor manufacturing processes and the widespread application of artificial intelligence (AI) technology, large chips place higher demands on packaging materials, processes, and the supply chain. Technological advancements are driving increasing demands on the size of packaging substrates, leading the industry to propose increasing substrate size to integrate more components and chips. However, the fabrication process of large-size packaging substrates faces numerous challenges, including interlayer alignment deviations and inhomogeneous intralayer structures during lamination, as well as issues related to manufacturing yield and cost control. Among these, dimensional accuracy and warpage control during the manufacturing process are key to improving large-size substrate manufacturing technology. The dimensional error range of large-size substrates is typically at the micrometer level, and controlling substrate expansion, contraction, and warpage during manufacturing is a significant challenge. Furthermore, large-size substrates are prone to warpage during manufacturing due to material stress or temperature changes, which can affect assembly and signal transmission performance. Summary of the Invention

[0003] The purpose of this invention is to solve the aforementioned problems by designing a heterogeneous stacked packaging substrate and its fabrication method. To achieve the above objective, this invention provides the following solution:

[0004] A heterogeneous stacked packaging substrate includes a packaging substrate, wherein the packaging substrate contains a glass core plate, and one or more first core plates are located between the surface of the packaging substrate and the glass core plate.

[0005] The glass core board and the first core board contain one or more circuit layers; the first core boards contain one or more circuit layers; the first core board and the surface of the substrate contain one or more circuit layers.

[0006] The packaging substrate contains metal pillars that connect to the circuit layer.

[0007] As a further improvement to this technical solution, the first core board is made of resin.

[0008] As a further improvement to this technical solution, the glass core plate and the surface of the packaging substrate contain two or more dielectric materials, with the first dielectric material connected to the surface of the glass core plate and the second dielectric material connected to the first core plate; the first dielectric material and the second dielectric material are made of different materials.

[0009] As a further improvement to this technical solution, the glass core plate and the surface of the encapsulation substrate contain two or more dielectric materials, with the first dielectric material connected to the surface of the glass core plate and the second dielectric material connected to the first core plate; the first dielectric material and the second dielectric material are made of the same material, but the thicknesses of the first dielectric material and the second dielectric material are different.

[0010] The linewidth of the circuit layer between the glass core board and the first core board is greater than the linewidth of the circuit layer between the first core boards; the linewidth of the circuit layer between the first core boards is greater than the linewidth of the circuit layer between the first core board and the surface of the substrate.

[0011] The line spacing of the circuit layer between the glass core board and the first core board is greater than the line spacing of the circuit layer between the first core boards; the line spacing of the circuit layer between the first core boards is greater than the line spacing of the circuit layer between the first core board and the surface of the substrate.

[0012] A method for fabricating a heterogeneous stacked packaging substrate includes the following steps:

[0013] S1. Create the first middleware;

[0014] S2. Press the two first intermediate parts together to both sides of the detachable core board to obtain the second intermediate part;

[0015] S3. Arrange circuit layers on both sides of the second intermediate component and fabricate metal pillars to connect the circuit layers;

[0016] S4. Stack a second dielectric material on both sides of the second intermediate component;

[0017] S5. Stack the first core board on both sides of the second intermediate component;

[0018] S6. Arrange circuit layers and a second dielectric on both sides of the second intermediate component, and fabricate metal pillars to connect the circuit layers;

[0019] S7. Repeat S5 to S6;

[0020] S8. Remove the detachable core board to obtain two semi-finished parts;

[0021] S9. Arrange circuit layers on both sides of the semi-finished part, and fabricate metal pillars to connect the circuit layers;

[0022] S10. Apply a weld shielding layer.

[0023] As a further improvement to this technical solution, the specific steps for creating the first middleware are as follows:

[0024] S1a. A through hole is made in a glass core board, a circuit layer is arranged on both sides of the glass core board, and a metal pillar is arranged in the through hole, the metal pillar connecting the circuit layer;

[0025] S1b. Stack a first dielectric material on both sides of the glass core plate;

[0026] S1c. Arrange circuit layers on both sides of the glass core board;

[0027] S1d. Repeat S1b to S1c.

[0028] As a further improvement to this technical solution, the specific steps for pressing the two first intermediate parts onto both sides of the detachable core board to obtain the second intermediate part are as follows:

[0029] S2a. Stack the first dielectric material on both sides of the removable core board;

[0030] S2b. Stack the first intermediate piece on both sides of the removable core board.

[0031] As a further improvement to this technical solution, the first core board is in a cured state, and the first core board is made of a different material than the second dielectric.

[0032] A method for fabricating a heterogeneous stacked packaging substrate includes the following steps:

[0033] S1. A through hole is made in a glass core board, a circuit layer is arranged on both sides of the glass core board, and a metal pillar is arranged in the through hole, the metal pillar connecting the circuit layer;

[0034] S2. Stack a first dielectric material of thickness h1 on both sides of the detachable core board, and then stack the glass core board;

[0035] S3. Stack a first dielectric material of thickness h1 on both sides of the removable core board again;

[0036] S4. Lay out the wiring layers and make metal pillars to connect the wiring layers;

[0037] S5. Remove the removable core board;

[0038] S6. A first dielectric material with a thickness of h2 is then stacked on both sides of the glass core plate;

[0039] S7. Arrange circuit layers on both sides of the glass core board, and fabricate metal pillars to connect the circuit layers;

[0040] S8. Repeat S6 to S7;

[0041] S9. A first dielectric material with a thickness of h2 is stacked on both sides of the glass core plate;

[0042] S10. Stack the first core plate on both sides of the glass core plate;

[0043] S11. Lay out the wiring layers and make metal pillars to connect the wiring layers;

[0044] S12. Stack a second dielectric material on both sides of the glass core plate;

[0045] S13. Arrange circuit layers on both sides of the glass core board and stack a second dielectric material to create metal pillars connecting the circuit layers;

[0046] S14. Repeat S12 to S13;

[0047] S15. Apply a weld shielding layer.

[0048] As a further improvement to this technical solution, the thickness h1 of the first dielectric is greater than the thickness h2 of the first dielectric.

[0049] Beneficial effects:

[0050] This invention proposes a heterogeneous stacked packaging substrate and its fabrication method. By combining different dielectric materials and different core boards during the substrate fabrication process, it effectively solves the warping caused by expansion and contraction of dielectric materials during stacking, as well as stress or temperature changes, thus ensuring flatness during the processing of large-size substrates. Furthermore, the combination of different dielectric materials allows for the fabrication of thin upper layers and thick lower layers, greatly improving the feasibility of manufacturing large-size packaging substrates. Attached Figure Description

[0051] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.

[0052] Figure 1 This is one of the structural schematic diagrams of a heterogeneous stacked packaging substrate according to the present invention;

[0053] Figure 2 This is a second schematic diagram of the structure of a heterogeneous stacked packaging substrate according to the present invention;

[0054] Figures 3a to 3d This is a cross-sectional schematic diagram of the fabrication process of the first intermediate component and the second intermediate component of the heterogeneous stacked packaging substrate according to the present invention.

[0055] Figures 4a to 4f This is a cross-sectional schematic diagram of the fabrication process of a heterogeneous stacked packaging substrate according to the present invention;

[0056] Figures 5a to 5g This is a cross-sectional schematic diagram of the fabrication process of another heterogeneous stacked packaging substrate according to the present invention.

[0057] Figure label:

[0058] 100, Second dielectric material; 101a, First surface; 101b, First solder resist layer; 102a, Second surface; 102b, Second solder resist layer; 200, First core board; 300, First dielectric material; 400, Glass core board; 401, First surface of glass core board; 402, Second surface of glass core board; 500, Circuit layer; 500a, Copper layer; 501, Metal pillar; 600, Removable core board. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0060] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” and “described” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this specification means the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0061] The present invention will now be described in detail with reference to the accompanying drawings.

[0062] Example 1:

[0063] like Figure 1 The diagram shows a structural schematic of a heterogeneous stacked packaging substrate.

[0064] The heterogeneous stacked packaging substrate includes a packaging substrate having a first surface 101a and a second surface 102a. The packaging substrate contains a glass core plate 400, which has a first surface 401 and a second surface 402. The first surface 401 and the first surface 101a of the packaging substrate are located on one side, and the second surface 402 and the second surface 102a of the packaging substrate are located on one side. A first core plate 200 is located between the first surface 401 and the first surface 101a of the packaging substrate.

[0065] One or more circuit layers 500 are contained between the first surface 401 of the glass core board and the first core board 200. The circuit layers 500 are contained in two dielectric materials. The first dielectric material 300 directly connected to the first surface 401 of the glass core board is PP, and the second dielectric material 100 directly connected to the first core board 200 is ABF. The one or more circuit layers 500 are connected by metal pillars 501.

[0066] One or more circuit layers 500 are contained between the first core board 200 and the first surface 101a of the packaging substrate. These circuit layers are contained within the second dielectric 100 and connected by metal pillars 501. The metal pillars 501 pass through the first core board 200 and connect the circuit layers 500 on both sides of the first core board 200.

[0067] Except for the parts where other devices, lines or solder balls are placed, the first surface 101a of the packaging substrate is covered with a first solder resist layer 101b. The first solder resist layer 101b prevents the packaging substrate from being corroded by moisture, dust and other factors, and provides electrical insulation protection.

[0068] One or more circuit layers 500 are contained between the second surface 402 of the glass core board and the second surface 102a of the encapsulation substrate. The circuit layers 500 are contained within a dielectric material, which is a first dielectric material 300, i.e., PP. The circuit layers 500 are connected by metal pillars 501. Except for the areas where other devices, circuits, or solder balls are placed, the second surface 102a of the encapsulation substrate is covered with a second solder resist layer 102b.

[0069] The glass core board 400 contains a metal pillar 501, which connects the circuit layers 500 on both sides of the glass core board 400.

[0070] Example 2:

[0071] like Figure 2 The diagram shows a structural schematic of a heterogeneous stacked packaging substrate.

[0072] The heterogeneous stacked packaging substrate includes a packaging substrate having a first surface 101a and a second surface 102a. The packaging substrate contains a glass core plate 400, which has a first surface 401 and a second surface 402. The first surface 401 and the first surface 101a of the packaging substrate are located on one side, and the second surface 402 and the second surface 102a of the packaging substrate are located on one side. A first core plate 200 is located between the first surface 401 and the first surface 101a of the packaging substrate. A first core plate 200 is also located between the second surface 402 and the second surface 102a of the packaging substrate.

[0073] One or more circuit layers 500 are contained between the first surface 401 of the glass core board and the first core board 200. The circuit layers 500 are contained within a first dielectric 300, which is PP or ABF. The dielectric between two adjacent circuit layers 500 is a single dielectric layer. The first dielectric 300 directly connected to the first surface 401 of the glass core board is the first layer of first dielectric 300, with a thickness of h1. The first dielectric 300 directly connected to the first core board 200 is the last layer of first dielectric 300. Except for the first dielectric layer, the thickness of each other first dielectric layer 300 is h2. The thickness h1 of the first dielectric layer 300 is greater than the thickness h2 of the other first dielectric layers 300. Preferably, the thickness h1 of the first dielectric layer 300 is 35 μm, and the thickness h2 of the other first dielectric layers 300 is 20 μm. The circuit layers 500 are connected by metal pillars 501.

[0074] One or more circuit layers 500 are contained between the first core board 200 and the first surface 101a of the packaging substrate. These circuit layers are contained within the second dielectric 100 and connected by metal pillars 501. The metal pillars 501 pass through the first core board 200 and connect the circuit layers 500 on both sides of the first core board 200.

[0075] Except for the parts where other devices, lines or solder balls are placed, the first surface 101a of the packaging substrate is covered with a first solder resist layer 101b. The first solder resist layer 101b prevents the packaging substrate from being corroded by moisture, dust and other factors, and provides electrical insulation protection.

[0076] One or more circuit layers 500 are contained between the second surface 402 of the glass core board and the first core board 200. The circuit layers 500 are contained within a first dielectric 300, which is PP or ABF. The dielectric between two adjacent circuit layers 500 is a single dielectric layer. The first dielectric 300 directly connected to the second surface 402 of the glass core board is the first layer of first dielectric 300, with a thickness of h1. The first dielectric 300 directly connected to the first core board 200 is the last layer of first dielectric 300. Except for the first layer of first dielectric 300, the thickness of each other layer of first dielectric 300 is h2. The thickness h1 of the first layer of first dielectric 300 is greater than the thickness h2 of the other layers of first dielectric 300. Preferably, the thickness h1 of the first layer of first dielectric 300 is 35 μm, and the thickness h2 of the other layers of first dielectric 300 is 20 μm. The circuit layers 500 are connected by metal pillars 501.

[0077] One or more circuit layers 500 are contained between the first core board 200 and the second surface 102a of the packaging substrate. These circuit layers are contained within the second dielectric 100 and connected by metal pillars 501. The metal pillars 501 pass through the first core board 200 and connect the circuit layers 500 on both sides of the first core board 200.

[0078] Except for the parts where other devices, circuits or solder balls are placed, the second surface 102a of the packaging substrate is covered with a second solder resist layer 102b.

[0079] Example 3:

[0080] like Figures 3a to 3d The figure shows a cross-sectional schematic diagram of the fabrication process of a first intermediate component and a second intermediate component of a heterogeneous stacked packaging substrate.

[0081] Through-holes are machined mechanically or laser-processed in the center of the glass core board 400. Ultrasonic cleaning or chemical cleaning agents are used to remove residual particles or debris from the holes to avoid affecting subsequent processing. Cleaning can use alkaline solutions to remove organic contaminants and acidic solutions to dissolve residual metal ions. The surface of the glass core board 400 is activated using plasma or a silane coupling agent, followed by hot air drying to prevent moisture residue. A seed metal layer is deposited on the surface of the glass core board 400 using physical vapor deposition (PVD) or chemical vapor deposition (CVD). The seed metal material is typically copper (Cu), but molybdenum (Mo) and titanium (Ti) can also be used. A photoresist layer with a thickness of 1-5 μm is applied to the surface of the glass core board 400 using spin coating, followed by exposure and development. Electroplating is then used to form the circuit. By applying current, copper or other metals are deposited from the electrolyte onto the seed layer. This process requires control of electroplating time and current density to ensure uniform metal filling. This method is suitable for circuits with a linewidth less than 10 μm. Accelerators, inhibitors, and leveling agents can be added to the electroplating solution to improve electroplating quality. After electroplating, a flash etching process is performed to quickly remove the exposed seed layer metal. Excess photoresist is removed using NMP or a dedicated photoresist remover, or a dry plasma method such as oxygen removal can be used. Finally, the glass core board 400 is annealed in an inert gas environment to release the metal stress generated during electroplating and reduce the metal resistivity. Circuit layers 500 are formed on both sides of the glass core board 400, and metal pillars 501 inside the glass core board 400 connect the circuit layers 500 on both sides of the glass core board 400.

[0082] A first dielectric 300, made of polypropylene (PP), is stacked on both sides of a glass core board 400. Then, a copper layer 500a is stacked on both sides of the glass core board 400. After processes such as photoresist coating, exposure, and development, a circuit layer 500 and metal pillars 501 are obtained, which connect the different circuit layers 500. According to the design scheme, the first dielectric 300 and the circuit layers 500 and metal pillars 501 can be repeatedly stacked to finally obtain the first intermediate component.

[0083] A first dielectric 300 is stacked on both sides of a removable core board 600, and then a first intermediate component is stacked on both sides of the removable core board 600 to obtain a second intermediate component.

[0084] Example 4:

[0085] like Figures 4a to 4f The figure shows a cross-sectional schematic diagram of the fabrication process of a heterogeneous stacked packaging substrate.

[0086] Metallic copper layers 500a are stacked on both sides of the second intermediate component, and then after processes such as coating photoresist, exposure, and development, circuit layer 500 and metal pillar 501 are obtained. The metal pillar 501 connects the circuit layers 500 of different layers.

[0087] A second dielectric 100, made of ABF, is stacked on both sides of the second intermediate component. This second dielectric 100 is made of a different material than the first dielectric 300. A first core board 200, made of a different material than the second dielectric 100, is stacked on both sides of the second intermediate component. Preferably, it can be made of bismaleimide triazine, polyphenylene ether, or polyimide. Furthermore, the first core board 200 is in a fully cured state, i.e., the C-STAGE state. The first core board 200 can suppress the shrinkage stress generated by the curing of the dielectric material during the layering of the encapsulation substrate. Because the first core board 200 has high rigidity and is stacked on top of the glass core board 400, it can effectively suppress the shrinkage stress generated by the first dielectric 300 and the second dielectric 100 during the curing process during the layering of the encapsulation substrate, thereby effectively improving the overall flatness of the encapsulation substrate.

[0088] Holes are drilled on both sides of the second intermediate component using mechanical or laser methods. These holes should penetrate the first core board 200 and the second dielectric 100 until the circuit layer 500 is exposed. Next, hole cleaning, pretreatment, seed layer metal placement, photoresist coating, exposure, and development are performed. Circuit layers 500 and metal pillars 501 are then placed on both sides of the second intermediate component. The circuit layer 500 is connected to the lower circuit layer 500 through the metal pillars 501. The second dielectric 100 is stacked on both sides of the second intermediate component, and circuit layers 500 and metal pillars 501 are placed thereon, with the metal pillars 501 connecting the circuit layers 500. Multiple layers of the second dielectric 100, circuit layers 500, and metal pillars 501 can be stacked and fabricated according to the chip design. As the number of layers on both sides of the second intermediate component increases, the first core board 200 can also be stacked once or multiple times as needed to increase overall flatness.

[0089] After completing the second intermediate component as required, the removable core board 600 is removed, resulting in two identical semi-finished products. Holes are drilled on both sides of the semi-finished products using mechanical or laser methods, followed by hole cleaning, pretreatment, seed layer metal placement, photoresist coating, exposure, and development. Circuit layers 500 and metal pillars 501 are then placed on both sides of the semi-finished products, with the circuit layer 500 connected to the lower circuit layer 500 via the metal pillars 501. Finally, solder resist layers are applied to both surfaces of the semi-finished products. The first surface 101a is covered with the first solder resist layer 101b, except for areas connecting to other equipment, circuits, or where solder balls are placed; the second surface 102a is covered with the second solder resist layer 102b, except for areas connecting to other equipment, circuits, or where solder balls are placed, thus obtaining the final packaged substrate. This second solder resist layer 102b prevents the packaged substrate from being corroded by moisture, dust, etc., and provides electrical insulation protection.

[0090] Example 5:

[0091] like Figures 5a to 5g The figure shows a cross-sectional schematic diagram of the fabrication process of a heterogeneous stacked packaging substrate.

[0092] Through-holes are machined mechanically or laser-processed in the center of the glass core board 400. Ultrasonic cleaning or chemical cleaning agents are used to remove residual particles or debris from the holes to avoid affecting subsequent processing. Cleaning can use alkaline solutions to remove organic contaminants and acidic solutions to dissolve residual metal ions. The surface of the glass core board 400 is activated using plasma or a silane coupling agent, followed by hot air drying to prevent moisture residue. A seed metal layer is deposited on the surface of the glass core board 400 using physical vapor deposition (PVD) or chemical vapor deposition (CVD). The seed metal material is typically copper (Cu), but molybdenum (Mo) and titanium (Ti) can also be used. A photoresist layer with a thickness of 1-5 μm is applied to the surface of the glass core board 400 using spin coating, followed by exposure and development. Electroplating is then used to form the circuit. By applying current, copper or other metals are deposited from the electrolyte onto the seed layer. This process requires control of electroplating time and current density to ensure uniform metal filling. This method is suitable for circuits with a linewidth less than 10 μm. Accelerators, inhibitors, and leveling agents can be added to the electroplating solution to improve electroplating quality. After electroplating, a flash etching process is performed to quickly remove the exposed seed layer metal. Excess photoresist is removed using NMP or a dedicated photoresist remover, or a dry plasma method such as oxygen removal can be used. Finally, the glass core board 400 is annealed in an inert gas environment to release the metal stress generated during electroplating and reduce the metal resistivity. Circuit layers 500 are formed on both sides of the glass core board 400, and metal pillars 501 inside the glass core board 400 connect the circuit layers 500 on both sides of the glass core board 400.

[0093] A first dielectric 300, which may be made of PP, is stacked on both sides of a substrate containing a removable core board 600. The thickness of the first dielectric 300 is h1, preferably 35 μm. Glass core boards 400 are stacked on both sides of the removable core board 600.

[0094] A first dielectric 300, also with a thickness of h1, is stacked on both sides of the removable core board 600. A circuit layer 500 and metal pillars 501 are arranged on both sides of the removable core board 600, with the circuit layer 500 connected to the lower circuit layer 500 via the metal pillars 501. A first dielectric with a thickness of h2, less than h1, is stacked on both sides of the removable core board 600; preferably, 20 μm. After stacking copper layers 500a on both sides of the removable core board 600, the removable core board 600 is removed.

[0095] Circuit layers 500 and metal pillars 501 are arranged on both sides of the glass core board 400. The circuit layers 500 are connected to the lower circuit layers 500 through the metal pillars 501. A first dielectric 300 is stacked on both sides of the glass core board 400, and the thickness of the first dielectric 300 is also h2. According to the chip design requirements, multiple layers of circuit layers 500 and metal pillars 501, as well as multiple layers of first dielectric 300 can be arranged, and each circuit layer 500 is connected through the metal pillars 501. At the same time, the thickness of each layer of first dielectric 300 is h2.

[0096] After reaching the required number of circuit layers, a first dielectric 300 with a thickness of h2 is stacked on both sides of the glass core 400, followed by the stacking of the first core 200. The first core 200 is made of a different material than the second dielectric 100; preferably, it can be made of bismaleimide triazine, polyphenylene ether, polyimide, etc. Furthermore, the first core 200 is in a fully cured state, i.e., the C-STAGE state. Because the first core 200 has high rigidity and is stacked on top of the glass core 400, it can effectively suppress the shrinkage stress generated by the first dielectric 300 and the second dielectric 100 during the curing process when adding layers to the encapsulation substrate, thereby effectively improving the overall flatness of the encapsulation substrate.

[0097] Holes are drilled on both sides of the glass core board 400 using mechanical or laser methods. These holes should penetrate the first core board 200 and the first dielectric material 300 with a thickness of h2 until the circuit layer 500 is exposed. Next, hole cleaning, pretreatment, seed layer metal placement, photoresist coating, exposure, and development are performed. Circuit layers 500 and metal pillars 501 are then placed on both sides of the glass core board 400, with the circuit layer 500 connected to the lower circuit layer 500 via the metal pillars 501. A second dielectric material 100 is stacked on both sides of the glass core board 400, and circuit layers 500 and metal pillars 501 are placed thereon, with the metal pillars 501 connecting the circuit layers 500. Multiple layers of the second dielectric material 100, circuit layers 500, and metal pillars 501 can be stacked and fabricated according to the chip design. As the number of layers on both sides of the glass core board 400 increases, the first core board 200 can also be stacked once or multiple times as needed to increase overall flatness.

[0098] After achieving the required 500 circuit layers, solder resist layers are applied to both sides of the glass core board 400. The first surface 101a of the substrate, except for areas connecting to other equipment, circuits, or where solder balls are placed, is covered by the first solder resist layer 101b; the second surface 102a, except for areas connecting to other equipment, circuits, or where solder balls are placed, is covered by the second solder resist layer 102b, thus obtaining the final packaged substrate. The second solder resist layer 102b prevents the packaged substrate from being corroded by moisture, dust, etc., and provides electrical insulation protection.

[0099] In summary, the heterogeneous stacked packaging substrate and its fabrication method proposed in this invention effectively solve the warping problems caused by expansion and contraction of dielectric materials, as well as stress or temperature changes, during the stacking process by combining different dielectric materials and different core boards, thus ensuring the flatness of large-size substrates during processing. Furthermore, the combination of different dielectric materials allows for the fabrication of thin upper layers and thick lower layers, significantly improving the feasibility of fabricating large-size packaging substrates.

Claims

1. A heterogeneous stacked packaging substrate, characterized in that, The package substrate contains a glass core board, and one or more first core boards between the surface of the package substrate and the glass core board; One or more circuit layers between the glass core board and the first core board; one or more circuit layers between the first core boards; one or more circuit layers between the first core board and the surface of the substrate; The package substrate contains a metal column, which connects the circuit layer; The glass core board and the surface of the package substrate contain two or more dielectrics, the first dielectric is connected to the surface of the glass core board, and the second dielectric is connected to the first core board; the first dielectric and the second dielectric are different in material.

2. The heterogeneous stacked package substrate of claim 1, wherein, The first core board is resin.

3. The heterogeneous stacked package substrate of claim 1, wherein, The glass core board and the surface of the package substrate contain two or more dielectrics, the first dielectric is connected to the surface of the glass core board, and the second dielectric is connected to the first core board; the first dielectric and the second dielectric are different in material. The line width of the circuit layer between the glass core board and the first core board is greater than the line width of the circuit layer between the first core boards; the line width of the circuit layer between the first core boards is greater than the line width of the circuit layer between the first core board and the surface of the substrate; The line distance of the circuit layer between the glass core board and the first core board is greater than the line distance of the circuit layer between the first core boards; the line distance of the circuit layer between the first core boards is greater than the line distance of the circuit layer between the first core board and the surface of the substrate.

4. A method for manufacturing a heterogeneous stacked package substrate according to any one of claims 1 to 3, wherein The steps include: S1. Make a first intermediate piece; S2. Press two first intermediate pieces to both sides of a detachable core board to obtain a second intermediate piece; S3. Arrange the circuit layer on both sides of the second intermediate piece, and make a metal column to connect the circuit layer; S4. Stack the second dielectric on both sides of the second intermediate piece; S5. Stack the first core board on both sides of the second intermediate piece; S6. Arrange the circuit layer and the second dielectric on both sides of the second intermediate piece, and make a metal column to connect the circuit layer; S7. Repeat S5 to S6; S8. Remove the detachable core board to obtain two semi-finished pieces; S9. Arrange the circuit layer on both sides of the semi-finished piece, and make a metal column to connect the circuit layer; S10. Arrange the anti-solder layer.

5. The method of claim 4, wherein the substrate is a glass substrate. The specific steps for making a first intermediate piece are: S1a. Make a through hole in the glass core board, arrange the circuit layer on both sides of the glass core board, and arrange a metal column in the through hole, which connects the circuit layer; S1b. Stack the first dielectric on both sides of the glass core board; S1c. Arrange the circuit layer on both sides of the glass core board; S1d. Repeat S1b to S1c.

6. The method of claim 4, wherein the substrate is a glass substrate. The specific steps for pressing two first intermediate pieces to both sides of a detachable core board to obtain a second intermediate piece are: S2a. Stack the first dielectric on both sides of the detachable core board; S2b. Stack the first intermediate piece on both sides of the detachable core board.

7. The method of claim 4, wherein the substrate is a glass substrate. The first core board is in a cured state, and the material of the first core board is different from that of the second dielectric.

8. A method for manufacturing a heterogeneous stacked package substrate as claimed in any one of claims 1 to 3, characterized by, The steps include: S1. Make a via hole in a glass core board, arrange a circuit layer on both sides of the glass core board, arrange a metal column in the via hole, the metal column connecting the circuit layer; S2. Stack a first dielectric with a thickness of h1 on both sides of a detachable core board, and then stack the glass core board; S3. Stack a first dielectric with a thickness of h1 on both sides of the detachable core board again; S4. Arrange a circuit layer, and make a metal column to connect the circuit layer; S5. Remove the detachable core board; S6. Stack a first dielectric with a thickness of h2 on both sides of the glass core board again; S7. Arrange a circuit layer on both sides of the glass core board, and make a metal column to connect the circuit layer; S8. Repeat S6 to S7; S9. Stack a first dielectric with a thickness of h2 on both sides of the glass core board; S10. Stack a first core board on both sides of the glass core board; S11. Arrange a circuit layer, and make a metal column to connect the circuit layer; S12. Stack a second dielectric on both sides of the glass core board; S13. Arrange a circuit layer on both sides of the glass core board, and stack a second dielectric, and make a metal column to connect the circuit layer; S14. Repeat S12 to S13; S15. Arrange a solder resist layer.

9. The method of claim 8, wherein the substrate is a glass substrate. The thickness h1 is greater than the thickness h2.

Images