Multi-chip packaging structure and manufacturing method
By employing a vertical interconnect structure and simplified manufacturing steps in a multi-chip package structure, the complexity and high cost of three-dimensional stacked package structures are solved, enabling efficient and low-cost mass production.
Patent Information
- Application Number
- CN202511316621.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-16
- Publication Date
- 2025-12-12
AI Technical Summary
Existing three-dimensional stacked packaging structures have complex processes, low yields, high packaging costs, and are not suitable for mass production.
The multi-chip packaging structure includes a first chip inside the plastic package and a second chip located below it. The second chip is electrically connected to the first chip through a vertical interconnect structure. The redistribution layer is located at the bottom of the plastic package, and the production steps are simplified by using a temporary bonding pad, reducing the number of metal wiring preparations.
It simplifies the process flow, improves the integration and yield of the package, reduces packaging costs, and is suitable for mass production.
Smart Images
Figure CN121123138A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor packaging technology, specifically relating to a multi-chip packaging structure and its fabrication method. Background Technology
[0002] Traditional semiconductor packaging mostly involves packaging a single chip to protect it and interconnect it with the outside. With the development of advanced packaging technology, microsystem packaging has become an important part of miniaturized electronic products. Microsystem packaging packages multiple micro-devices of different types and functions (such as sensor chips, information processing chips, and memory chips) together through three-dimensional stacking and high-density interconnection to form a system with multiple functions, thereby realizing the complete functions of specific application scenarios.
[0003] Among them, the three-dimensional stacked packaging structure is mostly formed by interconnecting multiple chips horizontally with redistribution metal layers to form a horizontal fan-out structure, and interconnecting multiple chips vertically with interconnection metal pillars and redistribution metal layers to form a vertical fan-out structure. Finally, the metal redistribution layers of different chip layers are brought out to the surface of the device to form the entire 3D-FO (three-dimensional fan-out package) device. This packaging solution has many process flows, complex operation, requires multiple RDL (routing layer) and vertical interconnection metal pillar preparations, has low yield, high packaging cost, and is not suitable for mass production. Summary of the Invention
[0004] This invention provides a multi-chip packaging structure and manufacturing method, aiming to solve the technical problems of existing three-dimensional stacked packaging structures, such as complex processes, complicated operations, low yield, high packaging costs, and unsuitability for mass production.
[0005] In a first aspect, embodiments of the present invention provide a multi-chip packaging structure, comprising: Plastic encapsulation; At least one first chip is encapsulated within the encapsulation body; The second chip is encapsulated within the encapsulation body. The second chip is located below the first chip. The projected area of the second chip in the vertical direction covers all of the first chip. A vertical interconnect structure electrically connected to the first chip is penetrating through the second chip in the vertical direction. The lower end of the vertical interconnect structure is exposed on the bottom surface of the encapsulation body. A redistribution layer is disposed at the bottom of the molding compound. The redistribution layer has a first electrical connection point that is electrically connected to the vertical interconnect structure and the pins of the second chip, and a second electrical connection point that is electrically connected to the first electrical connection point. The first connecting protrusion is electrically connected to the second electrical connection point.
[0006] The solution shown in the embodiments of this application, compared with the prior art: (1) The chip of this application has two sides, namely the horizontal layer where the first chip is located and the horizontal layer where the second chip is located. Compared with the traditional structure that stacks three or more layers in the vertical direction, this structure facilitates the stacking operation between chips, simplifies the process flow, is easy to operate, and is conducive to mass production.
[0007] (2) Traditionally, metal wiring is set at the bottom of each chip layer, and metal pillars that penetrate the plastic package of the remaining chip layers are electrically connected to the metal wiring. In this structure, in addition to arranging the chip, metal pillars need to be set on the outer periphery of the chip in each layer. Therefore, even if three or more layers are set, the high integration of the package is not achieved, and the area of the package is increased. In this application, the first chip is located on the upper layer of the second chip and is connected to the first chip through a vertical interconnect structure that penetrates the second chip. The vertical interconnect structure does not occupy the area on the outer periphery of the second chip, and all the first chips are within the vertical projection range of the second chip. After packaging, the vertical projection area of the entire package is close to the vertical projection area of the second chip (the difference is only the thickness of the plastic package on the outer periphery of the second chip). The package structure has higher integration, smaller coverage area, and only requires one redistribution layer, resulting in higher yield. It avoids multiple preparations of metal wiring and improves packaging efficiency.
[0008] In conjunction with the first aspect, in one possible implementation, the bottom surface of the second chip is flush with the bottom surface of the molding compound.
[0009] In conjunction with the first aspect, in one possible implementation, the vertical interconnect structure includes: An electrical via is used to penetrate the second chip vertically. A conductive metal is filled in the via. The second connection bump corresponds one-to-one with the conductive metal and is electrically connected to the first chip.
[0010] In conjunction with the first aspect, in one possible implementation, the second connecting bump is one or more combinations of a gold ball bump and a gold-tin bump.
[0011] In conjunction with the first aspect, in one possible implementation, multiple first chips are provided, with the top surfaces of the multiple first chips flush and spaced apart from the top surface of the molding compound.
[0012] In conjunction with the first aspect, in one possible implementation, the rewiring layer includes fan-out components corresponding one-to-one with the vertical interconnect structure. The fan-out components include a plurality of lead-out units stacked in the vertical direction. Each lead-out unit has a third connection bump at its top. The third connection bump of the uppermost lead-out unit is electrically connected to the vertical interconnect structure, and the lowermost lead-out unit is electrically connected to the first connection bump.
[0013] In conjunction with the first aspect, in one possible implementation, multiple lead-out units in the same fan-out component are staggered along the horizontal direction.
[0014] Secondly, embodiments of the present invention also provide a method for fabricating a multi-chip package structure, which includes the following steps: S10: Fabricate a vertical interconnect structure on the second chip; S20: Using a stacking device, all the first chips are stacked on top of the second chip and electrically connected to the vertical interconnect structure to form a chip assembly; S30: The chip assembly is mounted on a temporary bonding carrier, with the second chip facing down; S40: Molding is performed on the outer periphery of the chip assembly to form a molded wafer; S50: Separate the molded wafer from the temporary bonding carrier, flip the molded wafer and reinstall it on the temporary bonding carrier, with the second chip facing upwards at this time; S60: At this time, wiring and solder joint preparation are performed on the upward-facing surface of the second chip to form a wafer; S70: Divide the wafer after separating it from the temporary bonding carrier.
[0015] The solution shown in the embodiments of this application, compared with the prior art: By using a temporary bonding carrier, the first chip can be easily assembled on the top surface of the second chip, and the redistribution layer and the first connection bump can be assembled on the bottom surface of the second chip. With the second chip as the center, two operations are performed on the top and bottom of the second chip respectively, and only one wiring process is required. The complex three-dimensional stacking and molding and wiring are broken down into standardized operations, replacing the cumbersome process of multiple stacking, multiple molding and multiple wiring in the traditional way, simplifying the production steps and making it suitable for mass production. Temporary bonding carriers can fix chip components and molded wafers, preventing chip displacement during processing, improving the dimensional accuracy of the entire packaging structure, and optimizing yield.
[0016] In conjunction with the second aspect, in one possible implementation, the chip assembly and the temporary bonding carrier, and the molded wafer and the temporary bonding carrier, are bonded together by temporary bonding adhesive.
[0017] In conjunction with the second aspect, in one possible implementation, the wiring process includes thin film deposition, photolithography, etching, and dielectric layer fabrication processes. Attached Figure Description
[0018] Figure 1 This is a cross-sectional view of the multi-chip packaging structure provided in an embodiment of the present invention; Figure 2 A schematic diagram corresponding to step S10 of the method for fabricating a multi-chip package structure provided in an embodiment of the present invention; Figure 3 A schematic diagram corresponding to step S20 of the method for fabricating a multi-chip package structure provided in an embodiment of the present invention; Figure 4 A schematic diagram corresponding to step S30 of the method for fabricating a multi-chip package structure provided in an embodiment of the present invention; Figure 5 A schematic diagram corresponding to step S40 of the method for fabricating a multi-chip package structure provided in an embodiment of the present invention; Figure 6 A schematic diagram corresponding to step S50 of the method for fabricating a multi-chip package structure provided in an embodiment of the present invention; Figure 7 A schematic diagram corresponding to step S60 of the method for fabricating a multi-chip package structure provided in an embodiment of the present invention.
[0019] Explanation of reference numerals in the attached figures: 10 - Molded body; 20 - First Chip; 30 - Second chip; 31 - Vertical interconnect structure; 311 - Conductive metal; 312 - Second connection bump; 40 - Rewiring layer; 41 - Fan-out component; 42 - Lead-out unit; 43 - First electrical connection point; 44 - Second electrical connection point; 50 - First connecting protrusion; 60 - Temporary bond carrier disk. Detailed Implementation
[0020] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.
[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this application or its application or use. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0022] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0023] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore should not be construed as limiting the scope of protection of this invention.
[0024] Please refer to the following: Figures 1 to 7 The multi-chip package structure provided by the present invention will now be described. The multi-chip package structure includes a molding compound 10, at least one first chip 20, a second chip 30, a redistribution layer 40, and a first connection bump 50. The first chip 20 is encapsulated within the molding compound 10; the second chip 30 is encapsulated within the molding compound 10, located below the first chip 20, and the vertically projected area of the second chip 30 covers all of the first chips 20. A vertical interconnect structure 31, electrically connected to the first chip 20, penetrates vertically within the second chip 30, and the lower end of the vertical interconnect structure 31 is exposed on the bottom surface of the molding compound 10; the redistribution layer 40 is disposed at the bottom of the molding compound 10, and the redistribution layer 40 has a first electrical connection point 43 electrically connected to the pins of the vertical interconnect structure 31 and the second chip 30, and a second electrical connection point 44 electrically connected to the first electrical connection point 43; the first connection bump 50 is electrically connected to the second electrical connection point 44.
[0025] The first chip 20 is, for example, a compound chip, and the second chip 30 is, for example, a CMOS chip (an integrated circuit chip manufactured based on complementary metal-oxide-semiconductor technology). The first chip 20 and the second chip 30 can be paired as a compound chip + compound chip combination or a compound chip + CMOS chip combination. The second chip 30 is equivalent to a base chip. When it is necessary to expand other functions based on the second chip 30, a first chip 20 with corresponding functions (equivalent to a patch) is selected and assembled with the second chip 30 to obtain a package with the required functions. The first connecting bump 50 in the package structure is used for soldering to the circuit board to achieve electrical conduction.
[0026] Therefore, the second chip 30 is larger than the first chip 20, and all the first chips 20 are located above the second chip 30 and are electrically connected to the vertical interconnect structure 31 on the second chip 30. They are also electrically connected to the first connection bump 50 at the bottom through the vertical interconnect structure 31, which facilitates access to the circuit board. In addition, the first chip 20 and the second chip 30 are also electrically connected through the second connection bump 312 described below to achieve signal conduction. The second connection bump 312 is soldered to the corresponding pads on the first chip 20 and the second chip 30.
[0027] It should be noted that the molding compound 10 is an epoxy resin-based composite material, which mainly includes matrix resin, filler (e.g., fused silica powder), curing agent (e.g., phenolic resin), and additives (e.g., coupling agent, flame retardant, colorant), and can achieve the effects of mechanical support, moisture protection, corrosion protection, heat dissipation and electrical insulation on the outer periphery of the chip.
[0028] The chip packaging structure provided in this embodiment, compared with the prior art: (1) The chip of this application is distributed on both sides, namely the horizontal layer where the first chip 20 is located and the horizontal layer where the second chip 30 is located. Compared with the traditional structure that stacks three or more layers in the vertical direction, this structure facilitates the stacking operation between chips, simplifies the process flow, is easy to operate, and is conducive to mass production.
[0029] (2) Traditionally, metal wiring is set at the bottom of each chip layer, and metal pillars that penetrate the plastic package 10 of the remaining chip layers are electrically connected to the metal wiring. In this structure, in addition to arranging the chip, metal pillars need to be set on the outer periphery of the chip in each layer. Therefore, even if three or more layers are set, the high integration of the package is not achieved, and the area of the package is increased. In this application, the first chip 20 is located on the upper layer of the second chip 30 and is connected to the first chip 20 through the vertical interconnect structure 31 that penetrates the second chip 30. The vertical interconnect structure 31 does not occupy the area of the outer periphery of the second chip 30, and all the first chips 20 are within the vertical projection range of the second chip 30. After packaging, the vertical projection area of the entire package is close to the vertical projection area of the second chip 30 (the difference is only the thickness of the plastic package 10 on the outer periphery of the second chip 30). The package of this structure has higher integration, smaller coverage area, and only requires one redistribution layer 40. The yield is higher, the multiple preparation of metal wiring is avoided, and the packaging efficiency is improved.
[0030] In some embodiments, a specific implementation of the above-described multi-chip packaging structure may employ, as follows: Figure 1 The structure shown. See also Figure 1 The bottom surface of the second chip 30 is flush with the bottom surface of the molding compound 10. After the first chip 20 and the second chip 30 are assembled, the second chip 30 can be placed face down on a large flat surface, and a mold can be placed around the second chip 30. Molding material is poured into the space between the mold and the chip, and after solidification, the molding compound 10 is formed. The mold shape corresponding to this structure is simple, and there is no need to ensure that there is a height difference between the bottom surface of the molding compound 10 and the bottom surface of the second chip 30, which facilitates the molding operation, shortens the molding time, and improves the molding efficiency. After molding, since the bottom surface of the second chip 30 is flush with the bottom surface of the molding compound 10, the vertical interconnect structure 31 on the second chip 30 can be directly exposed after molding, which facilitates the installation of the redistribution layer 40 under the second chip 30. Compared with reprocessing to expose the vertical interconnect structure 31, the risk of chip damage caused by subsequent processing can be avoided.
[0031] In some embodiments, a specific implementation of the vertical interconnect structure 31 described above can adopt the following approach: Figure 1 The structure shown. See also Figure 1 The vertical interconnect structure 31 includes an electrical via, conductive metal, and a second connecting bump 312. The electrical via penetrates the second chip 30 in a vertical direction. The conductive metal 311 fills the electrical via. The second connecting bump 312 corresponds one-to-one with the conductive metal 311 and is electrically connected to the first chip 20.
[0032] The via penetrates the second chip 30 vertically. Compared to an inclined direction, the vertical path is shorter and occupies less internal space of the second chip 30, without damaging the circuit structure on the second chip 30, ensuring the stable function of the second chip 30 and enabling high integration of the second chip 30. The conductive metal 311 fills the via, enabling conductive connection between the first chip 20 and the lower redistribution layer 40. The second connection bump 312 on the top of the conductor metal is usually spherical, and the diameter of the second connection bump 312 is larger than the diameter of the via, which facilitates conductive connection with the pins on the first chip 20. In addition, the larger working surface makes operation more convenient, and the electrical connection stability with the first chip 20 is better, avoiding technical defects. The bumps allow a certain gap to be maintained between the first chip 20 and the second chip 30, which facilitates heat dissipation on the surfaces of the first chip 20 and the second chip 30. Furthermore, the conductive metal 311 penetrates the second chip 30, which can further conduct heat and extend the service life of the first chip 20 and the second chip 30.
[0033] Optionally, the second connecting bump 312 can be one or more combinations of gold ball bumps and gold-tin bumps. Specifically, different first chips 20 can correspond to second connecting bumps 312 of different materials. For example, the second connecting bump 312 corresponding to one first chip 20 can be a gold ball bump, and the second connecting bump 312 corresponding to another first chip 20 can be a gold-tin bump; or the second connecting bump 312 corresponding to each first chip 20 can be made of both gold ball material and gold-tin material, which can be selected according to actual production needs.
[0034] Both gold ball bumps and gold-tin bumps contain gold. Gold has high chemical stability and is not easily oxidized, corroded, or sulfided, which can ensure a relatively stable electrical connection effect and avoid increased contact resistance or open circuit. In addition, the bumps containing gold are smaller in size, making them suitable for chip-to-chip connections and meeting the requirements of high-density layout.
[0035] In addition, the second connecting bump 312 can be one or more of the following materials: solder-based alloy, copper-based composite structure, pure copper, conductive adhesive, etc.; the same applies to the first connecting bump 50.
[0036] In some embodiments, a specific implementation of the first chip 20 described above may employ the following approach: Figure 1 The structure shown. See also Figure 1Multiple first chips 20 are provided, with their top surfaces flush and spaced apart from the top surface of the molding compound 10. Since the top surface of the molding compound 10 needs to maintain a certain gap (more than 50 μm) with the first chips 20 to ensure the reliability of the first chips 20, if the multiple first chips 20 are of varying heights in the vertical direction, the top surface of the molding compound 10 needs to maintain the aforementioned gap with the top surface of the tallest first chip 20. This would increase the height of the molding compound 10 and the volume of the package structure, making it unsuitable for miniaturization. In this embodiment, the top surfaces of the multiple first chips 20 are flush, ensuring that the height of the molding compound 10 is minimized while meeting the aforementioned gap, thus meeting the requirements for miniaturization. The horizontal arrangement of the multiple first chips 20 allows for more uniform filling of the molding compound, reducing problems such as insufficient local molding thickness or bubbling caused by height differences, and improving the protective effect of the molding compound 10 on the chips.
[0037] In some embodiments, a specific implementation of the rewiring layer 40 described above may employ, as follows: Figure 1 The structure shown. See also Figure 1 The redistribution layer 40 includes fan-out components 41 corresponding one-to-one with the vertical interconnect structure 31. Each fan-out component 41 includes multiple lead-out units 42 stacked vertically. Each lead-out unit 42 has a third connection bump at its top. The third connection bump of the uppermost lead-out unit 42 is electrically connected to the vertical interconnect structure 31, and the lowermost lead-out unit 42 is electrically connected to a first connection bump 50. That is, the third connection bump of the uppermost lead-out unit forms a first electrical connection point 43, and the lower part of the lowermost lead-out unit also has a third connection bump forming a second electrical connection point 44.
[0038] It should be noted that some of the fan-out components 41 correspond one-to-one with the vertical interconnect structure 31, while the remaining fan-out components 41 correspond to the pads at the bottom of the second chip 30. The lead-out unit 42 is the metal wire, and the third connection bump can be made of one or more of the following materials: solder-based alloy, copper-based composite structure, pure copper, conductive adhesive, etc.
[0039] The vertical interconnect structure 31 on the second chip 30 is relatively small. By setting the fan-out component 41, the vertical interconnect structure 31 can be electrically connected to the first connection bump 50 at the bottom. The first connection bump 50 is relatively large, which facilitates soldering operations with the circuit board.
[0040] Furthermore, multiple lead-out units 42 in the same fan-out component 41 are staggered in the horizontal direction. The vertical interconnect structure 31 on the second chip 30 is densely distributed. By staggering the lead-out units 42 in the horizontal direction, the spacing of the second electrical connection points 44 below can be increased, the lateral space can be expanded, and the arrangement of the first connection bump 50 can be facilitated. This allows for the redistribution of the pads on the first chip 20 and the second chip 30 in the lateral space, which is beneficial for achieving a more reliable connection with the circuit board. The staggered distribution in the horizontal direction also allows for flexible adjustment of the lead-out units 42, reducing wiring congestion and reducing cross-interference in signal transmission.
[0041] In addition, besides the lead-out unit 42 and the third connection bump, the redistribution layer 40 is also filled with resin material on the outer periphery of the fan-out component 41. After the resin material is filled, it conforms to the outer contour of the molding compound 10, thereby ensuring that the overall packaging structure has a regular shape and is convenient for subsequent processing. The resin here plays the same role as the molding compound 10.
[0042] Based on the same inventive concept, see [link to inventive concept] Figures 2 to 7 This application also provides a method for fabricating a multi-chip package structure, which includes the following steps: S10: Fabricate a vertical interconnect structure on the second chip 30. 31: Fabricate vias on the second chip 30 and fill them with conductive metal to facilitate conductivity. Fabricate second connection bumps 312 on the top of the second chip 30 so that some of the second connection bumps 312 correspond one-to-one with the vias, and the remaining second connection bumps 312 are soldered to the pads on the second chip 30. S20: Using a stacking device, all the first chips 20 are stacked on top of the second chip 30 and electrically connected to the vertical interconnect structure 31 to form a chip assembly. The stacking device can be a wafer bonding machine, a high-precision placement machine, etc. By arranging all the first chips 20 on top of the second chip 30 in a reasonable manner and soldering the first chips 20 to the first connection bumps 50, the electrical connection between the first chips 20 and the vertical interconnect structure 31 and the second chip 30 is achieved. S30: Install the chip assembly on the temporary bonding carrier 60, with the second chip 30 facing down: use temporary bonding adhesive to bond the second chip 30 downwards onto the temporary bonding carrier 60, the surface of the temporary bonding carrier 60 being larger than the vertical projection surface of the required package structure. S40: Molding the chip assembly to form a molded wafer: The outer surface of the chip assembly is cleaned, a mold is placed on the outer periphery of the chip assembly, and the mold can also be bonded to a temporary bonding carrier 60 using temporary bonding adhesive. Molding material is prepared and poured into the mold. Then it is sent to a curing oven and heated at a specific temperature to fully cross-link and cure the molding material to form a molding body 10. At this time, the molding body 10 and the chip assembly form a molded wafer. S50: Separate the molded wafer from the temporary bonding carrier 60, flip the molded wafer and reinstall it (using temporary bonding adhesive) on the temporary bonding carrier 60, at which point the second chip 30 faces upward: the molded wafer and the temporary bonding carrier 60 can be separated by laser debonding and thermal debonding. S60: At this time, wiring (rewiring layer 40) and solder joints (first connection bumps 50) are prepared on the upward-facing surface of the second chip 30 to form a wafer. The wiring process includes thin film deposition (covering a uniform thin film material on the bottom surface of the second chip 30), photolithography (defining the required pattern on the thin film surface), etching (removing the unwanted thin film parts according to the shape defined by photolithography), and dielectric layer preparation (mainly the preparation of resin material). After the dielectric layer is prepared, it is coated on the periphery of the metal wire (i.e., the above-mentioned lead-out unit 42) to form an insulating barrier.
[0043] S70: After separating the wafer from the temporary bonding carrier 60, the wafer is diced: the separation can be performed using the above-mentioned laser debonding and thermal debonding methods, and then the entire wafer is diced to form the final product.
[0044] The chip packaging structure fabrication method provided in this embodiment, compared with the prior art, is as follows: By using the temporary bonding carrier 60, the first chip 20 can be easily assembled on the top surface of the second chip 30, and the redistribution layer 40 and the first connection bump 50 can be assembled on the bottom surface of the second chip 30. With the second chip 30 as the center, two operations are performed on the top and bottom of the second chip 30 respectively, and only one wiring process is needed. The complex three-dimensional stacking and molding and wiring are broken down into standardized operations, replacing the cumbersome process of multiple stacking, multiple molding and multiple wiring in the traditional way, simplifying the production steps and making it suitable for mass production. The temporary bonding carrier 60 can fix the chip assembly and the molded wafer, avoid chip displacement during processing, improve the dimensional accuracy of the entire packaging structure, and optimize the yield.
[0045] In this application, the first connecting protrusion 50 is greater than the second connecting protrusion 312, and the second connecting protrusion 312 is greater than the third connecting protrusion.
[0046] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A multi-chip packaging structure, characterized in that, include: Plastic encapsulation; At least one first chip is encapsulated within the encapsulation body; The second chip is encapsulated within the encapsulation body. The second chip is located below the first chip. The projected area of the second chip in the vertical direction covers all of the first chip. A vertical interconnect structure electrically connected to the first chip is penetrating through the second chip in the vertical direction. The lower end of the vertical interconnect structure is exposed on the bottom surface of the encapsulation body. A redistribution layer is disposed at the bottom of the molding compound. The redistribution layer has a first electrical connection point that is electrically connected to the vertical interconnect structure and the pins of the second chip, and a second electrical connection point that is electrically connected to the first electrical connection point. The first connecting protrusion is electrically connected to the second electrical connection point.
2. The multi-chip packaging structure as described in claim 1, characterized in that, The bottom surface of the second chip is flush with the bottom surface of the molding compound.
3. The multi-chip packaging structure as described in claim 1, characterized in that, The vertical interconnect structure includes: An electrical via is used to penetrate the second chip vertically. A conductive metal is filled in the via. The second connection bump corresponds one-to-one with the conductive metal and is electrically connected to the first chip.
4. The multi-chip packaging structure as described in claim 3, characterized in that, The second connecting bump is one or more combinations of gold ball bumps and gold-tin bumps.
5. The multi-chip packaging structure as described in claim 1, characterized in that, When there are multiple first chips, the top surfaces of the multiple first chips are flush and spaced apart from the top surface of the molding compound.
6. The multi-chip packaging structure as described in claim 1, characterized in that, The rewiring layer includes fan-out components that correspond one-to-one with the vertical interconnect structure. Each fan-out component includes multiple lead-out units stacked in the vertical direction. Each lead-out unit has a third connection bump at its top. The third connection bump of the uppermost lead-out unit is electrically connected to the vertical interconnect structure, and the lowermost lead-out unit is electrically connected to the first connection bump.
7. The multi-chip packaging structure as described in claim 6, characterized in that, Multiple lead-out units in the same fan-out assembly are staggered along the horizontal direction.
8. A method for fabricating a multi-chip package structure, characterized in that, The method for fabricating a multi-chip package structure as described in any one of claims 1-7 includes the following steps: S10: Fabricate a vertical interconnect structure on the second chip; S20: Using a stacking device, all the first chips are stacked on top of the second chip and electrically connected to the vertical interconnect structure to form a chip assembly; S30: The chip assembly is mounted on a temporary bonding carrier, with the second chip facing down; S40: Molding is performed on the outer periphery of the chip assembly to form a molded wafer; S50: Separate the molded wafer from the temporary bonding carrier, flip the molded wafer and reinstall it on the temporary bonding carrier, with the second chip facing upwards at this time; S60: At this time, wiring and solder joint preparation are performed on the upward-facing surface of the second chip to form a wafer; S70: Divide the wafer after separating it from the temporary bonding carrier.
9. The method for fabricating a multi-chip package structure as described in claim 8, characterized in that, The chip assembly and the temporary bonding carrier, as well as the molded wafer and the temporary bonding carrier, are bonded together with temporary bonding adhesive.
10. The method for fabricating a multi-chip package structure as described in claim 8, characterized in that, The wiring process includes thin film deposition, photolithography, etching, and dielectric layer fabrication.