Single-cell-level multi-phase parallel boost-buck DCDC energy storage system

Abstract

The invention, which relates to the technical field of power electronics and energy storage system integration, discloses a single-cell-level multiphase parallel boost-buck DCDC energy storage system comprising a bidirectional Buck-Boost circuit unit, an FPGA controller module, a redundant bypass module, a [delta] SOC-PID capacity difference adaptive module, a bus bar module, a heat dissipation module and a CAN-FD communication module. Through the design of the single-cell bidirectional boost-buck channel, strict grading and matching of the cells are not needed, the utilization rate of the single capacity is greatly improved, by means of the multi-phase parallel technology controlled by the FPGA and the efficient circuit structure, the module efficiency is improved, the high-power output requirement is met, the defects that an existing equalizer is insufficient in power and the Pack-level DCDC power limit are overcome, and the power consumption of the equalizer is reduced. By means of the delta SOC-PID capacity difference self-adaptive module, capacity differences of different batches of battery cells can be adapted, system instability caused by the capacity differences does not need to be worried about, flexible parallel expansion of multiple modules is supported, the modification cost is low, and high expansibility and economical efficiency are achieved.

Description

Technical Field

[0001] This invention relates to the field of power electronics and energy storage system integration technology, specifically a single-cell-level multiphase parallel buck-boost DC-DC energy storage system. Background Technology

[0002] In the field of power electronics and energy storage system integration, lithium-ion cells are the core unit for energy storage systems to store and release electrical energy. They convert electrical energy into chemical energy for storage through electrochemical principles, and then convert the chemical energy back into electrical energy for output when needed. They are the basic components of various energy storage devices and are widely used in scenarios such as off-grid power supply and emergency backup power.

[0003] Energy storage systems are an integrated system composed of lithium-ion cells, power conversion devices, control units, and heat dissipation systems. They enable efficient storage, flexible scheduling, and stable supply of electrical energy, playing a crucial role in renewable energy consumption, grid peak shaving and valley filling, and power supply to remote areas. They can mitigate the impact of the intermittency and volatility of renewable energy generation on the power grid, ensuring the stable operation of the power system. At the same time, they can provide continuous and reliable power support for islands without grid coverage, oil and gas drilling platforms, and field base stations, supporting the normal operation of production and business activities in related fields.

[0004] With the rapid development of the energy storage industry, the number of retired lithium-ion cells and new cells from different batches has increased significantly. These cells inevitably experience capacity decay and increased internal resistance during long-term use or production, leading to significant differences in capacity and internal resistance between different cells. Traditional energy storage systems often use series / parallel packs to combine cells. To reduce the impact of cell differences, cells need to be strictly graded and grouped, selecting cells with similar capacity and internal resistance to form a pack. However, even with this approach, the "weakest link effect" remains prominent during charge-discharge cycles—the capacity and lifespan of the entire pack are limited by the worst-performing cell, ultimately resulting in a capacity loss of over 20%, severely reducing cell utilization efficiency.

[0005] To address this issue, existing technologies have introduced equalizers to regulate voltage differences between cells. However, existing equalizers generally suffer from insufficient power and cannot support high-current load requirements. Pack-level DC-DC solutions rely on high-voltage buses of 300V or higher, which is costly when retrofitting existing medium- and low-voltage systems. High-rate off-grid scenarios such as island microgrids, oil and gas drilling, and 5G base stations not only face the problems of mixed cell batches and high maintenance difficulty, but also have high requirements for the current carrying capacity, temperature resistance, and power supply stability of the energy storage system. Therefore, developing a single-cell-level multiphase parallel buck-boost DC-DC energy storage system is of great significance. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a single-cell-level multiphase parallel buck-boost DC-DC energy storage system. Through a single-cell bidirectional buck-boost channel design, it eliminates the need for strict cell grading and grouping, significantly improving the utilization rate of individual cells and effectively solving the capacity loss problem of traditional series / parallel packs. Utilizing FPGA-controlled multiphase parallel technology and efficient circuit structure, it improves module efficiency and meets high-power output requirements. Based on the ΔSOC-PID capacity difference adaptive module, it can adapt to capacity differences between different batches of cells, eliminating concerns about system instability caused by capacity differences. It supports flexible parallel expansion of multiple modules with low modification costs and can be adapted to various scenarios such as off-grid microgrids, oil and gas drilling, and base stations, combining high scalability and economy.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a single-cell-level multi-phase parallel buck-boost DC-DC energy storage system, the system comprising: a bidirectional Buck-Boost circuit unit, an FPGA controller module, a redundant bypass module, a ΔSOC-PID capacity difference adaptive module, a bus module, a heat dissipation module, and a CAN-FD communication module; The input terminal of the bidirectional Buck-Boost circuit unit is connected to the lithium-ion battery cell one by one. The lithium-ion battery cell has a capacity of no more than 320Ah and a continuous operating current of no more than 160A. It adopts a four-switch Buck-Boost topology or Cúk topology to realize bidirectional power conversion between the battery cell and the system. The FPGA controller module is electrically connected to the bidirectional Buck-Boost circuit unit and is used to generate 4-12 phase shift PWM drive signals. The phase shift angle is 360° divided by the number of parallel phases to drive the bidirectional Buck-Boost circuit unit to realize multi-phase parallel connection. It also integrates fault diagnosis and phase calibration functions. One end of the redundant bypass module is connected to the bidirectional Buck-Boost circuit unit, and the other end is connected to the system power supply circuit. It consists of a fuse and a bypass MOSFET to form a dual redundancy structure. It is configured to bypass the faulty module when the bidirectional Buck-Boost circuit unit experiences an over-mild short-circuit fault. The ΔSOC-PID capacity difference adaptive module incorporates a GMM-Copula tolerance model to monitor the SOC differences between different cells and sends adjustment signals to the FPGA controller module to adjust the PWM drive signal, control the working state of the bidirectional Buck-Boost circuit unit, and achieve capacity balance. The bus module can output 48V and 72V DC voltages to achieve rated continuous output power and peak output power. It is equipped with a digital active current sharing ring and supports parallel expansion of multiple systems. The heat dissipation module is in contact with the heat-generating components of each module and adopts a phase change material and liquid cooling composite structure to control the operating temperature and temperature difference of each module. The CAN-FD communication module is connected to the ΔSOC-PID capacity difference adaptive module and FPGA controller module of each system, respectively, to realize the sharing of SOC and temperature data among the modules and support the collaborative work of the modules.

[0008] Furthermore, the input voltage of the bidirectional Buck-Boost circuit unit covers the voltage range during the charging and discharging process of the battery cell. The module internally includes a current sampling resistor and a voltage sampling terminal. The current sampling resistor is connected in series in the power supply circuit between the battery cell and the module to collect the charging and discharging current of the battery cell in real time and convert the current data into an electrical signal for transmission to the ΔSOC-PID capacity difference adaptive module. The voltage sampling terminal is connected in parallel across the battery cell to collect the battery cell voltage and transmit it to the ΔSOC-PID capacity difference adaptive module. The ΔSOC-PID capacity difference adaptive module calculates the real-time SOC value of the battery cell based on the current and voltage sampling data. The calculation process uses a dynamic weighted SOC estimation formula: ,in, for The current state of charge (SOC) of the battery cell. for SOC value at time, This refers to the initial SOC value of the battery cell. This refers to the rated capacity of the battery cell. for Constant charging and discharging current, For dynamic weighting coefficients, Voltage stability data for different SOC ranges are obtained through cell cycle testing. The ranges are divided according to the voltage fluctuation amplitude and corresponding coefficient values ​​are matched.

[0009] Furthermore, the FPGA controller module integrates a phase calibration submodule and a fault diagnosis submodule. The phase calibration submodule acquires the bus ripple current detection value by collecting the ripple current signal from the bus module and adjusts the phase shift angle accuracy based on the detection value. The fault diagnosis submodule acquires fault information by receiving the fault status signal sent by the redundant bypass module, triggers a fault alarm command upon fault detection, and simultaneously sends fault data to the CAN-FD communication module. When adjusting the phase shift angle, the phase calibration submodule of the FPGA controller module uses the ripple current suppression optimization formula to calculate the target phase shift angle. ,in, For the target phase shift angle, For the number of parallel phases, To measure the ripple current, To set the ripple current threshold, This is the phase adjustment coefficient. Based on the simulation model of multiphase parallel circuit, the relationship curve between ripple current and phase deviation under different phase numbers is determined by simulating the curve. The interval is divided according to the slope characteristics of the curve and the corresponding coefficient value is matched. The FPGA controller module is also equipped with a PWM signal output interface, which is connected to the drive end of the bidirectional Buck-Boost circuit unit to output the PWM drive signal.

[0010] Furthermore, the fuse in the redundant bypass module is connected in series between the bidirectional Buck-Boost circuit unit and the bus module. The rated current of the fuse matches the maximum operating current of the bidirectional Buck-Boost circuit unit. When the module current exceeds the set value, the fuse blows. The bypass MOSFET in the redundant bypass module is connected in parallel on both sides of the output terminal of the bidirectional Buck-Boost circuit unit. The bypass MOSFET is equipped with a drive circuit, which is connected to the fault output terminal of the FPGA controller module. The drive circuit adopts an optocoupler isolation design, and the optocoupler isolation voltage meets the system insulation requirements. After receiving the fault signal from the FPGA controller module, the drive circuit drives the MOSFET to conduct, thereby bypassing the faulty bidirectional Buck-Boost circuit unit.

[0011] Furthermore, the ΔSOC-PID capacity difference adaptive module is equipped with a SOC sampling period adjustment submodule and an SOC difference threshold judgment unit. The SOC sampling period adjustment submodule reads the cell capacity parameters and adjusts the sampling period according to the cell capacity. Different cell capacities correspond to different sampling periods. The ΔSOC-PID capacity difference adaptive module has a built-in SOC calculation unit that calculates the SOC value of each cell based on the current and voltage sampling data transmitted by the bidirectional Buck-Boost circuit unit. The SOC difference threshold judgment unit compares the SOC values ​​of each cell and calculates the SOC difference. When the SOC difference reaches the set threshold, the PID adjustment program is started to generate a PWM duty cycle adjustment signal and send it to the FPGA controller module to adjust the duty cycle of the PWM drive signal, thereby achieving cell capacity balance.

[0012] Furthermore, the digital active current sharing loop of the bus module includes a current detection chip and a current sharing control chip. The current detection chip is installed at the connection node between each bidirectional Buck-Boost circuit unit and the bus module to detect the output current of each bidirectional Buck-Boost circuit unit and transmit the detection data to the current sharing control chip. The current sharing control chip is connected to the FPGA controller module, compares the output current values ​​of each bidirectional Buck-Boost circuit unit, generates a current sharing adjustment signal, and sends it to the FPGA controller module to adjust the output current of each module. When calculating the current sharing adjustment signal, the current sharing control chip uses a dynamic current sharing deviation correction formula: ,in, For the first Current regulation of each bidirectional Buck-Boost circuit unit This represents the average output current of all bidirectional Buck-Boost circuit units. For the first Measured output current of a bidirectional Buck-Boost circuit unit This is the proportionality coefficient. The integral coefficient is... and The system load test determined that the current sharing deviation convergence time was recorded under different load rates. The interval was divided according to the convergence time and overshoot characteristics and the corresponding coefficient value was matched. The bus module is also equipped with an overvoltage protection unit, which includes a voltage detection circuit and a switching circuit. The voltage detection circuit collects the bus voltage and triggers the switching circuit to cut off unnecessary load circuits when the bus voltage exceeds the set value.

[0013] Furthermore, the phase change material in the heat dissipation module is filled around the power devices of the bidirectional Buck-Boost circuit unit and the chip of the FPGA controller module. The phase change material is a paraffin-based composite phase change material, which absorbs the heat generated by the power devices and the chip through thermal conduction. The liquid cooling circuit of the heat dissipation module adopts a serpentine flow channel design, with the flow channel attached to the outside of the phase change material and the surface of the conductive bus of the busbar module. The liquid cooling circuit is filled with coolant, which is an aqueous solution of ethylene glycol or other liquids that meet the requirements for low-temperature flow. The liquid cooling circuit is equipped with a circulation pump and heat dissipation fins. The circulation pump drives the coolant to flow in the flow channel, and the heat dissipation fins are used to dissipate the heat absorbed by the coolant to the environment to control the temperature difference between the modules.

[0014] Furthermore, the communication rate of the CAN-FD communication module covers the range required for normal system operation and peak data transmission. The module is equipped with multiple communication interfaces, which are connected to the communication terminals of each module in the system. The data transmission of the CAN-FD communication module adopts CRC check, and the CRC check uses a 15-bit polynomial. The CAN-FD communication module also has a communication interruption reconnection mechanism. When a communication interruption is detected, a data transmission recovery program is started to attempt to re-establish the communication connection. If the interruption time exceeds the set duration, a communication fault signal is sent to the FPGA controller module to trigger the corresponding system protection action.

[0015] Compared with existing technologies, this single-cell-level multi-phase parallel buck-boost DC-DC energy storage system has the following advantages: This invention utilizes a single-cell bidirectional buck-boost channel design, eliminating the need for strict cell grading and grouping, significantly improving the utilization rate of individual cell capacity, and effectively solving the capacity loss problem of traditional series / parallel packs. Leveraging FPGA-controlled multiphase parallel technology and efficient circuit structure, it enhances module efficiency, meets high-power output requirements, overcomes the insufficient power of existing equalizers and the power limitations of pack-level DC-DC converters, and, based on the ΔSOC-PID capacity difference adaptive module, can adapt to capacity differences between different batches of cells, eliminating concerns about system instability caused by capacity differences. It supports flexible parallel expansion of multiple modules with low modification costs, and can be adapted to various scenarios such as off-grid microgrids, oil and gas drilling, and base stations, combining high scalability and economy.

[0016] Other advantages, objectives and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination or study, or may be learned from the practice of the invention. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0018] Figure 1 This is a schematic diagram of a single-cell-level multiphase parallel buck-boost DC-DC energy storage system; Figure 2 A flowchart of the operation of a single-cell-level multiphase parallel buck-boost DC-DC energy storage system; Figure 3 This is a flowchart of a single-cell-level multiphase parallel buck-boost DC-DC energy storage system. Detailed Implementation

[0019] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below.

[0020] This invention provides a single-cell-level multi-phase parallel buck-boost DC-DC energy storage system, which can be adapted to different batches of cells and meet high power output requirements. See [link to relevant documentation]. Figure 1 The specific technical details are as follows: The system consists of a bidirectional Buck-Boost circuit unit, an FPGA controller module, a redundant bypass module, a ΔSOC-PID capacity difference adaptive module, a bus module, a heat dissipation module, and a CAN-FD communication module. The bidirectional Buck-Boost circuit unit corresponds one-to-one with a lithium-ion battery cell (capacity ≤320Ah, continuous operating current ≤160A), employing a four-switch Buck-Boost or Cúk topology to cover the cell's charge and discharge voltage range. It also includes a current sampling resistor and a voltage sampling terminal for data acquisition and transmission to the ΔSOC-PID capacity difference adaptive module.

[0021] The FPGA controller module is electrically connected to the bidirectional Buck-Boost circuit unit, generating 4-12 phase-shifted PWM drive signals (phase shift angle = 360° / number of parallel phases). It includes a built-in phase calibration and fault diagnosis submodule, which can adjust the phase shift angle accuracy, identify faults, and trigger alarms. A redundant bypass module is connected to the bidirectional Buck-Boost circuit unit at one end and to the power supply circuit at the other. It consists of a fuse and a bypass MOSFET forming a dual-redundancy structure, bypassing the faulty module when the circuit unit overheats or short-circuits.

[0022] The ΔSOC-PID capacity difference adaptive module incorporates a GMM-Copula tolerance model. Based on sampled data, it calculates the real-time SOC of the battery cell using a dynamic weighted SOC estimation formula. It includes a SOC sampling period adjustment submodule and a difference threshold judgment unit. When the difference exceeds the limit, PID regulation is triggered, sending a signal to the FPGA to adjust the PWM duty cycle to achieve capacity balancing. The bus module outputs 48V / 72V DC voltage and features a digital active current sharing loop (including current detection and current sharing control chips) and an overvoltage protection unit, supporting parallel expansion of multiple systems.

[0023] The heat dissipation module adopts a phase change material (paraffin-based composite phase change material) and a liquid cooling composite structure to control the temperature difference of the heat-generating components of each module. The CAN-FD communication module connects the ΔSOC-PID capacity difference adaptive module and the FPGA controller module, and adopts CRC check (15-bit polynomial) and communication interruption reconnection mechanism to realize data sharing and collaborative work.

[0024] Example 1 This embodiment of a single-cell-level multiphase parallel buck-boost DC-DC energy storage system is primarily applied in high-rate off-grid scenarios such as off-grid microgrids, oil and gas drilling platforms, and 5G base stations. These scenarios often face challenges such as mixed cell batches and high maintenance difficulty, while also placing high demands on the energy storage system's current carrying capacity, temperature resistance, and power supply stability. (See also...) Figure 1 , Figure 2 and Figure 3This embodiment utilizes the collaborative work of various modules to adapt to different batches of battery cells, meet high power output requirements, and ensure a continuous and stable power supply.

[0025] In actual operation, the system is first initialized, the CAN-FD communication module is started and parameter configuration is completed, and the input terminals of the bidirectional Buck-Boost circuit unit are connected one-to-one with the lithium-ion cells. This circuit unit adopts a four-switch Buck-Boost topology or Cúk topology, and its input voltage covers the voltage range during the charging and discharging process of the cell. The current sampling resistor inside the module is connected in series in the power supply circuit between the cell and the module to collect the charging and discharging current of the cell in real time, and converts the current data into an electrical signal and transmits it to the ΔSOC-PID capacity difference adaptive module; the voltage sampling terminal is connected in parallel across the two ends of the cell to collect the cell voltage and transmit it to the same module.

[0026] The ΔSOC-PID capacity difference adaptive module incorporates a GMM-Copula tolerance model and uses a dynamic weighted SOC estimation formula based on received current and voltage sampling data. Calculate the real-time SOC value of the battery cell, where Voltage stability data across different SOC ranges is obtained through cell cycle testing. Simultaneously, the module's SOC sampling period adjustment submodule reads the cell capacity parameters and adjusts the sampling period based on the cell capacity. The SOC difference threshold judgment unit compares the SOC values ​​of each cell and calculates the SOC difference. If the SOC difference is within limits, the FPGA controller module generates a 4-12 phase-shifted PWM drive signal (phase shift angle is 360° divided by the number of parallel phases), which is transmitted to the drive end of the bidirectional Buck-Boost circuit unit through the PWM signal output interface. The drive circuit realizes bidirectional power conversion between the cells and the system. If the SOC difference reaches a set threshold, the module initiates a PID control program, generating a PWM duty cycle adjustment signal and sending it to the FPGA controller module to adjust the duty cycle of the PWM drive signal, achieving cell capacity balancing.

[0027] The phase calibration submodule built into the FPGA controller module acquires the ripple current signal of the bus module, obtains the bus ripple current detection value, and uses the ripple current suppression optimization formula. Adjusting the phase shift angle accuracy, among which The fault diagnosis submodule is determined based on a multiphase parallel circuit simulation model. It receives fault status signals from the redundant bypass module. If an over-temperature or short-circuit fault is detected in the bidirectional Buck-Boost circuit unit, a fault alarm command is immediately triggered, and fault data is simultaneously sent to the CAN-FD communication module. At this time, the redundant bypass module begins operation. The fuse connected in series with the bidirectional Buck-Boost circuit unit and the bus module blows when the module current exceeds a set value. The bypass MOSFETs connected in parallel across the output terminals of the bidirectional Buck-Boost circuit unit, driven by a circuit (using optocoupler isolation design), receive a fault signal from the FPGA controller module and turn on the MOSFETs, thus bypassing the faulty module.

[0028] During system operation, the bus module outputs DC voltage. Current sensing chips in its digital active current sharing loop are installed at the connection points between each bidirectional Buck-Boost circuit unit and the bus module. These chips detect the output current of each circuit unit and transmit it to the current sharing control chip. The current sharing control chip is connected to the FPGA controller module. After comparing the output current values ​​of each circuit unit, it uses a dynamic current sharing deviation correction formula. A current sharing adjustment signal is generated and sent to the FPGA controller module to adjust the output current of each module. and This was determined through system load testing. Furthermore, in the overvoltage protection unit of the busbar module, the voltage detection circuit collects the busbar voltage. If the busbar voltage exceeds a set value, it triggers the switching circuit to disconnect unnecessary load circuits.

[0029] The heat dissipation module is in contact with the heat-generating components of each module. The paraffin-based composite phase change material inside it fills around the power devices of the bidirectional Buck-Boost circuit unit and the chip of the FPGA controller module, absorbing heat through thermal conduction. The liquid cooling circuit adopts a serpentine flow channel design, with the flow channel attached to the outside of the phase change material and the surface of the conductive bus of the busbar module. The coolant in the circuit flows under the drive of the circulation pump, and the absorbed heat is dissipated to the environment through the heat dissipation fins, controlling the operating temperature and temperature difference of each module.

[0030] The CAN-FD communication module connects to the ΔSOC-PID capacity difference adaptive module and the FPGA controller module, respectively. Its communication rate covers the rate requirements of different system operating states, and data transmission uses 15-bit polynomial CRC checksum. If a communication interruption is detected, a data transmission recovery program is initiated to attempt to re-establish the communication connection; if the interruption time exceeds a set duration, a communication fault signal is sent to the FPGA controller module, triggering corresponding system protection actions, thereby enabling the sharing of SOC and temperature data among modules and supporting collaborative module operation.

[0031] In summary, this embodiment, through the close cooperation of its modules, eliminates the need for strict cell grading and grouping, significantly improving the utilization rate of individual cell capacity and effectively solving the capacity loss problem of traditional series / parallel packs. Utilizing multi-phase parallel technology and a high-efficiency circuit structure, it meets high-power output requirements, overcoming the insufficient power of existing equalizers and the power limitations of pack-level DC-DC converters. Simultaneously, it is compatible with different batches of cells, supports flexible parallel expansion of multiple modules, and has low modification costs, demonstrating good practicality and economy in scenarios such as off-grid microgrids, oil and gas drilling platforms, and 5G base stations.

[0032] Example 2 This embodiment of a single-cell-level multiphase parallel buck-boost DC-DC energy storage system is primarily used in emergency backup power scenarios, such as emergency power supply for urban rail transit, backup power supply for large data centers, and emergency power supply for medical sites in remote areas. These scenarios have extremely high requirements for power supply continuity and often need to accommodate retired and newly purchased lithium-ion cells from different periods, while also needing to cope with sudden high-power supply demands. (See also...) Figure 1 , Figure 2 and Figure 3 This embodiment ensures stable power output even with significant differences in battery cell performance through the coordinated operation of various modules, guaranteeing a reliable power supply in emergency scenarios.

[0033] During system startup, initialization is completed first. The CAN-FD communication module establishes communication connections with each module and synchronously loads the basic parameters required for system operation. A bidirectional Buck-Boost circuit unit is connected one-to-one with each lithium-ion cell. This circuit unit uses a four-switch Buck-Boost or Cúk topology, and its input voltage range covers the voltage variation range of the cell throughout the entire charging and discharging process from fully charged to depleted. The current sampling resistor inside the circuit unit is connected in series in the main power supply circuit between the cell and the module, acquiring the current signal during charging and discharging in real time. This current signal is converted into a transmittable electrical signal and sent to the ΔSOC-PID capacity difference adaptive module. The voltage sampling terminals are connected in parallel across the positive and negative terminals of the cell, continuously acquiring the voltage across the cell. This voltage signal is also transmitted to the ΔSOC-PID capacity difference adaptive module, providing basic data for subsequent SOC calculations.

[0034] The ΔSOC-PID capacity difference adaptive module incorporates a GMM-Copula tolerance model. After receiving current and voltage sampling data, it calculates the real-time SOC value of the battery cell using a dynamic weighted SOC estimation formula. The formula is as follows: in, For dynamic weighting coefficients, voltage stability data for different SOC ranges needs to be obtained through cell cycle testing. Ranges are divided based on voltage fluctuation amplitude, and corresponding coefficient values ​​are matched. Simultaneously, the module's SOC sampling period adjustment submodule reads the cell capacity parameters and flexibly adjusts the sampling period according to the cell capacity to ensure SOC sampling accuracy for cells of different capacities. The SOC difference threshold judgment unit compares the real-time SOC values ​​of all cells one by one and calculates the SOC difference between any two cells.

[0035] If the SOC difference does not reach the set threshold, the FPGA controller module generates a 4-12 phase-shifted PWM drive signal according to the preset number of parallel phases. The phase shift angle is 360° divided by the number of parallel phases. The signal is transmitted to the drive end of the bidirectional Buck-Boost circuit unit through the PWM signal output interface. The drive circuit realizes the bidirectional conversion between cell energy and system energy. If the SOC difference exceeds the set threshold, the ΔSOC-PID capacity difference adaptive module immediately starts the PID adjustment program, generates a PWM duty cycle adjustment signal and sends it to the FPGA controller module. The FPGA controller module adjusts the duty cycle of the PWM drive signal, thereby controlling the charging and discharging current of the bidirectional Buck-Boost circuit unit to achieve capacity balance among the cells.

[0036] During operation, the FPGA controller module's built-in phase calibration submodule continuously acquires the ripple current signal of the bus module, obtains the bus ripple current detection value, and adjusts the phase shift angle accuracy using a ripple current suppression optimization formula. The formula is as follows: ,in, The phase adjustment coefficient needs to be determined based on a multi-phase parallel circuit simulation model. This is achieved by simulating the relationship between ripple current and phase deviation under different phase numbers, dividing the range according to the curve slope characteristics, and matching the corresponding coefficient values. The fault diagnosis submodule receives fault status signals from the redundant bypass module in real time. If an over-temperature or short-circuit fault is detected in the bidirectional Buck-Boost circuit unit, a fault alarm command is immediately triggered, and the fault data is simultaneously sent to the CAN-FD communication module. At this time, the redundant bypass module starts working. The fuse connected in series with the bidirectional Buck-Boost circuit unit and the bus module automatically blows when the module current exceeds the set value. The bypass MOSFETs connected in parallel on both sides of the output terminal of the bidirectional Buck-Boost circuit unit, whose drive circuit (using optocoupler isolation design, with optocoupler isolation voltage meeting system insulation requirements) receives the fault signal from the FPGA controller module, quickly drives the MOSFETs to conduct, bypassing the faulty module and ensuring the normal operation of the rest of the system.

[0037] The busbar module outputs DC voltage according to the power supply requirements of emergency scenarios. The current sensing chip in its digital active current sharing loop is installed at the connection node between each bidirectional Buck-Boost circuit unit and the busbar module. It monitors the output current of each circuit unit in real time and transmits the detected current data to the current sharing control chip. The current sharing control chip establishes a connection with the FPGA controller module. After comparing the output current values ​​of each circuit unit, it generates a current sharing adjustment signal using a dynamic current sharing deviation correction formula. The formula is as follows: in, This is the proportionality coefficient. The integral coefficients are determined through system load testing. The convergence time of the current sharing deviation is recorded under different load rates. Based on the convergence time and overshoot characteristics, intervals are divided and corresponding coefficient values ​​are matched. After the current sharing adjustment signal is sent to the FPGA controller module, the output current of each bidirectional Buck-Boost circuit unit is adjusted to achieve current sharing control. Furthermore, in the overvoltage protection unit of the bus module, the voltage detection circuit continuously collects the bus voltage. If the bus voltage exceeds the set value, the switching circuit is immediately triggered to disconnect unnecessary load circuits, preventing damage to the equipment due to excessive bus voltage.

[0038] The heat dissipation module is in close contact with the heat-generating components of each module. The paraffin-based composite phase change material inside is filled around the power devices of the bidirectional Buck-Boost circuit unit and the chip of the FPGA controller module, absorbing the heat generated by the power devices and chips during operation through thermal conduction. The liquid cooling circuit adopts a serpentine flow channel design, with the flow channel closely attached to the outside of the phase change material and the surface of the conductive bus of the busbar module. The circuit is filled with coolant that meets the requirements for low-temperature flow. The circulation pump drives the coolant to flow continuously in the flow channel. The heat absorbed by the coolant is dissipated to the surrounding environment through the heat dissipation fins, effectively controlling the operating temperature of each module and the temperature difference between modules, ensuring that the system operates at a suitable temperature.

[0039] The CAN-FD communication module maintains connections with both the ΔSOC-PID capacity difference adaptive module and the FPGA controller module. Its communication rate covers the requirements of normal system operation and peak data transmission. A 15-bit polynomial CRC checksum is used during data transmission to ensure accuracy. If a communication interruption is detected, the module immediately initiates a data transmission recovery procedure to attempt to re-establish the communication connection. If the interruption time exceeds a set duration, a communication fault signal is sent to the FPGA controller module, triggering corresponding system protection actions. This enables real-time sharing of SOC and temperature data among the modules, supporting collaborative module operation.

[0040] In summary, this embodiment, through the efficient collaboration of various modules, eliminates the need for strict cell grading and grouping, significantly improving the capacity utilization of cells from different batches and solving the capacity loss problem caused by cell differences in traditional series / parallel packs. Utilizing FPGA-controlled multiphase parallel technology and efficient circuit structure, it meets the high-power output requirements in emergency scenarios, overcoming the shortcomings of insufficient equalizer power and pack-level DC-DC power limitations. Simultaneously, the system supports flexible parallel expansion of multiple modules with low modification costs, demonstrating excellent stability, reliability, and economy in emergency backup power scenarios, providing an efficient solution for various emergency power supply needs.

[0041] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A single-cell-level multiphase parallel buck-boost DC-DC energy storage system, characterized in that, The system includes: a bidirectional Buck-Boost circuit unit, an FPGA controller module, a redundant bypass module, a ΔSOC-PID capacity difference adaptive module, a bus module, a heat dissipation module, and a CAN-FD communication module; The input terminal of the bidirectional Buck-Boost circuit unit is connected to the lithium-ion battery cell one by one. The lithium-ion battery cell has a capacity of no more than 320Ah and a continuous operating current of no more than 160A, which is used to realize bidirectional power conversion between the battery cell and the system. The FPGA controller module is electrically connected to the bidirectional Buck-Boost circuit unit and is used to generate 4-12 phase shift PWM drive signals. The phase shift angle is 360° divided by the number of parallel phases to drive the bidirectional Buck-Boost circuit unit to realize multi-phase parallel connection. It also integrates fault diagnosis and phase calibration functions. One end of the redundant bypass module is connected to the bidirectional Buck-Boost circuit unit, and the other end is connected to the system power supply circuit. It consists of a fuse and a bypass MOSFET to form a dual redundancy structure. It is configured to bypass the faulty module when the bidirectional Buck-Boost circuit unit experiences an over-mild short-circuit fault. The ΔSOC-PID capacity difference adaptive module has a built-in GMM-Copula tolerance model, which is used to monitor the SOC difference of different cells and send adjustment signals to the FPGA controller module to adjust the PWM drive signal and control the working state of the bidirectional Buck-Boost circuit unit. The bus module can output 48V and 72V DC voltages to achieve rated continuous output power and peak output power. It is equipped with a digital active current sharing ring and supports parallel expansion of multiple systems. The heat dissipation module is in contact with the heat-generating components of each module and adopts a phase change material and liquid cooling composite structure to control the operating temperature and temperature difference of each module. The CAN-FD communication module is used to enable the sharing of SOC and temperature data among modules, supporting the collaborative work of the modules.

2. The single-cell-level multiphase parallel buck-boost DC-DC energy storage system according to claim 1, characterized in that, The input voltage of the bidirectional Buck-Boost circuit unit covers the voltage range during the charging and discharging process of the battery cell. The module internally includes a current sampling resistor and a voltage sampling terminal. The current sampling resistor is connected in series in the power supply circuit between the battery cell and the module to collect the charging and discharging current of the battery cell in real time and convert the current data into an electrical signal for transmission to the ΔSOC-PID capacity difference adaptive module. The voltage sampling terminal is connected in parallel across the battery cell to collect the battery cell voltage and transmit it to the ΔSOC-PID capacity difference adaptive module. The ΔSOC-PID capacity difference adaptive module calculates the real-time SOC value of the battery cell based on the current and voltage sampling data. The calculation process uses a dynamic weighted SOC estimation formula. ,in, for The current state of charge (SOC) of the battery cell. for SOC value at time, This refers to the initial SOC value of the battery cell. This refers to the rated capacity of the battery cell. for Constant charging and discharging current, These are dynamic weighting coefficients.

3. The single-cell-level multiphase parallel buck-boost DC-DC energy storage system according to claim 1, characterized in that, The FPGA controller module integrates a phase calibration submodule and a fault diagnosis submodule. The phase calibration submodule acquires the ripple current detection value of the bus ripple current by collecting the ripple current signal from the bus module, and adjusts the phase shift angle accuracy based on the detection value. The fault diagnosis submodule acquires fault information by receiving the fault status signal sent by the redundant bypass module, triggers a fault alarm command upon fault detection, and simultaneously sends fault data to the CAN-FD communication module. When adjusting the phase shift angle, the phase calibration submodule of the FPGA controller module calculates the target phase shift angle using a ripple current suppression optimization formula. ,in, For the target phase shift angle, For the number of parallel phases, To measure the ripple current, To set the ripple current threshold, To provide a phase adjustment coefficient, the FPGA controller module also has a PWM signal output interface, which is connected to the drive terminal of the bidirectional Buck-Boost circuit unit to output a PWM drive signal.

4. The single-cell-level multi-phase parallel buck-boost DC-DC energy storage system according to claim 1, characterized in that, The fuse in the redundant bypass module is connected in series between the bidirectional Buck-Boost circuit unit and the bus module. The rated current of the fuse matches the maximum operating current of the bidirectional Buck-Boost circuit unit. When the module current exceeds the set value, the fuse blows. The bypass MOSFET in the redundant bypass module is connected in parallel on both sides of the output terminal of the bidirectional Buck-Boost circuit unit. The bypass MOSFET is equipped with a drive circuit, which is connected to the fault output terminal of the FPGA controller module. The drive circuit adopts an optocoupler isolation design, and the optocoupler isolation voltage meets the system insulation requirements. After receiving the fault signal from the FPGA controller module, the drive circuit drives the MOSFET to conduct.

5. The single-cell-level multiphase parallel buck-boost DC-DC energy storage system according to claim 1, characterized in that, The ΔSOC-PID capacity difference adaptive module is equipped with a SOC sampling period adjustment submodule and an SOC difference threshold judgment unit. The SOC sampling period adjustment submodule reads the cell capacity parameters and adjusts the sampling period according to the cell capacity. Different cell capacities correspond to different sampling periods. The ΔSOC-PID capacity difference adaptive module has a built-in SOC calculation unit that calculates the SOC value of each cell based on the current and voltage sampling data transmitted by the bidirectional Buck-Boost circuit unit. The SOC difference threshold judgment unit compares the SOC values ​​of each cell and calculates the SOC difference. When the SOC difference reaches the set threshold, the PID adjustment program is started, a PWM duty cycle adjustment signal is generated and sent to the FPGA controller module to adjust the duty cycle of the PWM drive signal.

6. The single-cell-level multiphase parallel buck-boost DC-DC energy storage system according to claim 1, characterized in that, The digital active current sharing loop of the bus module includes a current detection chip and a current sharing control chip. The current detection chip is installed at the connection node between each bidirectional Buck-Boost circuit unit and the bus module to detect the output current of each bidirectional Buck-Boost circuit unit and transmit the detected data to the current sharing control chip. The current sharing control chip is connected to the FPGA controller module and generates a current sharing adjustment signal after comparing the output current values ​​of each bidirectional Buck-Boost circuit unit. This signal is sent to the FPGA controller module to adjust the output current of each module. When calculating the current sharing adjustment signal, the current sharing control chip uses a dynamic current sharing deviation correction formula. ,in, For the first Current regulation of each bidirectional Buck-Boost circuit unit This represents the average output current of all bidirectional Buck-Boost circuit units. For the first Measured output current of a bidirectional Buck-Boost circuit unit This is the proportionality coefficient. As an integral coefficient, the bus module is also equipped with an overvoltage protection unit, which includes a voltage detection circuit and a switching circuit. The voltage detection circuit collects the bus voltage and triggers the switching circuit to disconnect unnecessary load circuits when the bus voltage exceeds the set value.

7. The single-cell-level multiphase parallel buck-boost DC-DC energy storage system according to claim 1, characterized in that, The phase change material in the heat dissipation module is filled around the power devices of the bidirectional Buck-Boost circuit unit and the chip of the FPGA controller module. It absorbs the heat generated by the power devices and the chip through thermal conduction. The liquid cooling circuit of the heat dissipation module adopts a serpentine flow channel design. The flow channel is attached to the outside of the phase change material and the surface of the conductive bus of the busbar module. The liquid cooling circuit is filled with coolant to control the temperature difference between the modules.

8. A single-cell-level multi-phase parallel buck-boost DC-DC energy storage system according to claim 1, characterized in that, The communication rate of the CAN-FD communication module covers the range required for normal system operation and peak data transmission. The module is equipped with multiple communication interfaces, which are connected to the communication terminals of each module in the system. The CAN-FD communication module is also equipped with a communication interruption reconnection mechanism. When a communication interruption is detected, a data transmission recovery program is started to attempt to re-establish the communication connection.

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