Modularized multi-level matrix converter layered architecture device and control method thereof
By using a hierarchical control architecture and observer algorithm based on DSP and FPGA, the problem of excessive capacitor voltage sensors in modular multilevel matrix converters is solved, resulting in cost reduction, improved real-time performance, strong adaptability, and flexible control strategies.
Patent Information
- Application Number
- CN202511147725.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-15
- Publication Date
- 2025-12-12
Smart Images
Figure CN121124576A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the technical field of modular multilevel matrix converters, and in particular to a modular multilevel matrix converter hierarchical architecture device and its control method without a capacitor voltage sensor. Background Technology
[0002] Compared to the modular multilevel converter (MMC), the modular multilevel matrix converter (M3C) for high-power operation has more bridge arms. Under high power, the number of sub-modules within the bridge arms needs to be increased. Each sub-module has a capacitor, and capacitor voltage equalization control is crucial in M3C. Therefore, voltage sampling of the capacitor voltage of each sub-module is required. This results in too many voltage sensors, increasing the cost of the converter and making it difficult to guarantee safety due to too many voltage sensors.
[0003] Traditional voltage sensor detection schemes are prone to damaging the sampling circuit when capacitor voltage instability causes the capacitor voltage to exceed the threshold of the hardware sampling circuit. Therefore, an observer algorithm is used to observe the capacitor voltage of the submodule, eliminating the need for a separate capacitor voltage sensor. M3C modules often require the simultaneous control of hundreds of switch states, but traditional centralized control has a heavy computational burden and struggles to guarantee real-time performance. Therefore, a hierarchical control architecture is necessary, with the FPGA controlling the bridge arms hierarchically, and the DSP handling centralized scheduling. This allows the same control system to change its control strategy according to different operating conditions. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide a modular multilevel matrix converter hierarchical architecture device and its control method without capacitor voltage sensor. It uses DSP to implement the upper-level control algorithm, FPGA to implement the lower-level switching PWM control, and DSP to implement unified scheduling of all FPGAs to achieve hierarchical control and fast control. Different control strategies can be flexibly modified by only changing the control algorithm in DSP.
[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical solution.
[0006] In a first aspect, the present invention provides a modular multilevel matrix converter hierarchical architecture device, including a three-phase AC input system, a bridge arm circuit and a three-phase AC output system;
[0007] The three-phase AC input system is connected to the input terminals of the protection circuit and the first starting circuit; the output terminals of the protection circuit and the first starting circuit are connected to the input of the bridge arm circuit; the output of the bridge arm circuit is connected to the input of the second starting circuit; the output of the second starting circuit is connected to the input of the three-phase AC output system; the three-phase AC input system is connected to the input of the input voltage and current sampling circuit; the bridge arm circuit is connected to the input of the bridge arm voltage sampling circuit and the bridge arm current sampling circuit; the three-phase AC output system is connected to the input of the output voltage and current sampling circuit.
[0008] The outputs of the input voltage and current sampling circuit, the bridge arm voltage sampling circuit, and the bridge arm current sampling circuit are all connected to the input of the first sampling signal conditioning circuit; the output of the output voltage and current sampling circuit is connected to the input of the second sampling signal conditioning circuit; the outputs of the first sampling signal conditioning circuit and the second sampling signal conditioning circuit are respectively connected to the DSP controller circuit, transmitting the voltage and current analog signals after the sampling signal conditioning circuit to the DSP controller circuit; the DSP controller circuit is connected to the FPGA controller circuit; the output of the FPGA controller circuit is connected to the isolation drive circuit; the output of the isolation drive circuit is connected to the bridge arm circuit.
[0009] In the DSP control circuit, the capacitor voltage of the bridge arm circuit submodule is observed by an observer, and the obtained capacitor voltage participates in the control algorithm in the DSP control circuit.
[0010] Furthermore, the switching signals of the bridge arm circuit are given through the FPGA controller circuit located at the lower level, and the start-up circuit and protection circuit are controlled through the DSP controller circuit located at the upper level.
[0011] Secondly, the present invention provides a control method for a modular multilevel matrix converter hierarchical architecture device, comprising the following steps:
[0012] A. The DSP controller circuit closes the first start-up circuit, and the first start-up circuit connects the current-limiting resistor into the circuit. At this time, no signal is given to the FPGA controller circuit. The capacitor voltage of the bridge arm circuit sub-module is pre-charged by uncontrolled rectification through the three-phase AC input system. The protection circuit does not start at this time.
[0013] B. The input current sampled by the input voltage and current sampling circuit enters the DSP controller circuit after passing through the sampling signal adjustment circuit. The DSP controller circuit determines whether the capacitor voltage pre-charging is complete. If so, it proceeds to the next step.
[0014] C. The DSP controller circuit controls the capacitor voltage and sends a modulation signal to the FPGA controller circuit to slowly increase the capacitor voltage reference value until the set value is reached.
[0015] D. The FPGA controller circuit controls the bridge arm switching transistors in the bridge arm circuit through an isolation drive circuit, and the observer works simultaneously.
[0016] The E.DSP controller circuit controls the capacitor voltage observed by the observer to a set value;
[0017] The F.DSP controller circuit transmits the given modulation signal to the FPGA controller circuit through the set control algorithm, gradually increasing the output voltage reference value to achieve soft start.
[0018] The control method of this invention mainly controls the process from startup to steady-state operation, and includes the operation of the observer in the control process.
[0019] Furthermore, in step F, when the DSP controller circuit transmits the given modulation signal to the FPGA controller circuit through the set control algorithm, the second start-up circuit is closed.
[0020] Furthermore, the control method of the present invention also includes: step G. During steady-state operation, the protection circuit is activated, and when the sampling values of the bridge arm voltage sampling circuit, bridge arm current sampling circuit, input voltage and current sampling circuit and output voltage and current sampling circuit are abnormal, the protection circuit implements measures.
[0021] Furthermore, in step G, the sampled value is periodically determined using a timer.
[0022] Furthermore, the present invention designs the observer using the following steps:
[0023] a. Establish discrete dynamic equations for the bridge arm with inductive and capacitive parameter perturbations using Kirchhoff's voltage law;
[0024] b. Establish the discrete disturbance observation equation of the bridge arm based on the discrete dynamic equation, including the observer current injection term and the observer capacitor voltage injection term;
[0025] c. The error equation is derived from the discrete dynamic equation and discrete disturbance observation equation obtained above, which includes the current observation error value and the capacitor voltage observation error value;
[0026] d. Select a Lyapunov function and calculate its reaching law;
[0027] e. Substitute the error equation into the approach law and simplify it to extract the observer current injection term and the observer capacitor voltage injection term;
[0028] f. Substitute the observer current injection term and the observer capacitor voltage injection term obtained in step e into the discrete perturbation observation equation to build an observer for the M3C capacitor voltage.
[0029] Furthermore, the discrete dynamic equations are as follows:
[0030]
[0031] In the formula, i au V represents the instantaneous current value of the bridge arm au. C U represents the amplitude of the capacitor voltage. a and u u Indicates the amplitude of the input voltage and the amplitude of the output voltage, u NO L is the potential difference between the output three-phase neutral point N and the input three-phase neutral point O. b C0 and C10 are the bridge arm inductance and submodule capacitance of bridge arm au, respectively, and T10 is the bridge arm inductance and submodule capacitance. s f is the sampling time. 1au It is an inductance parameter disturbance, f 2au It is a disturbance in the capacitance parameter, S au This represents the switching output state of the full-bridge submodule, where k+1 and k represent the values at time k+1 and time k, respectively.
[0032] Furthermore, the discrete perturbation observation equation is as follows:
[0033]
[0034] Where, η iau For the observer current injection term, η vau This is the observer capacitor voltage injection term. The ^ above the parameter indicates the observed estimate of the corresponding parameter.
[0035] Furthermore, the error equation is as follows:
[0036]
[0037] in, This represents the current observation error value. This represents the error value for capacitor voltage observation.
[0038] Compared with the prior art, the beneficial effects of the present invention are:
[0039] This invention utilizes an observer to monitor the capacitor voltage of the M3C bridge arm submodule, reducing the number of voltage sensors and sampling circuits. The hierarchical control method makes the control program easy to modify, update, and port, reducing the workload of developers and hardware costs, and improving the reliability and real-time performance of the system. Attached Figure Description
[0040] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0041] Figure 1 This is a schematic diagram of the modular multilevel matrix converter hierarchical architecture device of the present invention;
[0042] Figure 2 This is a flowchart of the control method for the modular multilevel matrix converter hierarchical architecture device of the present invention;
[0043] Figure 3 This is a circuit model diagram of the M3C circuit of the present invention;
[0044] Figure 4 This is a schematic diagram of the observer of the present invention;
[0045] Figure 5 This is a comparison diagram of the observed voltages of the observer of this invention;
[0046] Figure 6 This is a schematic diagram showing the soft-start to steady-state value of the output voltage of the present invention. Detailed Implementation
[0047] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0048] Example 1
[0049] This embodiment provides a modular multilevel matrix converter hierarchical architecture device without a capacitor voltage sensor.
[0050] like Figure 1 The modular multilevel matrix converter hierarchical architecture device shown includes a three-phase AC input system 1, a 3×3 bridge arm circuit 2, a three-phase AC output system 3, a DSP controller circuit 4, a first FPGA controller circuit 5, a second FPGA controller circuit 6, a third FPGA controller circuit 7, an isolation drive circuit 8, a protection circuit 9, a first startup circuit 10, a second startup circuit 11, an input voltage and current sampling circuit 12, an output voltage and current sampling circuit 13, a bridge arm voltage sampling circuit 14, a bridge arm current sampling circuit 15, a first sampling signal conditioning circuit 16, a second sampling signal conditioning circuit 17, and an observer 18.
[0051] The three-phase AC input system 1 is connected to the input terminals of the three-phase voltage source, protection circuit 9, and first starting circuit 10; the outputs of protection circuit 9 and first starting circuit 10 are connected to the input of 3×3 bridge arm circuit 2. When the input voltage and current are abnormal, protection circuit 9 is actually a relay, which directly disconnects the connection between three-phase AC input system 1 and 3×3 bridge arm circuit 2; the output of 3×3 bridge arm circuit 2 is connected to the input of second starting circuit 11; the output of second starting circuit 11 is connected to the input of three-phase AC output system 3.
[0052] The three-phase AC input system 1 is connected to the input of the input voltage and current sampling circuit 12; the 3×3 bridge arm circuit 2 is connected to the input of the bridge arm voltage sampling circuit 14 and the bridge arm current sampling circuit 15; the three-phase AC output system 3 is connected to the input of the output voltage and current sampling circuit 13; the input voltage and current sampling circuit 12, the bridge arm voltage sampling circuit 14, and the bridge arm current sampling circuit 15 are all connected to the input of the first sampling signal conditioning circuit 16; the output of the output voltage and current sampling circuit 13 is connected to the input of the second sampling signal conditioning circuit 17; the output of the first sampling signal conditioning circuit 16 and the output of the second sampling signal conditioning circuit 17 are connected to the DSP controller circuit 4; the DSP controller circuit 4 is connected to the first FPGA controller circuit 5, the second FPGA controller circuit 6, and the third FPGA controller circuit 7 respectively; the outputs of the first FPGA controller circuit 5, the second FPGA controller circuit 6, and the third FPGA controller circuit 7 are connected to the isolation drive circuit 8; the output of the isolation drive circuit 8 is connected to the 3×3 bridge arm circuit 2.
[0053] In the DSP control circuit, the capacitor voltage of the bridge arm circuit submodule is observed by an observer, and the obtained capacitor voltage participates in the control algorithm within the DSP control circuit. The switching signal of the bridge arm circuit is given by the lower-level FPGA controller circuit, and the start-up circuit and protection circuit are controlled by the upper-level DSP controller circuit.
[0054] This invention employs a modular multilevel matrix converter hierarchical architecture without capacitor voltage sensors, which has the following advantages:
[0055] (1) It is economical and does not require separate sampling of the capacitor voltage of the submodule, which greatly reduces the number of M3C voltage sensors under high power conditions.
[0056] (2) High safety: The observation of the sub-module capacitor voltage is achieved at the software level by using an observer, which will not cause the sub-module capacitor voltage to exceed the sampling threshold.
[0057] (3) High real-time performance, hierarchical control can be used. DSP can realize the control of the upper layer control algorithm, FPGA can realize the lower layer switch PWM control, and DSP can realize the unified scheduling of all FPGAs to achieve the purpose of fast control.
[0058] (4) It is highly adaptable. No circuit changes are required. Different control strategies can be flexibly modified simply by changing the control algorithm in the DSP.
[0059] Example 2
[0060] This embodiment provides a control method for a modular multilevel matrix converter hierarchical architecture device, the control flow of which from startup to steady-state operation is as follows: Figure 2 As shown, the specific steps are as follows:
[0061] A. The DSP controller circuit closes the first start-up circuit. The first start-up circuit connects the current-limiting resistor to the circuit to prevent the charging current from being too large. At this time, no signals are given to the first, second and third FPGA controller circuits. The capacitor voltage of the bridge arm circuit sub-module is pre-charged by uncontrolled rectification through the three-phase AC input system. The protection circuit does not start at this time to prevent false judgment.
[0062] B. The input current sampled by the input voltage and current sampling circuit enters the DSP controller circuit after passing through the sampling signal adjustment circuit. The DSP controller circuit determines whether the capacitor voltage pre-charging is over. When the input current value is close to 0, the pre-charging is over and the next step is performed.
[0063] C. The DSP controller circuit controls the capacitor voltage and sends modulation signals to the first, second and third FPGA controller circuits to slowly increase the capacitor voltage reference value until it reaches the set value. At this time, the output reference is 0.
[0064] D. The first FPGA controller circuit 5 controls the switching transistors of the au, av, and aw bridge arms in the 3×3 bridge arm circuit through the isolation drive circuit; the second FPGA controller circuit 6 controls the switching transistors of the bu, bv, and bw bridge arms in the 3×3 bridge arm circuit through the isolation drive circuit; the third FPGA controller circuit 7 controls the switching transistors of the cu, cv, and cw bridge arms in the 3×3 bridge arm circuit through the isolation drive circuit, and at the same time executes the observer to observe the capacitor voltage value.
[0065] E. The DSP controller circuit determines whether the capacitor voltage control observed by the observer has reached the set value. If so, it proceeds to the next step.
[0066] The F.DSP controller circuit transmits the given modulation signal to the first FPGA controller circuit, the second FPGA controller circuit, and the third FPGA controller circuit through the set control algorithm. At this time, the second start circuit is closed and the output voltage reference value is gradually increased to realize soft start.
[0067] G. During steady-state operation, the protection circuit is activated and the sampling value is judged periodically by a timer. When the sampling value of the bridge arm voltage sampling circuit 14, the bridge arm current sampling circuit 15, the input voltage and current sampling circuit 12 after the sampling signal conditioning circuit 16 or the output voltage and current sampling circuit 13 after the sampling signal conditioning circuit 17 is abnormal, the protection circuit implements measures to cut off the input of the three-phase AC input system.
[0068] This invention also includes a device for observing the voltage of the aforementioned M3C capacitor, which observes the capacitor voltage based on the system state, comprising the following steps:
[0069] a. such as Figure 3 The diagram shown is an M3C circuit model, taking bridge arm au as an example. A disturbance f with inductance parameters is established for bridge arm au. 1au and capacitance parameter disturbance f 2au The discrete dynamic equations.
[0070]
[0071] In the formula, i au V represents the instantaneous current value of the bridge arm au. C U represents the amplitude of the capacitor voltage. a and u u Indicates the amplitude of the input voltage and the amplitude of the output voltage, u NO L is the potential difference between the output three-phase neutral point N and the input three-phase neutral point O. b C0 and C10 are the bridge arm inductance and submodule capacitance of bridge arm au, respectively, and T10 is the bridge arm inductance and submodule capacitance. s f is the sampling time. 1au It is the inductance parameter disturbance and f 2au It is a disturbance in the capacitance parameter, S au The switching output state of the full-bridge module is 1, 0, or -1, where k+1 and k represent the values at time k+1 and k, respectively. This embodiment uses one bridge arm with three sub-modules as an example, then S... au and V C Both are 3×1 matrices.
[0072] b. Establish the discrete perturbation observation equation for the bridge arm au based on the discrete dynamic equation.
[0073]
[0074] This includes the observer current injection term n iau and observer capacitor voltage injection term n vau The parameters marked with ^ are all observed estimates.
[0075] c. By subtracting the disturbance observation equation (2) from the discrete dynamic equation (1) obtained above, the error equation can be derived.
[0076]
[0077] This includes current observation error values. and capacitor voltage observation error value
[0078] d. Select a Lyapunov function and calculate its reaching law.
[0079] The Lyapunov function is selected as follows:
[0080]
[0081] And calculate the reaching law:
[0082]
[0083] e. Substitute the error equation into the approach law and simplify it to extract the observer current injection term and the observer capacitor voltage injection term.
[0084] Substituting the error equation in equation (3) into the approach law and ignoring higher-order terms, we get:
[0085]
[0086] Inject current into the observer term Then equation (6) can be rewritten as:
[0087]
[0088] Take the observer capacitor voltage injection term If 0 < α < 1, then the condition for ΔV(k) < 0 can be obtained.
[0089] f. Substitute the observer current injection term and the observer capacitor voltage injection term obtained in step e into the discrete perturbation observation equation to build an observer for the M3C capacitor voltage.
[0090] like Figure 4 As shown, an M3C capacitor voltage observer is built for a single submodule of the bridge arm au, and 401 is executed to obtain... The value and η in 402 vau And 404 The values are added together to get 403. The value in 40 3 The value is obtained from 404 after a one-cycle delay. The value of i in 405 au The value of (k) and in 404 Subtracting the values gives e iau (k), execute 406 output e iau -η iau After outputting 406, executing 407 yields η. vau Executing 408 returned a result. The 409 is obtained by adding a one-period delay and a low-pass filter.
[0091] In this embodiment, a simulation of the M3C system is built to verify the control method proposed in this invention.
[0092] Figure 5 The diagram shows a comparison of the voltages observed by the observer. The voltage of the three-phase AC input system 1 is set to 80V, the capacitor voltage is set to 70V, and the voltage of the three-phase AC output system 3 is set to 60V. To save simulation time, the capacitor voltage is pre-charged by an uncontrolled rectifier before 0.1 seconds. Since no observer is needed at this time, the observer's observation is inaccurate. After 0.1 seconds, the pre-charging ends and the capacitor voltage control is activated. It can be seen that the observer converges quickly and accurately predicts the capacitor voltage value. Figure 6 The diagram shows the output voltage soft-start to steady-state value, demonstrating that the system can operate normally by using an observer instead of hardware sampling of the capacitor voltage.
[0093] It should be understood that the exemplary embodiments described herein are illustrative and not restrictive. Although one or more embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as defined by the appended claims.
Claims
1. A modular multilevel matrix converter hierarchical architecture device, comprising a three-phase AC input system, a bridge arm circuit, and a three-phase AC output system, characterized in that, The three-phase AC input system is connected to the input terminals of the protection circuit and the first starting circuit; the output terminals of the protection circuit and the first starting circuit are connected to the input terminals of the bridge arm circuit; the output terminal of the bridge arm circuit is connected to the input terminal of the second starting circuit; the output terminal of the second starting circuit is connected to the input terminal of the three-phase AC output system; the three-phase AC input system is connected to the input terminal of the input voltage and current sampling circuit; the bridge arm circuit is connected to the input terminals of the bridge arm voltage sampling circuit and the bridge arm current sampling circuit. Input connection of the three-phase AC output system and the output voltage and current sampling circuit; The outputs of the input voltage and current sampling circuit, the bridge arm voltage sampling circuit, and the bridge arm current sampling circuit are all connected to the input of the first sampling signal conditioning circuit; the output of the output voltage and current sampling circuit is connected to the input of the second sampling signal conditioning circuit; the outputs of the first sampling signal conditioning circuit and the second sampling signal conditioning circuit are respectively connected to the DSP controller circuit, transmitting the voltage and current analog signals after the sampling signal conditioning circuit to the DSP controller circuit; the DSP controller circuit is connected to the FPGA controller circuit; the output of the FPGA controller circuit is connected to the isolation drive circuit; the output of the isolation drive circuit is connected to the bridge arm circuit. In the DSP control circuit, the capacitor voltage of the bridge arm circuit submodule is observed by an observer, and the obtained capacitor voltage participates in the control algorithm in the DSP control circuit.
2. The modular multilevel matrix converter hierarchical architecture device according to claim 1, characterized in that, The bridge arm circuit switching signal is given by the FPGA controller circuit located in the lower layer, and the start-up circuit and protection circuit are controlled by the DSP controller circuit located in the upper layer.
3. The control method for the modular multilevel matrix converter hierarchical architecture device as described in claim 1 or 2, characterized in that, Including the following steps: A. The DSP controller circuit closes the first start-up circuit, and the first start-up circuit connects the current-limiting resistor into the circuit. At this time, no signal is given to the FPGA controller circuit. The capacitor voltage of the bridge arm circuit sub-module is pre-charged by uncontrolled rectification through the three-phase AC input system. The protection circuit does not start at this time. B. The input current sampled by the input voltage and current sampling circuit enters the DSP controller circuit after passing through the sampling signal adjustment circuit. The DSP controller circuit determines whether the capacitor voltage pre-charging is complete. If so, it proceeds to the next step. C. The DSP controller circuit controls the capacitor voltage and sends a modulation signal to the FPGA controller circuit to slowly increase the capacitor voltage reference value until the set value is reached. D. The FPGA controller circuit controls the bridge arm switching transistors in the bridge arm circuit through an isolation drive circuit, and the observer works simultaneously. The E.DSP controller circuit controls the capacitor voltage observed by the observer to a set value; The F.DSP controller circuit transmits the given modulation signal to the FPGA controller circuit through the set control algorithm, gradually increasing the output voltage reference value to achieve soft start.
4. The control method according to claim 3, characterized in that, In step F, when the DSP controller circuit transmits the given modulation signal to the FPGA controller circuit through the set control algorithm, the second start circuit is closed.
5. The control method according to claim 3, characterized in that, It also includes: Step G. During steady-state operation, the protection circuit is activated. When the sampling values of the bridge arm voltage sampling circuit, bridge arm current sampling circuit, input voltage and current sampling circuit and output voltage and current sampling circuit are abnormal, the protection circuit implements measures.
6. The control method according to claim 5, characterized in that, In step G, the sampled value is periodically determined using a timer.
7. The control method according to claim 3, characterized in that, The observer is designed using the following steps: a. Establish discrete dynamic equations for the bridge arm with inductive and capacitive parameter perturbations using Kirchhoff's voltage law; b. Establish the discrete disturbance observation equation of the bridge arm based on the discrete dynamic equation, including the observer current injection term and the observer capacitor voltage injection term; c. The error equation is derived from the discrete dynamic equation and discrete disturbance observation equation obtained above, which includes the current observation error value and the capacitor voltage observation error value; d. Select a Lyapunov function and calculate its reaching law; e. Substitute the error equation into the approach law and simplify it to extract the observer current injection term and the observer capacitor voltage injection term; f. Substitute the observer current injection term and the observer capacitor voltage injection term obtained in step e into the discrete perturbation observation equation to build an observer for the M3C capacitor voltage.
8. The control method according to claim 7, characterized in that, The discrete dynamic equations are as follows: In the formula, i au V represents the instantaneous current value of the bridge arm au. C U represents the amplitude of the capacitor voltage. a and u u Indicates the amplitude of the input voltage and the amplitude of the output voltage, u NO L is the potential difference between the output three-phase neutral point N and the input three-phase neutral point O. b C0 and C10 are the bridge arm inductance and submodule capacitance of bridge arm au, respectively, and T10 is the bridge arm inductance and submodule capacitance. s f is the sampling time. 1au It is an inductance parameter disturbance, f 2au It is a disturbance in the capacitance parameter, S au This represents the switching output state of the full-bridge submodule, where k+1 and k represent the values at time k+1 and time k, respectively.
9. The control method according to claim 8, characterized in that, The discrete perturbation observation equation is as follows: Where, η iau For the observer current injection term, η vau This is the observer capacitor voltage injection term. The ^ above the parameter indicates the observed estimate of the corresponding parameter.
10. The control method according to claim 9, characterized in that, The error equation is as follows: in, This represents the current observation error value. This represents the error value for capacitor voltage observation.