Electricity meter sampling filter chip and system integrated with programmable anti-aliasing filter

Abstract

The invention discloses an electric meter sampling filter chip and system integrated with a programmable anti-aliasing filter, and relates to the field of electric energy metering chips, the electric meter sampling filter chip comprises a programmable anti-aliasing filter module, a digital control and interface module and a cooperative control unit, through binary weighted control of a switched capacitor array, the cut-off frequency can be dynamically adjusted within the range of 1 kHz to 100 kHz, and the cut-off frequency can be adjusted within the range of 1 kHz to 100 kHz. Switching of a Bessel mode, a Butterworth mode and a Chebyshev mode is physically achieved by reconstructing a feedback network, a programmable AAF, an ADC, control logic and a digital interface are integrated into a single chip, and the number of external elements such as an RC network and an operational amplifier is reduced; aDC sampling data is analyzed through FFT, the signal-to-noise ratio is calculated in real time, the filter mode is automatically switched, a hardware interrupt pin triggers notification after configuration is completed, MCU polling is replaced, and frequency response is ensured to be accurate and controllable through laser trimming of a switched capacitor array.

Description

Technical Field

[0001] This invention relates to the field of electricity metering chips, and in particular to an electricity meter sampling filter chip and system with an integrated programmable anti-aliasing filter. Background Technology

[0002] As a core component of smart meters, energy metering chips require high-precision measurement of parameters such as voltage, current, and power. Anti-aliasing filters (AAFs) are crucial modules in the analog signal chain, responsible for suppressing high-frequency noise and aliasing interference. Current traditional technologies face the following bottlenecks in smart grid and renewable energy integration scenarios: 1. Fixed filter parameters: Traditional metering chips (such as TIMSP430FE and ADIADE series) integrate fixed parameters AAF. The cutoff frequency, type (Butterworth / Bessel), and order are determined in the design stage, which cannot adapt to complex power grid environments (such as industrial harmonics and sudden impulse noise).

[0003] 2. Defects of external filtering schemes: Some systems adjust the filtering characteristics by using external discrete RC networks, which increases hardware complexity and cost, and cannot dynamically adapt to real-time noise changes.

[0004] 3. Incompatibility with cross-domain technologies: Programmable filters in the audio / communication field (such as audio codecs, LTC1569) only focus on signal fidelity and do not meet the core requirements of power metering for phase accuracy (error ≤0.1°) and dynamic range (1000:1 current measurement). In addition, they require an external MCU and have low integration.

[0005] 4. Increased grid noise: The increased proportion of new energy grid connection (≥35% in 2024) has led to a surge in grid harmonics and switching noise (typical value at 150kHz), making it difficult for fixed filters to meet both the "wideband requirement of clean grid" and the "narrowband requirement of high-noise grid".

[0006] 5. Conflict between metering accuracy and real-time performance: Traditional fixed filters have a metering error of ≥0.5% under high-frequency interference, and parameter adjustment requires shutdown and re-welding of components, which cannot meet the "online real-time optimization" requirements of smart grids. Summary of the Invention

[0007] The purpose of this invention is to provide a meter sampling filter chip and system with an integrated programmable anti-aliasing filter to solve the problems mentioned in the background art.

[0008] To achieve the above objectives, the present invention provides the following technical solution: a meter sampling filter chip and system integrating a programmable anti-aliasing filter, comprising: The programmable anti-aliasing filter module provides initial isolation from other circuit regions through a guard ring structure. The programmable anti-aliasing filter module includes a switched capacitor array. The digital control and interface module includes a digital control interface configured as an I2C / SPI interface, which communicates with an external microcontroller. The collaborative control unit is placed in a deep N-well isolation structure to form an independent isolation island. The collaborative control unit includes a multi-mode operational amplifier network and a modulator. The multi-mode operational amplifier network adopts a folded common source and common gate design. The multi-mode operational amplifier network is close to the modulator to shorten the trace distance of the high-sensitivity analog signal. The modulator is surrounded by its own guard ring structure. The analog section of the programmable anti-aliasing filter module and the collaborative control unit is powered by the first power domain, while the digital control and interface module is independently powered by the second power domain. The meter sampling filter chip with integrated programmable anti-aliasing filter uses 180nm BCD process to achieve analog-to-digital isolation.

[0009] Preferably, the switched capacitor array consists of multiple capacitor units and a switching network, and the switched capacitor array adopts MIM capacitor array and laser trimming technology.

[0010] Preferably, the multimodal operational amplifier network is a programmable feedback network, which is configured as a Bessel filter, a Butterworth filter, and a Chebyshev filter mode. Among them, the Bessel mode optimizes phase linearity, with a phase error of no more than 0.1°; Butterworth mode optimizes passband flatness; Chebyshev mode optimizes high-frequency roll-off, achieving -30dB noise suppression at 150kHz.

[0011] Preferably, the digital control interface integrates a cyclic redundancy check module and a status interrupt pin, allowing the filter's cutoff frequency, filter type, and order to be set programmatically. The digital control and interface module also includes an operational amplifier mode register, which is configured to be physically connected to the multi-mode operational amplifier network.

[0012] Preferably, the collaborative control unit further includes a noise monitoring module and a non-volatile memory. The noise monitoring module calculates the signal-to-noise ratio by analyzing the modulator sampling data through fast Fourier transform and automatically switches the filter mode according to the signal-to-noise ratio threshold. The non-volatile memory is located at the edge of the digital area and is isolated by a deep N-well isolation structure isolation layer, and is used to store the adjustment values ​​of the operational amplifier and switched capacitor array.

[0013] Preferably, it includes the following steps: S1 noise monitoring: Collects raw noise signals from the environment; S2 parameter configuration: Set sampling frequency, filter threshold, and modulator accuracy parameters; S3 filter plate treatment: Removes interference noise from the signal; S4 modulator sampling: converts the filtered analog signal into a digital signal; S5 metering output: Outputs noise decibel value and frequency distribution measurement results; S6 Result Application Storage: Stores the data.

[0014] Preferably, the parameter configuration stage includes the initialization of the switched capacitor array and the calculation of control codes: After execution begins, the switched capacitor array is configured, key parameters are initialized, the cutoff frequency control code is input, the capacitor array control register is output, and the unit capacitance is set. Defined as The corresponding physical value is 0.5pF. Using the Q15 fixed-point format, the variable of the accumulated total capacitance is... Initialize to 0; The process involves iterative parsing and weighted accumulation of the control code, with index i ranging from 0 to 3, checking each bit of the cutoff frequency control code sequentially. i represents the current position of the frequency control code being checked. i=0 indicates checking the least significant bit, and i=3 indicates checking the most significant bit. In each loop, the bit operation cutoff frequency control code is used to check if the i-th bit is 1; If the value is 1, an accumulation operation is performed, and the accumulated value is the unit capacitance. Multiply by a weight, binary weighted design; Total capacitance The calculation formula is as follows:

[0015] This is the calculated total capacitance value; Unit capacitance; , , , Each bit represents the value of a 4-bit frequency control code; each bit can only be 0 or 1. , , , These are the weights in the "binary weighted" calculation, corresponding to 1, 2, 4, and 8 respectively; if If this bit is activated, then the calculation is performed. And accumulate to the top superior; if If the bit is not active, and the accumulated value is 0, then skip the bit and do not accumulate it. The loop ends when i ≥ 4, laser trimming compensation is applied, and the result is output to a register. ; ; The value to be written to the hardware capacitor array control register. This is the ideal capacitance value calculated by the software. This refers to the error value of an individual piece of hardware. Represents the first configuration register. This represents the second configuration register.

[0016] Preferably, the noise monitoring phase includes a signal-to-noise ratio adaptive switching mechanism: When a power grid signal is input, the modulator inside the chip starts working, sampling the input analog signal and converting it into a digital signal waveform. The microcontroller performs a fast Fourier transform analysis on the digital signal sampled by the modulator to calculate the current noise frequency harmonics. The system calculates the signal-to-noise ratio of the current signal and compares it with a preset threshold; When the signal-to-noise ratio is <70dB, it is a high-noise environment: the noise is very large and the signal quality is poor. Select the "Bessel wideband mode" cutoff frequency: 50kHz, configure the filter chip through the I2C / SPI interface, keep the modulator sampling rate at 100kHz, and at the same time, the interrupt pin triggers a hardware interrupt to notify the microcontroller that the configuration is complete. The microcontroller reads the status register to confirm the configuration and samples the input analog signal in real time through the modulator. When the signal-to-noise ratio is ≥70dB, it is a low-noise environment with high signal quality. Select the "Chebyshev narrowband mode" cutoff frequency: 100kHz. Configure the filter chip through the I2C / SPI interface, update the modulator sampling rate to 200kHz, and at the same time, the interrupt pin triggers a hardware interrupt to notify the microcontroller that the configuration is complete. The configuration is confirmed by reading the status register through the microcontroller, and the input analog signal is sampled in real time through the modulator.

[0017] Preferably, different configuration modes are selected according to the filter type; When Bessel mode is selected, the input is fed into the multimode op-amp network, the op-amp feedback resistor Rf is modified to 10kΩ, the LC network is disabled, and the op-amp control register value is output. When Butterworth mode is selected, the input is fed into the multimode op-amp network, and the op-amp feedback resistor Rf=15kΩ is modified to output the op-amp control register value. When Chebyshev mode is selected, the input is fed into the multimode op-amp network. The op-amp feedback resistor Rf is modified to 20kΩ to enable the LC network and output the op-amp control register value.

[0018] Preferably, data is received via the I2C / SPI interface. Before sending the data, the cyclic redundancy check value of the data is calculated, the cutoff frequency code and the filter type are merged, the I2C interface is called to write the cutoff frequency code and the filter type into register 0x11, with the filter type occupying the high 4 bits and the cutoff frequency code occupying the low 4 bits, the I2C interface is called to write the order into register 0x11, and the data and the cyclic redundancy check value are sent together to the filter chip. After receiving the data, the filter chip calculates the cyclic redundancy check value and compares it with the received cyclic redundancy check value. If the match is successful, the chip actually applies the configuration; if the match fails, the chip ignores the write and reports an error. Hardware interrupts are used instead of software polling to achieve efficient synchronization between the microcontroller and the filter chip; The microcontroller does not need to wait: After the configuration command is issued, the MCU can continue to perform other tasks without constantly checking whether the filter configuration is complete.

[0019] The technical effects and advantages of this invention are as follows: 1. Overcoming the bottleneck of fixed parameters to achieve dynamic adaptive filtering: The core of the programmable filter: Through binary weighted control of the switched capacitor array, the cutoff frequency can be dynamically adjusted in the range of 1kHz–100kHz to adapt to the wide bandwidth requirements from the power frequency fundamental wave (50Hz) to high frequency noise (150kHz); Multimode operational amplifier network: By reconstructing the feedback network (modifying the Rf resistor value and enabling the LC network), the switching between three modes—Bessel (phase error ≤ 0.1°), Butterworth (passband flatness optimization), and Chebyshev (150kHz noise suppression -30dB)—is physically achieved. 2. Eliminate defects in external solutions and improve integration and reliability: Monolithic integrated architecture: Integrating programmable AAF, The modulator core architecture, control logic, and digital interface are integrated into a single chip, reducing the number of external components such as RC networks and operational amplifiers. Efficient configuration of digital interface: Write to registers step by step via I2C / SPI interface (such as 0x11 merge filter type and cutoff frequency code), support CRC check and interrupt response, and configure response time ≤200μs; 3. Resolve cross-domain compatibility issues and meet specific metrology requirements: Phase accuracy guaranteed: Bessel mode optimizes phase linearity (0.1° error) to ensure accurate power calculation; Dynamic range extension: SNR≥78dB, GBW>10MHz, supports 1000:1 current dynamic range measurement, superior to audio filters; 4. To cope with complex power grid noise and achieve intelligent anti-interference: Noise monitoring and adaptation: ADC sampling data is analyzed by FFT, the signal-to-noise ratio is calculated in real time, and the filter mode is automatically switched (e.g., switch to Bessel wideband mode when SNR<70dB, switch to Chebyshev narrowband mode when SNR≥70dB). Noise suppression through isolation design: The Guard Ring isolation layer extends through the perimeter of the chip, and the Deep N-Well forms an independent isolation island, reducing the interference of digital power supply noise on analog signals; 5. Balanced accuracy and real-time performance, supporting smart grid development: Fast response mechanism: The hardware interrupt pin (INT_PIN) triggers a notification within 200μs after configuration, replacing MCU polling and meeting the millisecond-level control requirements of the smart grid; Laser adjustment ensures accuracy: The switched capacitor array is laser-adjusted (accuracy ±0.1%) to ensure precise and controllable frequency response. Attached Figure Description

[0020] Figure 1 This is a physical architecture diagram of the programmable anti-aliasing filter chip of the present invention; Figure 2 This is the physical circuit diagram of the switched capacitor array of the present invention; Figure 3 This is a diagram of the physical structure of the multimodal operational amplifier network of the present invention; Figure 4 This is a design diagram of the digital control interface of the present invention; Figure 5 This is a schematic diagram of the overall process of the present invention; Figure 6 This is a flowchart of the collaborative working mechanism of the present invention; Figure 7 This is a flowchart of the switched capacitor parameters of the present invention; Figure 8 A schematic diagram illustrating the filter type settings of this invention; Figure 9 This is a flowchart of the filter state machine control of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This invention provides, for example Figures 1-9 The meter sampling filter chip and system with integrated programmable anti-aliasing filter shown include: The programmable anti-aliasing filter module provides initial isolation from other circuit regions through a guard ring structure, resisting noise from digital circuits and the substrate, and achieving a signal-to-noise ratio (SNR) of ≥78dB and a gain-bandwidth product (GBW) of >10MHz. The programmable anti-aliasing filter module includes a switched capacitor array. The switched capacitor array changes the total capacitance value connected to the circuit by switching, thereby physically changing the cutoff frequency of the filter. The digital control and interface module includes a digital control interface configured as an I2C / SPI interface. The I2C / SPI interface communicates with an external microcontroller (MCU) and receives external control signals through the I2C / SPI interface, providing a convenient configuration channel. The digital control interface integrates a Cyclic Redundancy Check (CRC) module and a status interrupt pin. When the conversion is complete or an error occurs, the interrupt pin actively notifies the main controller, eliminating the need for continuous MCU polling and improving system efficiency. The Cyclic Redundancy Check (CRC) module is used to verify the correctness of data transmission and improve communication reliability. The filter cutoff frequency, filter type, and order can be set in a programmable manner. The digital control and interface module is isolated to the right of the meter sampling filter chip with an integrated programmable anti-aliasing filter, and is powered by an independent power supply to ensure that digital switching noise does not interfere with sensitive analog signals.

[0023] The collaborative control unit is housed in a deep N-well isolation structure, forming an independent isolation island. The collaborative control unit includes a multimode operational amplifier network and a modulator (ADC). The multimode operational amplifier network adopts a folded cascode design, which ensures a gain-bandwidth product (GBW) > 10MHz to accurately implement various complex transfer functions. By changing the connection method of the internal operational amplifiers or the feedback network, it can be physically reconstructed into one of the three filter types: Bessel, Butterworth, or Chebyshev, to adapt to different application requirements. The multimode operational amplifier network is placed close to the modulator (ADC) to shorten the trace distance for high-sensitivity analog signals, and the modulator (ADC) is surrounded by its own guard ring structure. Modulator-ADC uses The modulator core architecture uses sampling and noise shaping techniques to convert analog signals into high-resolution digital bitstreams with a signal-to-noise ratio (SNR) ≥78dB. This determines the chip's dynamic range and measurement accuracy, ensuring high-precision metrology.

[0024] The analog section of the programmable anti-aliasing filter module and the collaborative control unit is powered by the first power domain, while the digital control and interface module is independently powered by the second power domain. The meter sampling filter chip with integrated programmable anti-aliasing filter uses 180nm BCD process to achieve analog-to-digital isolation; The Guard Ring isolation layer runs through the entire chip, encircling the chip and isolating modules. This layer physically separates the noisy digital circuit power supply from the quiet, sensitive analog circuit power supply, significantly reducing the interference of digital switching noise on analog signals (especially high-precision ADCs) through the power supply. Differential wiring is used for critical analog signals inside the chip (such as filter input / output), effectively suppressing common-mode noise (such as power supply noise and substrate noise) and improving signal integrity.

[0025] By integrating programmable filters, high-precision ADCs, control logic, and digital interfaces into a single chip, the number of external components is reduced, and the product size is minimized.

[0026] Flexible programmability: The filter type and cutoff frequency can be configured through a digital interface, enabling a single hardware platform to adapt to a variety of different application scenarios and greatly improving design flexibility.

[0027] High precision and high reliability: from laser-tuned capacitors, high-performance operational amplifiers, and From the modulator core to the meticulous physical isolation design (deep N-well isolation structure, guard ring structure), measurement accuracy and stable anti-interference capability are achieved.

[0028] A switched capacitor array consists of multiple capacitor units and a switching network. The switched capacitor array adopts MIM (metal-insulator-metal) capacitor array and laser trimming technology.

[0029] MIM capacitors are common passive components in IC manufacturing processes. Their advantages include high precision, good temperature stability, and low parasitic effects. The switched capacitor array consists of 16 (4-bit binary weighted) capacitor units. It consists of a switching network and a digital control bit weighted configuration of the total capacitance value to achieve 16 programmable adjustment of the cutoff frequency in the range of 1kHz to 100kHz. Each capacitor is laser-trimmed with an accuracy of ±0.1%, which is the physical basis for the precise and controllable frequency response of the filter. By switching the switch, the total capacitance value of the circuit is changed, thereby physically altering the cutoff frequency of the filter.

[0030] The multimodal operational amplifier network is a programmable feedback network, which is configured as a Bessel filter, a Butterworth filter, and a Cheby filter mode. Among them, the Bessel mode optimizes phase linearity, with a phase error of no more than 0.1°; Butterworth mode optimizes passband flatness; Chebyshev mode optimizes high-frequency roll-off, achieving -30dB noise suppression at 150kHz.

[0031] Capacitor control logic: Receive user commands, decode them, and then physically control the switching on and off of the switches in the switched capacitor array; The digital control and interface module also includes an op-amp mode register. The op-amp mode register is configured to be physically connected to the multi-mode op-amp network. The register bit fields are used to combine the filter type and cutoff frequency control code, store the filter type selected by the user, support step-by-step configuration and cyclic redundancy check (CRC) verification to ensure the reliability of command transmission. The response time of the digital control interface is no more than 200μs.

[0032] The collaborative control unit also includes a noise monitoring module and a non-volatile memory. The noise monitoring module analyzes the modulator (ADC) sampled data using Fast Fourier Transform (FFT) to calculate the signal-to-noise ratio and automatically switches the filter mode according to the signal-to-noise ratio threshold. The non-volatile memory is located at the edge of the digital area and is isolated by a Deep N-Well isolation layer. It is used to store the tuning values ​​of the operational amplifier and switched capacitor array.

[0033] Example 1: A meter sampling filter chip system integrating a programmable anti-aliasing filter, comprising the following steps: S1 noise monitoring: Collects raw noise signals from the environment; S2 parameter configuration: Set sampling frequency, filter threshold, and modulator (ADC) accuracy parameters; S3 filter plate treatment: Removes interference noise from the signal; S4 modulator (ADC) sampling: converts the filtered analog signal into a digital signal; S5 metering output: Outputs noise decibel value and frequency distribution measurement results; S6 Result Application Storage: Stores the data.

[0034] The parameter configuration phase includes the initialization of the switched capacitor array and the calculation of control codes: After execution begins, the switched capacitor array is configured, key parameters are initialized, the cutoff frequency control code is input, the capacitor array control register is output, and the unit capacitance is set. Defined as This corresponds to a physical value of 0.5pF and uses the Q15 fixed-point format, which is an efficient method for processing decimals in embedded systems; it amplifies the decimal value. The accumulated total capacitance is then stored and calculated using integers. Initialize to 0 to prepare for subsequent weighted accumulation; The process involves iterative parsing and weighted accumulation of the control code, with index i ranging from 0 to 3, checking each bit of the cutoff frequency control code sequentially. i represents the current position of the frequency control code being checked. i=0 indicates checking the least significant bit, and i=3 indicates checking the most significant bit. In each loop, the bit operation cutoff frequency control code is used to check if the i-th bit is 1; If the value is 1, an accumulation operation is performed, and the accumulated value is the unit capacitance. Multiply by a weight, binary weighted design; Total capacitance The calculation formula is as follows:

[0035] This is the calculated total capacitance value; Unit capacitance; , , , Each bit represents the value of a 4-bit frequency control code; each bit can only be 0 or 1. , , , These are the weights in the "binary weighted" calculation, corresponding to 1, 2, 4, and 8 respectively; if (If this bit is activated), then calculate... And accumulate to the top superior; if If the bit is not active, then if the sum is 0, skip the bit and do not accumulate. Achieving dynamic adjustability: Through 16 combinations of 4-bit control codes, it is possible to generate values ​​ranging from 0× To (1+2+4+8)=15× There are 16 different total capacitance values, thus enabling precise control of the cutoff frequency; The loop ends when i ≥ 4, laser trimming compensation is applied, and the result is output to a register. ; ; The value to be written to the hardware capacitor array control register. This is the ideal capacitance value calculated by the software. This refers to the error value of an individual piece of hardware. Represents the first configuration register. This represents the second configuration register.

[0036] Example 2: The noise monitoring phase includes a signal-to-noise ratio adaptive switching mechanism. When a power grid signal is input, the modulator (ADC) inside the chip starts working, sampling the input analog signal and converting it into a digital signal waveform. The microcontroller (MCU) performs Fast Fourier Transform (FFT) analysis on the digital signal sampled by the modulator (ADC), calculates the current noise frequency harmonics, and converts the time-domain signal into a frequency-domain signal, thereby clearly showing the intensity distribution of different frequency components, identifying the main frequency bands where noise is concentrated, and based on the spectrum results, the system can accurately calculate the current power grid signal-to-noise ratio (SNR).

[0037] The system calculates the signal-to-noise ratio (SNR) of the current signal and compares it with a preset threshold (70dB).

[0038] When the signal-to-noise ratio (SNR) is <70dB, it is considered a high-noise environment: the noise is very high and the signal quality is poor. The "Bessel wideband mode" cutoff frequency is selected at 50kHz. Setting a higher cutoff frequency allows richer high-frequency harmonic components in the signal to pass through, ensuring waveform integrity. The filter chip is configured via the I2C / SPI interface to maintain the modulator (ADC) sampling rate at 100kHz. Since the cutoff frequency is 50kHz, the original 100kHz sampling rate still satisfies the Nyquist theorem and therefore does not need to be changed. Simultaneously, the interrupt pin (INT_PIN) triggers a hardware interrupt to notify the microcontroller (MCU) that the configuration is complete. The microcontroller (MCU) reads the status register to confirm the configuration and samples the input analog signal in real time via the modulator (ADC). When the signal-to-noise ratio (SNR) is ≥70dB, indicating a low-noise environment with high signal quality, the "Chebyshev narrowband mode" cutoff frequency is selected at 100kHz. Setting a relatively low cutoff frequency allows for more aggressive filtering of high-frequency noise. The filter chip is configured via the I2C / SPI interface, and the modulator-translated converter (ADC) sampling rate is updated to 200kHz. According to the Nyquist sampling theorem, the sampling rate must be greater than twice the highest frequency of the signal. Since the filter cutoff frequency is set to 100kHz, updating the ADC sampling rate to 200kHz is sufficient and efficient, avoiding unnecessary data burden caused by excessively high sampling. At the same time, the interrupt pin (INT_PIN) triggers a hardware interrupt to notify the microcontroller (MCU) that the configuration is complete. The microcontroller (MCU) reads the status register to confirm the configuration and samples the input analog signal in real time through the modulator (ADC).

[0039] After the filter chip completes the mode switching and ADC sampling rate reconfiguration, it will send a hardware interrupt signal to the MCU through a dedicated interrupt pin (INT_PIN). The new configuration has taken effect and a new acquisition cycle can begin. Based on real-time noise information, the system automatically switches between "Bessel wideband mode" and "Chebyshev narrowband mode" to maintain optimal operating conditions.

[0040] Select different configuration modes based on the filter type; When Bessel mode is selected, the input is fed into the multimode op-amp network, the op-amp feedback resistor Rf is modified to 10kΩ, the LC network is disabled, and the op-amp control register value is output. When Butterworth mode is selected, the input is fed into the multimode op-amp network, and the op-amp feedback resistor Rf=15kΩ is modified to output the op-amp control register value. When Chebyshev mode is selected, the input is fed into the multimode op-amp network. The op-amp feedback resistor Rf is modified to 20kΩ to enable the LC network and output the op-amp control register value.

[0041] Data is received via the I2C / SPI interface. Before sending data, the cyclic redundancy check (CRC) value of the data is calculated. The cutoff frequency code and filter type are combined. The I2C interface is called to write the cutoff frequency code and filter type into register 0x11, with the filter type occupying the high 4 bits and the cutoff frequency code occupying the low 4 bits. The I2C interface is called to write the order into register 0x11. The data and the cyclic redundancy check (CRC) value are sent together to the filter chip. After receiving the data, the filter chip calculates the Cyclic Redundancy Check (CRC) value and compares it with the received CRC value. If the match is successful, the chip actually applies the configuration; if the match fails, the chip ignores the write and reports an error. Using hardware interrupts instead of software polling enables efficient synchronization between the microcontroller (MCU) and the filter chip; The microcontroller (MCU) does not need to wait: After the configuration command is issued, the MCU can continue to perform other tasks without constantly checking whether the filter configuration is complete.

[0042] Event-driven: After the filter chip completes its internal configuration (including register updates, settling time, etc., with a total time ≤200μs), it is ready to receive interrupt signals. Once the microcontroller (MCU) sends this signal, the chip will immediately generate an interrupt to the microcontroller (MCU), informing it that "the configuration has taken effect and data transmission has begun". To meet the real-time requirements of the power grid: The "configuration-interrupt response" mode stabilizes the configuration delay within a very short and predictable time (200μs), ensuring the deterministic response of the entire system. 200μs is the minimum and sufficient time set according to the chip datasheet requirements, ensuring that the chip has enough time to latch the register value and switch to the new working state, avoiding data operations when the state is unstable, thus ensuring the real-time performance and reliability of the system from another dimension. It strictly followed the safety process of "parameter preparation - step-by-step writing - sending a completion signal"; High reliability: The correctness of configuration commands is guaranteed through multiple means, including step-by-step writing, hardware cyclic redundancy check (CRC) verification, and precise bit manipulation. High real-time performance: By utilizing hardware interrupts and precise delays, it achieves fast and deterministic synchronization with the microcontroller (MCU), perfectly meeting the real-time requirements of power grids and other applications.

[0043] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A meter sampling filter chip integrating a programmable anti-aliasing filter, characterized in that, include: The programmable anti-aliasing filter module provides initial isolation from other circuit regions through a guard ring structure. The programmable anti-aliasing filter module includes a switched capacitor array. The digital control and interface module includes a digital control interface configured as an I2C / SPI interface, which communicates with an external microcontroller. The collaborative control unit is placed in a deep N-well isolation structure to form an independent isolation island. The collaborative control unit includes a multi-mode operational amplifier network and a modulator. The multi-mode operational amplifier network adopts a folded common source and common gate design. The multi-mode operational amplifier network is close to the modulator to shorten the trace distance of the high-sensitivity analog signal. The modulator is surrounded by its own guard ring structure. The analog section of the programmable anti-aliasing filter module and the collaborative control unit is powered by the first power domain, while the digital control and interface module is independently powered by the second power domain. The meter sampling filter chip with integrated programmable anti-aliasing filter uses 180nm BCD process to achieve analog-to-digital isolation.

2. The meter sampling filter chip with integrated programmable anti-aliasing filter according to claim 1, characterized in that, The switched capacitor array consists of multiple capacitor units and a switching network, and the switched capacitor array adopts MIM capacitor array and laser trimming technology.

3. The meter sampling filter chip with integrated programmable anti-aliasing filter according to claim 1, characterized in that, The multimodal operational amplifier network is a programmable feedback network, which is configured as a Bessel filter, a Butterworth filter, and a Chebyshev filter mode. Among them, the Bessel mode optimizes phase linearity, with a phase error of no more than 0.1°; Butterworth mode optimizes passband flatness; Chebyshev mode optimizes high-frequency roll-off, achieving -30dB noise suppression at 150kHz.

4. The meter sampling filter chip with integrated programmable anti-aliasing filter according to claim 1, characterized in that, The digital control interface integrates a cyclic redundancy check module and a status interrupt pin, allowing the filter's cutoff frequency, filter type, and order to be set programmatically. The digital control and interface module also includes an operational amplifier mode register, which is configured to be physically connected to the multi-mode operational amplifier network.

5. The meter sampling filter chip with integrated programmable anti-aliasing filter according to claim 1, characterized in that, The collaborative control unit also includes a noise monitoring module and a non-volatile memory. The noise monitoring module calculates the signal-to-noise ratio by analyzing the modulator sampled data through fast Fourier transform and automatically switches the filter mode according to the signal-to-noise ratio threshold. The non-volatile memory is located at the edge of the digital area and is isolated by a deep N-well isolation structure layer. It is used to store the adjustment values ​​of the operational amplifier and switched capacitor array.

6. A meter sampling filter chip system with an integrated programmable anti-aliasing filter, as described in any one of claims 1-5, characterized in that, Includes the following steps: S1 noise monitoring: Collects raw noise signals from the environment; S2 parameter configuration: Set sampling frequency, filter threshold, and modulator accuracy parameters; S3 filter plate treatment: Removes interference noise from the signal; S4 modulator sampling: converts the filtered analog signal into a digital signal; S5 metering output: Outputs noise decibel value and frequency distribution measurement results; S6 Result Application Storage: Stores the data.

7. The meter sampling filter chip system with integrated programmable anti-aliasing filter according to claim 6, characterized in that, The parameter configuration phase includes the initialization of the switched capacitor array and the calculation of control codes: After execution begins, the switched capacitor array is configured, key parameters are initialized, the cutoff frequency control code is input, the capacitor array control register is output, and the unit capacitance is set. Defined as The corresponding physical value is 0.5pF. Using the Q15 fixed-point format, the variable of the accumulated total capacitance is... Initialize to 0; The process involves iterative parsing and weighted accumulation of the control code, with index i ranging from 0 to 3, checking each bit of the cutoff frequency control code sequentially. i represents the current position of the frequency control code being checked. i=0 indicates checking the least significant bit, and i=3 indicates checking the most significant bit. In each loop, the bit operation cutoff frequency control code is used to check if the i-th bit is 1; If the value is 1, an accumulation operation is performed, and the accumulated value is the unit capacitance. Multiply by a weight, binary weighted design; Total capacitance The calculation formula is as follows: This is the calculated total capacitance value; Unit capacitance; , , , Each bit represents the value of a 4-bit frequency control code; each bit can only be 0 or 1. , , , These are the weights in the "binary weighted" calculation, corresponding to 1, 2, 4, and 8 respectively; if If this bit is activated, then the calculation is performed. And accumulate to the top superior; if If the bit is not active, and the accumulated value is 0, then skip the bit and do not accumulate. The loop ends when i ≥ 4, laser trimming compensation is applied, and the result is output to a register. ; ； The value to be written to the hardware capacitor array control register. This is the ideal capacitance value calculated by the software. This refers to the error value of an individual piece of hardware. Represents the first configuration register. This represents the second configuration register.

8. The meter sampling filter chip system with integrated programmable anti-aliasing filter according to claim 6, characterized in that, The noise monitoring phase includes a signal-to-noise ratio adaptive switching mechanism: When a power grid signal is input, the modulator inside the chip starts working, sampling the input analog signal and converting it into a digital signal waveform. The microcontroller performs a fast Fourier transform analysis on the digital signal sampled by the modulator to calculate the current noise frequency harmonics. The system calculates the signal-to-noise ratio of the current signal and compares it with a preset threshold; When the signal-to-noise ratio is <70dB, it is a high-noise environment: the noise is very large and the signal quality is poor. Select the "Bessel wideband mode" cutoff frequency: 50kHz, configure the filter chip through the I2C / SPI interface, keep the modulator sampling rate at 100kHz, and at the same time, the interrupt pin triggers a hardware interrupt to notify the microcontroller that the configuration is complete. The microcontroller reads the status register to confirm the configuration and samples the input analog signal in real time through the modulator. When the signal-to-noise ratio is ≥70dB, it is a low-noise environment with high signal quality. Select "Chebyshev Narrowband Mode" with a cutoff frequency of 100kHz. Configure the filter chip through the I2C / SPI interface, update the modulator sampling rate to 200kHz, and trigger a hardware interrupt on the interrupt pin to notify the microcontroller that the configuration is complete. The microcontroller reads the status register to confirm the configuration and samples the input analog signal in real time through the modulator.

9. The meter sampling filter chip system with integrated programmable anti-aliasing filter according to claim 6, characterized in that, Select different configuration modes based on the filter type; When Bessel mode is selected, the input is fed into the multimode op-amp network, the op-amp feedback resistor Rf is modified to 10kΩ, the LC network is disabled, and the op-amp control register value is output. When Butterworth mode is selected, the input is fed into the multimode op-amp network, and the op-amp feedback resistor Rf=15kΩ is modified to output the op-amp control register value. When Chebyshev mode is selected, the input is fed into the multimode op-amp network. The op-amp feedback resistor Rf is modified to 20kΩ to enable the LC network and output the op-amp control register value.

10. The meter sampling filter chip system with integrated programmable anti-aliasing filter according to claim 6, characterized in that, Data is received via the I2C / SPI interface. Before sending the data, the cyclic redundancy check value of the data is calculated. The cutoff frequency code and filter type are merged. The I2C interface is called to write the cutoff frequency code and filter type into register 0x11. The filter type occupies the high 4 bits and the cutoff frequency code occupies the low 4 bits. The I2C interface is called to write the order into register 0x11. The data and the cyclic redundancy check value are sent together to the filter chip. After receiving the data, the filter chip calculates the cyclic redundancy check value and compares it with the received cyclic redundancy check value. If the match is successful, the chip actually applies the configuration; if the match fails, the chip ignores the write and reports an error. Hardware interrupts are used instead of software polling to achieve efficient synchronization between the microcontroller and the filter chip; The microcontroller does not need to wait: After the configuration command is issued, the microcontroller can continue to perform other tasks without constantly checking whether the filter configuration is complete.

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