Signal processing circuit and receiver

Abstract

The invention provides a signal processing circuit and a receiver, and relates to the technical field of signal processing.The signal processing circuit comprises a signal input interface, a signal processing unit, a signal conversion unit and a signal output interface which are sequentially connected; the signal processing unit comprises a low-frequency extraction unit, a main amplification unit and a signal merging unit, the low-frequency extraction unit and the main amplification unit are arranged in parallel, input ends of the low-frequency extraction unit and the main amplification unit are connected with the signal input interface, and output ends of the low-frequency extraction unit and the main amplification unit are connected with the signal merging unit; according to the signal processing circuit and the receiver provided by the invention, the low-frequency extraction unit and the main amplification unit are arranged in parallel, so that synchronous processing of the main amplification unit and the low-frequency extraction unit is realized to obtain the synthesized signal, a signal with high-frequency compensation and low-frequency gain recovery can be formed, and an output signal with better jitter performance is obtained after signal conversion; the stability of a post-stage processing circuit can be remarkably improved, and the bit error rate of a receiver is further reduced.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and in particular to a signal processing circuit and receiver. Background Technology

[0002] Typically, a wired signal transmission system consists of three parts: a transmitter, a transmission cable, and a receiver. The transmitter acts as the transmitting end, and the receiver acts as the receiving end. Both the transmitter and receiver have corresponding PCB (Printed Circuit Board) circuitry. In practical applications, the PCB circuitry often integrates a bandpass filter, which can suppress low-frequency and high-frequency interference while allowing the useful signal to pass through. This prevents interference signals from affecting the receiver and also avoids electromagnetic radiation generated during cable transmission from interfering with other equipment.

[0003] However, the filters on the PCB board where the PBC circuit resides, while eliminating interference signals, also attenuate the useful signal. Therefore, when the transmitted signal output by the transmitter enters the receiver after passing through the channel, the signal integrity will decrease, causing the receiver's bit error rate to increase. To compensate for the impact of channel loss, signal compensation is required based on the channel characteristics.

[0004] Signal compensation can be implemented at either the transmitting or receiving end. For high-frequency component attenuation, compensation can be achieved using techniques such as de-emphasis at the transmitting end, continuous-time linear equalization at the receiving end, and feedback decision equalization. For low-frequency component attenuation, existing solutions employ feedback compensation techniques; however, this technique has significant limitations, resulting in poor compensation effectiveness and increasing the risk of bit errors in the receiver. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a signal processing circuit and a receiver to alleviate the technical problem of poor receiver compensation technology leading to increased risk of bit error rate in the receiver.

[0006] In a first aspect, embodiments of the present invention provide a signal processing circuit applied to a receiver. The signal processing circuit includes: a signal input interface, a signal processing unit, a signal conversion unit, and a signal output interface connected in sequence. The signal processing unit includes a low-frequency extraction unit, a main amplification unit, and a signal combining unit. The low-frequency extraction unit and the main amplification unit are connected in parallel, and the input terminals of the low-frequency extraction unit and the main amplification unit are connected to the signal input interface. The output terminals of the low-frequency extraction unit and the main amplification unit are connected to the signal combining unit. The signal input interface is used to receive an input signal. The low-frequency extraction unit is used to extract the low-frequency envelope contained in the input signal to obtain a low-frequency compensation component. The main amplification unit is used to amplify and equalize the input signal to obtain a main path signal. The signal combining unit is used to combine the low-frequency compensation component and the main path signal to obtain a synthesized signal. The signal conversion unit is used to convert the synthesized signal into a corresponding digital signal and output it.

[0007] In conjunction with the first aspect, the present invention provides a first possible implementation of the first aspect, wherein the signal processing unit further includes a primary amplifier; wherein the input terminal of the primary amplifier is connected to the signal input interface; the output terminal of the primary amplifier is connected to the input terminals of the low-frequency extraction unit and the main amplification unit; and the input signal, after being amplified by the primary amplifier, enters the low-frequency extraction unit and the main amplification unit.

[0008] In conjunction with the first aspect, this embodiment of the invention provides a second possible implementation of the first aspect, wherein the main amplification unit includes a continuous-time linear equalizer; the continuous-time linear equalizer is used to compensate for high-frequency components contained in the input signal and synchronously convert the compensated voltage signal into a second current signal.

[0009] In conjunction with the second possible implementation of the first aspect, this embodiment of the invention provides a third possible implementation of the first aspect, wherein the low-frequency extraction unit includes a low-pass filter and a transconductance unit connected in sequence; the low-pass filter is used to extract the low-frequency envelope voltage signal included in the input signal; the transconductance unit is used to convert the low-frequency envelope voltage signal into a first current signal; the signal combining unit includes a current adder; the current adder is used to combine the first current signal and the second current signal to obtain the synthesized signal.

[0010] In conjunction with the second possible implementation of the first aspect, this embodiment of the invention provides a fourth possible implementation of the first aspect, wherein the low-frequency extraction unit includes a low-pass filter and a hysteresis unit connected in sequence; the low-pass filter is used to extract the low-frequency envelope voltage signal included in the input signal; the hysteresis unit includes a first comparator and a second comparator connected in parallel, as well as a control logic circuit and a current DAC unit; wherein the first comparator and the second comparator are comparators with opposite hysteresis voltage polarities; the input terminals of the first comparator and the second comparator are connected to the output terminal of the low-pass filter, and the output terminals of the first comparator and the second comparator are connected to the control logic circuit; the first comparator and the second comparator are used to output a corresponding symbol signal according to the range of the low-frequency envelope voltage signal; the control logic circuit is used to output a corresponding enable signal based on the symbol signal and send the enable signal to the current DAC unit; the current DAC unit is used to inject a corresponding compensation current into the signal merging unit according to the enable signal.

[0011] In conjunction with the fourth possible implementation of the first aspect, this embodiment of the invention provides a fifth possible implementation of the first aspect, wherein the initial symbol signal of the first comparator is configured as a high-level symbol; when the low-frequency envelope voltage signal is greater than 0, the first comparator outputs a high-level symbol; when the low-frequency envelope voltage signal is less than a preset low-voltage threshold, the output of the first comparator switches to a low-level symbol; the initial symbol signal of the second comparator is configured as a low-level symbol; when the low-frequency envelope voltage signal is greater than a preset high-voltage threshold, the second comparator outputs a high-level symbol; when the low-frequency envelope voltage signal is less than 0, the output of the second comparator switches to a low-level symbol.

[0012] In conjunction with the fifth possible implementation of the first aspect, this embodiment of the invention provides a sixth possible implementation of the first aspect, wherein the control logic circuit is further configured to: monitor the symbol signals output by the first comparator and the second comparator; if the symbol signals output by the first comparator and the second comparator are continuous symbol signals, and the continuous symbol signals are low-level symbols, then output a first enable signal, the first enable signal being an enable signal for controlling the current DAC unit to perform negative low-frequency compensation; if the symbol signals output by the first comparator and the second comparator are continuous symbol signals, and the continuous symbol signals are high-level symbols, then output a second enable signal, the second enable signal being an enable signal for controlling the current DAC unit to perform positive low-frequency compensation.

[0013] In conjunction with the fourth possible implementation of the first aspect, this embodiment of the invention provides a seventh possible implementation of the first aspect, wherein the signal merging unit includes a current adder; the enable signal output by the control logic circuit includes a first enable signal and a second enable signal; the current DAC unit includes a switching circuit and a differential current mirror circuit connected to the switching circuit; the differential current mirror circuit includes a first current mirror circuit and a second current mirror circuit, and output terminals corresponding to the first current mirror circuit and the second current mirror circuit respectively; wherein the output terminals corresponding to the first current mirror circuit and the second current mirror circuit are connected to the positive and negative terminals of the current adder respectively; the switching circuit is used to respond to the first enable signal or the second enable signal, and control the switching of the first current mirror circuit and the second current mirror circuit through the first enable signal or the second enable signal, so as to inject a corresponding compensation current into the current adder of the signal merging unit.

[0014] In conjunction with the seventh possible implementation of the first aspect, this embodiment of the invention provides an eighth possible implementation of the first aspect, wherein the first current mirror circuit includes a first switch and a first current source connected in series; the second current mirror circuit includes a second switch and a second current source connected in series; the first switch is disposed between the output terminal of the first current mirror circuit and the first current source; the second switch is disposed between the output terminal of the second current mirror circuit and the second current source; the switch circuit includes an output terminal connected to the first switch and an output terminal connected to the second switch; or, the first current mirror circuit includes a first current source, a first switch, a second switch, and a second current source connected in series; the output terminal of the first current mirror circuit is disposed between the first switch and the second switch; the second current mirror circuit includes a third current source, a third switch, a fourth switch, and a fourth current source connected in series; the output terminal of the second current mirror circuit is disposed between the third switch and the fourth switch; the switch circuit includes an output terminal connected to the first switch and the third switch and an output terminal connected to the second switch and the fourth switch.

[0015] Secondly, embodiments of the present invention also provide a receiver, the receiver being configured with the signal processing circuit described in the first aspect.

[0016] The embodiments of the present invention bring the following beneficial effects: The signal processing circuit and receiver provided in this embodiment of the invention include a signal input interface, a signal processing unit, a signal conversion unit, and a signal output interface connected in sequence in the signal processing circuit. The signal processing unit includes a low-frequency extraction unit, a main amplification unit, and a signal combining unit, wherein the low-frequency extraction unit and the main amplification unit are arranged in parallel. The signal input interface is used to receive the input signal. The low-frequency extraction unit is used to extract the low-frequency envelope contained in the input signal to obtain a low-frequency compensation component. The main amplification unit is used to amplify and equalize the input signal to obtain the main path signal. The signal combining unit is used to combine the low-frequency compensation component and the main path signal to obtain a composite signal. The signal conversion unit is used to convert the composite signal into a corresponding digital signal and output it. Since the low-frequency extraction unit and the main amplification unit are arranged in parallel, a dual-channel parallel processing mechanism can be realized, enabling the main amplification unit and the low-frequency extraction unit to process synchronously. The composite signal obtained by combining the two signals can be superimposed with the low-frequency compensation component to form a signal that combines high-frequency compensation and low-frequency gain recovery. After signal conversion, an output signal with better jitter performance can be obtained, which can significantly improve the stability of the subsequent processing circuit and thus reduce the bit error rate of the receiver.

[0017] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0018] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0019] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of a signal processing circuit provided in an embodiment of the present invention; Figure 2 A circuit diagram of a signal processing circuit provided in an embodiment of the present invention; Figure 3 A circuit diagram of another signal processing circuit provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the working principle of a signal processing circuit provided in an embodiment of the present invention; Figure 5 A schematic diagram of a current DAC unit provided in an embodiment of the present invention; Figure 6 A schematic diagram of another current DAC unit provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of another signal processing circuit provided in an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Currently, in wired transmission systems, existing solutions for attenuation of low-frequency components mostly adopt a feedback compensation method, that is, by extracting the low-frequency components of the received signal, comparing them with preset values ​​to generate a compensation signal, and adjusting the low-frequency signal components through a feedback loop to achieve low-frequency signal component compensation. However, this solution has obvious limitations, such as the feedback loop requiring multiple symbol cycles to complete low-frequency component extraction, comparison, and adjustment, making it unable to respond promptly to sudden pulse signals. Furthermore, the feedback loop needs to be re-established after each received signal pulse, and the low-frequency components of different data segments differ, making it impossible to reuse compensation parameters. This delayed compensation characteristic causes low-frequency compensation to fail in the initial stage of the received signal, thereby increasing the risk of bit errors in the receiver.

[0022] Based on this, the signal processing circuit and receiver provided in this embodiment of the invention can adopt a feedforward low-frequency gain compensation scheme to reduce the bit error rate of the receiver.

[0023] To facilitate understanding of this embodiment, a signal processing circuit disclosed in this embodiment of the invention will first be described in detail.

[0024] In one possible implementation, the present invention provides a signal processing circuit applied to a receiver. Specifically, the signal processing circuit serves as the front-end signal processing circuit of the receiver, directly processing the input signal received by the receiver. The signal output by the signal processing circuit can be further input to a subsequent processing circuit for processing and identification.

[0025] Specifically, such as Figure 1 The diagram shows a schematic of a signal processing circuit. The signal processing circuit provided in this embodiment of the invention includes a signal input interface 10, a signal processing unit 20, a signal conversion unit 30, and a signal output interface 40 connected in sequence.

[0026] The signal processing unit 20 includes a low-frequency extraction unit 201, a main amplification unit 202, and a signal merging unit 203. The low-frequency extraction unit 201 and the main amplification unit 202 are connected in parallel. The input terminals of the low-frequency extraction unit 201 and the main amplification unit 202 are connected to the signal input interface 10, and the output terminals of the low-frequency extraction unit 201 and the main amplification unit 202 are connected to the signal merging unit 203.

[0027] The signal input interface 10 is used to receive the input signal; the low-frequency extraction unit 201 is used to extract the low-frequency envelope contained in the input signal to obtain the low-frequency compensation component; the main amplification unit 202 is used to amplify and equalize the input signal to obtain the main path signal; the signal merging unit 203 is used to merge the low-frequency compensation component and the main path signal to obtain the synthesized signal; and the signal conversion unit is used to convert the synthesized signal into the corresponding digital signal and output it.

[0028] In practical use, the aforementioned low-frequency extraction unit is also called the low-frequency component extraction path, and the main amplification unit is also called the main processing path. Furthermore, the aforementioned signal conversion unit usually includes a comparator, which processes the synthesized signal through a preset threshold to obtain a digital signal. Therefore, the aforementioned signal conversion unit actually implements the function of analog-to-digital conversion.

[0029] In traditional receiver architectures, small-amplitude signals (i.e., input signals) input from transmission cables need to be processed by amplification and equalization circuits. The core objective is to provide the comparator of the signal conversion unit with a signal of larger amplitude and better integrity, so as to determine the output signal with less jitter. To address the challenge of compensating for low-frequency attenuation in PCB circuits on a PCB board during burst reception scenarios, in this embodiment of the invention, the aforementioned signal processing circuit can be used as a feedforward low-frequency gain compensation module in the receiver's receiving link. It employs a dual-path parallel processing mechanism with a low-frequency extraction unit and a main amplification unit connected in parallel. This allows the main amplification unit to perform conventional amplification and equalization processing, while the synchronously activated low-frequency extraction unit acquires the low-frequency envelope contained in the input signal through amplification and low-pass filtering. During the signal combining stage, the processing results of the two signals are integrated by the signal combining unit. This results in a signal with both high-frequency compensation and low-frequency gain recovery—the synthesized signal in this embodiment—after the main path signal of the main amplification unit is superimposed with the low-frequency compensation component. This synthesized signal is ultimately fed into the comparator of the signal converter, generating an output signal with superior jitter performance. This significantly improves the stability of subsequent processing circuits, thereby reducing the receiver's bit error rate.

[0030] In practical use, the signal processing unit in this embodiment of the invention further includes a primary amplifier; the input terminal of the primary amplifier is connected to the signal input interface; the output terminal of the primary amplifier is connected to the input terminals of the low-frequency extraction unit and the main amplification unit; after the input signal is amplified by the primary amplifier, it enters the low-frequency extraction unit and the main amplification unit.

[0031] For ease of understanding, Figure 2 A circuit diagram of a signal processing circuit is shown, including the aforementioned primary amplifier U1. For ease of explanation, Figure 2 In this context, RX input represents the input signal, and RX output represents the output signal.

[0032] Furthermore, in this embodiment of the invention, the main amplification unit includes a continuous-time linear equalizer; the continuous-time linear equalizer is used to compensate for high-frequency components contained in the input signal and synchronously convert the compensated voltage signal into a second current signal. The low-frequency extraction unit includes a low-pass filter and a transconductance unit connected in sequence; the low-pass filter is used to extract the low-frequency envelope voltage signal included in the input signal; the transconductance unit is used to convert the low-frequency envelope voltage signal into a first current signal; the signal combining unit includes a current adder; the current adder is used to combine the first current signal and the second current signal to obtain a synthesized signal.

[0033] Specifically, Figure 2 The diagram also illustrates a continuous-time linear equalizer, a low-pass filter (LPF), a transconductance unit (gm), a current adder (J1), and a comparator (comp) in the signal conversion unit. The input signal received by the receiver is first amplified by a primary amplifier (U1), and then enters the continuous-time linear equalizer and the low-pass filter. The low-pass filter extracts the low-frequency envelope voltage signal of the input signal, which is then converted into a first current signal by the transconductance unit. The continuous-time linear equalizer compensates for the high-frequency components of the input signal and synchronously converts the adjusted voltage signal into a second current signal. For the current adder, the first and second current signals from the main amplification unit and the low-frequency extraction unit are combined to form a synthesized signal with low-frequency compensation and a large swing. This synthesized voltage signal is finally input to the comparator to determine the receiver's output signal.

[0034] in, Figure 2The diagram shows a continuous-time linear equalizer (CTLE) followed by a transconductance, i.e., CTLE gm. In practical applications, the main function of this CTLE is to equalize the input signal to improve signal quality. Furthermore, CTLEs typically have high-frequency response characteristics, allowing for signal equalization within a high-frequency range. A typical CTLE consists of a current source and a current control circuit, used to adjust the output current according to the signal's frequency characteristics. Therefore, a CTLE is often also referred to as a CTLE current source. In this embodiment, the specific model and parameters of the CTLE can be set according to actual usage, and this embodiment does not impose any limitations on this.

[0035] Furthermore, in this embodiment of the invention, in order to facilitate compensation for low-frequency components included in the input signal, in addition to the above-mentioned series connection of the low-pass filter and hysteresis unit, the low-frequency extraction unit in this embodiment of the invention may also include a low-pass filter and a hysteresis unit connected in sequence.

[0036] Specifically, for ease of explanation, Figure 3 A circuit diagram of another signal processing circuit is also shown, such as... Figure 3 As shown, a low-pass filter (LPF) is included to extract the low-frequency envelope voltage signal included in the input signal. Further, Figure 3 It also includes hysteresis units, specifically, such as Figure 3 As shown in the embodiment of the present invention, the hysteresis unit includes a first comparator D1 and a second comparator D2 connected in parallel, as well as a control logic circuit 31 and a current DAC unit 32; wherein, the first comparator D1 and the second comparator D2 are comparators with opposite hysteresis voltage polarities; and, the input terminals of the first comparator D1 and the second comparator D2 are connected to the output terminal of the low-pass filter LPF, and the output terminals of the first comparator D1 and the second comparator D2 are connected to the control logic circuit 31; the first comparator D1 and the second comparator D2 are used to output corresponding symbol signals according to the range of the low-frequency envelope voltage signal; the control logic circuit 31 is used to output corresponding enable signals based on the symbol signals and send the enable signals to the current DAC unit 32; the current DAC unit 32 is used to inject corresponding compensation current into the signal merging unit according to the enable signal.

[0037] In practical implementation, Figure 3 The signal processing circuit shown is Figure 2 The main difference in the signal processing circuits shown lies in the post-processing circuit following the low-pass filter. Figure 2 In the middle, the low-frequency envelope voltage signal is converted into a current signal by the transconductance unit and then input to the current adder. Meanwhile, Figure 3In the middle, the low-frequency envelope voltage signal output from the low-pass filter is simultaneously fed into two comparators with opposite hysteresis voltage polarities, namely... Figure 3 The first comparator D1 and the second comparator D2 in the system.

[0038] In practical use, it is usually necessary to configure the initial parameters of the first comparator D1 and the second comparator D2. Specifically, in this embodiment of the invention, the initial symbol signal of the first comparator D1 is configured as a high-level symbol; when the low-frequency envelope voltage signal is greater than 0, the first comparator D1 outputs a high-level symbol; when the low-frequency envelope voltage signal is less than a preset low-voltage threshold, the output of the first comparator D1 switches to a low-level symbol; the initial symbol signal of the second comparator D2 is configured as a low-level symbol; when the low-frequency envelope voltage signal is greater than a preset high-voltage threshold, the second comparator D2 outputs a high-level symbol; when the low-frequency envelope voltage signal is less than 0, the output of the second comparator D2 switches to a low-level symbol.

[0039] For ease of explanation, in this embodiment of the invention, the low voltage threshold is represented by -V. HYS The high voltage threshold is indicated by V. HYS This indicates that a high-level symbol is represented as 1, and a low-level symbol is represented as 0.

[0040] Based on the above configuration, for the first comparator D1 on the upper side, it outputs 1 when the input voltage is greater than 0, and outputs 1 when the input voltage is less than -V. HYS When the input voltage is greater than V, the output is 0; for the second comparator D2 on the lower side, when the input voltage is greater than V... HYS The output is 1 when the voltage is below zero and 0 when the voltage is below zero. The output states of the two comparators as a function of the input signal are summarized in Table 1 below. In Table 1, D1_last represents the hold signal of the first comparator. For example, when the input signal of the first comparator D1 decreases, the initial output signal is configured as 1. When the signal is less than 0, it will not immediately change, but will continue to hold the previous signal D1_last. When the input signal further decreases to -V... HYS Only when the input signal of the second comparator rises will it jump to 0. Similarly, D2_last represents the hold signal of the second comparator. For example, when the input signal of the second comparator D2 rises, the initial output signal is configured to 0. When the signal is greater than 0, it will not jump immediately, but will continue to hold the previous signal D2_last. When the input signal rises further to V... HYS Only then will it jump to become.

[0041] Table 1:

[0042] Based on Table 1 above, Vin represents the low-frequency envelope voltage signal input to the first and second comparators. In the aforementioned hysteresis unit, as can be seen from Table 1, when the amplitude of the low-frequency envelope voltage signal is less than -V... HYS At this time, the outputs of the first comparator D1 and the second comparator D2 are two low-level symbols 0, which is also called multiple consecutive 0 symbols. When the amplitude of the low-frequency envelope voltage signal is greater than V... HYS At this time, the outputs of the first comparator D1 and the second comparator D2 are two high-level code symbols 1, which is also called multiple consecutive 0 code symbols and multiple consecutive 1 code symbols.

[0043] The working principle of a specific signal processing circuit can be described as follows: Figure 4 As shown, where, Figure 4 The solid line in the diagram represents the waveform of the low-frequency envelope voltage signal. Figure 4 In this embodiment, D1 represents the output value of the first comparator D1, and D2 represents the output value of the second comparator D2. Furthermore, in this embodiment, the initial symbol signal of the first comparator is configured as a high-level symbol, and the initial symbol signal of the second comparator is configured as a low-level symbol. Figure 4 In the initial state, the first comparator D1 is set to 1 and the second comparator D2 is reset to 0.

[0044] Depend on Figure 4 It can be seen that initially, the low-frequency envelope voltage signal is within ±V HYS When the voltage fluctuates within the specified range, it does not exceed the low voltage threshold -V. HYS and high voltage threshold V HYS At this time, the first comparator D1 and the second comparator D2 do not change; that is, the first comparator D1 remains 1 and the second comparator D2 remains 0.

[0045] As time progresses, the low-frequency envelope voltage signal gradually increases, corresponding to... Figure 4 The rising phase of the wave peak. When the low-frequency envelope voltage signal exceeds V... HYS At this time, based on the characteristics of the comparators, both the first comparator D1 and the second comparator D2 will output a high level. Since the initial symbol signal of the first comparator is itself configured as a high-level symbol, the first comparator D1 remains at 1, while the second comparator D2 jumps to 1. When the low-frequency envelope voltage signal falls back to a value greater than 0 and is between 0 and V... HYS When the voltage fluctuates between these values, since the first comparator is configured to output a high-level symbol, comparator D1 remains at 1. Meanwhile, comparator D2, having not yet reached the zero-voltage transition signal, also remains at 1 due to hysteresis. Figure 4 In the middle, the part of the waveform where the peak drops to 0.

[0046] When the low-frequency envelope voltage signal continues to fall back to a value less than 0 and is in -VHYS To V HYS When the frequency fluctuates, the second comparator D2 returns to 0 because it is configured to output a low-level symbol, while the first comparator D1 remains at 1 due to hysteresis. When the low-frequency envelope voltage signal is below -V... HYS ,arrive Figure 4 When the wave reaches a trough, the first comparator D1 jumps to 0, while the second comparator D2 remains at 0.

[0047] Depend on Figure 4 It can be seen that the low-frequency envelope voltage signal exhibits a large fluctuation amplitude, i.e., greater than V. HYS and less than -V HYS The occurrence of sudden pulse signals can lead to bit error risks in the receiver and needs to be avoided. In this embodiment of the invention, compensation can be provided for situations where low-frequency envelope voltage signals exhibit large fluctuations. Figure 4 As can be seen, during the peak phase, the first comparator D1 remains at 1 and the second comparator D2 jumps to 1, that is, the continuous symbol signal is a high-level symbol; and during the trough phase, the first comparator D1 jumps to 0 and the second comparator D2 remains at 0, that is, the continuous symbol signal is a low-level symbol. Therefore, in this embodiment of the invention, compensation is based on the continuous symbol signal that appears.

[0048] Specifically, in this embodiment of the invention, the control logic circuit described above is used to monitor the symbol signals output by the first comparator and the second comparator. If the symbol signals output by the first comparator and the second comparator are continuous symbol signals, and the continuous symbol signals are low-level symbols, that is, corresponding to... Figure 4 During the trough phase, negative low-frequency compensation is required. Therefore, a first enable signal is output, which enables the DAC unit to perform negative low-frequency compensation. If the symbol signals output by the first and second comparators are continuous symbol signals, and the continuous symbol signals are high-level symbols, that is, corresponding to... Figure 4 During the peak phase, if multiple consecutive 1-symbols are detected, positive low-frequency compensation is required. At this time, a second enable signal can be output, which is the enable signal for the control current DAC unit to perform positive low-frequency compensation.

[0049] When the amplitude of the low-frequency envelope voltage signal is at Figure 4 -V in HYS To V HYS When the interval is defined, it is determined that there are no consecutive symbols, that is, the symbols output by the first comparator D1 and the second comparator D2 are different. At this time, no low-frequency compensation is performed. Moreover, thanks to the hysteresis characteristics of the two comparators, the low-frequency compensation function and the turn-off process also exhibit hysteresis characteristics.

[0050] In practical applications, the control logic circuit can output corresponding enable signals based on the different symbol signals output by the first and second comparators. That is, different symbol signals correspond to different enable signals. For ease of understanding, Table 2 below shows a correspondence between symbol signals and enable signals. As shown in Table 2, the mapping between the outputs of the first comparator D1 and the second comparator D2 and the enable signals can be realized.

[0051] In Table 2, D1 represents the output value of the first comparator D1, D2 represents the output value of the second comparator D2, and EN and polar represent the enable signals.

[0052] Table 2:

[0053] In Table 2 above, D2 / D1 represents the combination of the symbol signals output by the second comparator and the first comparator, combined with... Figure 4 According to Table 1 above, the possible combinations of D2 / D1 are 00, 01, 10, and 11. As mentioned earlier, 00 and 11 are continuous symbol signals, with 00 being a continuous low-level symbol signal and 11 being a continuous high-level symbol signal, requiring low-frequency compensation. Therefore, in this embodiment of the invention, the enable signal EN corresponds to the symbol signal. For example, referring to Table 2, when the symbol signal is a continuous symbol signal, the enable signal EN is 1; while for non-continuous symbol signals, the enable signal EN is 0.

[0054] Furthermore, in this embodiment of the invention, in order to further distinguish between the enable signal for negative low-frequency compensation and the enable signal for positive low-frequency compensation, the polar enable signal is used for further distinction. That is, in Table 2, when the continuous symbol signal is a low-level symbol, the polar enable signal is configured to be 0, and when the continuous symbol signal is a high-level symbol, the polar enable signal is 1. In other words, the first enable signal in this embodiment of the invention is EN=1 and polar=0, and the second enable signal is EN=1 and polar=1.

[0055] For the case where EN=0, it means that low-frequency compensation is not required. Therefore, the first enable signal or the second enable signal of the control current DAC unit will not be generated. Thus, the polar enable signal will not be affected whether it is 0 or 1. Therefore, it is replaced by "X" in Table 2 above.

[0056] Furthermore, the current DAC unit in this embodiment of the invention is used to inject a compensation current of corresponding polarity into the current adder based on the first enable signal and the second enable signal composed of the EN and polar signals in Table 2 above.

[0057] Specifically, Figure 5 A schematic diagram of a current DAC unit is shown. In a specific implementation, the signal merging unit includes a current adder; the enable signal output by the control logic circuit includes a first enable signal or a second enable signal. Specifically, the current DAC unit in this embodiment includes a switching circuit and a differential current mirror circuit connected to the switching circuit; the differential current mirror circuit includes a first current mirror circuit and a second current mirror circuit, and output terminals corresponding to the first and second current mirror circuits respectively.

[0058] Specifically, such as Figure 5 As shown, the switching circuit in this embodiment of the invention is composed of logic devices, such as... Figure 5 The circuit is composed of AND gates and NOT gates. The output terminals of the first current mirror circuit and the second current mirror circuit are respectively connected to the positive and negative terminals of the current adder. The switching circuit is used to respond to the EN enable signal and the polar enable signal in the first enable signal or the second enable signal. The first enable signal or the second enable signal controls the switching of the first current mirror circuit and the second current mirror circuit respectively, so as to inject the corresponding compensation current into the current adder of the signal merging unit.

[0059] Furthermore, such as Figure 5 As shown, in this embodiment of the invention, the first current mirror circuit includes a first switch S1 and a first current source A1 connected in series; the second current mirror circuit includes a second switch S2 and a second current source A2 connected in series; the first switch S1 is disposed between the output terminal outn of the first current mirror circuit and the first current source A1; the second switch S2 is disposed between the output terminal outp of the second current mirror circuit and the second current source A2; the switching circuit includes an output terminal connected to the first switch S1 and an output terminal connected to the second switch S2, so as to control the on / off state of the first switch S1 and the second switch S2 by a first enable signal or the EN enable signal and the polar enable signal in the second enable signal.

[0060] based on Figure 5 The current DAC unit shown has its enable signal polar and EN signal passing through a switching circuit to control the first switch S1 and the second switch S2, respectively. The output terminal outp is connected to the positive terminal of the current adder, and outn is connected to the negative terminal, thereby realizing positive compensation, negative compensation, or zero compensation of low-frequency components according to the input signal state.

[0061] In practical use, referring to the mapping relationship between the outputs of the first comparator D1 and the second comparator D2 and the enable signal shown in Table 2 above, the first switch S1 and the second switch S2 can be alternately turned on or completely turned off under the control of the enable signal, thereby achieving positive compensation, negative compensation or zero compensation of low frequency components.

[0062] Furthermore, the current DAC unit can also employ current-pumping, current-pulling, or mixed operating modes. By adjusting the polarity of the current mirror switch, it can be ensured that the direction of the compensation current always matches the characteristics of the input signal. Specifically, Figure 6 A schematic diagram of another current DAC unit is shown, illustrating the structure of a current DAC unit in hybrid operating mode, as follows. Figure 6 As shown, the first current mirror circuit includes a first current source A1, a first switch S1, a second switch S2, and a second current source A2 connected in series; the output terminal outn of the first current mirror circuit is located between the first switch S1 and the second switch S2; the second current mirror circuit includes a third current source A3, a third switch S3, a fourth switch S4, and a fourth current source A4 connected in series; the output terminal outp of the second current mirror circuit is located between the third switch S3 and the fourth switch S4; the switching circuit and... Figure 5 Similarly, it is composed of logic devices such as AND gates and NOT gates, and the switching circuit includes output terminals connected to the first switch S1 and the third switch S3, as well as output terminals connected to the second switch S2 and the fourth switch S4.

[0063] based on Figure 6 The current DAC unit shown above also refers to the mapping relationship between the outputs of the first comparator D1 and the second comparator D2 and the enable signal shown in Table 2 above. The enable signal output by the switching circuit can control the alternating conduction of the first switch S1 and the third switch S3, as well as the second switch S2 and the fourth switch S4, or turn them all off, thereby achieving the corresponding current compensation.

[0064] The specific control method of the current DAC unit can be set according to the actual use situation, and the embodiments of the present invention do not limit it.

[0065] Furthermore, in this embodiment of the invention, the signal processing circuit further includes a pre-processing amplification circuit disposed between the signal input interface and the signal processing unit; the pre-processing amplification circuit is used to amplify the input signal and send the amplified input signal to the signal processing unit. Furthermore, the signal processing circuit also includes a post-processing amplification circuit disposed between the signal processing unit and the signal conversion unit; the post-processing amplification circuit is used to amplify the synthesized signal to increase the gain of the synthesized signal.

[0066] Specifically, for ease of understanding, in Figure 1 On this basis, Figure 7 A schematic diagram of another signal processing circuit is shown, except... Figure 1 In addition to the structure shown, it also includes: a pre-processing amplifier circuit 50 and a post-processing amplifier circuit 60, based on Figure 7 The signal processing circuit shown can share part of the preprocessing amplifier circuit 50 between the low-frequency extraction unit 201 and the main amplification unit 202 to simplify the structure. At the same time, it allows the addition of a gain stage, i.e., a post-processing amplifier circuit 60, after the signal merging unit 203, which can maximize the signal swing without signal distortion and further improve the jitter performance of the comparator output signal.

[0067] In summary, the signal processing circuit provided in this embodiment of the invention, which uses a feedforward circuit for low-frequency compensation, can better compensate for the low-frequency attenuation of the useful signal introduced by the filter on the PBC board compared with the traditional structure. This allows the output signal of the burst receiver to have better jitter performance, which is beneficial to the operation of the subsequent clock data recovery circuit and reduces the deterioration of the bit error rate caused by the attenuation of low-frequency components.

[0068] Furthermore, embodiments of the present invention also provide a receiver configured with the above-described signal processing circuit.

[0069] The receiver provided in this embodiment of the invention has the same technical features as the signal processing circuit provided in the above embodiments, so it can also solve the same technical problems and achieve the same technical effects.

[0070] The computer program product for a signal processing circuit and receiver provided in this embodiment of the invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the preceding method embodiments. For specific implementation details, please refer to the method embodiments, which will not be repeated here.

[0071] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the receiver described above can be referred to the corresponding process in the foregoing embodiments, and will not be repeated here.

[0072] Furthermore, in the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0073] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0074] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0075] Finally, it should be noted that the above embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A signal processing circuit, characterized in that, Applied to a receiver, the signal processing circuit includes: a signal input interface, a signal processing unit, a signal conversion unit, and a signal output interface connected in sequence; The signal processing unit includes a low-frequency extraction unit, a main amplification unit, and a signal merging unit. The low-frequency extraction unit and the main amplification unit are connected in parallel. The input terminals of the low-frequency extraction unit and the main amplification unit are connected to the signal input interface, and the output terminals of the low-frequency extraction unit and the main amplification unit are connected to the signal merging unit. The signal input interface is used to receive input signals; The low-frequency extraction unit is used to extract the low-frequency envelope contained in the input signal to obtain a low-frequency compensation component. The main amplification unit is used to amplify and equalize the input signal to obtain the main path signal; The signal merging unit is used to merge the low-frequency compensation component and the main path signal to obtain a composite signal; The signal conversion unit is used to convert the synthesized signal into a corresponding digital signal and output it.

2. The signal processing circuit according to claim 1, characterized in that, The signal processing unit also includes a primary amplifier; The input terminal of the primary amplifier is connected to the signal input interface; the output terminal of the primary amplifier is connected to the input terminals of the low-frequency extraction unit and the main amplification unit. The input signal is amplified by the primary amplifier and then enters the low-frequency extraction unit and the main amplification unit.

3. The signal processing circuit according to claim 1, characterized in that, The main amplification unit includes a continuous-time linear equalizer; The continuous-time linear equalizer is used to compensate for the high-frequency components contained in the input signal and synchronously convert the compensated voltage signal into a second current signal.

4. The signal processing circuit according to claim 3, characterized in that, The low-frequency extraction unit includes a low-pass filter and a transconductance unit connected in sequence. The low-pass filter is used to extract the low-frequency envelope voltage signal included in the input signal; The transconductance unit is used to convert the low-frequency envelope voltage signal into a first current signal; The signal combining unit includes a current adder; The current adder is used to combine the first current signal and the second current signal to obtain the composite signal.

5. The signal processing circuit according to claim 3, characterized in that, The low-frequency extraction unit includes a low-pass filter and a hysteresis unit connected in sequence. The low-pass filter is used to extract the low-frequency envelope voltage signal included in the input signal; The hysteresis unit includes a first comparator and a second comparator connected in parallel, as well as a control logic circuit and a current DAC unit; wherein the first comparator and the second comparator are comparators with opposite hysteresis voltage polarities. The input terminals of the first comparator and the second comparator are connected to the output terminal of the low-pass filter, and the output terminals of the first comparator and the second comparator are connected to the control logic circuit. The first comparator and the second comparator are used to output corresponding symbol signals according to the range of the low-frequency envelope voltage signal; The control logic circuit is used to output a corresponding enable signal based on the symbol signal, and send the enable signal to the current DAC unit; The current DAC unit is used to inject a corresponding compensation current into the signal merging unit according to the enable signal.

6. The signal processing circuit according to claim 5, characterized in that, The initial symbol signal of the first comparator is configured as a high-level symbol; when the low-frequency envelope voltage signal is greater than 0, the first comparator outputs a high-level symbol; when the low-frequency envelope voltage signal is less than a preset low voltage threshold, the output of the first comparator switches to a low-level symbol. The initial symbol signal of the second comparator is configured as a low-level symbol; when the low-frequency envelope voltage signal is greater than a preset high-voltage threshold, the second comparator outputs a high-level symbol. When the low-frequency envelope voltage signal is less than 0, the output of the second comparator switches to a low-level symbol.

7. The signal processing circuit according to claim 6, characterized in that, The control logic circuit is also used for: Monitor the symbol signals output by the first comparator and the second comparator; If the symbol signals output by the first comparator and the second comparator are continuous symbol signals, and the continuous symbol signals are low-level symbols, then a first enable signal is output. The first enable signal is an enable signal that controls the current DAC unit to perform negative low-frequency compensation. If the symbol signals output by the first comparator and the second comparator are continuous symbol signals, and the continuous symbol signals are high-level symbols, then a second enable signal is output. The second enable signal is an enable signal that controls the current DAC unit to perform positive low-frequency compensation.

8. The signal processing circuit according to claim 5, characterized in that, The signal combining unit includes a current adder; The enable signals output by the control logic circuit include a first enable signal and a second enable signal; The current DAC unit includes a switching circuit and a differential current mirror circuit connected to the switching circuit. The differential current mirror circuit includes a first current mirror circuit and a second current mirror circuit, and output terminals corresponding to the first current mirror circuit and the second current mirror circuit, respectively; wherein the output terminals corresponding to the first current mirror circuit and the second current mirror circuit are connected to the positive terminal and the negative terminal of the current adder, respectively. The switching circuit is used to respond to the first enable signal or the second enable signal, and control the switching of the first current mirror circuit and the second current mirror circuit through the first enable signal or the second enable signal, so as to inject the corresponding compensation current into the current adder of the signal merging unit.

9. The signal processing circuit according to claim 8, characterized in that, The first current mirror circuit includes a first switch and a first current source connected in series; the second current mirror circuit includes a second switch and a second current source connected in series; the first switch is disposed between the output terminal of the first current mirror circuit and the first current source; the second switch is disposed between the output terminal of the second current mirror circuit and the second current source. The switching circuit includes an output terminal connected to the first switch and an output terminal connected to the second switch; or, The first current mirror circuit includes a first current source, a first switch, a second switch, and a second current source connected in series; the output terminal of the first current mirror circuit is located between the first switch and the second switch; the second current mirror circuit includes a third current source, a third switch, a fourth switch, and a fourth current source connected in series; the output terminal of the second current mirror circuit is located between the third switch and the fourth switch. The switching circuit includes an output terminal connected to the first switch and the third switch, and an output terminal connected to the second switch and the fourth switch.

10. A receiver, characterized in that, The receiver is equipped with the signal processing circuit according to any one of claims 1 to 9.

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