Resource allocation method, first device, storage medium and product

Abstract

The invention discloses a resource allocation method. The method comprises the steps that first equipment receives a first message sent by a first terminal; wherein the first message is used for estimating the transmission delay between the first terminal and the first equipment; the first device determines a first time delay interval to which the first terminal belongs based on the estimated transmission time delay; and the first device allocates a memory block matched with the first time delay interval to the first terminal in the public shared memory pool. The invention further discloses first equipment, a computer readable storage medium and a computer program product.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of communications, and particularly to a resource allocation method, a first device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] Currently, in non-terrestrial network (NTN) satellite communications, to balance user capacity and processing load across different coverage areas, methods such as beam skipping, multiple point beam rates, and time-slicing are often used to dynamically cover different ground beam positions to meet user service needs under different ground beam positions. However, the large distance between satellites and the ground results in significant communication latency, and the coverage area of ​​satellite beams ranges from a few square kilometers to tens of thousands of square kilometers. Therefore, the data transmission latency of users located at different beam rates varies greatly. Even for the same user, due to the high-speed movement of the satellite, the user's data transmission latency is constantly changing, and the range of variation is also large. These large transmission latencyes pose a significant challenge to base station data storage design.

[0003] It should be noted that, to address the issues caused by the aforementioned high latency, a Hybrid Automatic Repeat Request (HARQ) mechanism is often used for uplink and downlink data transmission at NTN base stations. The 3rd Generation Partnership Project (3GPP) specifies a maximum of 32 HARQ processes for low-Earth orbit satellites. Due to the impact of high transmission latency, the data cache size varies significantly between different locations of User Equipment (UE) and between different time periods for the same UE. If data cache is allocated to all locations at 32 processes, it would inevitably lead to enormous data storage overhead. However, terminals closer to the satellite do not actually need to allocate the maximum storage during communication, thus resulting in a waste of storage resources. Summary of the Invention

[0004] This application provides a resource allocation method, a first device, a computer-readable storage medium, and a computer program product, providing a scheme for dynamically allocating memory for a terminal.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] Firstly, embodiments of this application provide a resource allocation method applied to a first device, the method comprising:

[0007] Receive a first message sent by a first terminal; wherein the first message is used to estimate the transmission delay between the first terminal and the first device;

[0008] Based on the estimated transmission delay, the first delay interval to which the first terminal belongs is determined;

[0009] In the public shared memory pool, a memory block matching the first latency interval is allocated to the first terminal.

[0010] Secondly, embodiments of this application provide a first device, the first device comprising:

[0011] A receiving module is configured to receive a first message sent by a first terminal; wherein the first message is used to estimate the transmission delay between the first terminal and the first device;

[0012] The processing module is used to determine the first delay interval to which the first terminal belongs based on the estimated transmission delay;

[0013] The processing module is further configured to allocate a memory block matching the first latency interval to the first terminal in a public shared memory pool.

[0014] Thirdly, embodiments of this application provide a first device, the first device comprising:

[0015] Memory, used to store executable instructions;

[0016] When the processor executes executable instructions stored in the memory, it performs the steps of the resource allocation method described above.

[0017] Fourthly, embodiments of this application provide a computer-readable storage medium storing one or more computer programs thereon, which can be executed by one or more processors to implement the steps of the resource allocation method described above.

[0018] Fifthly, embodiments of this application provide a computer program product, including a computer program, which, when executed by a processor, implements the steps of the above-described resource allocation method.

[0019] This application proposes a dynamic memory allocation scheme that cleverly utilizes the transmission latency estimated from the messages reported by the terminal and the differences in the data buffer size required by different terminals at different transmission latencies. A unified public shared memory pool is set up, and the required memory blocks are dynamically allocated in the public shared memory pool according to the changes in transmission latency, which effectively solves the problem of large memory overhead in related technologies. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a communication system according to an embodiment of this application;

[0021] Figure 2 This is a schematic diagram illustrating the transmission delay between a satellite and a terminal provided in related technologies.

[0022] Figure 3 This is a schematic diagram of the cached data packets corresponding to the uplink and downlink service scheduling provided in related technologies;

[0023] Figure 4 A flowchart illustrating the resource allocation method provided in an embodiment of this application;

[0024] Figure 5 A schematic diagram illustrating the allocation of HARQ process caches for each terminal after the establishment of a public HARQ memory pool, as provided in this application.

[0025] Figure 6 A schematic diagram illustrating the allocation of data blocks for each terminal user after the establishment of a public MAC memory pool, as provided in this application;

[0026] Figure 7 A schematic block diagram of a first device provided in an embodiment of this application;

[0027] Figure 8 This is a schematic structural diagram of a first device provided in an embodiment of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] The embodiments of this application can be applied to various communication systems, such as: satellite communication systems, Global System of Mobile communication (GSM) systems, Code Division Multiple Access (CDMA) systems, Wideband Code Division Multiple Access (WCDMA) systems, General Packet Radio Service (GPRS), 4th generation (4G) communication systems (e.g., Long Term Evolution (LTE) systems), 5th generation (5G) communication systems (e.g., New Radio (NR) systems), evolution systems of NR systems, Universal Mobile Telecommunication System (UMTS), Wireless Local Area Networks (WLAN), Wireless Fidelity (Wi-Fi), next-generation communication systems, or other communication systems.

[0030] Figure 1 This is a schematic diagram of a communication system according to an embodiment of this application.

[0031] like Figure 1 As shown, the communication system 100 may include terminal equipment 110, satellite 120 and gateway station 130.

[0032] Generally, a communication system 100 includes transparent satellite architecture and non-transparent satellite architecture. Transparent transmission, also known as bend-tube relay transmission, means that the signal only undergoes frequency conversion and signal amplification on the satellite, and the satellite is transparent to the signal. Non-transparent transmission, also known as regenerative (access / processing on the satellite) transmission, means that the satellite has some or all of the base station functions.

[0033] For example, terminal device 110 can send short messages to satellite 120, and satellite 120 only relays the short messages sent by terminal device 110 directly to ground gateway station 130.

[0034] The link between terminal device 110 and gateway station 130 via satellite 120 includes a service link between terminal device 110 and satellite 120, and a feeder link between satellite 110 and gateway station 130.

[0035] exist Figure 1 In the communication system 100 shown, satellite 120 can be an access network device that communicates with terminal device 110. The access network device can provide communication coverage for a specific geographical area and can communicate with terminal device 110 located within that coverage area.

[0036] For example, the satellite 120 in the communication system 100 can be a low earth orbit (LEO) satellite, or an inclined geosynchronous orbit (IGSO), middle earth orbit (MEO) satellite, or a geostationary earth orbit (GEO) satellite.

[0037] Here, satellites can provide communication, navigation, and positioning services to terminal devices through multiple beams. Satellites use multiple beams to cover service cells, and different beams can communicate through one or more of time-division, frequency-division, and space-division multiplexing methods. Satellites can also communicate wirelessly with ground equipment via broadcast communication signals and navigation signals.

[0038] The network devices in this application embodiment may include one or more satellites 120 and / or gateway stations 130.

[0039] For example, a gateway station, also known as a gateway network, can connect to satellites and is typically responsible for distributing and collecting satellite communication service data, exchanging internal data within the satellite network, and routing data to external networks.

[0040] It should be understood that in the embodiments of this application, the network device can be a means for implementing the functions of the network device, or a means that enables the network device to implement the functions, such as a chip system, which can be installed in the network device.

[0041] In this application embodiment, terminal device 110 can refer to user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, wireless communication device, user agent, or user device. The terminal device in this application embodiment can also be a satellite phone, cellular phone, smartphone, wireless data card, wireless modem, machine-type communication device, cordless phone, Session Initiation Protocol (SIP) phone, Wireless Local Loop (WLL) station, Personal Digital Assistant (PDA), handheld device with wireless communication function, computing device or other processing device connected to a wireless modem, in-vehicle device or wearable device, virtual reality (VR) terminal device, augmented reality (AR) terminal device, wireless terminal in industrial control, wireless terminal in autonomous driving, wireless terminal in telemedicine, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, terminal device in NR network, or terminal device in future communication network, etc.

[0042] It should be understood that in the embodiments of this application, the terminal device can be a means for implementing the functions of the terminal device, or a means for supporting the terminal device in implementing the functions, such as a chip system, which can be installed in the terminal. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0043] Figure 1 The example shows two UEs, one gateway station and one satellite. Optionally, the communication system 100 may include multiple satellites, and each satellite may include other numbers of UEs within its coverage area. This application embodiment does not limit this.

[0044] It should be noted that, Figure 1This application merely illustrates the system to which this application applies; of course, the methods shown in the embodiments of this application can also be applied to other systems. Furthermore, the terms "system" and "network" are often used interchangeably herein. The term "and / or" in this application merely describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this application generally indicates that the preceding and following related objects have an "or" relationship. It should also be understood that "instruction" mentioned in the embodiments of this application can be a direct instruction, an indirect instruction, or an indication of a related relationship. For example, A instructing B can mean that A directly instructs B, for example, B can be obtained through A; it can also mean that A indirectly instructs B, for example, A instructs C, B can be obtained through C; or it can mean that there is a related relationship between A and B. It should also be understood that "correspondence" mentioned in the embodiments of this application can indicate a direct or indirect correspondence between two things, or an related relationship between two things, or a relationship of instruction and being instructed, configuration and being configured, etc. It should also be understood that the "predefined" or "predefined rules" mentioned in the embodiments of this application can be implemented by pre-storing corresponding codes, tables, or other means that can be used to indicate relevant information in the device (e.g., including terminal devices and network devices), and this application does not limit the specific implementation method. For example, predefined can refer to those defined in a protocol. It should also be understood that in the embodiments of this application, the "protocol" can refer to standard protocols in the field of communication, such as LTE protocol, NR protocol, and related protocols applied to future communication systems, and this application does not limit this.

[0045] To facilitate understanding of the technical solutions of the embodiments of this application, the relevant technologies of the embodiments of this application are described below. The following relevant technologies are optional solutions and can be combined with the technical solutions of the embodiments of this application in any way, and they all fall within the protection scope of the embodiments of this application.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0047] Before explaining this application, the transmission delay between the satellite and the terminal in the related art is described below:

[0048] Because satellites are far from the ground, they incur significant transmission delays compared to terrestrial networks during communication. This is especially true for satellite beamwidth coverage radii ranging from tens to thousands of kilometers, where the transmission delay differs greatly between users at the beam edge and the beamwidth center. For example, the maximum round-trip time (RTT) for LEO satellites can reach approximately 50 milliseconds (ms), while for GEO satellites, the maximum RTT can reach approximately 600 ms. In low-Earth orbit (LEO) satellite communication, the transmission delay between the terminal and the satellite varies from a few milliseconds to tens of milliseconds. Figure 2 This is a schematic diagram illustrating the transmission delay between a satellite and a terminal, as provided in related technologies. For example... Figure 2 As shown, for the same user or terminal (e.g. Figure 2 In the case of terminal 1, terminal 2, or terminal 3, during communication, as the satellite moves (e.g., using...), Figure 2 As the satellite moves (as shown), the distance between the user or terminal and the satellite will change, and the transmission delay between the user or terminal and the satellite will also change. For example, as the satellite moves, the transmission delay between terminal 1 and the satellite will change from T... 1,1 Change to T 2,2 As the satellite moves, the transmission delay between terminal 2 and the satellite increases from T... 2,1 Change to T 2,2 As the satellite moves, the transmission delay between terminal 3 and the satellite increases from T... 3,1 Change to T 3,2 Among them, T i,j This represents the one-way transmission delay of terminal i at time j.

[0049] During communication, base stations need to cache data when scheduling uplink and downlink services. Figure 3 This is a schematic diagram of the cached data packets corresponding to uplink and downlink service scheduling provided in related technologies. For example... Figure 3 As shown, in the downlink direction, the Medium Access Control (MAC) layer needs to collect multiple Service Data Unit (SDU) packets (i.e., SDU1, SDU2, ..., SDU) from the Radio Link Control (RLC). n After packet assembly, the MAC layer obtains the downlink data buffer and transmits transport blocks to the physical layer for processing based on system resource scheduling. For uplink, the MAC layer needs to collect the terminal uplink data processed by the physical layer, such as multiple transport blocks (TBs) (i.e., TB1, TB2, ..., TB3). nAfter packet assembly, the MAC uplink data cache is obtained and sent to the RLC. Additionally, during physical layer processing, data caching is also required for multi-process uplink and downlink HARQ handling. Related technologies do not differentiate between the latency impact of different user locations, uniformly allocating cache based on the maximum latency scenario, resulting in significant memory wastage.

[0050] Figure 4 This is a flowchart illustrating a resource allocation method provided in an embodiment of this application, as shown below. Figure 4 As shown, this method is applied to Figure 1 In the communication system 100 shown, the method includes:

[0051] Step 201: The first device receives a first message sent by the first terminal; wherein the first message is used to estimate the transmission delay between the first terminal and the first device.

[0052] In this embodiment of the application, the first terminal, namely Figure 1 Terminal device 110 in the middle sends a signal to the first device, namely Figure 1 The network device sends a first message, the first device receives the first message, and estimates the transmission delay between the first terminal and the first device based on the first message.

[0053] Here, the first message may include the timing advance (TA) of the first terminal, and the first device estimates the transmission delay of the first terminal based on the TA of the first terminal.

[0054] Here, the first message could be a Medium Access Control (MAC) Control Element (CE) message.

[0055] It should be noted that because different terminal devices are at different distances from the network device, uplink information sent by different terminal devices will arrive at the network device at different times, causing signal interference. Therefore, terminal devices need to maintain regular synchronization with the network device. After downlink synchronization is completed, the terminal device can accurately receive downlink signals sent by the network device; after uplink synchronization is completed, the network device can accurately receive uplink signals sent by the terminal device. Here, uplink synchronization is mainly achieved by the terminal device using a specific TA (Transmission Timing) to adjust the uplink transmission time.

[0056] Step 202: The first device determines the first delay interval to which the first terminal belongs based on the estimated transmission delay.

[0057] It should be noted that the first device determines the first delay interval that matches the estimated transmission delay from the M delay intervals corresponding to the coverage area of ​​the first device.

[0058] Here, the delay range included in each of the M delay intervals is different.

[0059] Step 203: The first device allocates a memory block in the public shared memory pool that matches the first latency interval for the first terminal.

[0060] In this embodiment of the application, there may be one or more public shared memory pools; there may be two public shared memory pools, one for scheduling data and the other for processes; there may be one public shared memory pool, namely, a public shared memory pool for both scheduling data and processes.

[0061] In this embodiment of the application, the memory blocks (memory blocks are the storage units of the cache) allocated for different latency intervals are different.

[0062] This application sets up a unified public shared memory pool. When allocating resources to terminals, it can allocate resources from the unified public shared memory pool that match the terminal's own transmission latency based on the terminal's own transmission latency. In this way, instead of allocating according to the maximum storage, it saves the waste of storage resources.

[0063] This application provides a resource allocation method, comprising: a first device receiving a first message sent by a first terminal; wherein the first message is used to estimate the transmission delay between the first terminal and the first device; the first device determines a first delay interval to which the first terminal belongs based on the estimated transmission delay; and the first device allocates a memory block matching the first delay interval to the first terminal in a common shared memory pool. In other words, this application proposes a dynamic memory allocation scheme that cleverly utilizes the transmission delay estimated by the message reported by the terminal and the differences in the data buffer size required by different terminals at different transmission delays. It sets up a unified common shared memory pool and dynamically allocates the required memory blocks in this pool according to changes in transmission delay, effectively solving the problem of high memory overhead in related technologies.

[0064] In some embodiments, the public shared memory pool includes a first public shared memory pool for Layer 2 data (such as MAC data) and a second public shared memory pool for processes (such as HARQ scheduling data). Then, step 203, where the first device allocates a memory block matching the first latency interval to the first terminal in the public shared memory pool, can be implemented through steps A1 to A3, or through steps A1, A4 to A5.

[0065] Step A1: The first device acquires the peak rate R of the first terminal. max The duration t corresponding to all processes in the first time delay interval harqThe number of processes P corresponding to the first delay interval, and the scheduling time interval TTI corresponding to the first device.

[0066] In this embodiment of the application, R max It can be determined based on multiple historical data packets sent by the first device based on the first terminal, for example, all historical data packets received the previous day. Of course, for R... max The accuracy of this data can be based on all historically received data packets.

[0067] In this embodiment of the application, the scheduling time interval is preset and can be set to 1ms.

[0068] Step A2, the first device is based on the duration t harq and peak rate R max Determine the first cache block C1 required by the first terminal.

[0069] In this embodiment of the application, the number corresponding to the first cache block can be the duration t. harq and peak rate R max The product of (i.e., C1 = t) harq *R max ), or the product of duration and peak rate, rounded down (i.e., C1 = rounded down (t)). harq *R max )).

[0070] Step A3: The first device allocates a memory block that matches the first cache block to the first terminal in the first public shared memory pool.

[0071] In this embodiment of the application, a memory block matching the first cache block is allocated to the first terminal in the first public shared memory pool for transmitting scheduling data.

[0072] Step A4: The first device is based on the peak rate R max Duration t harq The number of processes P and the scheduling time interval TTI are used to determine the second cache block C2 corresponding to a single process.

[0073] In this embodiment, the number corresponding to the second cache block can be the product of the peak rate and the duration, divided by the scheduling time interval, and finally divided by the number of processes (i.e., C2 = t). harq *R max / P / TTI), or the product of peak rate and duration, then divided by the scheduling time interval, then divided by the number of processes, and finally rounded down to the nearest integer (i.e., C2 = rounded down (t)). harq *R max / P / TTI)).

[0074] Step A5: The first device allocates a memory block matching the second cache block for each process in at least one process required by the first terminal in the second public shared memory pool.

[0075] In this embodiment of the application, each process of the first terminal is allocated a memory block that matches the second cache block in the first public shared memory pool for the process to call.

[0076] In some embodiments, if the first terminal performs uplink transmission, it obtains the bit width W of the soft bit information buffered by each process; based on the peak rate R... max Duration t harq The second cache block C2 is determined by the number of processes P, the scheduling time interval TTI, and the bit width W.

[0077] For example, the number corresponding to the second cache block C2 could be the peak rate R. max With duration t harq The product of these factors is then divided by the scheduling time interval TTI, followed by the number of processes P, and finally multiplied by the bit width W to obtain the number (i.e., C2 = t). harq *R max / P / TTI*W), or peak rate R max With duration t harq The product of the two numbers is then divided by the scheduling time interval TTI, then divided by the number of processes P, multiplied by the bit width W, and finally rounded down to the nearest integer (i.e., C2 = integer(t)). harq *R max / P / TTI*W)).

[0078] In some embodiments, if the first terminal performs downlink transmission, it obtains the minimum coding rate X and the number of redundant versions Y corresponding to each process cache; based on the peak rate R... max Duration t harq The second cache block is determined by the number of processes P, the scheduling time interval TTI, the minimum coding rate X, and the number of redundant versions Y.

[0079] For example, the number corresponding to the second cache block could be the peak rate R. max With duration t harq The product of these factors is then divided by the scheduling time interval TTI, then divided by the number of processes P, and finally multiplied by the number of redundant versions Y and divided by the minimum coding rate X to obtain the number (i.e., C2 = t). harq *R max / P / TTI*Y / X), or peak rate R max With duration t harq The product of these factors is then divided by the scheduling time interval (TTI), then divided by the number of processes (P), multiplied by the number of redundant versions (Y), and finally divided by the minimum coding rate (X), and rounded down to the nearest integer (i.e., C2 = integer(t)). harq*R max / P / TTI*Y / X)).

[0080] In some embodiments, the method provided in this application includes the following: calculating the size of a public shared memory pool.

[0081] The calculations for the first public shared memory pool include the following steps:

[0082] Step B1: The first device determines the M time delay intervals corresponding to the coverage area of ​​the first device.

[0083] Where M is a positive integer; the M time delay intervals include the first time delay interval.

[0084] Here, the first device obtains the maximum transmission delay T from the terminals within its coverage area to the first device. pmax and minimum transmission delay T pmin Based on maximum transmission delay T pmax and minimum transmission delay T pmin Calculate M time delay intervals.

[0085] Here, the maximum transmission delay T can be set. pmax With minimum transmission delay T pmin The time delay intervals are divided into M equal parts to obtain M time delay intervals; or they are divided according to the number of terminals, for example, so that the number of terminals in each of the M time delay intervals is the same.

[0086] Step B2: The first device obtains the first number of terminals included in each delay interval and the second number of processes corresponding to each delay interval.

[0087] Step B3: The first device calculates the third cache block S required for a single process. Hbase .

[0088] It should be noted that the third cache block can be the cache block corresponding to the largest process.

[0089] Here, the third cache block can be the second cache block.

[0090] Step B4: The first device calculates the first shared memory pool C based on M, the first quantity, the second quantity, and the third cache block. s .

[0091] For example, Among them, P i Let U be the number of processes in interval i. i Let M be the number of users in interval i, and M be the number of delay intervals.

[0092] The calculations for the second public shared memory pool include the following steps:

[0093] Step C1: The first device obtains the total number S of all processes included in the M latency intervals corresponding to the coverage area of ​​the first device. m .

[0094] Step C2: The first device calculates the third cache block S required for a single process. Hbase .

[0095] Step C3: The first device calculates the second shared memory pool C based on the total number of processes and the third cache block. b .

[0096] For example, C b =S Hbase *S m .

[0097] In some embodiments, if the latency interval to which the first terminal belongs switches from the first latency interval to the second latency interval, a memory block matching the second latency interval is allocated to the first terminal in the public shared memory pool.

[0098] It should be noted that during real-time communication, the TA value of each terminal is periodically detected. When the TA value changes and enters another latency interval, the terminal switches from the first latency interval to the second latency interval. Based on the HARQ number corresponding to the latency interval and the terminal's HARQ process support capability, the terminal's HARQ process number needs to be adjusted. Based on the HARQ change, the memory block size required for UE cache data is recalculated and reallocated in the memory pool.

[0099] In some embodiments, if the memory block size of the first terminal changes, it is determined whether to reallocate the public shared memory pool.

[0100] It should be noted that when reallocating memory blocks, the total number of processes across all terminals is counted and the total memory block size C is calculated. new When the total memory block size C is counted new Exceeding the current public memory pool size C cur And the current public memory pool occupancy rate exceeds the threshold T. h1 (e.g., total size C) cur When 90% of the memory is allocated, the public memory pool is reallocated, with the size based on the newly calculated memory block size. When the newly calculated memory block C... new Smaller than the current public memory pool size C cur And the occupancy rate of the public memory pool is lower than the threshold T. h2 At that time, the shared memory pool is reallocated, with the size set to the newly calculated value C. new *(1+r), where r is a scaling factor, for example, 0.1. When the newly calculated public memory pool size exceeds the original size, the original size remains unchanged.

[0101] In some embodiments, a first address table is established; based on the first address table, memory blocks in a public shared memory pool are managed.

[0102] It should be noted that the first address table includes information on all memory blocks in the memory pool. Each memory block's information includes three fields: a free flag, the starting address of the memory block, and the length of the memory block. When each UE needs to allocate a new process memory block, it queries the free flag of memory blocks in the memory pool, selects a free memory block, and sets its free flag to "occupied." When the process data processing is complete and the memory block is no longer needed, it simply sets its occupied flag to "free," thus facilitating the allocation of the memory block by other UEs.

[0103] This application proposes a dynamic memory allocation scheme. The core idea is to establish a unified shared memory pool to address the differences in data buffer size required by different UEs at different transmission latencies. It cleverly utilizes the TA (Transmission Time Acquisition) reported by each UE to estimate the UE's transmission latency. Based on changes in transmission latency, it dynamically allocates the required memory blocks from this shared memory pool, thus solving the problem of wasted storage resources in related technologies. This dynamic memory allocation scheme includes the following steps:

[0104] 1. Divide the time delay interval within the satellite coverage area.

[0105] In some embodiments, the coverage area of ​​each beam of the satellite is divided into M zones according to the transmission delay, with each zone being a delay interval.

[0106] For example, for wavelet 1 under LEO1, the maximum transmission delay from UE1 on the ground to LEO1 is T. pmax The minimum transmission delay from UE1 to LEO1 is T. pmin Then [T] pmin T pmax The time delay is divided into M intervals, S1:[T pmin S1, S2: [T1, T2), ..., S M :[T M-1 ,T pmax ].

[0107] 2. Determine the number of users in each latency interval.

[0108] In some embodiments, for the maximum number of users N supported by the satellite base station, the UEs are allocated to different latency intervals according to the user geographical location distribution rules and the corresponding transmission latency.

[0109] For example, N users are evenly distributed across different latency intervals, i.e., latency intervals S1 to S2. M-1 Contains Ni =celling(N / M), where i belongs to [1,M-1], S M The interval contains N M = N-(M-1)*celling(N / M), where celling() means rounding up.

[0110] 3. Determine the number of processes in each delay interval.

[0111] In some embodiments, the number of processes in each interval is estimated based on the latency interval.

[0112] It should be noted that the number of processes = maximum transmission delay / scheduling time interval. For each UE, a correspondence between the number of HARQ processes and the transmission delay is established to obtain the number of HARQ processes H1, H2, ..., H in each delay interval. M .

[0113] For example, if the NTN base station schedules data at a transmission time interval (TTI) of 1ms, one way to calculate the maximum number of uplink or downlink processes for a user is to divide the upper limit of the delay interval by the TTI. For instance, suppose the minimum delay for a certain beam coverage area is 4ms and the maximum delay is 16ms, divided into three delay intervals: interval S1 is [4,8], in which the maximum number of processes for the UE is 8; interval S2 is (8,12], in which the maximum number of processes for the UE is 12; and interval S3 is (12,16], in which the maximum number of processes for the UE is 16.

[0114] 4. Estimate the cache block size for each terminal.

[0115] In some embodiments, each UE may need to allocate multiple cache blocks according to different protocol layers, such as MAC layer data cache blocks, physical layer HARQ process data cache blocks, etc.

[0116] In some embodiments, the size of the memory block required for caching data is related to the frequency bandwidth supported by the base station, the number of data streams received or transmitted (the number of multiple-input multiple-output (MIMO) layers), the service type, the channel environment, etc. The size of the MAC layer data cache block and the HARQ process data cache block is related to the transmission delay and the number of HARQ processes.

[0117] For example, one method for calculating the terminal buffer block size is as follows: Let the UE peak rate be R. max The duration corresponding to the total number of HARQ processes in this UE is t. harq The calculated data size to be sent within the HARQ duration is R. max *tharq (If the terminal's uplink and downlink peak rates and the number of HARQ processes are different, they can be calculated separately.)

[0118] For the size of a single terminal MAC cache block, press R. max *t harq This value is assigned.

[0119] Regarding the HARQ single-process data buffer block size, assuming the number of HARQ processes allocated to this terminal is P, and the scheduling interval is 1ms, then the baseline value S of the memory block required for each process to buffer data is... Hbase =R max *t harq / P.

[0120] For uplink transmission, since the data buffered by each HARQ process is generally soft-bit information, it also needs to be multiplied by the bit width of the soft-bit information. For example, assuming the physical layer uses an 8-bit width to represent one bit of soft information during HARQ processing, then R needs to be multiplied by the bit width of the soft-bit information. max *t harq / P then multiply by 8.

[0121] For downlink transmission, since the data cached by the HARQ process consists of different redundant encoded versions, the actual memory block size needs to be calculated based on the minimum coding rate and the number of redundant versions. For example, assuming the minimum coding rate is 1 / 3 and the number of redundant versions is 4, the single-process cache size is S. Hbase *4 / (1 / 3). In this embodiment, to facilitate management and multi-user reuse, a uniform HARQ data block size can be used for all UEs within a base station.

[0122] 5. Calculate and allocate the initial size of the shared memory pool.

[0123] This application can set up one or more public shared memory pools. For example, a public shared memory pool can be set up for the MAC uplink and downlink data scheduling cache of all users, and a public shared memory pool can be set up for the HARQ process data cache of all users. The initial size of the public shared memory pool is calculated based on the number of users supported by the base station, the latency partitions of users in the base station coverage area, and the number of HARQ processes and the process data cache size corresponding to each latency partition.

[0124] For example, one calculation method for the MAC scheduling data shared memory pool is as follows: Among them, P i Let U be the number of processes in interval i. i Let M be the number of users in interval i, and M be the number of latency intervals. Here, when determining the MAC scheduling data shared memory pool, all UEs are set to the same peak rate for calculation.

[0125] For the shared memory pool of HARQ processes, one calculation method is as follows: Among them, S H The size of a single-process memory block; P i Let U be the number of processes in interval i. i Let M be the number of users in interval i, and M be the number of latency intervals. Here, the memory block size for a single process differs for uplink and downlink transmissions; see step 4 for details on the calculation method.

[0126] In some embodiments, an initial shared memory pool is allocated when the base station starts up, based on the above calculations.

[0127] 6. Dynamic allocation of terminal memory blocks.

[0128] In some embodiments, after the base station starts up, when a terminal accesses the network, the base station allocates memory blocks to the newly accessed UE based on the timing advance measurement (TA) reported by the terminal. Based on the TA value, the base station queries the latency interval to which the UE currently belongs. Within this latency interval, it queries the size of the corresponding MAC uplink / downlink scheduling data buffer block and the size of the uplink / downlink buffer block corresponding to the HARQ process, and then allocates UE memory blocks in the shared memory pool.

[0129] Figure 5 This application provides a schematic diagram illustrating the allocation of HARQ process caches for each terminal after the establishment of a public HARQ memory pool; for example... Figure 5 As shown, each terminal can allocate processes from the shared HARQ memory pool as needed during real-time communication, based on the actual number of processes required (the number of processes per terminal also changes dynamically during communication). For example, Figure 5 The public HARQ memory pool C shown b The allocation is as follows: the first HARQ process cache of the first terminal (i.e., B) 1,1 ), the second HARQ process cache of the first terminal (i.e., B) 1,2 ), the first HARQ process cache of the second terminal (i.e., B) 2,1 ), the first HARQ process cache of the third terminal (i.e., B) 3,1 The second HARQ process cache of the second terminal (i.e., B) 2,2 ), the second HARQ process cache of the third terminal (i.e., B) 3,2 ), the first HARQ process cache of the fourth terminal (i.e., B) 4,1 ), ..., the HARQ process cache of the i-th terminal (i.e., B) i,j ).

[0130] It should be noted that the allocated HARQ process memory blocks can change dynamically. Once the HARQ process finishes processing data, the memory blocks can be released. If a new HARQ process needs to transmit data, the memory blocks can be reallocated in the common memory pool. This ensures that multiple UEs can dynamically use memory pool resources.

[0131] Figure 6 This application provides a schematic diagram illustrating the allocation of data blocks for each terminal user after the establishment of a public MAC memory pool; for example... Figure 6 The diagram illustrates the allocation of the MAC shared memory pool. Each terminal user calculates the size of its uplink or downlink scheduling data buffer block based on its own transmission latency interval, and allocates the buffers sequentially within the shared memory pool. The allocated memory blocks for each UE are continuously usable. Only when a UE's latency interval changes is the original memory block released and a new memory block reallocated based on the memory block size corresponding to the new latency interval. For example, Figure 6 The public MAC memory pool allocation shown is as follows: data block allocated to terminal user 1 (M1), data block allocated to terminal user 2 (M2), data block allocated to terminal user 3 (M3), ..., data block allocated to terminal user i (M... i ).

[0132] 7. Adjustments to the public shared memory pool.

[0133] In some embodiments, during real-time communication between satellite base station users, the TA value of each user is periodically detected. When a user's TA value changes and enters a different latency interval, the number of HARQ processes for the UE needs to be adjusted based on the HARQ number corresponding to that latency interval and the UE's HARQ process support capability. Furthermore, based on the HARQ change, the memory block size required for UE data caching is recalculated and reallocated in the memory pool. Simultaneously, based on the changes in the memory block size of each UE, it is determined whether to reallocate the shared memory pool. The total number of processes for all UEs is counted, and the total memory block size C is calculated. new When the total memory block size C is counted new Exceeding the current public memory pool size C cur And the current public memory pool occupancy rate exceeds the threshold T. h1 (e.g., total size C) cur When 90% of the memory is allocated, the public memory pool is reallocated, with the size based on the newly calculated memory block size. When the newly calculated memory block C... new Smaller than the current public memory pool size C cur And the occupancy rate of the public memory pool is lower than the threshold T. h2 At that time, the shared memory pool is reallocated, with the size set to the newly calculated value C. new*(1+r), where r is a scaling factor, for example, 0.1. When the newly calculated public memory pool size exceeds the original size, the original size remains unchanged.

[0134] 8. For memory blocks in the memory pool, establish an address table to manage memory blocks managed by HARQ process.

[0135] Here, the address table includes information on all memory blocks in the memory pool. Each memory block's information includes three fields: a free flag, the starting address of the memory block, and the length of the memory block. When each UE needs to allocate a new process memory block, it queries the free flag of memory blocks in the memory pool, selects a free memory block, and sets the free flag of that memory block to "occupied." When the process data processing is complete and no longer needed, the occupied flag of the memory block is simply set to "free," which facilitates the allocation of the memory block by other UEs.

[0136] Embodiments of this application provide a first device that can be used to implement Figure 4 A corresponding embodiment provides a resource allocation method, referring to... Figure 7 As shown, the first device 700 includes:

[0137] The receiving module 701 is used to receive a first message sent by the first terminal; wherein the first message is used to estimate the transmission delay between the first terminal and the first device;

[0138] Processing module 702 is used to determine the first delay interval to which the first terminal belongs based on the estimated transmission delay;

[0139] The processing module 702 is used to allocate a memory block matching the first latency interval to the first terminal in a common shared memory pool.

[0140] In other embodiments of this application, the public shared memory pool includes a first public shared memory pool, and an acquisition module 703 is used to acquire the peak rate of the first terminal and the duration of all processes in the first latency interval.

[0141] Processing module 702 is used to determine the first buffer block required by the first terminal based on the duration and peak rate;

[0142] The processing module 702 is used to allocate a memory block that matches the first cache block to the first terminal in the first public shared memory pool.

[0143] In other embodiments of this application, the public shared memory pool includes a second public shared memory pool, and the acquisition module 703 is used to acquire the number of processes corresponding to the first latency interval, the peak rate of the first terminal, the scheduling time interval of the first device, and the duration of all processes in the first latency interval.

[0144] Processing module 702 is used to determine the second cache block corresponding to a single process based on peak rate, duration, number of processes, and scheduling time interval;

[0145] Processing module 702 is configured to allocate a memory block matching the second cache block for each of at least one process required by the first terminal in the second common shared memory pool.

[0146] In other embodiments of this application, the acquisition module 703 is used to acquire the bit width of the soft bit information cached by each process if the first terminal performs uplink transmission;

[0147] Processing module 702 is used to determine the second cache block based on peak rate, duration, number of processes, scheduling time interval and bit width.

[0148] In other embodiments of this application, the acquisition module 703 is used to acquire the minimum coding rate and the number of redundant versions corresponding to each process cache if the first terminal performs downlink transmission.

[0149] Processing module 702 is used to determine the second cache block based on peak rate, duration, number of processes, scheduling interval, minimum coding rate and number of redundant versions.

[0150] In other embodiments of this application, the processing module 702 is used to determine M delay intervals corresponding to the coverage area of ​​the first device; wherein M is a positive integer; the M delay intervals include the first delay interval;

[0151] The acquisition module 703 is used to acquire a first number of terminals included in each delay interval and a second number of processes corresponding to each delay interval;

[0152] Processing module 702 is used to calculate the third cache block required by a single process;

[0153] Processing module 702 is used to calculate the first common shared memory pool based on M, the first quantity, the second quantity, and the third cache block.

[0154] In other embodiments of this application, the acquisition module 703 is used to acquire the maximum and minimum transmission delay from the terminal within the coverage area of ​​the first device to the first device;

[0155] Processing module 702 is used to calculate M delay intervals based on the maximum transmission delay and the minimum transmission delay.

[0156] In other embodiments of this application, the processing module 702 is used to allocate a memory block matching the second latency interval to the first terminal in the public shared memory pool if the latency interval to which the first terminal belongs switches from the first latency interval to the second latency interval.

[0157] In other embodiments of this application, the processing module 702 is used to determine whether to reallocate the public shared memory pool if the memory block size of the first terminal changes.

[0158] In other embodiments of this application, the processing module 702 is used to establish a first address table and manage memory blocks in the public shared memory pool based on the first address table.

[0159] In other embodiments of this application, the acquisition module 703 is used to acquire the number of all processes included in the M latency intervals corresponding to the coverage area of ​​the first device;

[0160] Processing module 702 is used to calculate the third cache block required by a single process;

[0161] Processing module 702 is used to calculate the second common shared memory pool based on the total number of processes and the third cache block.

[0162] The descriptions of the above device embodiments are similar to those of the above method embodiments, and have similar beneficial effects. For technical details not disclosed in the device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0163] It should be noted that, in the embodiments of this application, if the above-described resource allocation method is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the related technology, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a terminal device to execute all or part of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware and software combination.

[0164] Figure 8 This is a schematic structural diagram of a first device 800 provided in an embodiment of this application. Figure 8 The first device 800 shown includes a processor 810, which can call and run computer programs from memory to implement the methods in the embodiments of this application.

[0165] Optionally, such as Figure 8 As shown, the first device 800 may further include a memory 820. The processor 810 can retrieve and run computer programs from the memory 820 to implement the methods described in this embodiment.

[0166] The memory 820 can be a separate device independent of the processor 810, or it can be integrated into the processor 810.

[0167] Optionally, such as Figure 8 As shown, the first device 800 may further include a transceiver 830, which the processor 810 can control to communicate with other devices. Specifically, it can send information or data to other devices or receive information or data sent by other devices.

[0168] The transceiver 830 may include a transmitter and a receiver. The transceiver 830 may further include an antenna, and the number of antennas may be one or more.

[0169] Optionally, the first device 800 can implement the corresponding processes implemented by the first device in the various methods of the embodiments of this application, which will not be described in detail here for the sake of brevity.

[0170] This application also provides a computer program product, including a computer program that can be executed by the processor 810 of the first device 800 to perform the steps described in any of the foregoing methods.

[0171] It should be understood that the processor in the embodiments of this application may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor described above can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0172] As one embodiment, the processor may include one or more general-purpose central processing units (CPUs). Each of these processors may be a single-core processor or a multi-core processor. Here, "processor" may refer to one or more devices, circuits, and / or processing cores used for processing data (e.g., executing instructions).

[0173] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be ROM, Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), or flash memory. The volatile memory can be Random Access Memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0174] This application also provides a computer-readable storage medium for storing computer programs.

[0175] Optionally, the computer-readable storage medium can be applied to the first device in the embodiments of this application, and the computer program causes the computer to execute the corresponding processes implemented by the first device in the various methods of the embodiments of this application. For the sake of brevity, it will not be described in detail here.

[0176] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0177] A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0178] The resource allocation method, first device, computer-readable storage medium, and computer program product provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

[0179] It should be understood that the phrases "an embodiment," "an embodiment," "an embodiment of this application," "the foregoing embodiment," "some implementations," or "some embodiments" mentioned throughout the specification mean that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, the phrases "an embodiment," "an embodiment," "an embodiment of this application," "the foregoing embodiment," "some implementations," or "some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0180] Unless otherwise specified, any step performed by the first device in the embodiments of this application may be executed by the processor of the first device. Unless otherwise specified, the embodiments of this application do not limit the order in which the first device performs the following steps. Furthermore, the methods used to process data in different embodiments may be the same or different methods.

[0181] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0182] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0183] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0184] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0185] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0186] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0187] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0188] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0189] The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0190] It should be noted that in the various embodiments involved in this application, all steps or some steps may be performed, as long as a complete technical solution can be formed.

[0191] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A resource allocation method, characterized in that, Applied to a first device, the method includes: Receive a first message sent by a first terminal; wherein the first message is used to estimate the transmission delay between the first terminal and the first device; Based on the estimated transmission delay, the first delay interval to which the first terminal belongs is determined; In the public shared memory pool, a memory block matching the first latency interval is allocated to the first terminal.

2. The method according to claim 1, characterized in that, The public shared memory pool includes a first public shared memory pool, and the process of allocating memory blocks matching the first latency interval for the first terminal in the public shared memory pool includes: Obtain the peak rate of the first terminal and the duration of all processes in the first latency interval; Based on the duration and the peak rate, the first cache block required by the first terminal is determined; In the first public shared memory pool, a memory block matching the first cache block is allocated to the first terminal.

3. The method according to claim 1, characterized in that, The public shared memory pool includes a second public shared memory pool. The process of allocating memory blocks matching the first latency interval to the first terminal within the public shared memory pool includes: Obtain the number of processes corresponding to the first latency interval, the peak rate of the first terminal, the scheduling time interval of the first device, and the duration of all processes in the first latency interval; Based on the peak rate, the duration, the number of processes, and the scheduling time interval, determine the second cache block corresponding to a single process; In the second public shared memory pool, a memory block matching the second cache block is allocated for each process in at least one process required by the first terminal.

4. The method according to claim 3, characterized in that, The step of determining the second cache block corresponding to a single process based on the peak rate, the duration, the number of processes, and the scheduling time interval includes: If the first terminal performs uplink transmission, it obtains the bit width of the soft bit information cached by each process; The second cache block is determined based on the peak rate, the duration, the number of processes, the scheduling time interval, and the bit width.

5. The method according to claim 3, characterized in that, The step of determining the second cache block corresponding to a single process based on the peak rate, the duration, the number of processes, and the scheduling time interval includes: If the first terminal performs downlink transmission, obtain the minimum coding rate and the number of redundant versions corresponding to each process cache; The second cache block is determined based on the peak rate, the duration, the number of processes, the scheduling time interval, the minimum coding rate, and the number of redundant versions.

6. The method according to claim 2, characterized in that, The method further includes: M delay intervals are determined within the coverage area of ​​the first device; wherein M is a positive integer; the M delay intervals include the first delay interval; Obtain the first number of terminals included in each latency interval and the second number of processes corresponding to each latency interval; The third cache block required for a single process; The first public shared memory pool is calculated based on M, the first quantity, the second quantity, and the third cache block.

7. The method according to claim 6, characterized in that, Determining the M time delay intervals corresponding to the coverage area of ​​the first device includes: Obtain the maximum and minimum transmission delay from terminals within the coverage area of ​​the first device to the first device; Based on the maximum transmission delay and the minimum transmission delay, calculate M delay intervals.

8. The method according to claim 1, characterized in that, The method further includes: If the latency interval to which the first terminal belongs switches from the first latency interval to the second latency interval, a memory block matching the second latency interval is allocated to the first terminal in the public shared memory pool.

9. The method according to claim 1, characterized in that, The method further includes: If the size of the memory block of the first terminal changes, determine whether to reallocate the public shared memory pool.

10. The method according to claim 1, characterized in that, The method further includes: Establish the first address table; Based on the first address table, memory blocks in the public shared memory pool are managed.

11. The method according to claim 3, characterized in that, The method further includes: Obtain the total number of all processes included in the M latency intervals corresponding to the coverage area of ​​the first device; The third cache block required for a single process; The second public shared memory pool is calculated based on the total number of processes and the third cache block.

12. A first device, characterized in that, The first device includes: A receiving module is configured to receive a first message sent by a first terminal; wherein the first message is used to estimate the transmission delay between the first terminal and the first device; The processing module is used to determine the first delay interval to which the first terminal belongs based on the estimated transmission delay; The processing module is further configured to allocate a memory block matching the first latency interval to the first terminal in a public shared memory pool.

13. A first device, characterized in that, The first device includes: Memory, used to store executable instructions; A processor, when executing executable instructions stored in the memory, implements the resource allocation method according to any one of claims 1 to 11.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the resource allocation method according to any one of claims 1 to 11.

15. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the resource allocation method according to any one of claims 1 to 11.

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